WO2022264697A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022264697A1
WO2022264697A1 PCT/JP2022/018987 JP2022018987W WO2022264697A1 WO 2022264697 A1 WO2022264697 A1 WO 2022264697A1 JP 2022018987 W JP2022018987 W JP 2022018987W WO 2022264697 A1 WO2022264697 A1 WO 2022264697A1
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Prior art keywords
region
semiconductor device
boundary
contact
boundary region
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English (en)
French (fr)
Japanese (ja)
Inventor
崇一 吉田
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2023529663A priority Critical patent/JP7732510B2/ja
Priority to CN202280007627.2A priority patent/CN116490960A/zh
Publication of WO2022264697A1 publication Critical patent/WO2022264697A1/ja
Priority to US18/320,997 priority patent/US20230299078A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617—Combinations of vertical BJTs and only diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to semiconductor devices.
  • Patent Document 1 JP-A-2018-073911
  • Patent Document 2 International Publication No. 2019/176327
  • a semiconductor device in a first aspect of the present invention, includes a transistor portion and a diode portion, and includes a first conductivity type drift region provided in a semiconductor substrate and a second conductivity type drift region provided above the drift region. an emitter region of a first conductivity type overlying the base region and having a higher doping concentration than the drift region; and a second conductivity type overlying the base region and having a higher doping concentration than the base region. and a plurality of trench portions provided on the front surface of the semiconductor substrate, the transistor portion having a boundary region provided adjacent to the diode portion, and the plurality of trench portions.
  • the lifetime control region is provided beyond the boundary region from the diode portion to the transistor portion provided with the emitter region, and the boundary region is provided extending in the extending direction of the plurality of trench portions.
  • a second conductivity type plug region having a higher doping concentration than a base region; and a contact region and a base region alternately arranged in an extending direction on a front surface of a boundary region.
  • the boundary region may consist of one mesa portion sandwiched between two of the plurality of trench portions.
  • the contact regions and the emitter regions may be alternately arranged in the extending direction.
  • the contact region in the boundary region may be provided in a position corresponding to the contact region in the transistor portion other than the boundary region in the extending direction.
  • the thinning rate which is the ratio of the base area exposed on the front surface, may be 30% or more and 80% or less.
  • the length in which the plug region extends in the extending direction may be longer than the length in which the contact region extends in the extending direction.
  • the diode section may have a plug region.
  • the plug region of the boundary region may have the same doping concentration as the plug region of the diode section.
  • the plurality of trench portions in the boundary region may be dummy trench portions.
  • the emitter region closest to the boundary region in the array direction may be sandwiched between dummy trench portions.
  • the boundary region may not be provided with the emitter region.
  • a collector region of the second conductivity type provided on the back surface of the semiconductor substrate may be provided below the boundary region.
  • a cathode region of the first conductivity type provided on the back surface of the semiconductor substrate may be provided below the boundary region.
  • the lifetime control region may be provided on the entire surface of the semiconductor substrate when viewed from above.
  • the transistor section may have a first conductivity type accumulation region provided above the drift region and having a higher doping concentration than the drift region.
  • the accumulation region may be provided both in the boundary region and in the transistor portion other than the boundary region.
  • the accumulation region may be provided in both the transistor section and the diode section.
  • FIG. 1A shows an example of the aa' cross section of the semiconductor device 100.
  • FIG. 1A shows an example of a bb′ cross section of the semiconductor device 100.
  • FIG. 1A shows an example of a cc' cross section of the semiconductor device 100.
  • FIG. A modification of the semiconductor device 100 is shown.
  • a modification of the semiconductor device 100 is shown.
  • a modification of the semiconductor device 100 is shown.
  • a semiconductor device 500 of a comparative example is shown.
  • An example of IV characteristics of the semiconductor device 100 and the semiconductor device 500 is shown.
  • one side in a direction parallel to the depth direction of the semiconductor substrate is called “upper”, and the other side is called “lower”.
  • One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface.
  • the directions of "top”, “bottom”, “front”, and “back” are not limited to the direction of gravity or the mounting direction to a substrate or the like when the semiconductor device is mounted.
  • the plane parallel to the upper surface of the semiconductor substrate is the XY plane
  • the depth direction of the semiconductor substrate is the Z axis.
  • top view the case where the semiconductor substrate is viewed in the Z-axis direction.
  • the first conductivity type is the N type and the second conductivity type is the P type is shown, but the first conductivity type may be the P type and the second conductivity type may be the N type.
  • the conductivity types of substrates, layers, regions, etc. in each embodiment have opposite polarities.
  • layers and regions prefixed with N or P mean that electrons or holes are majority carriers, respectively.
  • + and - attached to N and P mean that the doping concentration is higher and lower than the layer or region not attached, respectively, ++ is higher doping concentration than +, -- means a lower doping concentration than -.
  • doping concentration refers to the concentration of dopants that are donors or acceptors. Its unit is therefore cm ⁇ 3 .
  • the concentration difference between donors and acceptors may be referred to as doping concentration.
  • the doping concentration can be measured by the SR method.
  • the chemical concentrations of donors and acceptors may be used as doping concentrations.
  • the doping concentration can be measured by the SIMS method. Unless otherwise specified, any of the above doping concentrations may be used.
  • the doping concentration in the doping region may be the peak value of the doping concentration distribution in the doping region.
  • FIG. 1A shows an example of a top view of the semiconductor device 100.
  • FIG. A semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80 .
  • the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT).
  • RC-IGBT Reverse Conducting IGBT
  • the transistor portion 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the top surface of the semiconductor substrate 10 .
  • Collector region 22 has a second conductivity type.
  • the collector region 22 in this example is of P+ type as an example.
  • the transistor section 70 includes transistors such as IGBTs.
  • Transistor portion 70 includes a boundary region 90 located at the boundary between transistor portion 70 and diode portion 80 . Note that the boundary region 90 may have the cathode region 82 on the back side of the semiconductor substrate 10 .
  • the diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10 .
  • Cathode region 82 has a first conductivity type.
  • the cathode region 82 in this example is of the N+ type as an example.
  • the diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10 .
  • FWD free wheel diode
  • FIG. 1A shows the area around the chip end, which is the edge side of the semiconductor device 100, and omits other areas.
  • an edge termination structure portion may be provided in the region on the negative side in the Y-axis direction of the semiconductor device 100 of this example.
  • the edge termination structure relieves electric field concentration on the top side of the semiconductor substrate 10 .
  • Edge termination structures include, for example, guard rings, field plates, RESURF, and combinations thereof. In this example, for the sake of convenience, the edge on the negative side in the Y-axis direction will be described, but the other edges of the semiconductor device 100 are the same.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like.
  • the semiconductor substrate 10 of this example is a silicon substrate.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface of a semiconductor substrate 10. Prepare.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10 .
  • the emitter electrode 52 is provided above the gate trench portion 40 , the dummy trench portion 30 , the emitter region 12 , the base region 14 , the contact region 15 and the well region 17 . Also, the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17 .
  • the emitter electrode 52 and the gate metal layer 50 are made of a material containing metal.
  • the emitter electrode 52 may be made of aluminum or an alloy containing aluminum as a main component (eg, an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or the like).
  • At least a partial region of the gate metal layer 50 may be formed of aluminum, an aluminum-based alloy (eg, an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or the like).
  • the emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound or the like under the region made of aluminum or the like. Emitter electrode 52 and gate metal layer 50 are provided separately from each other.
  • the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween.
  • the interlayer insulating film 38 is omitted in FIG. 1A.
  • a contact hole 54 , a contact hole 55 and a contact hole 56 are provided through the interlayer insulating film 38 .
  • the contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 .
  • a plug made of tungsten or the like may be formed inside the contact hole 55 .
  • the contact hole 56 connects the emitter electrode 52 and the dummy conductive portion within the dummy trench portion 30 .
  • a plug made of tungsten or the like may be formed inside the contact hole 56 .
  • the connecting portion 25 electrically connects the front surface side electrode such as the emitter electrode 52 or the gate metal layer 50 and the semiconductor substrate 10 .
  • the connection 25 is provided between the gate metal layer 50 and the gate conductor.
  • the connecting portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion.
  • the connection portion 25 is a conductive material such as polysilicon doped with impurities.
  • the connecting portion 25 is polysilicon (N+) doped with N-type impurities.
  • the connecting portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.
  • the gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example).
  • the gate trench portion 40 of this example includes two extending portions 41 extending along an extending direction (in this example, the Y-axis direction) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction. and a connecting portion 43 connecting the two extending portions 41 .
  • At least a portion of the connecting portion 43 may be curved. By connecting the ends of the two extending portions 41 of the gate trench portion 40, electric field concentration at the ends of the extending portions 41 can be alleviated.
  • the gate metal layer 50 may be connected with the gate conductive portion.
  • the dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52 . Like the gate trench portions 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example).
  • the dummy trench portion 30 of this example may have a U-shape on the front surface of the semiconductor substrate 10, similarly to the gate trench portion 40. As shown in FIG. That is, the dummy trench portion 30 may have two extending portions 31 extending along the extending direction and a connection portion 33 connecting the two extending portions 31 .
  • the transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench section 40 and the dummy trench section 30 at a ratio of 2:3. For example, the transistor section 70 has one extension portion 31 between two extension portions 41 . Further, the transistor portion 70 has two extending portions 31 adjacent to the gate trench portion 40 .
  • the ratio of the gate trench portion 40 and the dummy trench portion 30 is not limited to this example.
  • a ratio of the gate trench portion 40 and the dummy trench portion 30 may be 1:1 or 2:4.
  • the dummy trench portion 30 may not be provided in the transistor portion 70 , and the entire gate trench portion 40 may be used.
  • the well region 17 is a region of the second conductivity type provided closer to the front surface of the semiconductor substrate 10 than the drift region 18, which will be described later.
  • Well region 17 is an example of a well region provided on the edge side of semiconductor device 100 .
  • Well region 17 is of P+ type, for example.
  • the well region 17 is formed within a predetermined range from the edge of the active region on the side where the gate metal layer 50 is provided.
  • the diffusion depth of well region 17 may be deeper than the depths of gate trench portion 40 and dummy trench portion 30 .
  • a portion of gate trench portion 40 and dummy trench portion 30 on the side of gate metal layer 50 is formed in well region 17 .
  • the bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extending direction may be covered with the well region 17 .
  • the contact hole 54 is formed above each region of the emitter region 12 and the contact region 15 in the transistor section 70 . Also, the contact hole 54 is provided above the base region 14 in the diode section 80 . Contact hole 54 is provided above contact region 15 in boundary region 90 . The contact hole 54 is provided above the base region 14 in the diode section 80 . None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. One or more contact holes 54 may be provided extending in the extension direction. A plug region 19 may be provided below the contact hole 54 . The plug region 19 will be described later.
  • the boundary region 90 is a region provided in the transistor section 70 and adjacent to the diode section 80 . Border region 90 has contact region 15 . Since the boundary region 90 has the contact region 15, it is possible to extract holes remaining in the diode section 80 during the turn-off operation, thereby suppressing breakdown due to latch-up.
  • the boundary region 90 in this example does not have an emitter region 12 . This can suppress a decrease in latch-up resistance.
  • the boundary region 90 of this example consists of one mesa portion 91 sandwiched between two trench portions.
  • the boundary region 90 By forming the boundary region 90 into one mesa portion 91, the area of the active regions of the transistor portion 70 and the diode portion 80 can be kept wide, and deterioration of electrical characteristics (for example, forward current-voltage characteristics, etc.) can be suppressed. becomes possible.
  • the boundary region 90 may be composed of three or more trench portions and a plurality of mesa portions 91 .
  • the trench portion of the boundary region 90 is the dummy trench portion 30 .
  • the boundary region 90 of this example is arranged so that both ends in the X-axis direction are the dummy trench portions 30 . Also, the emitter region 12 closest to the boundary region 90 in the arrangement direction is sandwiched between the dummy trench portions 30 . With this structure, it is possible to suppress the influence of fluctuations in gate potential on electrical characteristics (for example, current-voltage characteristics in the forward direction).
  • the mesa portion 71 , the mesa portion 91 and the mesa portion 81 are mesa portions provided adjacent to the trench portion in a plane parallel to the front surface of the semiconductor substrate 10 .
  • the mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. .
  • the extending portion of each trench portion may be one trench portion. That is, the mesa portion may be a region sandwiched between the two extending portions.
  • the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40 in the transistor portion 70 .
  • Mesa portion 71 has well region 17 , emitter region 12 , base region 14 and contact region 15 on the front surface of semiconductor substrate 10 .
  • the emitter regions 12 and the contact regions 15 are alternately provided in the extending direction.
  • the mesa portion 91 is provided in the boundary area 90 .
  • Mesa portion 91 has base region 14 , contact region 15 and well region 17 on the front surface of semiconductor substrate 10 .
  • the base regions 14 and the contact regions 15 are alternately provided in the extending direction. In this manner, since the contact regions 15 are thinned out, the boundary region 90 suppresses excessive hole injection during diode operation, and reduces the reverse recovery loss Err, the turn-on loss Eon, and the reverse recovery surge voltage. be able to.
  • the mesa portion 81 is provided in a region sandwiched between adjacent dummy trench portions 30 in the diode portion 80 .
  • Mesa portion 81 has base region 14 and well region 17 on the front surface of semiconductor substrate 10 .
  • the base region 14 is a region of the second conductivity type provided on the front surface side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80 .
  • Base region 14 is, for example, P-type.
  • the base regions 14 may be provided at both ends of the mesa portion 71 and the mesa portion 91 in the Y-axis direction on the front surface of the semiconductor substrate 10 . Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.
  • the emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18 .
  • the emitter region 12 in this example is of N+ type as an example.
  • An example dopant for emitter region 12 is arsenic (As).
  • Emitter region 12 is provided in contact with gate trench portion 40 on the front surface of mesa portion 71 .
  • the emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other.
  • the emitter region 12 is also provided below the contact hole 54 .
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30 .
  • the emitter region 12 of this example is in contact with the dummy trench portion 30 .
  • Emitter region 12 may not be provided in mesa portion 91 .
  • the contact region 15 is a second conductivity type region with a higher doping concentration than the base region 14 .
  • the contact region 15 in this example is of P+ type as an example.
  • the contact region 15 of this example is provided on the front surfaces of the mesa portion 71 and the mesa portion 91 .
  • the contact region 15 may be provided in the X-axis direction from one to the other of two trench portions sandwiching the mesa portion 71 or the mesa portion 91 .
  • the contact region 15 may or may not be in contact with the gate trench portion 40 .
  • the contact region 15 may or may not be in contact with the dummy trench portion 30 .
  • contact region 15 is in contact with dummy trench portion 30 and gate trench portion 40 .
  • the contact region 15 is also provided below the contact hole 54 . Note that the contact region 15 may also be provided in the mesa portion 81 .
  • the contact regions 15 and the emitter regions 12 are alternately arranged in the extending direction.
  • the contact regions 15 in the boundary region 90 are provided in correspondence with the contact regions 15 in the transistor section 70 other than the boundary region 90 in the extending direction.
  • the corresponding positions in the extending direction indicate that the positions in the extending direction of the contact regions 15 are at least overlapped.
  • a mask for implanting the dopant of the contact region 15 is provided extending in the X-axis direction beyond the plurality of trench portions. As a result, patterning accuracy can be improved even when the width of the mesa portion in the X-axis direction is reduced.
  • the base region 14 in the boundary region 90 may be provided in correspondence with the position in the extending direction of the emitter region 12 in the transistor section 70 other than the boundary region 90 .
  • the plug region 19 is provided in the contact hole 54 by extending in the extending direction without thinning.
  • the plug regions 19 extend in the extension direction beyond the base regions 14 and the contact regions 15 above the base regions 14 and the contact regions 15 that are alternately arranged in the extension direction. That is, in the boundary region 90, the length in which the plug region 19 extends in the extending direction is longer than the length in which the contact region 15 extends in the extending direction. In the boundary region 90, the length of the plug region 19 extending in the extending direction may be longer than the length of the base region 14 extending in the extending direction.
  • FIG. 1B shows an example of the aa' cross section of the semiconductor device 100 in FIG. 1A.
  • the aa′ cross section is the XZ plane passing through the emitter region 12 of the mesa portion 71 .
  • the aa′ section of this example passes through the contact region 15 of the mesa portion 91 .
  • a semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52 and a collector electrode 24 in the aa' section. Emitter electrode 52 is formed above semiconductor substrate 10 and interlayer insulating film 38 .
  • the drift region 18 is a first conductivity type region provided in the semiconductor substrate 10 .
  • the drift region 18 in this example is of the N ⁇ type as an example.
  • Drift region 18 may be a remaining region of semiconductor substrate 10 where no other doping regions are formed. That is, the doping concentration of drift region 18 may be the doping concentration of semiconductor substrate 10 .
  • the buffer region 20 is a first conductivity type region provided below the drift region 18 .
  • the buffer region 20 of this example is of N type as an example.
  • the doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 .
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.
  • the collector region 22 is provided below the buffer region 20 in the transistor section 70 .
  • the cathode region 82 is provided below the buffer region 20 in the diode section 80 .
  • the boundary between collector region 22 and cathode region 82 is the boundary between transistor section 70 and diode section 80 .
  • the collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10 .
  • the collector electrode 24 is made of a conductive material such as metal.
  • the base region 14 is a region of the second conductivity type provided above the base region 14 in the mesa portion 71 , the mesa portion 91 and the mesa portion 81 .
  • the base region 14 is provided in contact with the gate trench portion 40 .
  • the base region 14 may be provided in contact with the dummy trench portion 30 .
  • the emitter region 12 is provided between the base region 14 and the front surface 21 in the mesa portion 71 . Emitter region 12 is provided in contact with gate trench portion 40 . The emitter region 12 may or may not be in contact with the dummy trench portion 30 . Note that the emitter region 12 does not have to be provided in the mesa portion 91 .
  • the plug region 19 is a second conductivity type region having a higher doping concentration than the base region 14 and the contact region 15 .
  • the plug region 19 in this example is of P++ type as an example.
  • the plug region 19 in this example is provided on the front surface 21 . In the aa′ cross section, the plug region 19 is provided above the base region 14 in the mesa portion 81 and the mesa portion 91 .
  • the plug region 19 in this example contacts the base region 14 .
  • the plug region 19 is separated from the adjacent trench portion.
  • the plug region 19 may be provided extending in the Y-axis direction along the contact hole 54 in the mesa portion 91 and the mesa portion 81 . Plug regions 19 of mesa 81 and mesa 91 in this example have the same doping concentration, but may have different doping concentrations.
  • the accumulation region 16 is a region of the first conductivity type provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 is.
  • the accumulation region 16 of this example is of the N+ type as an example.
  • the accumulation region 16 is provided in the transistor section 70 .
  • the accumulation region 16 of this example is provided in both the boundary region 90 and the transistor section 70 other than the boundary region 90 .
  • the transistor portion 70 other than the boundary region 90 is the region in which the mesa portion 71 is formed.
  • the accumulation region 16 is provided in contact with the gate trench portion 40 .
  • the accumulation region 16 may or may not contact the dummy trench portion 30 .
  • the doping concentration of accumulation region 16 is higher than the doping concentration of drift region 18 .
  • the dose of ion implantation in the accumulation region 16 may be 1E12 cm ⁇ 2 or more and 1E13 cm ⁇ 2 or less.
  • the ion implantation dose of the accumulation region 16 may be 3E12 cm ⁇ 2 or more and 6E12 cm ⁇ 2 or less.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21 .
  • Each trench portion extends from the front surface 21 to the drift region 18 .
  • each trench portion also penetrates these regions and reaches drift region 18 .
  • the fact that the trench penetrates the doping region is not limited to the order of forming the doping region and then forming the trench.
  • a structure in which a doping region is formed between the trench portions after the trench portions are formed is also included in the structure in which the trench portion penetrates the doping regions.
  • the gate trench portion 40 has a gate trench formed in the front surface 21 , a gate insulating film 42 and a gate conductive portion 44 .
  • a gate insulating film 42 is formed to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench.
  • the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10 .
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • Gate trench portion 40 is covered with interlayer insulating film 38 on front surface 21 .
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10 .
  • a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 in contact with the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 .
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32 and a dummy conductive portion 34 formed on the front surface 21 side.
  • the dummy insulating film 32 is formed covering the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32 .
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10 .
  • the dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21 .
  • the interlayer insulating film 38 is provided on the front surface 21 .
  • An emitter electrode 52 is provided above the interlayer insulating film 38 .
  • the interlayer insulating film 38 is provided with one or a plurality of contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10 .
  • Contact hole 55 and contact hole 56 may be similarly provided through interlayer insulating film 38 .
  • the lifetime control region 150 is a region where a lifetime killer is intentionally formed by implanting impurities into the semiconductor substrate 10 or the like. Lifetime killers are recombination centers for carriers. A lifetime killer may be a crystal defect. For example, lifetime killers may be vacancies, double vacancies, complex defects between these and elements constituting the semiconductor substrate 10, or dislocations. Also, the lifetime killer may be a rare gas element such as helium or neon, or a metal element such as platinum. The lifetime control region 150 can be formed by implanting helium or the like into the semiconductor substrate 10 .
  • the lifetime control region 150 is provided on the front surface 21 side of the semiconductor substrate 10 . Lifetime control region 150 is provided in both transistor section 70 and diode section 80 . The lifetime control region 150 may be formed by implanting impurities from the front surface 21 side, or may be formed by implanting impurities from the back surface 23 side.
  • the lifetime control region 150 is provided across the boundary region 90 from the diode portion 80 to the transistor portion 70 provided with the emitter region 12 in the arrangement direction.
  • the lifetime control region 150 of this example is provided on the entire surface of the semiconductor substrate 10 when viewed from above. Therefore, lifetime control region 150 can be formed without using a mask.
  • the impurity dose for forming the lifetime control region 150 may be 0.5E10 cm ⁇ 2 or more and 1E13 cm ⁇ 2 or less. Also, the impurity dose for forming the lifetime control region 150 may be 5E10 cm ⁇ 2 or more and 5E11 cm ⁇ 2 or less.
  • the lifetime control region 150 of this example is formed by injection from the back surface 23 side.
  • the lifetime control region 150 is formed by irradiating helium from the rear surface 23 side. Thereby, the influence on the front surface 21 side of the semiconductor device 100 can be avoided.
  • whether the lifetime control region 150 is formed by injection from the front surface 21 side or by injection from the back surface 23 side is determined by the SR method or measurement of leakage current. It can be determined by acquiring the state of the 21 side.
  • the collector region 22 of this example is provided on the back surface 23 below the boundary region 90 .
  • the boundary between collector region 22 and cathode region 82 is located at the boundary between transistor section 70 and diode section 80 .
  • FIG. 1C shows an example of the bb' cross section of the semiconductor device 100 in FIG. 1A.
  • the bb' cross section is the XZ plane passing through the contact region 15 at the mesa portion 71 .
  • the bb' cross section of this example passes through the contact region 15 at the mesa portion 91 as well.
  • the mesa portion 71 has a base region 14 , a contact region 15 and an accumulation region 16 .
  • the mesa portion 91 has a base region 14 , a contact region 15 , an accumulation region 16 and a plug region 19 .
  • the mesa portion 91 differs from the mesa portion 71 in that it has the plug region 19 .
  • the mesa portion 81 has a base region 14, an accumulation region 16, and a plug region 19, similarly to the aa' section.
  • the contact region 15 is provided above the base region 14 in the mesa portion 91 .
  • the contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91 .
  • the plug region 19 is provided above the contact region 15 of the mesa portion 91 in the bb' section.
  • the plug region 19 in this example is in contact with the contact region 15 .
  • the plug region 19 is provided in the mesa portion 91 on both the aa' cross section and the bb' cross section. That is, the plug region 19 is provided extending in the extension direction on the front surface 21 .
  • the lifetime control region 150 is provided in both the transistor section 70 and the diode section 80 as in the case of the aa' cross section. Since the semiconductor device 100 of this example includes the lifetime control regions 150 in both the transistor portion 70 and the diode portion 80, holes are uniformly released at the time of turn-off, and the carrier balance between the transistor portion 70 and the diode portion 80 is maintained. Improve.
  • FIG. 1D shows an example of a cc' cross section of the semiconductor device 100 in FIG. 1A.
  • the cc′ cross section is the YZ cross section of the mesa portion 91 .
  • the base region 14 and the contact region 15 are exposed to the front surface 21 at the mesa portion 91 .
  • the base regions 14 and the contact regions 15 are alternately arranged on the front surface 21 at a predetermined thinning rate.
  • a thinning rate is indicated by L1/(L1+L2). That is, the thinning rate indicates the proportion of the base area exposed on the front surface 21 in the boundary area 90 .
  • the length L1 is the width in the Y-axis direction between the bottoms of the contact regions 15 on the front surface 21 side.
  • the length L1 may be 2.2 ⁇ m or more and 30 ⁇ m or less.
  • length L1 is 2.2 ⁇ m.
  • the length L2 is the width in the Y-axis direction of the bottom of the contact region 15 on the front surface 21 side.
  • the length L2 may be 0.5 ⁇ m or more and 5.0 ⁇ m or less.
  • length L2 is 0.6 ⁇ m.
  • Length L2 may be greater than length L1.
  • the bottom of the contact region 15 is a portion where the boundary between the base region 14 and the contact region 15 is generally flat in the Y-axis direction.
  • the base regions 14 and the contact regions 15 are alternately provided at the predetermined thinning rate in the boundary region 90. Therefore, the reverse recovery current Irp is reduced, the reverse recovery loss Err and the surge voltage are reduced. can be reduced.
  • the semiconductor device 100 can suppress an increase in contact resistance and suppress breakdown during turn-off and reverse recovery. Further, since the semiconductor device 100 does not have the emitter region 12 in the boundary region 90, the deterioration of the latch-up resistance can be suppressed. Thereby, the semiconductor device 100 can improve the trade-off characteristics between the diode forward voltage Vf and the reverse recovery loss Err, reduce the reverse recovery surge voltage, and suppress variations in the SW resistance.
  • FIG. 2 shows a modification of the semiconductor device 100.
  • FIG. This example shows an example of the aa' section in FIG. 1A.
  • the semiconductor device 100 of this example differs from the example of FIG. 1B in that the storage regions 16 are provided in both the transistor section 70 and the diode section 80 . It may be the same as the embodiment of FIG. 1B except for the differences from the embodiment of FIG. 1B.
  • the accumulation region 16 of this example is provided over the entire surface of the transistor section 70 and the diode section 80 . Thereby, the semiconductor device 100 can avoid the influence of mask misalignment of the accumulation region 16 .
  • Mesa portion 81 includes base region 14 , accumulation region 16 , and plug region 19 .
  • Accumulation region 16 is provided between base region 14 and drift region 18 .
  • the doping concentration of storage region 16 may be the same for transistor portion 70 and diode portion 80 .
  • FIG. 3 shows a modification of the semiconductor device 100.
  • FIG. This example shows an example of the aa' section in FIG. 1A.
  • the semiconductor device 100 of this example differs from the example of FIG. 1B in that a cathode region 82 is provided below the boundary region 90 . It may be the same as the embodiment of FIG. 1B except for the differences from the embodiment of FIG. 1B.
  • the cathode region 82 of this example is provided on the back surface 23 below the boundary region 90 .
  • the boundary between collector region 22 and cathode region 82 is located at the boundary between boundary region 90 and transistor section 70 other than boundary region 90 .
  • the boundary between the collector region 22 and the cathode region 82 in this example is provided below the dummy trench portion 30 adjacent to the mesa portion 91, but is not limited to this.
  • a boundary between the collector region 22 and the cathode region 82 may be located below the mesa portion 91 .
  • FIG. 4 shows a modification of the semiconductor device 100.
  • FIG. This example shows an example of the aa' section in FIG. 1A.
  • the semiconductor device 100 of this example differs from the example of FIG. 1B in that the lifetime control region 150 is provided not on the entire surface of the semiconductor substrate 10 but on a part thereof. It may be the same as the embodiment of FIG. 1B except for the differences from the embodiment of FIG. 1B.
  • the lifetime control region 150 is provided beyond the boundary region 90 from the diode portion 80 to the transistor portion 70 provided with the emitter region 12 in the arrangement direction.
  • the lifetime control region 150 of this example is provided over the entire surface of the diode section 80 and part of the transistor section 70 .
  • Length L3 is the length in the arrangement direction from the boundary between collector region 22 and cathode region 82 to the end of lifetime control region 150 .
  • the length L3 may be the same as the thickness of the semiconductor substrate 10 or may be larger than the thickness of the semiconductor substrate 10 . By appropriately setting the length L3, carrier injection can be suppressed.
  • FIG. 5 shows a semiconductor device 500 of a comparative example.
  • Semiconductor device 500 includes a boundary region 590 .
  • Mesa portion 591 of boundary region 590 has contact region 515 exposed to the front surface of semiconductor substrate 10 .
  • the contact region 515 is provided on the entire surface of the region sandwiched between the base regions 14 at both ends in the Y-axis direction. That is, in the mesa portion 591, the contact regions 515 and the base regions 14 are not provided alternately.
  • FIG. 6A shows an example of IV characteristics of the semiconductor device 100 and the semiconductor device 500.
  • FIG. There is no significant difference in IV characteristics between the semiconductor device 100 and the semiconductor device 500 .
  • FIG. 6B shows an example of reverse recovery characteristics of the semiconductor device 100 and the semiconductor device 500.
  • the semiconductor device 100 can improve the reverse recovery characteristics without significantly affecting the IV characteristics.
  • FIG. 7 shows the relationship between the thinning rate [%] and the change rate [%] of the reverse recovery loss Err.
  • the reverse recovery loss Err decreases as the thinning rate increases.
  • the thinning rate may be 20.0% or more, and may be 30.0% or more.
  • the thinning rate may be 80.0% or less, 70.0% or less, or 60.0% or less.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
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