WO2022249872A1 - 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法 - Google Patents

半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法 Download PDF

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WO2022249872A1
WO2022249872A1 PCT/JP2022/019691 JP2022019691W WO2022249872A1 WO 2022249872 A1 WO2022249872 A1 WO 2022249872A1 JP 2022019691 W JP2022019691 W JP 2022019691W WO 2022249872 A1 WO2022249872 A1 WO 2022249872A1
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layer
electrode
semiconductor
semiconductor device
znga
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French (fr)
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誠 中積
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Nikon Corp
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Priority to CN202280046363.1A priority Critical patent/CN117716515A/zh
Priority to JP2023523394A priority patent/JP7632606B2/ja
Priority to KR1020237039432A priority patent/KR102813570B1/ko
Publication of WO2022249872A1 publication Critical patent/WO2022249872A1/ja
Priority to US18/516,083 priority patent/US20240201125A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4145—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/28—Electrolytic cell components
    • G01N27/30—Electrodes, e.g. test electrodes; Half-cells
    • G01N27/327—Biochemical electrodes, e.g. electrical or mechanical details for in vitro measurements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4146—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS involving nanosized elements, e.g. nanotubes, nanowires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a semiconductor device, an electronic device, a pH sensor, a biosensor, a semiconductor device manufacturing method, and an electronic device manufacturing method.
  • the present invention claims priority of Japanese patent application number 2021-088679 filed on May 26, 2021, and for designated countries where incorporation by reference of documents is permitted, the content described in the application is incorporated into this application by reference.
  • amorphous oxides such as oxides composed of In, Ga, and Zn (IGZO; In--Ga--Zn--O) are used (Patent Reference 1).
  • IGZO In--Ga--Zn--O
  • Patent Reference 1 Such conventional semiconductor materials do not have sufficient chemical durability, so when manufacturing a semiconductor device, a structure for protecting the semiconductor materials from chemical damage is provided and processing such as an etching process is performed.
  • a first aspect of the present invention has a first electrode, a second electrode, and a semiconductor layer in contact with the first electrode and the second electrode, and the semiconductor layer has 5 to A semiconductor device comprising a first oxide layer comprising 20 nm of spinel-type ZnGa 2 O 4 and a second oxide layer comprising 5-50 nm of In, Ga and Zn.
  • a second aspect of the present invention is an electronic device comprising the semiconductor device of the first aspect.
  • a third aspect of the present invention is a pH sensor comprising the semiconductor device of the first aspect.
  • a fourth aspect of the present invention is a biosensor comprising the semiconductor device of the first aspect.
  • a fifth aspect of the present invention includes the steps of forming a semiconductor layer, forming a conductive layer on the semiconductor layer, etching the conductive layer in accordance with a predetermined pattern, and forming a first electrode. and forming a second electrode.
  • a sixth aspect of the present invention is a method for manufacturing an electronic device, including a step of forming a semiconductor device by the method for manufacturing a semiconductor device according to the fifth aspect.
  • FIG. 1 is a schematic diagram of a semiconductor device A according to the first embodiment.
  • FIG. 2 is a schematic diagram of a semiconductor device B according to the second embodiment.
  • FIG. 3 is a schematic diagram of a pH sensor C including a semiconductor device according to this embodiment.
  • FIG. 4 is a diagram showing an example of a method for manufacturing the semiconductor device A according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a method for manufacturing the semiconductor device B according to the second embodiment.
  • FIG. 6 is a graph showing measurement results of characteristics of the semiconductor device A according to the first embodiment.
  • FIG. 7 is a graph showing measurement results of characteristics of a semiconductor device having semiconductor layers of various thicknesses post-treated at an annealing temperature of 120.degree.
  • FIG. 1 is a schematic diagram of a semiconductor device A according to the first embodiment.
  • FIG. 2 is a schematic diagram of a semiconductor device B according to the second embodiment.
  • FIG. 3 is a schematic diagram of a pH sensor C including a
  • FIG. 8 is a graph showing measurement results of characteristics of a semiconductor device having semiconductor layers of various thicknesses post-treated at an annealing temperature of 150.degree.
  • FIG. 9 is a graph showing measurement results of characteristics of a semiconductor device including IGZTO semiconductor layers of various thicknesses post-treated at an annealing temperature of 120°C.
  • FIG. 10 is a graph showing measurement results of properties of a semiconductor device comprising an IGZTO semiconductor layer post-treated at an annealing temperature of 150.degree.
  • this embodiment is a form for carrying out the present invention, and are not intended to limit the present invention to the following contents.
  • the positional relationships in the drawings such as up, down, left, and right, are based on the positional relationships shown in the drawings.
  • the dimensional ratios of the drawings are not limited to the illustrated ratios.
  • FIG. 1 is a schematic diagram of a semiconductor device A according to the first embodiment.
  • FIG. 2 is a schematic diagram of a semiconductor device B according to the second embodiment.
  • the semiconductor device A according to the first embodiment is a bottom gate/top contact (BGTC) type semiconductor device.
  • the semiconductor device A has a first electrode 71, a second electrode 72, and a semiconductor layer 60 in contact with the first electrode and the second electrode.
  • the semiconductor layer 60 includes a spinel-type ZnGa 2 O 4 layer 50 (first oxide layer) and an IGZO layer 40 (second oxide layer).
  • a first electrode 71 and a second electrode 72 are located on the insulating layer 30 , partly overlying the spinel-type ZnGa 2 O 4 layer 50 .
  • the IGZO layer 40 is an oxide inorganic semiconductor containing In, Ga, and Zn.
  • the semiconductor device B according to the second embodiment is a bottom gate/top contact (BGTC) type semiconductor device.
  • the semiconductor device B has a first electrode 71, a second electrode 72, and a semiconductor layer 60 in contact with the first electrode and the second electrode.
  • the semiconductor layer 60 includes a spinel-type ZnGa 2 O 4 layer 50 (first oxide layer) and an IGZTO layer 41 (second oxide layer).
  • a first electrode 71 and a second electrode 72 are located on the insulating layer 30 , partly overlying the spinel-type ZnGa 2 O 4 layer 50 .
  • the IGZTO layer 41 is an oxide inorganic semiconductor containing In, Ga, Zn, and Sn.
  • Semiconductor devices A and B each have a substrate 10 , a third electrode 20 formed on the substrate 10 , and an insulating layer 30 formed on the third electrode 20 .
  • the third electrode 20 is provided facing the semiconductor layer 60 with the insulating layer 30 interposed therebetween.
  • the first electrode 71 is the source electrode
  • the second electrode 72 is the drain electrode
  • the third electrode 20 is the gate electrode.
  • the semiconductor devices A and B use the spinel-type ZnGa 2 O 4 layer 50, there are advantages in that the film formation temperature is low, the film formation speed is high, and impurities are less likely to enter. In addition, there is the advantage that even when flexible substrates are used, they are easy to manufacture.
  • metal oxide films such as silicon oxide and aluminum oxide have been widely used as protective layers (passivation layers) for semiconductor layers, but these films have many problems such as high film formation temperatures and slow film formation rates.
  • CVD method chemical vapor deposition method
  • the film formation temperature is high, a large-scale CVD film formation apparatus is required, and hydrogen and carbon derived from the material gas are required.
  • RF radio frequency
  • the semiconductor devices A and B can solve these problems at once by using the spinel-type ZnGa 2 O 4 layer 50 as the protective layer.
  • a spinel-type ZnGa 2 O 4 layer can be formed relatively easily and efficiently as compared with the metal oxide films and the like described above.
  • the spinel-type ZnGa 2 O 4 layers 50 of the semiconductor devices A and B are extremely stable against acids, bases, etc. while having semiconductor characteristics. Therefore, the semiconductor devices A and B exhibit excellent passivation effects comparable to or better than those of the protective layer using a conventional metal oxide film, and the semiconductor devices A and B are also excellent in terms of semiconductor characteristics.
  • the electrode can be placed directly on the semiconductor layer without an ESL (etch stop layer) or the like.
  • ESL etch stop layer
  • the use of the spinel-type ZnGa 2 O 4 layer 50 eliminates the need for such treatment.
  • the configurations of the semiconductor devices A and B will be described below.
  • the material of the substrate 10 is not particularly limited, and known materials can be adopted. Specific examples include glass, resin, silicon, metal, alloy, and foils thereof. Among these, one selected from the group consisting of glass, resin, silicon, and combinations thereof is preferable.
  • resins examples include polyacrylate, polycarbonate, polyurethane, polystyrene, cellulose polymer, polyolefin, polyamide, polyimide, polyester, polyphenylene, polyethylene, polyethylene terephthalate, polypropylene, ethylene-vinyl copolymer, and polyvinyl chloride. can.
  • the spinel-type ZnGa 2 O 4 layer 50 does not have to be formed using a CVD method with a high film formation temperature. Therefore, even when a resin material having a low heat resistance temperature is used as the substrate 10, the spinel-type ZnGa 2 O 4 layer 50 can be preferably formed.
  • the substrate 10 may have flexibility. If the substrate 10 is a flexible film substrate (sometimes referred to as a "sheet substrate"), a roll-to-roll method for continuously forming a film in a roll form, or a roll-to-roll method may be used. A two-sheet (Roll to Sheet) method can be adopted, and high efficiency, simplification, and yield improvement of the manufacturing process can be expected.
  • a flexible film substrate sometimes referred to as a "sheet substrate”
  • a roll-to-roll method for continuously forming a film in a roll form or a roll-to-roll method may be used.
  • a two-sheet (Roll to Sheet) method can be adopted, and high efficiency, simplification, and yield improvement of the manufacturing process can be expected.
  • the roll-to-roll method refers to a method in which a roll-shaped film substrate is unwound, film is continuously formed, and the film is wound up again into a roll.
  • the roll-to-sheet method refers to a method in which a roll-shaped film substrate is unwound to continuously form a film, which is then cut into a sheet.
  • the third electrode 20 is a gate electrode.
  • the third electrode 20 is not particularly limited, and a known electrode can be adopted. Specific examples include single layers of Mo, W, Al, Cu, Au, Cu--Al alloys, Al--Si alloys, Mo--W alloys, Ni--P alloys, and laminates thereof.
  • a method for manufacturing the third electrode 20, which is a gate electrode, is not particularly limited, and a suitable method can be appropriately adopted in consideration of the materials of the substrate 10 and the gate electrode.
  • the third electrode 20, which is the gate electrode, may be made of conductive silicon and may also serve as the substrate 10.
  • the insulating layer 30 is not particularly limited, and known materials can be adopted. Specific examples include inorganic materials such as SiO 2 , Si 3 N 4 , SiON, Al 2 O 3 , Ta 2 O 5 and HfO 2 , photocurable resins and thermosetting resins.
  • the semiconductor layer 60 is formed in contact with the first electrode 71 and the second electrode 72 .
  • the first electrode 71 and the second electrode 72 are arranged on the insulating layer 30, part of which is on the spinel-type ZnGa 2 O 4 layer 50 (first oxide layer). It's covered.
  • the semiconductor layer 60 includes a ZnGa 2 O 4 layer 50 (first oxide layer) and an IGZO layer 40 or IGZTO layer 41 (second oxide layer).
  • the IGZO layer 40 is an inorganic oxide semiconductor containing In, Ga, and Zn.
  • the IGZTO layer 41 is an oxide inorganic semiconductor containing In, Ga, Zn, and Sn.
  • the IGZO layer 40 or the IGZTO layer 41 may be doped with a carrier element from the viewpoint of further improving semiconductor characteristics.
  • the carrier element is not particularly limited, and one known in the doping process can be used. Specific examples include hydrogen, monovalent metals, divalent metals, and trivalent metals. Among these, in the present embodiment, the semiconductor layer 60 is more preferably doped with hydrogen.
  • the film thickness of the IGZO layer is 5-50 nm, preferably 10-40 nm, more preferably 10-30 nm.
  • the thickness of the IGZTO layer is 5-50 nm, preferably 10-40 nm, more preferably 10-30 nm.
  • the spinel-type ZnGa 2 O 4 forming the spinel-type ZnGa 2 O 4 layer 50 (first oxide layer) crystallizes at a relatively low temperature.
  • the spinel-type ZnGa 2 O 4 can be hydrogen-free. That is, the protective layer that is not doped with hydrogen or that does not substantially contain hydrogen can be preferably used.
  • the phrase "substantially does not contain” as used herein means that the component is not actively added, and does not exclude unavoidable inclusion or mixing.
  • the hydrogen content of the spinel-type ZnGa 2 O 4 layer 50 is preferably 1 ⁇ 10 21 atm/cc or less, more preferably 1 ⁇ 10 18 atm/cc or less. is more preferable.
  • This hydrogen content can be measured by secondary ion mass spectroscopy (SIMS).
  • the spinel-type ZnGa 2 O 4 layer 50 (first oxide layer) can also function as a passivation film.
  • the passivation film isolates the IGZO layer 40 or the IGZTO layer 41 (second oxide layer) from the environment, and protects the IGZO layer 40 or the IGZTO layer 41 (second oxide layer) from moisture, metal ions, and the like. can do.
  • the thickness of the spinel-type ZnGa 2 O 4 layer 50 is 5 to 20 nm, preferably 5 to 15 nm, more preferably 5 to 10 nm.
  • a conductive layer 70 is formed on the semiconductor layer 60, and a first electrode 71 and a second electrode 72 are formed by etching the conductive layer 70 in accordance with a predetermined pattern.
  • a first electrode 71 and a second electrode 72 are formed by a normal photolithography process.
  • the source electrode is not particularly limited, and a known electrode can be adopted. Specific examples include single layers of Mo, W, Al, Cu, Au, Cu--Al alloys, Al--Si alloys, Mo--W alloys, Ni--P alloys, and laminates thereof.
  • the drain electrode 72 is not particularly limited, and a known electrode can be adopted. Specific examples include single layers of Mo, W, Al, Cu, Au, Cu--Al alloys, Al--Si alloys, Mo--W alloys, Ni--P alloys, and laminates thereof.
  • the transistors are configured such that the first electrode 71, the second electrode 72, and the third electrode 20 are the source electrode, the drain electrode, and the gate electrode, respectively. good too.
  • the semiconductor device according to this embodiment is not limited to the configurations shown in FIGS. 1 and 2, and various configurations can be adopted.
  • the semiconductor devices A and B described so far are not only excellent in semiconductor properties such as electronic conductivity, but also have acid resistance and base resistance due to the spinel-type ZnGa 2 O 4 layer 50 (first oxide layer). It can also confer chemical resistance, such as durability.
  • the semiconductor device according to this embodiment can be suitably used for various sensors such as pH sensors and biosensors, as well as electronic devices such as TFT liquid crystal and organic EL. An example will be described below.
  • FIG. 3 is a schematic diagram of a pH sensor C including a semiconductor device according to this embodiment.
  • the pH sensor C is, for example, a pH sensor (Ion-Sensitive-FET; ion-sensitive field effect transistor) using the semiconductor device according to this embodiment.
  • the pH sensor C has the semiconductor device according to this embodiment, and a silicon rubber pool wall 80 and a reference electrode 90 provided on the semiconductor device. Then, the pool formed by the pool wall 80 is filled with a solution S to be measured (for example, hydrochloric acid in the case of an acidic solution, sodium hydroxide solution in the case of an alkaline solution, etc.), and the potential difference with the reference electrode 90 is measured. Measure. Since the pH of the solution S depends on the amount of protons in the solution, the measurement principle of the pH sensor is to electrically measure the amount of protons in the solution and calculate the pH value based on the measured amount of protons.
  • a solution S to be measured for example, hydrochloric acid in the case of an acidic solution, sodium hydroxide solution in the case of an alkaline solution, etc.
  • the semiconductor device according to this embodiment can impart high stability to strong acids and strong bases. Therefore, a pH sensor using this exhibits high stability in a wide pH range from pH 1 to 14, and is capable of rapid and accurate measurement even if the target sample is strong acid or strong base.
  • the semiconductor device according to this embodiment can also be used as a biosensor (also referred to as a biosensor chip).
  • a biosensor is a chemical sensor that utilizes a biogenic molecular recognition mechanism, and is used as a chemical recognition element for pH change, redox reaction, and the like in vivo.
  • the semiconductor device according to the present embodiment since the semiconductor device according to the present embodiment has high stability in a wide pH range, it can be used as a biosensor capable of accurate sensing even if the object to be measured is strongly acidic or strongly basic.
  • a semiconductor surface is modified with a specific antibody, and a biosensor that measures the amount of protons when a detection target such as DNA specific to this is adsorbed can be used.
  • FIG. 4 is a diagram showing an example of a method for manufacturing the semiconductor device A according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a method for manufacturing the semiconductor device B according to the second embodiment.
  • the manufacturing method shown in FIG. 4 is a manufacturing method of the semiconductor device A of the bottom-gate/top-contact type.
  • This manufacturing method includes a step of forming a semiconductor layer 60 including a spinel-type ZnGa 2 O 4 layer 50 (first oxide layer) and an IGZO layer 40 (second oxide layer) on a substrate 10. , a step of forming a conductive layer 70 on the substrate 10, and a step of etching the conductive layer 70 in accordance with a predetermined pattern to form a first electrode 71 and a second electrode 72. be.
  • the manufacturing method shown in FIG. 5 is a method for manufacturing a bottom-gate/top-contact semiconductor device B, which is the same as the manufacturing method shown in FIG. The process of
  • the third electrode 20 is formed on the surface of the substrate 10 .
  • the third electrode 20 corresponds to the gate electrode described above.
  • a method of forming the third electrode 20 on the surface of the substrate 10 is not particularly limited, and a suitable method can be appropriately adopted in consideration of the materials of the substrate 10 and electrodes.
  • an insulating layer 30 is formed on the surface of the substrate 10 on which the third electrode 20 is formed, and the third electrode 20 is covered with the insulating layer 30 .
  • a method for forming the insulating layer 30 is not particularly limited, and a suitable method can be appropriately adopted in consideration of the materials of the substrate 10, the third electrode 20, the insulating layer 30, and the like.
  • a semiconductor layer 60 is formed on the surface of the insulating layer 30 .
  • the semiconductor layer 60 is formed by covering the IGZO layer 40 with a spinel-type ZnGa 2 O 4 layer 50 .
  • the semiconductor layer 60 is formed by covering the IGZTO layer 41 with a spinel-type ZnGa 2 O 4 layer 50 .
  • the spinel-type ZnGa 2 O 4 layer 50 can protect the inside of the device from external moisture, metal ions, and the like.
  • the film formation temperature has been required to be 400° C. or higher.
  • the film formation temperature of the spinel-type ZnGa 2 O 4 layer 50 used as the protective layer is low and the film formation speed is high, so that the semiconductor device can be manufactured simply and efficiently. be able to.
  • the film formation temperature is preferably low.
  • the film forming temperature of the spinel-type ZnGa 2 O 4 layer 50 is 190 to 250°C, preferably 190 to 210°C.
  • All of the layers constituting the semiconductor layer 60 are preferably formed by a sputtering method.
  • it can be formed using a sputtering device, and a plurality of cathodes may be used.
  • a sputtering device For the sputtering, single simultaneous sputtering with one type of material as a target may be employed, or co-sputtering with a plurality of types of materials as targets may be employed.
  • the target used for forming the IGZO layer 40 or the IGZTO layer 41 is the same as the target used for the spinel-type ZnGa 2 O 4 layer 50, the sputtering target can be used in common. , it becomes possible to continuously form films in the same apparatus.
  • the IGZO layer 40 included in the semiconductor device A may be formed using an oxide sintered body of InGaZnO 4 as a target (simultaneous single sputtering). Also, three kinds of In 2 O 3 , Ga 2 O 3 , and ZnO may be used simultaneously in a multi-element manner to tilt the composition ratio and control the IGZO layer to have a desired composition (simultaneous multi-element sputtering, co-sputtering).
  • the film formation of the IGZTO layer 41 included in the semiconductor device B may be performed using KOS-B02 (manufactured by Kobelco Research Institute, Inc.) as a target (simultaneous sputtering).
  • KOS-B02 manufactured by Kobelco Research Institute, Inc.
  • the composition ratio may be graded to control the IGZTO layer having a desired composition (simultaneous use of multiple elements). sputter, co-sputter).
  • an n-type semiconductor material in the case of an n-type semiconductor material, it can be manufactured by element doping and oxygen deficiency in the film.
  • Elements from which an n-type semiconductor can be obtained are not particularly limited, but examples thereof include Al, In, Sn, Sb, and Ta.
  • the method for generating oxygen vacancies is not particularly limited, and known methods can be employed.
  • heat treatment is preferably performed in an oxygen-free atmosphere or in a reducing gas atmosphere such as hydrogen or water vapor.
  • a reducing gas atmosphere such as hydrogen or water vapor.
  • film formation is performed in a state in which hydrogen is mixed in a sputtering gas, and n-type carrier doping is performed using interstitial hydrogen. These treatments may be performed in a chamber after film formation, or may be baked as a post-process.
  • the spinel-type ZnGa 2 O 4 layer 50 can be deposited by co-sputtering using gallium zinc oxide and zinc oxide as targets.
  • a method of co-sputtering using gallium oxide and zinc oxide as targets, or a method of co-sputtering using gallium and zinc as targets and oxidizing with a reactive gas during film formation may be used.
  • a method of sputtering using a mixture of zinc oxide and gallium oxide as a target and oxidizing with a reaction gas during film formation may be used.
  • the semiconductor layer 60 develops strong resistance to strong acids and strong bases. Therefore, as a manufacturing process, a step of protecting the semiconductor layer and the like can be omitted.
  • the deposition temperature of the spinel-type ZnGa 2 O 4 layer 50 has a lower limit of 190° C. or higher, preferably 200° C. or higher, and an upper limit of 250° C. or lower, preferably 210° C. °C or less.
  • Excessive heating promotes evaporation of Zn particles that fly to the surface of the substrate 10, and may cause a deviation (composition deviation) from the stoichiometric ratio of Ga and Zn, but the sintered body containing Zn or ZnO By simultaneously discharging the target, the Zn concentration in the film can be increased, and composition deviation can be effectively prevented.
  • a step of forming a first electrode 71 and a second electrode 72 is performed by forming a conductive layer 70 on a semiconductor layer 60 and etching the conductive layer 70 in accordance with a predetermined pattern.
  • the first electrode 71 is the source electrode and the second electrode 72 is the drain electrode.
  • a normal photolithography process can be used as a method for forming the first and second electrodes.
  • a resist layer is formed on the conductive layer 70, and the resist layer is exposed to a predetermined pattern of light and developed.
  • the first electrode 71 and the second electrode 72 can be formed.
  • a positive material or a negative material may be used as the resist layer.
  • the etching solution is preferably an acidic solution. Since resist materials used in ordinary photolithography processes are often soluble in alkali, the conductive layer can be preferably etched without dissolving the resist layer by using an acidic solution.
  • semiconductor devices A and B can be obtained. It should be noted that the semiconductor device thus obtained may be subjected, if necessary, to other processes in order to obtain a desired device configuration. For example, a pretreatment process before forming each part, a surface polishing process after forming each part, a dicing process, a mounting process on a lead frame, an assembly process for packaging after circuit formation, a wire bonding process, A mold encapsulation step or the like can be employed as appropriate.
  • Example 1 A semiconductor device A having a semiconductor layer of ZnGa 2 O 4 (10 nm)/IGZO (15 nm)
  • a highly conductive n-type silicon substrate was prepared by forming a thermal oxide film (SiO 2 ) of 200 nm on a silicon wafer having an n-type specific resistance of 0.0017 ⁇ cm or less.
  • a 15 nm IGZO layer was formed on this substrate.
  • the IGZO layer was formed by RF sputtering using an IGZO sintered target with an atomic concentration of In:Ga:Zn of 2:2:1.
  • the substrate temperature during film formation was 105° C., and Ar was used as the sputtering gas.
  • oxygen was introduced as a reactive gas at a volume ratio of 10% with respect to Ar.
  • a 10-nm spinel-type ZnGa 2 O 4 layer was formed so as to cover the IGZO layer, thereby obtaining a ZnGa 2 O 4 /IGZO semiconductor layer.
  • the spinel-type ZnGa 2 O 4 layer was formed using a ZnGa 2 O 4 sintering target with the same sputtering apparatus as that used for forming the IGZO layer.
  • a suitable temperature at which ZnGa 2 O 4 crystallizes into a spinel type is 190° C. or higher.
  • the composition ratio of Zn and Ga was adjusted to 8:1 by controlling the target output, and the substrate was heated at 230° C. to form a ZnGa 2 O 4 layer with a spinel crystal structure.
  • Ar gas containing no hydrogen was used as the sputtering gas.
  • oxygen was introduced as a reactive gas at a volume ratio of 10% with respect to Ar. In this way, it was controlled so that there would be no hydrogen or oxygen deficiency.
  • the film was formed under the conditions of a back pressure of 1 ⁇ 10 ⁇ 4 Pa or less and a film forming pressure of 0.22 Pa.
  • a resist material was applied onto the obtained ZnGa 2 O 4 /IGZO semiconductor layer, and after patterning the resist material by a general photolithography process, an etchant (ITO-07: manufactured by Kanto Kagaku) was heated to 40°C. The semiconductor layer was patterned by etching at for about 120 seconds.
  • ITO-07 manufactured by Kanto Kagaku
  • an Al film (thickness: 100 nm) serving as source/drain electrodes was formed by a vacuum evaporation method so as to cover the semiconductor layer.
  • the vacuum deposition method at this time was performed using a resistance heating type vacuum deposition apparatus.
  • a resist material is applied on the Al film, and after patterning the resist material by a general photolithography process, the Al film is removed by immersing it in an etching solution (KSMF-100: manufactured by Kanto Kagaku) at 40° C. for about 40 seconds. Source/drain electrodes were formed by etching.
  • KSMF-100 manufactured by Kanto Kagaku
  • the semiconductor layer was annealed in an atmospheric environment at 105° C. for 3 hours (annealing furnace: constant temperature machine with safety door manufactured by Espec Co., Ltd.) to fabricate a semiconductor device A having the structure shown in FIG.
  • the transfer characteristics were measured using a semiconductor parameter analyzer (4300A-SCS manufactured by Keithley), and the film thickness was measured using P16+ manufactured by KLA-Tencor. The results are shown in FIG.
  • a highly conductive n-type silicon substrate was prepared by forming a thermal oxide film (SiO 2 ) of 200 nm on a silicon wafer having an n-type specific resistance of 0.0017 ⁇ cm or less.
  • a 10 nm IGZTO layer was formed on this substrate.
  • the IGZTO layer is formed by RF sputtering using an IGZTO target (KOS-B02: manufactured by Kobelco Research Institute, Inc.) and a ZnGa 2 O 4 sintered target with a Zn:Ga atomic concentration of 8:1. did.
  • the substrate temperature during film formation was 105° C., and Ar was used as the sputtering gas.
  • oxygen was introduced as a reactive gas at a volume ratio of 10% with respect to Ar.
  • a 10 nm spinel-type ZnGa 2 O 4 layer was formed so as to cover the above-described IGZTO layer to obtain a ZnGa 2 O 4 /IGZTO semiconductor layer.
  • the ZnGa 2 O 4 layer was formed by using a ZnGa 2 O 4 sintering target and the same sputtering apparatus as used for forming the IGZO layer.
  • the target output was controlled so that the composition ratio of Zn and Ga was 8:1, and the substrate was heated at 230° C. to form a ZnGa 2 O 4 layer with a spinel crystal structure.
  • Ar gas containing no hydrogen was used as the sputtering gas.
  • oxygen was introduced as a reactive gas at a volume ratio of 10% with respect to Ar. In this way, it was controlled so that there would be no hydrogen or oxygen deficiency. Then, the film was formed under the conditions of a back pressure of 1 ⁇ 10 ⁇ 4 Pa or less and a film forming pressure of 0.22 Pa.
  • the obtained resist material for the semiconductor layer of ZnGa 2 O 4 /IGZTO was applied, and after patterning the resist material by a general photolithography process, it was etched with an etchant (ITO-07: manufactured by Kanto Kagaku) heated to 40°C. The semiconductor layer was patterned by etching for about 3 minutes.
  • ITO-07 manufactured by Kanto Kagaku
  • Mo electrodes (thickness: 100 nm) serving as source/drain electrodes were formed by a vacuum evaporation method so as to cover the semiconductor layer.
  • the vacuum deposition method at this time was performed using a resistance heating type vacuum deposition apparatus.
  • a resist material is applied on the Mo film, and after patterning the resist material by a general photolithography process, it is etched by immersing it in an etching solution (KSMF-100: manufactured by Kanto Kagaku) heated to 40 ° C. for about 40 seconds. By doing so, source/drain electrodes were formed.
  • KSMF-100 manufactured by Kanto Kagaku
  • the semiconductor layer was annealed in an atmospheric environment at 120°C for 3 hours (annealing furnace: constant temperature machine with a safety door manufactured by Espec Co., Ltd.) to fabricate a semiconductor device B having the structure shown in FIG.
  • the transfer characteristics were measured using a semiconductor parameter analyzer (4300A-SCS manufactured by Keithley), and the film thickness was measured using P16+ manufactured by KLA-Tencor. The results are shown in FIG.
  • a semiconductor device including semiconductor layers with different film thicknesses was manufactured, and the transfer characteristics were evaluated. Comparative Examples 1-3 do not have a ZnGa 2 O 4 layer.
  • the semiconductor device was fabricated under the same conditions as in Example 2 except for the semiconductor layer formation conditions (film thickness, presence/absence of ZnGa 2 O 4 layer), etching conditions, and post-treatment.
  • the designed film thickness was controlled by the sputtering time.
  • the etching conditions were room temperature and immersion for 1 minute.
  • Post-treatment was performed at an annealing temperature of 120° C. or 150° C. for 3 hours.
  • the film thickness was measured using a KLA-Tencor P16+.
  • the transfer characteristics were measured using a semiconductor parameter analyzer (manufactured by Keithley: 4300A-SCS). The results are shown in FIGS. 7 to 10.
  • Example 3 Semiconductor layer: Spinel type ZnGa 2 O 4 (10 nm)/IGZTO (20 nm) Annealing temperature: 120°C Measurement results: Fig. 7
  • Example 4 Semiconductor layer: Spinel type ZnGa 2 O 4 (10 nm)/IGZTO (30 nm) Annealing temperature: 120°C Measurement results: Fig. 7
  • Example 5 Semiconductor layer: Spinel type ZnGa 2 O 4 (10 nm)/IGZTO (10 nm) Annealing temperature: 150°C Measurement results: Figure 8
  • Example 6 Semiconductor layer: Spinel type ZnGa 2 O 4 (10 nm)/IGZTO (20 nm) Annealing temperature: 150°C Measurement results: Figure 8

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7457311B1 (ja) 2023-09-11 2024-03-28 株式会社Pxp 太陽電池及び太陽電池の製造方法
WO2024221390A1 (zh) * 2023-04-28 2024-10-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板的制备方法
WO2025141646A1 (ja) * 2023-12-25 2025-07-03 株式会社ニコン 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、及び半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016519443A (ja) * 2013-05-24 2016-06-30 シーブライト・インコーポレイテッドＣｂｒｉｔｅ Ｉｎｃ． 安定した高移動度のｍｏｔｆｔおよび低温での製作
JP2016189461A (ja) * 2015-03-27 2016-11-04 株式会社半導体エネルギー研究所 半導体装置
WO2018025647A1 (ja) * 2016-08-03 2018-02-08 株式会社ニコン 半導体装置、ｐＨセンサ、バイオセンサ、及び半導体装置の製造方法
WO2020174540A1 (ja) * 2019-02-25 2020-09-03 株式会社ニコン 半導体装置、ｐＨセンサ及びバイオセンサ並びに半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5095864B2 (ja) 2009-12-09 2012-12-12 シャープ株式会社 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016519443A (ja) * 2013-05-24 2016-06-30 シーブライト・インコーポレイテッドＣｂｒｉｔｅ Ｉｎｃ． 安定した高移動度のｍｏｔｆｔおよび低温での製作
JP2016189461A (ja) * 2015-03-27 2016-11-04 株式会社半導体エネルギー研究所 半導体装置
WO2018025647A1 (ja) * 2016-08-03 2018-02-08 株式会社ニコン 半導体装置、ｐＨセンサ、バイオセンサ、及び半導体装置の製造方法
WO2020174540A1 (ja) * 2019-02-25 2020-09-03 株式会社ニコン 半導体装置、ｐＨセンサ及びバイオセンサ並びに半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024221390A1 (zh) * 2023-04-28 2024-10-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板的制备方法
JP7457311B1 (ja) 2023-09-11 2024-03-28 株式会社Pxp 太陽電池及び太陽電池の製造方法
WO2025141646A1 (ja) * 2023-12-25 2025-07-03 株式会社ニコン 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、及び半導体装置の製造方法

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