WO2022247135A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022247135A1
WO2022247135A1 PCT/CN2021/126858 CN2021126858W WO2022247135A1 WO 2022247135 A1 WO2022247135 A1 WO 2022247135A1 CN 2021126858 W CN2021126858 W CN 2021126858W WO 2022247135 A1 WO2022247135 A1 WO 2022247135A1
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Prior art keywords
level
node
clock signal
circuit
output
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PCT/CN2021/126858
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English (en)
French (fr)
Inventor
邵喜斌
廖燕平
陈东川
缪应蒙
姚树林
张银龙
苏秋杰
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/912,952 priority Critical patent/US20240212563A1/en
Priority to EP21942699.6A priority patent/EP4207151A4/en
Priority to JP2023524426A priority patent/JP2024522249A/ja
Publication of WO2022247135A1 publication Critical patent/WO2022247135A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • Embodiments of the disclosure relate to a display panel and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel usually includes multiple rows of gate scanning signal lines and multiple columns of data lines interleaved with the gate scanning signal lines.
  • the driving of the gate scanning signal line can be realized by a bound integrated driving circuit.
  • the gate scanning signal line driver circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to control the gate. Pole scanning signal line for driving.
  • a GOA comprising a plurality of cascaded shift register units may be used to provide switch state voltage signals (scanning signals) for multiple rows of gate scanning signal lines of the pixel array, thereby controlling multiple rows of gate scanning signal lines to be turned on sequentially, for example.
  • the data lines are used to provide data signals to the pixel units in the corresponding row in the pixel array, so as to form gray voltages required for each gray scale of the displayed image in each pixel unit, and then display a frame of image.
  • At least one embodiment of the present disclosure provides a display panel, including: a gate drive circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-serialization circuits; the timing controller is configured to provide a first clock signal; The plurality of anti-serialization circuits are connected to the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and adjust the timing controller to a second clock signal.
  • the second clock signal is output to the plurality of clock signal lines, wherein the falling time of the falling edge of the second clock signal is shorter than the falling time of the falling edge of the first clock signal;
  • the gate driving circuit includes A plurality of cascaded shift register units are respectively connected to the plurality of clock signal lines, and the gate drive circuit is configured to output the second clock signal as an output signal row by row, thereby shortening the Falling time of falling edge;
  • each of the plurality of anti-serialization circuits includes at least one resistor and at least one inductor.
  • the at least one resistor and the at least one inductor are connected in series or in parallel.
  • a first end of the at least one resistor is connected to the timing controller, and a second end of the at least one resistor is connected to the at least one inductor.
  • the total resistance of the equivalent resistance of the anti-serialization circuit is 1 ohm to 1000 ohms; the total inductance of the equivalent inductance of the anti-serialization circuit From 1 microhenry to 1000 microhenries.
  • the at least one resistor includes a first resistor and a second resistor
  • the at least one inductance includes a first inductance and a second inductance
  • the first resistor and the The first inductance is connected in parallel to form a first element
  • the second resistor and the second inductance are connected in parallel to form a second element; the first element and the second element are connected in series.
  • the total resistance of the equivalent resistance of the first element and the equivalent resistance of the second element is 1 ohm to 1000 ohm; or, the first The total inductance of the equivalent inductance of the first element and the equivalent inductance of the second element is 1 microhenry to 1000 microhenry.
  • the first clock signal includes a first level and a second level arranged sequentially in the time domain, and the second clock signal is included in the The third level and the fourth level arranged in sequence in the time domain; the first level is higher than the second level, and the third level is higher than the fourth level; the first The four levels include a first sub-level and a second sub-level; in the time domain, the second sub-level is located between the third level and the first sub-level, and the second The sublevel is lower than the first sublevel.
  • the first level is equal to the third level
  • the first sub-level is equal to the second level
  • the third level includes a third sub-level and a fourth sub-level, and in the time domain, the fourth sub-level is located at the Between the third sub-level and the second sub-level, the third sub-level is higher than the fourth sub-level.
  • the fourth sub-level is equal to the first level.
  • the first clock signal includes a first level and a second level arranged sequentially in the time domain, and the second clock signal includes The third level and the fourth level arranged in sequence, the first level is higher than the second level, the third level is higher than the fourth level; the second level level above the fourth level.
  • the third level is higher than the first level.
  • the display panel provided by at least one embodiment of the present disclosure further includes a level conversion circuit configured to convert the first clock signal into the second clock signal.
  • the shift register unit includes an input circuit, an output circuit and a first node control circuit; the input circuit is connected to the first node and is configured to respond to an input The signal charges the first node; the output circuit is connected to the first node, and is configured to output an output signal at the output terminal under the control of the level signal of the first node; the second A node control circuit is respectively connected to the second node and the third node, and configured to control the levels of the second node and the third node in response to the input signal.
  • the shift register unit further includes: a total reset circuit, the total reset circuit is connected to the first node and the total reset terminal, and is configured to receiving the general reset signal from the general reset terminal and controlling the level of the first node in response to the general reset signal.
  • the shift register unit further includes a first node reset circuit connected to the first node and configured to respond to a reset signal Reset the first node.
  • the shift register unit further includes a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit;
  • the first node and the second node are connected to the third node, and are configured to control the electrical level of the second node and the third node under the control of the level signal of the first node.
  • the first node noise reduction circuit is connected to the first node and the second node and the third node, and is configured to be at the level of the second node and the third node Under the control of the signal, noise reduction is performed on the first node;
  • the output noise reduction circuit is connected to the second node, the third node and the output terminal, and is configured to be connected between the second node and the Under the control of the level signal of the third node, noise reduction is performed on the output terminal.
  • the output terminal includes a shift output terminal and at least one scan signal output terminal.
  • the at least one scan signal output terminal includes a scan signal output terminal
  • the output circuit includes a second transistor, a third transistor and a storage capacitor; the second The gate of the transistor is connected to the first node, the first pole of the second transistor is connected to the clock signal terminal to receive the second clock signal, the second pole of the second transistor is connected to the shift output terminal connection; the gate of the third transistor is connected to the first node, the first pole of the third transistor is connected to the clock signal terminal to receive the second clock signal, and the third transistor The second pole is connected to the scan signal output end; the first pole of the storage capacitor is connected to the first node, and the second pole of the second capacitor is connected to the scan signal output end; the second A clock signal is transmitted to the output as the output signal.
  • the display panel provided by at least one embodiment of the present disclosure further includes a display area, a peripheral area surrounding the display area, and a circuit board;
  • the display area includes a plurality of pixels arranged in an array, configured to receive the gate drive The output signal of the circuit for display;
  • the gate drive circuit and the plurality of clock signal lines are located in the peripheral area, and the peripheral area includes a corner portion, and the corner portion includes a part of the gate drive circuit
  • the shift register unit and the multiple clock signal lines; the timing controller and the anti-crosstalk circuit are located on the circuit board.
  • At least one embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure.
  • FIG. 1A is a schematic diagram of a pixel charging sequence
  • Fig. 1B is a schematic diagram of the display screen of H-1Line in an ideal state
  • Fig. 1C is a schematic diagram of the display screen sequence of H-1Line in the actual state
  • FIG. 2 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of a first clock signal and a second clock signal provided by at least one embodiment of the present disclosure
  • 4B is a schematic diagram of an output signal output by a gate drive circuit before and after adding an anti-serialization circuit provided by at least one embodiment of the present disclosure
  • FIG. 4C is a schematic diagram of a parasitic capacitance of a clock signal line provided by at least one embodiment of the present disclosure
  • FIG. 4D is a schematic diagram of a circuit load model provided by at least one embodiment of the present disclosure.
  • FIG. 4E is a schematic plan view of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of another display panel provided by at least one embodiment of the present disclosure.
  • Fig. 6 is a schematic waveform diagram of a first clock signal and a second clock signal provided by at least one embodiment of the present disclosure
  • Fig. 7 is a schematic waveform diagram of a second clock signal and an output signal provided by at least one embodiment of the present disclosure
  • FIG. 8 is an enlarged schematic diagram of an output signal provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of another second clock signal provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a shift register unit provided by an embodiment of the present disclosure.
  • Fig. 11 is a circuit diagram of a specific implementation example of the shift register unit shown in Fig. 10;
  • FIG. 12 is a driving timing diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 13 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the resolution and refresh rate of the display screen can reach 8K and 120Hz (Hertz), 4K and 240Hz, etc.
  • These products all have one thing in common: the 1H time (1H time means, for example, the time for turning on or charging one row of pixels in a liquid crystal display panel) is short. Table 1 shows the corresponding 1H time for different display products. The shorter the 1H time, the more difficult it is to charge the pixels in this row.
  • FIG. 1A is a schematic diagram of a pixel charging sequence.
  • the gate scan signal when the gate scan signal is at a high level, the data signal D1 corresponding to the pixels in the first row is written into the pixels in the first row (that is, the pixels in the first row are charged), and the gate scan signal D1 Charging can only be ended when it is at a low level, but because the falling time Tf of the falling edge of the gate scanning signal is relatively large, the gate scanning signal has not completely changed to a low level, and the data signal D2 corresponding to the second row of pixels has been output. Therefore, a serial time t is generated.
  • the part of the data signal D2 corresponding to the pixels in the second row will be written into the pixels in the first row, distorting the data written in the pixels in the first row, that is, not only the data signal D1 that needs to be displayed, It also includes the data signal D2 corresponding to the pixels in the second row.
  • the longer the serial time t the more severe the distortion.
  • the grid line load (resistance and capacitance) must be reduced.
  • the gate lines of display products with a resolution of 8K are all copper lines, and the process has reached the maximum copper thickness that can be achieved by the process. Therefore, the optimization range is limited to reduce the load of the gate line by process, and other solutions must be found.
  • At least one embodiment of the present disclosure provides a display panel, including: a gate drive circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-serial circuits; the timing controller is configured to provide a first clock signal; a plurality of anti-serial circuits The serial circuit is connected to the timing controller and a plurality of clock signal lines, and is configured to adjust the first clock signal provided by the timing controller into a second clock signal, and output the second clock signal to the plurality of clock signal lines, and the second The falling time of the falling edge of the clock signal is less than the falling time of the falling edge of the first clock signal; the gate drive circuit includes a plurality of cascaded shift register units, respectively connected to a plurality of clock signal lines, and the gate drive circuit is configured as The second clock signal is output row by row as the output signal, thereby shortening the falling time of the falling edge of the output signal; each of the plurality of anti-serialization circuits includes at least one resistor and at least one inductor
  • an inductive load can be formed by connecting an inductor in series between the timing controller and the gate drive circuit to offset the capacitive load on the clock signal line, so that there is only a resistive load on the clock signal line, avoiding The parasitic capacitance on the clock signal line prolongs the falling time of the falling edge of the clock signal, so that serial display can be avoided; in addition, a resistor is connected in series between the timing controller and the gate drive circuit, which can reduce the frequency of the clock signal line. The current reduces the heating of the clock signal line and improves the performance of the display panel.
  • Fig. 2 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel may be a display panel with a resolution of 8K and a refresh rate of 120 Hz, and of course it may also be a display panel with other resolutions or refresh rates, which are not limited by the embodiments of the present disclosure.
  • the display panel 1 includes a gate driving circuit 10 .
  • the display panel 1 further includes a display area 40 .
  • the display area 40 includes a pixel array connected to the gate driving circuit 10 .
  • the pixel array includes multiple rows and columns of sub-pixels 410 .
  • the display panel 1 may further include a data driving circuit 30 and a plurality of data lines DL.
  • the multiple data lines D are electrically connected to the multiple columns of sub-pixels 410 and are configured to transmit the data signals provided by the data driving circuit 30 to the multiple columns of sub-pixels 410 .
  • the data driving circuit 30 is used to provide data signals to the pixel array; the gate driving circuit 10 is used to provide gate scanning signals to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel 410 through the data line DL, and the gate driving circuit 10 is electrically connected to the sub-pixel 410 through the gate scanning signal line GL.
  • the gate driving circuit is used to drive display panels such as liquid crystal display panels and organic light-emitting diode display panels, and sequentially provide gate scanning signals for multiple gate scanning signal lines of the display panel, thereby displaying a frame on the display panel. Progressive or interlaced scanning is performed during the period of the screen.
  • FIG. 3 is a schematic diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 3 on the basis of the example shown in FIG. An anti-serial circuit.
  • the display area 40 and the data driving circuit 30 are not shown in FIG. 3 .
  • m can be equal to 2, 4, 6, 12, 16, etc., that is, the multiple clock signal lines can include 2, 4, 6, 12, 16, etc., that is, the number of clock signal lines is an integer multiple of 2, and this
  • the distance between the multiple clock signal lines may be between 4 microns and 100 microns, such as 4-20 microns, which is not limited in the embodiments of the present disclosure.
  • the timing controller 300 is configured to provide a first clock signal.
  • a plurality of anti-serialization circuits 400 are connected to the timing controller 300 and a plurality of clock signal lines CLK1 to CLKm, and are configured to adjust the first clock signal provided by the timing controller 300 into a second clock signal, and convert the second The clock signal is output to a plurality of clock signal lines CLK1 to CLKm.
  • multiple anti-serialization circuits 400 are connected to multiple clock signal lines CLK1 in a one-to-one correspondence, that is, one clock signal line is connected to one anti-serialization circuit 400 , which is not limited in embodiments of the present disclosure.
  • the anti-crosstalk circuit 400 can also be arranged between the timing controller 300 and other power lines, for example, to provide the first voltage to the first voltage terminal to the fourth voltage terminal shown in FIG. 10 The power supply line to the fourth voltage to reduce the peak current, etc., which is not limited by the embodiments of the present disclosure.
  • the gate drive circuit 10 includes a plurality of cascaded shift register units GOA, respectively connected to a plurality of clock signal lines CLK1 to CLKm, and the gate drive circuit 10 is configured to use the second clock signal as The output signal is output row by row, thereby shortening the falling time of the falling edge of the output signal.
  • the multiple clock signal lines include the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line Clock signal line CLK5, sixth clock signal line CLK6, seventh clock signal line CLK7, eighth clock signal line CLK8, ninth clock signal line CLK9, tenth clock signal line CLK10, eleventh clock signal line CLK11, tenth clock signal line Two clock signal lines CLK12.
  • the first clock signal line CLK1 is connected to the clock signal end of the 12n-11th stage shift register; the second clock signal line CLK2 is connected to the clock signal end of the 12n-10th stage shift register;
  • the third clock signal line CLK3 is connected to the clock signal end of the 12n-9 stage shift register;
  • the fourth clock signal line CLK4 is connected to the clock signal end of the 12n-8 stage shift register;
  • the fifth clock signal line CLK5 is connected to the 1st stage shift register
  • the clock signal end of the 12n-7 stage shift register is connected;
  • the sixth clock signal line CLK6 is connected to the clock signal end of the 12n-6 stage shift register;
  • the seventh clock signal line CLK7 is connected to the 12n-5 stage shift register
  • the clock signal end is connected;
  • the eighth clock signal line CLK8 is connected to the clock signal end of the 12n-4 stage shift register;
  • the ninth clock signal line CLK9 is connected to the clock signal end of the 12n-3 stage shift register;
  • FIG. 4A is a schematic diagram of a first clock signal and a second clock signal provided by at least one embodiment of the present disclosure
  • FIG. 4B is a gate drive circuit output before and after adding an anti-serialization circuit 400 provided by at least one embodiment of the present disclosure.
  • a schematic diagram of the output signal For example, as shown in FIG. 4A , the upper and lower waveform diagrams are respectively a comparison diagram of the first clock signal and the second clock signal at the near end of the timing controller 300 and the first clock signal at the far end of the timing controller 300 and the comparison diagram of the second clock signal.
  • the falling time t1 of the falling edge of the second clock signal (the waveform shown by the solid line in FIG. 4A ) is shorter than the falling edge of the first clock signal (the waveform shown by the dotted line in FIG. 4A ).
  • the solid line is the second clock signal output by the gate driving circuit as the output signal
  • the dotted line is the first clock signal output by the gate driving circuit as the output signal.
  • FIG. 4C is a schematic diagram of a parasitic capacitance of a clock signal line provided by at least one embodiment of the present disclosure.
  • the capacitive load of the clock signal line CLK1 comes from the parasitic capacitance C11 generated at the overlap of the transfer electrode E1 of the clock signal line CLK1 and the clock signal line CLK2-CLKm connected to different shift register units And the parasitic capacitance C21 generated at the intersection of the gate of the output transistor of the shift register unit (the third transistor T3 shown in FIG. 12 below) and the transfer electrode E1 overlaps.
  • the capacitive load (for example, parasitic capacitances C11 and C21) of the clock signal line can be offset by introducing an inductive load on the clock signal line in series, so that the impedance of the clock signal is reduced, thereby The falling time of the falling edge of the clock signal is reduced, thereby reducing the falling time of the falling edge of the output signal, so that the serial phenomenon can be avoided.
  • each of the plurality of anti-serialization circuits 400 includes at least one resistor and at least one inductor.
  • at least one resistor and at least one inductor are connected in series or in parallel.
  • the total resistance of the equivalent resistance of each anti-serialization circuit 400 is 1 ohm ( ⁇ ) to 1000 ohms; the total inductance of the equivalent inductance of each anti-serialization circuit is 1 microhenry to 1000 microhenry.
  • the total resistance of each equivalent resistance of the anti-serialization circuit 400 is 150 ⁇ , and the total inductance of each equivalent inductance is 100 microhenries.
  • other values can also be used. For details, refer to It depends on the actual situation, which is not limited by the embodiments of the present disclosure.
  • a first end of at least one resistor is connected to the timing controller 300 , and a second end of at least one resistor is connected to at least one inductor.
  • the anti-serialization circuit 400 connected to the clock signal line CLK1 includes a resistor R1 and an inductor L1 .
  • the anti-serial circuit 400 connected to the clock signal line CLK2 includes a resistor R2 and an inductor L2;
  • the anti-serial circuit 400 connected to the clock signal line CLK3 includes a resistor R3 and an inductor L3;
  • the serial circuit 400 includes a resistor Rm-1 and an inductor Lm-1;
  • the anti-serialization circuit 400 connected to the clock signal line CLKm includes a resistor Rm and an inductor Lm.
  • the first ends of the resistors R1-Rm are connected to the timing controller 300, the second ends of the resistors R1-Rm are respectively connected to the first ends of the inductors L1-Lm, and the second ends of the inductors L1-Lm are respectively connected to multiple clocks
  • the signal lines CLK1-CLKm are connected in one-to-one correspondence.
  • the resistance values of the above-mentioned resistors can be equal, for example, the resistance value of the resistor R1 is equal to the resistance value of the resistor R2, the resistance value of the resistor R3 is equal to the resistance value of the resistor Rm-1, and the resistance value of the resistor Rm is equal, for example, equal to 150 ⁇ ,
  • the resistance values of the above-mentioned resistors can be unequal, for example, can be determined according to the distance between the timing controller 300 and the clock signal line, the greater the distance between the timing controller 300 and the clock signal line, the smaller the resistance value, for example , the resistance value of the resistor R1 is smaller than the resistance value of the resistor R2 and smaller than the value of the resistor Rm, which may depend on the actual situation, which is not limited in the embodiments of the present disclosure.
  • the inductances of the above-mentioned inductors can be equal, for example, the inductance of the inductor L1 is equal to the inductance of the inductor L2, the inductance of the inductor L3 is equal to the inductance of the inductor L3m-1, and the inductance of the inductor Lm is equal, for example, equal to 100 microns Heng, of course, the inductance of each of the above-mentioned inductors may also be unequal, for example, it may be determined according to the distance between the timing controller 300 and the clock signal line, the greater the distance between the timing controller 300 and the clock signal line, the greater the inductance.
  • the inductance of the inductor L1 is smaller than the inductance of the inductor L2 and smaller than the inductance of the inductor Lm, which depends on the actual situation, which is not limited in the embodiments of the present disclosure.
  • FIG. 3 only shows the situation that at least one resistor includes one resistor, at least one inductor includes one inductor, and the resistor and inductor are connected in series, but the embodiments of the present disclosure This is not limited, and more resistors and inductors may also be included.
  • FIG. 4E is a schematic plan view of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel has a display area 11 and a peripheral area 12 surrounding the display area 11 .
  • the peripheral region 12 includes corner portions 13 .
  • the display area 11 includes a plurality of pixels arranged in an array for receiving the output signal of the gate driving circuit as a gate scanning signal for display.
  • the peripheral area 12 has structures such as a gate drive circuit 10 for driving a plurality of sub-pixels in the display area 11 to display, a plurality of clock signal lines, and the like.
  • the display panel also includes a circuit board 600, and for example, a timing controller 300 and an anti-crosstalk circuit 400 can be arranged on the circuit board 600.
  • a timing controller 300 and an anti-crosstalk circuit 400 can be arranged on the circuit board 600.
  • a resistor R1 is connected in series on the clock signal line between the timing controller 300 and the inductor L1 to reduce the temperature of the corners of the display panel and prevent the display panel from becoming overheated and causing blackening and fire hazards.
  • the drive capability of the shift register unit GOA is strong, and the current of the clock signal line is large.
  • the corner temperature of the display panel with a resolution of 8K and a refresh rate of 120Hz can reach above 70°C.
  • the corner part can be lowered to 50°C. Therefore, series resistors on the clock signal line can reduce the temperature of the corner part of the display panel, improve user experience, and prolong the service life of the display panel.
  • the resistors and inductors connected in series shown in FIG. 3 are examples with the fewest components.
  • an inductor is incorporated next to a resistor, and a resistor is incorporated next to an inductor, all of which belong to the protection scope of the present disclosure. Embodiments of the present disclosure do not limit this.
  • FIG. 5 is a schematic diagram of another display panel provided by at least one embodiment of the present disclosure.
  • at least one resistor includes a first resistor R1 and a second resistor R1'
  • at least one inductor includes a first inductor L1' and a second inductor L1
  • the first resistor R1 and a first resistor The inductor L1 ′ is connected in parallel to form the first element 410
  • the second resistor R1 ′ and the second inductor L1 are connected in parallel to form the second element 420 .
  • the first element 410 and the second element 420 are connected in series.
  • the first element 410 and the second element 420 can be equivalent to an inductance, and the total inductance of the equivalent inductance of the first element 410 and the equivalent inductance of the second element 420 is 1 microhenry to 1000 microhenries. Henry; or, in some other examples, when the first element and the second element are equivalently resistors, the total resistance of the equivalent resistance of the first element and the equivalent resistance of the second element is 1 ohm to 1000 ohm.
  • the first element 410 or the second element 420 may include a plurality of resistors connected in series or in parallel.
  • the resistance value of the resistor is 1 ohm to 1000 ohms; when it includes 2 resistors connected in parallel, the resistance value of each resistor can be 2000 ohms, so that parallel
  • the final resistance value is 1000 ohms, as long as the equivalent resistance of the first element 410 or the equivalent resistance of the second element 420 (that is, the total resistance of the equivalent resistance of the anti-crosstalk circuit 400) is 1 ohm to 1000 ohms is enough, which is not limited in the embodiment of the present disclosure.
  • the first element 410 or the second element 420 may include a plurality of inductors connected in series or in parallel.
  • the inductance of the inductor is 1 microhenry to 1000 microhenry; when it includes multiple inductors connected in series or in parallel, the resistance value of each inductor can To adjust, as long as the total inductance of the equivalent inductance of the first element 410 or the equivalent inductance of the second element 420 (that is, the total inductance of the equivalent inductance of the anti-crosstalk circuit 400) is 1 microhenry to 1000 microhenry That is, the embodiment of the present disclosure does not limit it.
  • FIG. 4D is a schematic diagram of a circuit load model provided by at least one embodiment of the present disclosure.
  • the load can be abstracted as an RLC network, and the network impedance is:
  • the real part R is the resistance
  • the imaginary part is the reactance
  • f is the signal frequency
  • j is the imaginary unit.
  • the modulus of impedance magnitude Z is the modulus of impedance magnitude Z. It can be seen from this formula that when C in the circuit is constant, increasing the inductance L can reduce the circuit impedance Z, when When , the circuit impedance is minimum, which is the resistance value R. After that, increase the inductance again, and the impedance starts to increase again.
  • the display panel of the above-mentioned embodiments of the present disclosure can form an inductive load by connecting an inductor in series between the timing controller and the gate drive circuit, and offset the capacitive load on the clock signal line, so that there is only a resistive load on the clock signal line. Avoid the parasitic capacitance on the clock signal line from prolonging the falling time of the falling edge of the clock signal; in addition, connecting a resistor in series between the timing controller and the gate drive circuit can reduce the current on the clock signal line and reduce the clock signal Line heat, improve the performance of the display panel.
  • FIG. 6 is a schematic waveform diagram of a first clock signal and a second clock signal provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic waveform diagram of a second clock signal and an output signal provided by at least one embodiment of the present disclosure
  • Fig. 8 is an enlarged schematic diagram of an output signal provided by at least one embodiment of the present disclosure.
  • the waveform of the output signal output from the output terminal depends on the input waveform of the gate driving circuit, that is, depends on the waveform of the second clock signal provided by the clock signal line.
  • the waveform of the second clock signal provided by the clock signal line includes multi-level levels, so that the waveform of the output signal output from the output terminal of the gate drive circuit also includes multi-level levels.
  • the multi-level Level levels refer to a low level including multiple low levels or a high level including multiple high levels, which is not limited in embodiments of the present disclosure.
  • the second clock signal with multi-level levels can optimize the problem of long falling time of the falling edge of the output signal, for example, according to 10% (VGH-VGL1) to 90% (VGH-VGL1) of the falling edge of the output signal Part of it is used to determine the falling time of the falling edge.
  • VGH is the first level shown in FIG. 6
  • VGL1 is the first voltage provided by the first voltage terminal shown in FIG. 10 . Since the low level output by the output terminal of the shift register unit is when the output noise reduction circuit 180 shown in FIG. 10 is turned on, the first voltage provided by the first voltage terminal VGL1 is output to the output terminal. Therefore, the The value of the undershoot height is VGH-VGL1.
  • the first clock signal includes the first level VGH and the second level LVGL arranged in sequence in the time domain
  • the second clock signal includes the first level VGH and the second level LVGL arranged in sequence in the time domain.
  • Three-level VGH3 and fourth level the first level VGH is higher than the second level LVGL
  • the third level VGH3 is higher than the fourth level
  • the fourth level includes the first sub-level LVGL1 and the second sub-level level LVGL2
  • the second sub-level LVGL2 is located between the third level VGH3 and the first sub-level LVGL1.
  • the second sub-level LVGL2 is lower than the first sub-level LVGL1, so that the falling edge of the second clock signal can form an undershoot from the third level VGH3 to the second sub-level LVGL2, Thus, the falling time of the falling edge can be shortened.
  • the value range may be -4V to -20V, depending on the actual situation, which is not limited in the embodiments of the present disclosure.
  • the first sub-level LVG1 may be equal to the first voltage provided by the first voltage terminal VGL1 shown in FIG.
  • the voltage is, for example, -8V, which may depend on actual conditions, which is not limited in the embodiments of the present disclosure.
  • the first level VGH and the third level VGH3 are at a high level, and the second level LVGL and the fourth level are at a low level. Let me repeat.
  • the first level VGH and the third level VGH3 are equal or approximately equal, and the first sub-level LVGL1 and the second level LVGL are equal or approximately equal, which is not limited by embodiments of the present disclosure. .
  • the gate drive circuit since the gate drive circuit outputs the second clock signal as the output signal, the falling edge of the output signal also forms an undershoot from the third level VGH3 to the second sub-level LVGL2, thus The falling time of the falling edge of the output signal can be shortened, and the falling time of the falling edge of the output signal can be shortened from the first time (that is, the falling time is the distance between A1 to A3 in the horizontal direction) to the second time (that is, the falling time is the distance between A1 and A2 in the horizontal direction).
  • Fig. 9 is a schematic diagram of another second clock signal provided by at least one embodiment of the present disclosure.
  • the third level VGH3 includes a third sub-level VGH5 and a fourth sub-level VGH4, and in the time domain, the fourth sub-level VGH4 is located in the third sub-level Between the level VGH5 and the second sub-level LVGL2 , that is, in the time domain, the third sub-level VGH5 is prior to the fourth sub-level VGH4 , and the second sub-level LVGL2 is prior to the first sub-level LVGL1 .
  • the third sub-level VGH5 is higher than the fourth sub-level VGH4, so that when the third sub-level VGH5 of the second clock signal is output, the gate of the third transistor T3 can be increased according to the charge conservation law of the capacitor. (that is, the voltage of the N1 node shown in FIG. 12 ), so that the third transistor T3 is turned on more thoroughly.
  • the charge conservation law of the capacitor that is, the voltage of the N1 node shown in FIG. 12
  • the fourth sub-level VGH4 is equal or approximately equal to the first level VGH, that is, the fourth sub-level VGH4 is equal or approximately equal to the third level VGH3, which is not made in the embodiments of the present disclosure. limit.
  • the width of the second sub-level LVGL2 and the third sub-level VGH5 can be 0.5H-m/2H, or 0.5H-2H, 1H is the charging time of one row of pixels .
  • the width of the second sub-level LVGL2 and the third sub-level VGH5 can be less than or equal to 6H, that is, the time for charging 6 sub-pixels in a row, and the specific width range It depends on the actual situation, which is not limited in the embodiments of the present disclosure.
  • the waveform of the second clock signal may not use multi-level levels, and directly form the undershoot of VGH5-LVGL2 on the falling edge.
  • the first clock signal includes a first level and a second level arranged in sequence in the time domain
  • the second clock signal includes a third level and a fourth level arranged in sequence in the time domain. level, the first level is higher than the second level, the third level is higher than the fourth level; the second level is higher than the fourth level.
  • the third level is higher than the first level.
  • the first level is VGH shown in Figure 6
  • the second level is LVGL shown in Figure 6
  • the third level is VGH5 shown in Figure 9
  • the fourth level is The LVGL2 shown in 9 has a width of m/2H.
  • the value range of the voltage and the fourth voltage provided by the fourth voltage terminal VGH2 shown in FIG. 10 can be 25V-40V.
  • the sub-level VGH5 is 36V
  • the fourth sub-level VGH4 is 32V.
  • the third level VGH3 is 32V, which may depend on the actual situation. Embodiments of the present disclosure do not limit this .
  • the display panel further includes a level conversion circuit (not shown in the figure), configured to convert a logic level signal into a first clock signal or configured to convert the first clock signal into the first clock signal shown in FIG. 6 .
  • a level conversion circuit (not shown in the figure), configured to convert a logic level signal into a first clock signal or configured to convert the first clock signal into the first clock signal shown in FIG. 6 .
  • the above-mentioned second clock signal with multi-level signals shown in FIG. 9 shown in FIG. 9 .
  • the level conversion circuit can convert the logic level into a first clock signal with multi-level signals, and then output the first clock signal to the anti-crosstalk circuit 400, and the anti-crosstalk circuit outputs a multi-level clock signal
  • the second clock signal is connected to multiple clock signal lines; in some other examples, the level conversion circuit can convert the first clock signal into the above-mentioned second clock signal with multi-level signals shown in FIG. 6 or FIG.
  • the second clock signal can be set to a multi-level level through the level conversion circuit, and then the second clock signal set to the multi-level level Output to a plurality of clock signal lines, which is not limited in the embodiments of the present disclosure.
  • the clock signal adopts a multi-level design of high and low or high and low, which can make the second clock signal form an undershoot to reduce the delay of the falling time of the falling edge, thereby shortening the falling of the falling edge of the output signal Therefore, the driving capability of the gate drive circuit can be enhanced to a certain extent, and can be used for driving all products, such as display products with a resolution of 4K, display products with a resolution of 8K, COF (Chip On Flex or Chip On Film, Chip-on-chip film) products, etc.
  • display products with a resolution of 4K display products with a resolution of 8K
  • COF Chip On Flex or Chip On Film, Chip-on-chip film
  • only the multi-stage level setting of the clock signal can be used, and the driving capability of the shift register unit can be enhanced to a certain extent.
  • only resistors can be connected in series between the timing controller 300 and multiple signal lines, which can effectively reduce the current of the clock signal line and greatly reduce the temperature at the corner of the display panel, which is applicable to clock signal lines A product with a small quantity but a sufficient charging rate.
  • only an inductance can be connected in series between the timing controller 300 and multiple signal lines, and the inductance value is, for example, between 10 microhenry and 500 microhenry, so that the delay of the clock signal line can be greatly optimized.
  • the inductance value is, for example, between 10 microhenry and 500 microhenry, so that the delay of the clock signal line can be greatly optimized.
  • the shift register unit can adopt a circuit structure in the field, for example, 4T1C, 10T4C, 21T1C, etc. can be used, and the embodiment of the present disclosure does not limit this, and the specific driving process can refer to the conventional introduction in the field, which is not described here. Let me repeat.
  • FIG. 10 is a schematic diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit 500 includes an input circuit 110 , an output circuit 120 , a first node N1 and a first node control circuit 130 .
  • a gate drive circuit can be obtained by cascading a plurality of shift register units 500, and the gate drive circuit is used to drive a display panel, and sequentially provide scanning signals for multiple gate lines of the display panel, thereby displaying a frame on the display panel Progressive or interlaced scanning is performed during the period of the screen.
  • the input circuit 110 is connected to the first node N1 (for example, a pull-up node here), and is configured to charge the first node N1 in response to an input signal.
  • the input circuit 110 is connected to the input signal terminal INT and the first node N1, configured to conduct under the control of the input signal provided by the input signal terminal INT, so that the input signal terminal INT is connected to the first node N1 , so that the input signal provided by the input signal terminal INT is input to the first node N1, and the potential of the first node N1 is charged (for example, pulled up) to the working potential.
  • the output circuit 120 includes an output terminal OUT, connected to the first node N1, and configured to output an output signal at the output terminal OUT under the control of the level signal of the first node N1.
  • the output circuit 120 is connected to the clock signal terminal CLK, the first node N1 and the output terminal OUT, and is configured to be turned on under the control of the level signal of the first node N1 to provide the clock signal terminal CLK
  • the second clock signal is transmitted to the output terminal OUT, and output at the output terminal OUT as an output signal.
  • the output circuit 120 is also connected to a voltage terminal, and uses the second clock signal provided by the clock signal terminal CLK as a control signal to control whether to connect the voltage terminal to the output terminal OUT, thereby controlling whether to connect the voltage terminal to the output terminal OUT.
  • the voltage signal at the voltage terminal is transmitted to the output terminal OUT and output at the output terminal OUT as an output signal.
  • the clock signal terminal CLK is connected to one of the clock signal lines CLK1-CLKm to receive the second clock signal, so as to output the second clock signal as an output signal to the output terminal OUT.
  • the output terminal OUT may include a plurality of output terminals, such as a shift output terminal and at least one scan signal output terminal, so that an output signal such as the second clock signal provided by the clock signal terminal CLK is output to the shift output terminal and the scan signal output terminal to improve the driving capability of the shift register unit 500 .
  • at least one scan signal output terminal includes one scan signal output terminal.
  • the shift output terminal is used to provide input signals and reset signals for the shift register unit 500 of the next stage, and the scan signal output terminal is used to provide driving signals for the pixel circuits of a row of pixel units in the display panel.
  • each scan signal output terminal may also output different output signals. limit.
  • the first node control circuit 130 is connected to the second node N2 and the third node N3 respectively, and is configured to control the levels of the second node N2 and the third node N3 in response to an input signal.
  • the first node control circuit 130 can be configured to communicate with the second node N2, the third node N3, the second voltage terminal VGL2 (for example, providing a low level) or an additional voltage terminal (for example, a low voltage terminal) and
  • the input terminal INT is connected, so that under the control of the input signal input at the input terminal INT, the second node N2 and the third node N3 are electrically connected to the second voltage terminal VGL2 or the low voltage terminal to ensure that the first node is pulled up.
  • the levels of the second node N2 and the third node N3 are pulled down to the second voltage.
  • the "effective output level" of the shift register unit refers to the ability to enable the switching transistor in the pixel circuit of the display panel connected to it to be turned on so that it can write to the pixel circuit.
  • the level of the data signal accordingly "inactive output level” refers to a level that cannot make the switching transistor in the pixel circuit connected thereto be turned on (ie, the switching transistor is turned off).
  • the active output level can be higher or lower than the inactive output level.
  • the shift register unit outputs a square wave pulse signal at the output terminal during operation, the valid output level corresponds to the level of the square wave pulse part of the square wave pulse signal, and the invalid output level corresponds to the non-square wave pulse part level.
  • the shift register unit further includes a first node reset circuit 150 .
  • the first node reset circuit 150 is connected to the first node N1 and configured to reset the first node N1 in response to a reset signal.
  • the first node reset circuit 150 may be configured to be connected to the first node N1, the second voltage terminal VGL2 (for example, providing a low level) or an additional voltage terminal (for example, a low voltage terminal) and the reset terminal RST, Therefore, under the control of the reset signal input from the reset terminal RST, the first node N1 can be electrically connected to the second voltage terminal VGL2 or the low voltage terminal, so as to pull down and reset the first node N1.
  • the shift register unit 500 further includes a second node control circuit 160 , a first node noise reduction circuit 170 and an output noise reduction circuit 180 .
  • the second node control circuit 160 is connected to the first node N1 and the second node N2 and the third node N3, and is configured to control the level signal of the first node N1 to control the level is controlled.
  • the second node control circuit 160 is connected to the first node N1, the second node N2, the third node N3, the second voltage terminal VGL2, the third voltage terminal VGH1 and the fourth voltage terminal VGH2 or otherwise provided
  • the voltage terminals (for example, high voltage terminals) are connected to pull down the second node N2 and the third node N3 to a low level; when the first node N1 is at a low level, the second node N2 and the third node N3 are connected to the first node N3
  • One of the three voltage terminals VGH1 or the fourth voltage terminal VGH2 is connected, and is configured such that when the first node N1 is at a high level, for example, the second node N2 and the third node N3 are connected to the second voltage terminal VGL2 or an additionally provided
  • the level of the second node N2 is controlled by the level of the first node N1 and the third voltage provided by the third voltage terminal VGH1
  • the level of the third node N3 is controlled by the level of the first node N1 and The fourth voltage control provided by the fourth voltage terminal VGH2 will be described in detail below.
  • the third voltage terminal VGH1 and the fourth voltage terminal VGH2 can be set to input high level alternately, that is, when the third voltage terminal VGH1 inputs a high level, the fourth voltage terminal VGH1 inputs a low level, When the third voltage terminal VGH1 inputs a low level, the fourth voltage terminal VGH2 inputs a high level, so that the second node N2 and the third node N3 work alternately, so that the transistors connected to it can work alternately, prolonging the use of these transistors life.
  • the third voltage terminal VGH1 and the fourth voltage terminal VGH2 can also be replaced by clock signal terminals that alternately provide high levels (when the implemented transistors are P-type, then DC low levels) , which is not limited by the embodiments of the present disclosure.
  • the first node noise reduction circuit 170 is connected to the first node N1, the second node N2, and the third node N3, and is configured to control the levels of the second node N2 and the third node N3, noise reduction.
  • the first node noise reduction circuit 170 is connected to the first node N1, the second node N2, the third node N3 and the second voltage terminal VGL2, and is configured such that when the second node N2 and the third node N3 are at a high level, for example conduction, so that the first node N1 is connected to the second voltage terminal VGL2 or an additionally provided voltage terminal (for example, a low voltage terminal), and the potential of the first node N1 is pulled down to a non-operating potential, so as to realize the reduction of the first node N1 noise.
  • the output noise reduction circuit 180 is connected to the second node N2, the third node N3 and the output terminal OUT, and is configured to perform noise reduction on the output terminal OUT under the control of the levels of the second node N2 and the third node N3.
  • the output noise reduction circuit 180 is connected to the second node N2, the third node N3, the second voltage terminal VGL2 and the output terminal OUT, and is configured to be turned on when the second node N2 is at a high level, so that the output terminal OUT and The second voltage terminal VGL2 or an additional voltage terminal (for example, a low voltage terminal) is connected to achieve noise reduction on the output terminal OUT.
  • the shift register unit 500 further includes an overall reset circuit 190 .
  • the general reset circuit 190 is connected to the first node N1 and is configured to reset the first node N1 in response to a general reset signal.
  • the total reset circuit 190 can be configured to be connected to the first node N1, the second voltage terminal VGL2 (for example, providing a low level) or an additional voltage terminal (for example, a low voltage terminal) and the total reset terminal TRST, so that Under the control of the total reset signal input from the total reset terminal TRST, the first node N1 can be electrically connected to the second voltage terminal VGL2 or the low voltage terminal, so as to perform a pull-down reset on the first node N1.
  • the first voltage terminal VGL1 is configured to provide a DC low-level signal (for example, lower than or equal to the low-level part of the clock signal), such as grounding.
  • a DC low-level signal for example, lower than or equal to the low-level part of the clock signal
  • the DC low-level signal is referred to as the first voltage, for example, the following
  • the embodiments are the same as above, and will not be repeated here.
  • the second voltage terminal VGL2 is configured to provide a DC low-level signal (for example, lower than or equal to the low-level part of the clock signal), such as grounding, and the DC low-level signal is referred to as a second voltage here, for example, the The second voltage may be less than or equal to the first voltage, and the following embodiments are the same, so details are not repeated here.
  • a DC low-level signal for example, lower than or equal to the low-level part of the clock signal
  • grounding such as grounding
  • the DC low-level signal is referred to as a second voltage here, for example, the The second voltage may be less than or equal to the first voltage, and the following embodiments are the same, so details are not repeated here.
  • the third voltage terminal VGH1 is configured to provide a DC high-level signal, and the signal provided by it is called the third voltage
  • the fourth voltage terminal VGH2 is also configured to provide a DC high-level signal, and the signal provided by it is called the first voltage.
  • the third voltage and the fourth voltage may be the same voltage, and both are greater than the first voltage and the second voltage, and the following embodiments are the same, and will not be repeated here.
  • FIG. 11 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 10 .
  • the shift register unit 500 includes the second to twenty-ninth transistors T2 - T29 , and also includes a storage capacitor C.
  • each transistor is an N-type transistor as an example for illustration, but this does not constitute a limitation to the embodiments of the present disclosure.
  • the input circuit 110 may be implemented as a fourth transistor T4.
  • the gate and the first pole of the fourth transistor T4 are electrically connected to each other, and are configured to be connected to the input terminal INT to receive an input signal, and the second pole is configured to be connected to the first node N1, so that when the fourth transistor T4 is connected to the input terminal
  • the conduction signal for example, a high level signal
  • the gate and the first electrode of the fourth transistor T4 may also be respectively connected to the input terminal INT or other high voltage terminals (such as the third voltage terminal VGH1 or the fourth voltage terminal VGH2), which is not discussed in the embodiments of the present disclosure. limit.
  • the output circuit 120 may be implemented to include a second transistor T2, a third transistor T3 and a storage capacitor C.
  • the gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the clock signal terminal CLK to receive the second clock signal, and the second pole of the second transistor T2 is connected to the shift output terminal CR .
  • the gate of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the clock signal terminal CLK to receive the second clock signal, and the second pole of the third transistor T3 is connected to the scanning signal output terminal OUT1 ( That is, the output terminal Gout shown in FIG. 3 is connected.
  • a first pole of the storage capacitor C is connected to the first node N1, and a second pole of the storage capacitor C is connected to the scanning signal output terminal OUT1. It should be noted that, it is not limited thereto, and the shift register unit may further include more output signals and corresponding scanning signal output terminals.
  • the clock signal terminal CLK is connected to the clock signal lines CLK1-CLKm shown in FIG. 3 to receive the second clock signal in the above-mentioned embodiment.
  • the first node control circuit 130 may be implemented as a fourteenth transistor T14 and a twenty-fourth transistor T24.
  • the gate of the fourteenth transistor T14 is connected to the input terminal INT to receive the input signal
  • the first pole of the fourteenth transistor T14 is connected to the second node N2
  • the second pole of the fourteenth transistor T14 is connected to the second
  • the voltage terminal VGL2 is connected
  • the gate of the twenty-fourth transistor T24 is connected to the input terminal INT to receive the input signal
  • the first pole of the twenty-fourth transistor T24 is connected to the first pole and the third node N3
  • the twenty-fourth transistor T24 is connected to the first pole and the third node N3.
  • the second pole of the transistor T24 is connected to the second voltage terminal VGL2.
  • the first node reset circuit 150 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the reset terminal RST to receive a reset signal, the first pole is connected to the first node N1 , and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the fifth transistor T5 When the fifth transistor T5 is turned on in response to the reset signal, it electrically connects the first node N1 to the second voltage terminal VGL2 , so that the first node N1 can be reset.
  • the reset terminal RST is connected to the output terminal of the shift register cascaded with it, so as to realize the real-time reset of the first node N1 of the shift register unit of the stage during the shift output process of the gate scanning signal, so as to avoid False output at the output.
  • the general reset circuit 190 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the general reset terminal TRST to receive the general reset signal, the first pole is connected to the first node N1, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the sixth transistor T6 When the sixth transistor T6 is turned on in response to the general reset signal, it electrically connects the first node N1 to the second voltage terminal VGL2 , so that the first node N1 can be reset.
  • the overall reset circuit 190 is configured to globally reset all cascaded shift register units at the beginning of a frame of image display or at the end of a frame of image display.
  • the timing of the total reset signal is earlier than the trigger signal (will be introduced in detail later) when controlling the start of the display stage of a frame of image, so that all The first node N1 of the shift register unit is reset to avoid abnormality in the display screen.
  • the second node control circuit 160 may be implemented as a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the gate of the seventh transistor T7 is connected to the first control node CN1, the first pole is connected to the third voltage terminal VGH1 to receive the third voltage, and the second pole is connected to the second node N2; the gate of the eighth transistor T8 is connected to the first A node N1 is connected, the first pole is connected to the second node N2, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the gate of the ninth transistor T9 and its first pole are electrically connected to each other, and are configured to be connected to the third voltage terminal VGH1 to receive the third voltage, and the second pole is connected to the first control node CN1; the tenth transistor T10 The gate is connected to the first node N1, the first pole is connected to the first control node CN1, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the second node control circuit 160 further includes a twenty-seventh transistor T27 , a twenty-eighth transistor T28 , a twenty-ninth transistor T29 and a twentieth transistor T20 .
  • the gate of the twenty-seventh transistor T27 is connected to the second control node CN2, the first pole is connected to the fourth voltage terminal VGH2 to receive the fourth voltage, and the second pole is connected to the third node N3; the gate of the twenty-eighth transistor T28 The gate is connected to the first node N1, the first pole is connected to the third node N3, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the gate of the twenty-ninth transistor T29 and its first pole are electrically connected to each other, and are configured to be connected to the fourth voltage terminal VGH2 to receive the fourth voltage, and the second pole is connected to the second control node CN2;
  • the gate of the transistor T20 is connected to the first node N1, the first pole is connected to the second control node CN2, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the first node noise reduction circuit 170 may be implemented as an eleventh transistor T11 and a twenty-first transistor T21.
  • the gate of the eleventh transistor T11 is connected to the second node N2, the first pole is connected to the first node N1, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the eleventh transistor T11 is turned on when the second node N2 is at a high potential, and connects the first node N1 to the second voltage terminal VGL2 , so that the first node N1 can be pulled down to achieve noise reduction.
  • the gate of the twenty-first transistor T21 is connected to the third node N3, the first pole is connected to the first node N1, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the twenty-first transistor T21 is turned on when the third node N3 is at a high potential, and connects the first node N1 to the second voltage terminal VGL2 , so as to pull down the first node N1 to achieve noise reduction.
  • the eleventh transistor T11 and the twenty-first transistor T21 work alternately under the control of the levels of the second node N2 and the third node N3 respectively, so as to prolong the service life of these transistors.
  • the output terminal OUT includes a shift output terminal CR and a scanning signal output terminal OUT1 (that is, the output terminal Gout of the gate drive circuit), and the output noise reduction circuit 180 can be implemented as a twelfth transistor T12, a The twenty-second transistor T22, the thirteenth transistor T13, and the twenty-third transistor T23.
  • the twelfth transistor T12 and the twenty-second transistor T22 are used for noise reduction of the shift output terminal CR
  • the thirteenth transistor T13 and the twenty-third transistor T23 are used for noise reduction of the scan signal output terminal OUT1.
  • the output noise reduction circuit 180 may further include more transistors to achieve noise reduction on the scanning signal output terminals.
  • the gate of the twelfth transistor T12 is connected to the second node N2, the first pole is connected to the shift output terminal CR, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the twelfth transistor T12 is turned on when the second node N2 is at a high potential, and connects the shift output terminal CR to the second voltage terminal VGL2 , so that the noise of the shift output terminal CR can be reduced.
  • the gate of the twenty-second transistor T22 is connected to the third node N3, the first pole is connected to the shift output terminal CR, and the second pole is connected to the second voltage terminal VGL2 to receive the second voltage.
  • the twenty-second transistor T22 is turned on when the third node N3 is at a high potential, and connects the shift output terminal CR to the second voltage terminal VGL2 , so as to reduce the noise of the shift output terminal CR.
  • the twelfth transistor T12 and the twenty-second transistor T22 work alternately under the control of the levels of the second node N2 and the third node N3 respectively, so as to prolong the service life of these transistors.
  • the gate of the thirteenth transistor T13 is connected to the second node N2, the first pole is connected to the scan signal output terminal OUT1, and the second pole is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the thirteenth transistor T13 is turned on when the second node N2 is at a high potential, and connects the scanning signal output terminal OUT1 to the first voltage terminal VGL1 , so as to reduce the noise of the scanning signal output terminal OUT1 .
  • the gate of the twenty-third transistor T23 is connected to the third node N3, the first pole is connected to the scan signal output terminal OUT1, and the second pole is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the twenty-third transistor T23 is turned on when the third node N3 is at a high potential, and connects the scanning signal output terminal OUT1 to the first voltage terminal VGL1 , so as to reduce the noise of the scanning signal output terminal OUT1 .
  • the thirteenth transistor T13 and the twenty-third transistor T23 work alternately under the control of the levels of the second node N2 and the third node N3 respectively, so as to prolong the service life of these transistors.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode The value increases, thereby realizing the operation of the corresponding transistor (such as turning on);
  • pulse-down means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode decreases, thereby realizing the corresponding Operation of transistors (e.g. cut off).
  • pulse-up means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode decreases, thereby realizing the corresponding transistor
  • Pull-down refers to charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode rises, thereby realizing the operation of the corresponding transistor (such as cut-off) .
  • the first node N1, the second node N2, the third node N3, the first control node CN1 and the second control node CN2 do not represent actual components, but Is the meeting point that represents the related electrical connections in a circuit diagram.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first pole of the transistor is a drain
  • the second pole is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 500 provided by the embodiments of the present disclosure can also use P-type transistors.
  • the first pole of the transistor is the source
  • the second pole is the drain.
  • the poles of transistors of a certain type are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals can be provided with corresponding high voltages or low voltages.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon such as hydrogenated amorphous Crystalline silicon
  • FIG. 12 is a driving sequence diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • the potential level of the signal timing diagram shown in Figure 12 is only schematic, and does not represent the real potential value or relative ratio.
  • the high level signal corresponds to the turn-on signal of the N-type transistor
  • the low level The signal corresponds to the cut-off signal of the N-type transistor.
  • the working principle of the Nth-stage shift register unit 500 of the gate driving circuit 10 shown in FIG. 11 will be described below with reference to the signal timing diagram shown in FIG. 12 .
  • the working principle of the shift register unit 500 is as follows.
  • the input terminal INT provides a high level
  • the clock signal terminal CLK provides a low level of the second clock signal
  • the fourth transistor T4 is turned on, and the first node N1 is charged to the first high level
  • the fourteenth transistor T14 and the twenty-fourth transistor T24 are turned on, so that the second node N2 and the third node N3 are pulled down to low level.
  • the second transistor T2 and the third transistor T3 are turned on in response to the first high level of the first node N1, thereby outputting the low level of the second clock signal provided by the clock signal terminal CLK to the shift output terminal CR and scanning signal output terminal OUT1.
  • the input terminal INT inputs a low level
  • the clock signal terminal CLK provides a high level of the second clock signal
  • the second pole of the storage capacitor C changes from a low level to a high level, and according to the voltage across the capacitor The voltage cannot be abruptly changed, and the voltage of the first pole of the storage capacitor C (that is, the first node N1) is bootstrapped. Therefore, at this stage, the first node N1 is charged to the second high level, so that the second transistor T2 and the third transistor T3 are turned on in response to the second high level of the first node N1, and at the same time, at this stage, the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output a high level.
  • the second clock signal adopts the waveform shown in FIG. 9, according to the characteristic that the voltage across the capacitor cannot be abruptly changed, the voltage of the first pole of the storage capacitor C (that is, the first node N1) is bootstrapped, Therefore, at this stage, the first node N1 is charged to the third sub-level VGH5, so that the voltage of the first node N1 is bootstrapped higher, so that the second transistor T2 and the third transistor T3 can be turned on more. Thoroughly, it is beneficial to the output of the second clock signal.
  • the clock signal terminal CLK provides the low level of the second clock signal
  • the second pole of the storage capacitor C changes from a high level to a low level, and according to the characteristic that the voltage at both ends of the capacitor cannot change abruptly, the storage
  • the voltage of the first pole of the capacitor C (that is, the first node N1) is changed to the first high level, therefore, at this stage, the second transistor T2 and the third transistor T3 respond to the first high level of the first node N1 level conduction, the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output the low level of the second clock signal.
  • the reset terminal RST provides the high level of the reset signal, therefore, the fifth transistor T5 is turned on, so that the first node N1 is connected to the second voltage terminal VGL2, so that the voltage of the first node N1 is changed to low level, the second node N2 and the third node N3 become high level, therefore, at this stage, the second transistor T2 and the third transistor T3 are turned off in response to the low level of the first node N1, and the twelfth transistor T12, the twenty-second transistor T22, the thirteenth transistor T13 and the twenty-third transistor T23 are turned on, so that the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output a low level.
  • the total reset terminal TRST provides a high level of the total reset signal, so that the sixth transistor T6 is turned on, so that the first nodes N1 of all shift register units of the gate drive circuit can be reset.
  • FIG. 13 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 100 includes the display panel 1 provided by any embodiment of the present disclosure.
  • the display device 100 in this embodiment can be: any display device such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. A product or part with a display function.
  • the display device 100 may also include other conventional components such as a display panel, which is not limited in this embodiment of the present disclosure.

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Abstract

一种显示面板（1）及显示装置（100），可以防止串行显示现象。该显示面板（1）包括栅极驱动电路（10）、多条时钟信号线（CLK1-CLKm）、时序控制器（300）和多个防串行电路（400）；时序控制器（300）配置为提供第一时钟信号；多个防串行电路（400）与时序控制器（300）和多条时钟信号线（CLK1-CLKm）连接，且配置为将时序控制器（300）提供的第一时钟信号调节为第二时钟信号，并将第二时钟信号输出至多条时钟信号线（CLK1-CLKm），第二时钟信号的下降沿的下降时间（t1）小于第一时钟信号的下降沿的下降时间（t2）；栅极驱动电路（10）包括多个级联的移位寄存器单元（500）分别和多条时钟信号线（CLK1-CLKm）连接，栅极驱动电路（10）配置为将第二时钟信号作为输出信号逐行输出；多个防串行电路（400）的每个包括至少一个电阻（R1-Rm）和至少一个电感（L1-Lm）。

Description

显示面板及显示装置
本公开要求于2021年5月28日递交的中国专利申请第202110594338.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。
技术领域
本公开的实施例涉及一种显示面板及显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅极扫描信号线和与栅极扫描信号线交错的多列数据线。对栅极扫描信号线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅极扫描信号线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅极扫描信号线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅极扫描信号线提供开关态电压信号(扫描信号)，从而例如控制多行栅极扫描信号线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
发明内容
本公开至少一实施例提供一种显示面板，包括：栅极驱动电路、多条时钟信号线、时序控制器和多个防串行电路；所述时序控制器配置为提供第一时钟信号；所述多个防串行电路与所述时序控制器和所述多条时钟信号线连接，且配置为将所述时序控制器提供的所述第一时钟信号调节为第二时钟信号，并将所述第二时钟信号输出至所述多条时钟信号线，其中，所述第二时钟信号的下降沿的下降时间小于所述第一时钟信号的下降沿的下降时间；所述栅极驱动电路包括多个级联的移位寄存器单元，分别和所述多条时钟信号线连接，所述栅极驱动电路配置为将所述第二时钟信号作为输出信号逐行输出，从而缩短所述输出信号的下降沿的下降时间；所述多个防串行电路的每个包括至少一个电阻和至少一个电感。
例如，在本公开至少一实施例提供的显示面板中，所述至少一个电阻和所述至少一个电感串联连接或并联连接。
例如，在本公开至少一实施例提供的显示面板中，所述至少一个电阻的第一端和所述时序控制器连接，所述至少一个电阻的第二端和所述至少一个电感连接。
例如，在本公开至少一实施例提供的显示面板中，所述防串行电路的等效电阻的总阻值为1欧姆至1000欧姆；所述防串行电路的等效电感的总电感量为1微亨至1000微亨。
例如，在本公开至少一实施例提供的显示面板中，所述至少一个电阻包括第一电阻和第 二电阻，所述至少一个电感包括第一电感和第二电感，所述第一电阻和所述第一电感并联形成第一元件，所述第二电阻和所述第二电感并联形成第二元件；所述第一元件和所述第二元件串联连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一元件的等效电阻和所述第二元件的等效电阻的总阻值为1欧姆至1000欧姆；或者，所述第一元件的等效电感和所述第二元件的等效电感的总电感量为1微亨至1000微亨。
例如，在本公开至少一实施例提供的显示面板中，所述第一时钟信号包括在时域上按顺序排布的第一电平和第二电平，所述第二时钟信号包括在所述时域上按顺序排布的第三电平和第四电平；所述第一电平高于所述第二电平，所述第三电平高于所述第四电平；所述第四电平包括第一子电平和第二子电平；在所述时域上，所述第二子电平位于所述第三电平和所述第一子电平之间，所述第二子电平低于所述第一子电平。
例如，在本公开至少一实施例提供的显示面板中，所述第一电平和所述第三电平相等，第一子电平和第二电平相等。
例如，在本公开至少一实施例提供的显示面板中，所述第三电平包括第三子电平和第四子电平，在所述时域上，所述第四子电平位于所述第三子电平和所述第二子电平之间，所述第三子电平高于所述第四子电平。
例如，在本公开至少一实施例提供的显示面板中，所述第四子电平和所述第一电平相等。
例如，在本公开至少一实施例提供的显示面板中，所述第一时钟信号包括在时域上按顺序排布的第一电平和第二电平，所述第二时钟信号包括在时域上按顺序排布的第三电平和第四电平，所述第一电平高于所述第二电平，所述第三电平高于所述第四电平；所述第二电平高于所述第四电平。
例如，在本公开至少一实施例提供的显示面板中，所述第三电平高于所述第一电平。
例如，本公开至少一实施例提供的显示面板还包括电平转换电路，配置为将所述第一时钟信号转换为所述第二时钟信号。
例如，在本公开至少一实施例提供的显示面板中，所述移位寄存器单元包括输入电路、输出电路和第一节点控制电路；所述输入电路与第一节点连接，且配置为响应于输入信号对所述第一节点进行充电；所述输出电路与所述第一节点连接，且配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；所述第一节点控制电路分别与所述第二节点和第三节点连接，且配置为响应于所述输入信号，控制所述第二节点和所述第三节点的电平。
例如，在本公开至少一实施例提供的显示面板中，所述移位寄存器单元还包括：总复位电路，所述总复位电路与所述第一节点和所述总复位端连接，且配置为从所述总复位端接收所述总复位信号并响应于所述总复位信号，对所述第一节点的电平进行控制。
例如，在本公开至少一实施例提供的显示面板中，所述移位寄存器单元还包括第一节点复位电路，所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一 节点进行复位。
例如，在本公开至少一实施例提供的显示面板中，所述移位寄存器单元还包括第二节点控制电路、第一节点降噪电路和输出降噪电路；所述第二节点控制电路分别与所述第一节点以及所述第二节点和所述第三节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点和所述第三节点的电平进行控制；所述第一节点降噪电路与所述第一节点以及所述第二节点和所述第三节点连接，且配置为在所述第二节点和所述第三节点的电平信号的控制下，对所述第一节点进行降噪；所述输出降噪电路与所述第二节点、所述第三节点以及所述输出端连接，且配置为在所述第二节点和所述第三节点的电平信号的控制下，对所述输出端进行降噪。
例如，在本公开至少一实施例提供的显示面板中，所述输出端包括移位输出端和至少一个扫描信号输出端。
例如，在本公开至少一实施例提供的显示面板中，所述至少一个扫描信号输出端包括一个扫描信号输出端，所述输出电路包括第二晶体管、第三晶体管和存储电容；所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第二极和所述移位输出端连接；所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述第二时钟信号，所述第三晶体管的第二极和所述扫描信号输出端连接；所述存储电容的第一极和所述第一节点连接，所述第二电容的第二极和所述扫描信号输出端连接；所述第二时钟信号被传输至所述输出端作为所述输出信号。
例如，本公开至少一实施例提供的显示面板还包括显示区域、围绕所述显示区域的周边区域和电路板；所述显示区域包括阵列排布的多个像素，配置为接收所述栅极驱动电路的输出信号以进行显示；所述栅极驱动电路、所述多条时钟信号线位于所述周边区域，所述周边区域包括转角部分，所述转角部分包括所述栅极驱动电路中的部分移位寄存器单元和所述多条时钟信号线；所述时序控制器和所述防串扰电路位于所述电路板上。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为一种像素充电时序的示意图；
图1B为理想状态下H-1Line的显示画面的示意图；
图1C为实际状态下H-1Line的显示画面串行的示意图；
图2为本公开至少一实施例提供的一种显示面板的示意图；
图3为本公开至少一实施例提供的另一种显示面板的示意图；
图4A为本公开至少一实施例提供的一种第一时钟信号和第二时钟信号的示意图；
图4B为本公开至少一实施例提供的一种加入防串行电路前后栅极驱动电路输出的输出信号的示意图；
图4C为本公开至少一实施例提供的一种时钟信号线的寄生电容的示意图；
图4D为本公开至少一实施例提供的一种电路负载模型的示意图；
图4E为本公开至少一实施例提供的一种显示面板的平面示意图；
图5为本公开至少一实施例提供的另一种显示面板的示意图；
图6为本公开至少一实施例提供的一种第一时钟信号和第二时钟信号的波形示意图；
图7为本公开至少一实施例提供的一种第二时钟信号和输出信号的波形示意图；
图8为本公开至少一实施例提供的一种输出信号的放大示意图；
图9为本公开至少一实施例提供的另一种第二时钟信号的示意图；
图10为本公开一实施例提供的一种移位寄存器单元的示意图；
图11为图10中所示的移位寄存器单元的一种具体实现示例的电路图；
图12为本公开至少一实施例提供的一种移位寄存器单元的驱动时序图；以及
图13为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的耦接，而是可以包括电性的耦接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
目前，为了适应市场需求，提高用户体验，显示产品朝着高分辨率、高刷新频率的方向发展。例如，显示屏的分辨率和刷新频率可以达到8K和120Hz(赫兹)、4K和240Hz等，另外，面板厂为了降低成本而开发的具有双栅的8K和60Hz的显示屏以及无界显示屏等产 品也越来越多。这些产品都有一个共性：1H时间(1H时间表示例如液晶显示面板中1行像素打开或充电的时间)短。表1为不同显示产品分别对应的1H时间，1H时间越短，该行像素充电越困难。
表1
Figure PCTCN2021126858-appb-000001
例如，对像素进行充电时，为确保数据能正确显示，需在对像素进行充电完成后，及时关闭栅线上的栅极扫描信号的有效电平(例如，高电平)的传输，然后再进行下一行像素的充电，否则会发生串行：即上一行的数据显示到下一行，或者下一行的数据显示到上一行。
图1A为一种像素充电时序的示意图。例如，如图1A所示，在栅极扫描信号为高电平时，将第1行像素对应的数据信号D1写入第1行像素(即对第1行像素的充电)，在栅极扫描信号为低电平时才能结束充电，但由于栅极扫描信号的下降沿的下降时间Tf较大，导致栅极扫描信号还未完全变为低电平，第2行像素对应的数据信号D2已经输出，因此，产生串行时间t。在串行时间t内，第2行像素对应的数据信号D2的部分会写入第1行像素，使写入第1行像素的数据发生失真，即不仅仅是其需要显示的数据信号D1，还包括第2行像素对应的数据信号D2。串行时间t越长，失真越严重。
并且，在对分辨率和刷新频率分别为8K和120Hz的显示产品的实际样品验证中，发现存在严重的串行问题。特别是当显示面板显示H-1line画面(Pattern)时，由于存在串行，导致显示产品显示的画面为例如图1C所示的黑线不够黑、白线不够白的画面，而不是如图1B所示的理想状态下H-1Line的显示画面(例如如图1B所示的黑线仅显示黑，白线仅显示白的画面)，因此，H-1Line画面产生串行，即显示画面完全失真。串行较严重时，则看到H-1line画面为所有行全亮。
因此，要解决例如分辨率和刷新频率为8K、120Hz的显示产品重载H-1line画面的串行问题，必须减小栅线负载(电阻和电容)。然而，分辨率为8K的显示产品的栅线均为铜线，且工艺上均已经达到工艺能实现的最大铜厚度，因此，靠工艺降低栅线负载，优化幅度有限，必须寻找其他解决方法。
本公开至少一实施例提供一种显示面板，包括：栅极驱动电路、多条时钟信号线、时序控制器和多个防串行电路；时序控制器配置为提供第一时钟信号；多个防串行电路与时序控制器和多条时钟信号线连接，且配置为将时序控制器提供的第一时钟信号调节为第二时钟信号，并将第二时钟信号输出至多条时钟信号线，第二时钟信号的下降沿的下降时间小于第一时钟信号的下降沿的下降时间；栅极驱动电路包括多个级联的移位寄存器单元，分别和多条时钟信号线连接，栅极驱动电路配置为将第二时钟信号作为输出信号逐行输出，从而缩短 输出信号的下降沿的下降时间；多个防串行电路的每个包括至少一个电阻和至少一个电感。
本公开实施例的显示面板通过在时序控制器和栅极驱动电路之间串入电感，可以形成感性负载，抵消时钟信号线上的容性负载，从而使得时钟信号线只存在阻性负载，避免时钟信号线上的寄生电容对时钟信号的下降沿的下降时间的延长，从而可以避免串行显示；另外，在时序控制器和栅极驱动电路之间串入电阻，可以减小时钟信号线上的电流，降低时钟信号线发热，提高显示面板的性能。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
图2为本公开至少一实施例提供的一种显示面板的示意图。例如，该显示面板可以是分辨率为8K、刷新频率为120Hz的显示面板，当然也可以是具有其他分辨率或刷新频率的显示面板，本公开的实施例对此不作限制。例如，如图2所示，在一些示例中，该显示面板1包括栅极驱动电路10。例如，如图2所示，在另一些示例中，该显示面板1还包括显示区域40，显示区域40包括像素阵列，与栅极驱动电路10连接，像素阵列包括多行多列子像素410。例如，在另一些示例中，该显示面板1还可以包括数据驱动电路30和多条数据线DL。多条数据线D与多列子像素410电连接，且配置为将数据驱动电路30提供的数据信号传输至多列子像素410。
例如，数据驱动电路30用于提供数据信号给像素阵列；栅极驱动电路10用于提供栅极扫描信号给像素阵列。数据驱动电路30通过数据线DL与子像素410电连接，栅极驱动电路10通过栅极扫描信号线GL与子像素410电连接。
例如，该栅极驱动电路用于驱动例如液晶显示面板、有机发光二极管显示面板等显示面板，为显示面板的多条栅极扫描信号线依序提供栅极扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
图3为本公开至少一实施例提供的另一种显示面板的示意图。例如，如图3所示，在图2所示的示例的基础上，该一种显示面板1还包括多条时钟信号线CLK1至CLKm(m为大于0的偶数)、时序控制器300和多个防串行电路。为了表示清楚、简洁，图3中并没有示出显示区域40和数据驱动电路30，具体可参照图2中的介绍，在此不再赘述。
例如，m可以等于2、4、6、12、16等，即多条时钟信号线可以包括2、4、6、12、16条等，即时钟信号线的条数是2的整数倍，本公开的实施例对此不作限制。例如，多条时钟信号线之间的距离可以为4微米至100微米之间，例如为4-20微米，本公开的实施例对此不作限制。
例如，时序控制器300配置为提供第一时钟信号。
例如，多个防串行电路400与时序控制器300和多条时钟信号线CLK1至CLKm连接，且配置为将时序控制器300提供的第一时钟信号调节为第二时钟信号，并将第二时钟信号输出至多条时钟信号线CLK1至CLKm。
例如，在一些示例中，多个防串行电路400与多条时钟信号线CLK1一一对应连接，即一条时钟信号线连接一个防串行电路400，本公开的实施例对此不作限制。
例如，在另一些示例中，该防串扰电路400也可以设置在时序控制器300和其他电源线之间，例如，向图10中所示的第一电压端至第四电压端提供第一电压至第四电压的电源线，以降低峰值电流等，本公开的实施例对此不作限制。
例如，如图3所示，栅极驱动电路10包括多个级联的移位寄存器单元GOA，分别和多条时钟信号线CLK1至CLKm连接，栅极驱动电路10配置为将第二时钟信号作为输出信号逐行输出，从而缩短输出信号的下降沿的下降时间。
例如，当m＝12时，如图3所示，多条时钟信号线包括第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5、第六时钟信号线CLK6、第七时钟信号线CLK7、第八时钟信号线CLK8、第九时钟信号线CLK9、第十时钟信号线CLK10、第十一时钟信号线CLK11、第十二时钟信号线CLK12。
例如，如图3所示，第一时钟信号线CLK1和第12n-11级移位寄存器的时钟信号端连接；第二时钟信号线CLK2和第12n-10级移位寄存器的时钟信号端连接；第三时钟信号线CLK3和第12n-9级移位寄存器的时钟信号端连接；第四时钟信号线CLK4和第12n-8级移位寄存器的时钟信号端连接；第五时钟信号线CLK5和第12n-7级移位寄存器的时钟信号端连接；第六时钟信号线CLK6和第12n-6级移位寄存器的时钟信号端连接；第七时钟信号线CLK7和第12n-5级移位寄存器的时钟信号端连接；第八时钟信号线CLK8和第12n-4级移位寄存器的时钟信号端连接；第九时钟信号线CLK9和第12n-3级移位寄存器的时钟信号端连接；第十时钟信号线CLK10和第12n-2级移位寄存器的时钟信号端连接；第十一时钟信号线CLK11和第12n-1级移位寄存器的时钟信号端连接；第十二时钟信号线CLK12和第12n级移位寄存器的时钟信号端连接；n为大于等于1的整数。
需要注意的是，其他条数的时钟信号线与移位寄存器单元的连接方式与12条时钟信号线类似，在此不再赘述，当然也可以采用其他连接方式，本公开的实施例对此不作限制。
图4A为本公开至少一实施例提供的一种第一时钟信号和第二时钟信号的示意图；图4B为本公开至少一实施例提供的一种加入防串行电路400前后栅极驱动电路输出的输出信号的示意图。例如，如图4A所示，上下两幅波形图分别为在时序控制器300的近端的第一时钟信号和第二时钟信号的对比图和在时序控制器300的远端的第一时钟信号和第二时钟信号的对比图。
例如，如图4A所示，第二时钟信号(如图4A中实线所示的波形)的下降沿的下降时间t1小于第一时钟信号(如图4A中虚线所示的波形)的下降沿的下降时间t2。
例如，如图4B所示，实线为栅极驱动电路输出的第二时钟信号作为输出信号，虚线为栅极驱动电路输出的第一时钟信号作为输出信号。如图4B所示，栅极驱动电路10将第二时钟信号作为输出信号逐行输出时，输出信号的下降沿的下降时间由t2缩短至t1，从而可以避免串行现象的发生。
图4C为本公开至少一实施例提供的一种时钟信号线的寄生电容的示意图。
例如，如图4C所示，时钟信号线CLK1的电容负载来源于时钟信号线CLK1的转接电 极E1和与不同的移位寄存器单元连接的时钟信号线CLK2-CLKm交叠处产生的寄生电容C11以及移位寄存器单元的输出晶体管(如下图12中所示的第三晶体管T3)的栅极和转接电极E1交叠处产生的寄生电容C21。在本公开的一些实施例中，通过在时钟信号线上串入电感引入感性负载，可以抵消时钟信号线的容性负载(例如，寄生电容C11和C21)，使得时钟信号的阻抗减小，从而使得时钟信号的下降沿的下降时间减小，进而使得输出信号的下降沿的下降时间减小，从而可以避免串行现象的发生。
需要注意的是，为了表示清楚、简洁，上面仅以时钟信号线CLK1为例进行说明，其他时钟信号线CLK2-CLKm与时钟信号线CLK1类似，在此不再赘述。
例如，多个防串行电路400的每个包括至少一个电阻和至少一个电感。例如，至少一个电阻和至少一个电感串联连接或并联连接。
例如，每个防串行电路400的等效电阻的总阻值为1欧姆(Ω)至1000欧姆；每个防串行电路的等效电感的总电感量为1微亨至1000微亨。例如，在一些示例中，每个防串行电路400的等效电阻的总阻值为150Ω，每个等效电感的总电感量为100微亨，当然，还可以是其他数值，具体可参照实际情况而定，本公开的实施例对此不作限制。
例如，至少一个电阻的第一端和时序控制器300连接，至少一个电阻的第二端和至少一个电感连接。
例如，如图3所示，与时钟信号线CLK1连接的防串行电路400包括电阻R1和电感L1。例如，与时钟信号线CLK2连接的防串行电路400包括电阻R2和电感L2；与时钟信号线CLK3连接的防串行电路400包括电阻R3和电感L3；与时钟信号线CLKm-1连接的防串行电路400包括电阻Rm-1和电感Lm-1；与时钟信号线CLKm连接的防串行电路400包括电阻Rm和电感Lm。
例如，电阻R1-Rm的第一端和时序控制器300连接，电阻R1-Rm的第二端分别和电感L1-Lm的第一端连接，电感L1-Lm的第二端分别和多条时钟信号线CLK1-CLKm一一对应连接。
例如，上述各个电阻的阻值可以相等，例如，电阻R1的阻值等于电阻R2的阻值等于电阻R3的阻值等于电阻Rm-1的阻值等于电阻Rm的阻值，例如，等于150Ω，当然上述各个电阻的阻值可以不相等，例如，可以根据时序控制器300至时钟信号线之间的距离确定，时序控制器300距离时钟信号线之间的距离越大，阻值越小，例如，电阻R1的阻值小于电阻R2的阻值小于电阻Rm的值，具体可视实际情况而定，本公开的实施例对此不作限制。
例如，上述各个电感的电感量可以相等，例如，电感L1的电感量等于电感L2的电感量等于电感L3的电感量等于电感L3m-1的电感量等于电感Lm的电感量，例如，等于100微亨，当然上述各个电感的电感量也可以不相等，例如，可以根据时序控制器300至时钟信号线之间的距离确定，时序控制器300距离时钟信号线之间的距离越大，电感量越小，例如，电感L1的电感量小于电感L2的电感量小于电感Lm的电感量，具体可视实际情况而 定，本公开的实施例对此不作限制。
需要注意的是，为了表示清楚简洁，图3中仅示出了至少一个电阻包括1个电阻，至少1个电感包括1个电感，且该电阻和电感串联连接的情况，但是本公开的实施例对此不作限制，还可以包括更多个电阻和电感。
图4E为本公开至少一实施例提供的一种显示面板的平面示意图，如图4E所示，该显示面板具有显示区域11和围绕显示区域11的周边区域12。例如，在周边区域12进行弯曲时，周边区域12包括转角部分13。例如，显示区域11包括阵列排布的多个像素，用于接收栅极驱动电路的输出信号作为栅极扫描信号以进行显示。周边区域12具有驱动显示区域11中的多个子像素进行显示的栅极驱动电路10和多条时钟信号线等结构。
例如，如图4E所示，该显示面板还包括电路板600，与例如，时序控制器300和防串扰电路400可以设置在该电路板600上，具体设置可参考本领域的设置，在此不再赘述。
在一些示例中，在时序控制器300与电感L1之间的时钟信号线上串入电阻R1，可以降低显示面板转角部分的温度，防止显示面板发热严重导致发黑问题及火灾隐患。对于分辨率为8K、刷新频率为120Hz的显示产品由于时钟信号线传输信号的频率较高，移位寄存器单元GOA的驱动能力强，时钟信号线的电流大，显示面板的转角部分由于时钟信号线布线转弯导致布线密集，且考虑边框，一般温度都会比较高，验证数据测试，分辨率为8K、刷新频率为120Hz的显示面板工作时的转角温度可以达到70℃以上，通过串电阻，显示面板的转角部分可以降低至50℃，因此，在时钟信号线上串电阻可以降低显示面板转角部分的温度，提高用户体验，延长显示面板的使用寿命。
由于所有无源器件都可以等效为电阻和电感的串联，电阻和电容的并联。因此，图3中所示的串入的电阻和电感均为最少器件的示例，在另一些示例中，例如在电阻旁边并入电感，在电感旁边并入电阻，均属于本公开的保护范围，本公开的实施例对此不作限制。
图5为本公开至少一实施例提供的另一种显示面板的示意图。例如，如图5所示，在该示例中，至少一个电阻包括第一电阻R1和第二电阻R1`，至少一个电感包括第一电感L1`和第二电感L1，第一电阻R1和第一电感L1`并联形成第一元件410，第二电阻R1`和第二电感L1并联形成第二元件420。例如，如图5所示，该第一元件410和第二元件420串联连接。
例如，在该示例中，第一元件410和第二元件420可以等效为电感，第一元件410的等效电感和第二元件420的等效电感的总电感量为1微亨至1000微亨；或者，在另一些示例中，当第一元件和第二元件等效为电阻时，第一元件的等效电阻和第二元件的等效电阻的总阻值为1欧姆至1000欧姆。
例如，在另一些示例中，例如，第一元件410或第二元件420可以包括多个串联或并联的电阻。例如，当防串扰电路400仅包括1个电阻时，该电阻的阻值为1欧姆至1000欧姆，当包括2个并联连接的电阻时，每个电阻的阻值可以为2000欧姆，从而使得并联后的电阻值为1000欧姆，只要满足该第一元件410的等效电阻或第二元件420的等效电阻的阻值 (即防串扰电路400的等效电阻的总阻值)为1欧姆至1000欧姆即可，本公开的实施例对此不作限制。
例如，在另一些示例中，例如，第一元件410或第二元件420可以包括多个串联或并联的电感。例如，当防串扰电路400仅包括1个电感时，该电感的电感量为1微亨至1000微亨，当包括多个串联或并联连接的电感时，每个电感的阻值可以根据实际情况进行调整，只要满足该第一元件410的等效电感或第二元件420的等效电感的总电感量(即防串扰电路400的等效电感的总电感量)为1微亨至1000微亨即可，本公开的实施例对此不作限制。
图4D为本公开至少一实施例提供的一种电路负载模型的示意图。例如，如图4D所示，对于一个电路网络，负载都可以抽象为RLC网络，该网络阻抗为：
Figure PCTCN2021126858-appb-000002
其中，实部R为电阻，虚部
Figure PCTCN2021126858-appb-000003
为电抗，w＝2πf为角频率，f为信号频率，j为虚数单位。
例如，阻抗幅度为Z的模。由该公式可知，当电路中C一定时，增大电感L，可以使电路阻抗Z减小，当
Figure PCTCN2021126858-appb-000004
时，电路阻抗最小，为电阻值R。此后，再增大电感，阻抗又开始增大。
本公开上述实施例的显示面板通过在时序控制器和栅极驱动电路之间串入电感，可以形成感性负载，抵消时钟信号线上的容性负载，从而使得时钟信号线只存在阻性负载，避免时钟信号线上的寄生电容对时钟信号的下降沿的下降时间的延长；另外，在时序控制器和栅极驱动电路之间串入电阻，可以减小时钟信号线上的电流，降低时钟信号线发热，提高显示面板的性能。
图6为本公开至少一实施例提供的一种第一时钟信号和第二时钟信号的波形示意图；图7为本公开至少一实施例提供的一种第二时钟信号和输出信号的波形示意图；图8为本公开至少一实施例提供的一种输出信号的放大示意图。
例如，对于栅极驱动电路，输出端输出的输出信号的波形取决于栅极驱动电路的输入波形，即，取决于时钟信号线提供的第二时钟信号的波形。例如，时钟信号线提供的第二时钟信号的波形包括多阶电平，可使栅极驱动电路的输出端输出的输出信号的波形也包括多阶电平，例如，如图7所示，多阶电平指一个低电平包括多阶低电平或一个高电平包括多阶高电平，本公开的实施例对此不作限制。
例如，多阶电平的第二时钟信号可以优化输出信号的下降沿的下降时间长的问题，例如，根据输出信号的下降沿的10％(VGH-VGL1)～90％(VGH-VGL1)的部分作为判断下降沿的下降时间，由于输出信号的波形变为多阶电平后，输出信号的下降沿形成下冲，故输出信号的下降沿的下降时间变小。例如，VGH为图6所示的第一电平，VGL1为图10中所示的第一电压端提供的第一电压。由于移位寄存器单元的输出端输出的低电平为图10中所示的输出降噪电路180导通时，将第一电压端VGL1提供的第一电压输出至输出端，因此，下降 沿的下冲高度取值为VGH-VGL1。
例如，在一些示例中，第一时钟信号包括在时域上按顺序排布的第一电平VGH和第二电平LVGL，第二时钟信号包括在所述时域上按顺序排布的第三电平VGH3和第四电平；第一电平VGH高于第二电平LVGL，第三电平VGH3高于第四电平；第四电平包括第一子电平LVGL1和第二子电平LVGL2；在时域上，第二子电平LVGL2位于第三电平VGH3和第一子电平LVGL1之间。例如，在一些示例中，第二子电平LVGL2低于第一子电平LVGL1，从而可以使得第二时钟信号的下降沿形成从第三电平VGH3至第二子电平LVGL2的下冲，从而可以缩短下降沿的下降时间。
例如，在一些示例中，第一子电平LVGL1＝-10V(伏特),第二子电平LVGL2＝-15V，当然还可以是其他数值，例如，第一子电平和第二子电平的取值范围可以为-4V至-20V，具体可视实际情况而定，本公开的实施例对此不作限制。
例如，第一子电平LVG1可以和图10中所示的第一电压端VGL1提供的第一电压相等，例如，均为-10V，图10中所示的第二电压端VGL2提供的第二电压例如为-8V，具体可视实际情况而定，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，第一电平VGH和第三电平VGH3为高电平，第二电平LVGL和第四电平为低电平，以下实施例与此相同，不再赘述。
例如，如图6所示，第一电平VGH和第三电平VGH3相等或大致相等，第一子电平LVGL1和第二电平LVGL相等或大致相等，本公开的实施例对此不作限制。
例如，如图8所示，由于栅极驱动电路输出第二时钟信号作为输出信号，因此，输出信号的下降沿也会形成从第三电平VGH3至第二子电平LVGL2的下冲，从而可以缩短输出信号的下降沿的下降时间，将输出信号的下降沿的下降时间由第一时间(即下降时间为A1至A3之间的在水平方向的距离)缩短至第二时间(即下降时间为A1至A2之间的在水平方向的距离)。
图9为本公开至少一实施例提供的另一种第二时钟信号的示意图。
例如，如图9所示，在另一些示例中，第三电平VGH3包括第三子电平VGH5和第四子电平VGH4，在时域上，第四子电平VGH4位于第三子电平VGH5和第二子电平LVGL2之间，即在时域上，第三子电平VGH5先于第四子电平VGH4先于第二子电平LVGL2先于第一子电平LVGL1。
例如，第三子电平VGH5高于第四子电平VGH4，从而可以在输出该第二时钟信号的第三子电平VGH5时，根据电容的电荷守恒定律，提高第三晶体管T3的栅极(即图12所示的N1节点)的电压，从而使得第三晶体管T3打开的更彻底，具体可参考下面关于图10-图12的描述，在此不再赘述。
例如，在一些示例中，第四子电平VGH4和第一电平VGH相等或大致相等，即第四子电平VGH4和第三电平VGH3相等或大致相等，本公开的实施例对此不作限制。
例如，如图6和图9所示，该第二子电平LVGL2和第三子电平VGH5的宽度可以为 0.5H-m/2H，也可以为0.5H-2H，1H为1行像素充电的时间。例如，当包括12条时钟信号线时，即m＝12，第二子电平LVGL2和第三子电平VGH5的宽度可以小于等于6H，即6个1行子像素充电的时间，具体宽度范围可视实际情况而定，本公开的实施例对此不作限制。
例如，在一些示例中，第二时钟信号的波形也可以不采用多阶电平，直接在下降沿形成VGH5-LVGL2的下冲。例如，在该示例中，第一时钟信号包括在时域上按顺序排布的第一电平和第二电平，第二时钟信号包括在时域上按顺序排布的第三电平和第四电平，第一电平高于第二电平，第三电平高于第四电平；第二电平高于第四电平。第三电平高于第一电平。
例如，第一电平为图6中所示的VGH，第二电平为图6中所示的LVGL，第三电平为图9中所示的VGH5，第四电平为图6或图9中所示的LVGL2，其宽度均为m/2H。
在该实施例中，由于第二时钟信号的波形下降沿形成VGH5-LVGL2的下冲，该下冲比第一时钟信号的下降沿处的下冲VGH-LVGL大，因此，会缩短下降沿的下降时间。
例如，第一电平VGH、第三电平VGH3、第三电平VGH3包括的第三子电平VGH5和第四子电平VGH4、图10中所示的第三电压端VGH1提供的第三电压、图10中所示的第四电压端VGH2提供的第四电压的取值范围均可以是25V-40V，例如，在图9所示的示例中，第一电平VGH为32V，第三子电平VGH5为36V，第四子电平VGH4为32V，在图6所示的示例中，第三电平VGH3为32V，具体可视实际情况而定，本公开的实施例对此不作限制。
例如，在另一些示例中，该显示面板还包括电平转换电路(图中未示出)，配置为将逻辑电平信号转换为第一时钟信号或者配置为将第一时钟信号转换为图6或图9所示的上述具有多阶信号的第二时钟信号。
例如，在一些示例中，电平转换电路可以将逻辑电平转换为具有多阶信号的第一时钟信号，然后将该第一时钟信号输出至防串扰电路400，防串扰电路输出具有多阶的第二时钟信号至多条时钟信号线；在另一些示例中，电平转换电路可以将第一时钟信号转换为图6或图9所示的上述具有多阶信号的第二时钟信号然后在输入至防串扰电路中，也可以从防串扰电路接收第二时钟信号后在经过电平转换电路对第二时钟信号进行多阶电平的设置，然后将设置为多阶电平后的第二时钟信号输出至多条时钟信号线中，本公开的实施例对此不作限制。
例如，该时钟信号采用一高多低或多高多低的多阶电平设计，可以使得第二时钟信号形成下冲减小下降沿的下降时间的延迟，从而缩短输出信号的下降沿的下降时间，因此，栅极驱动电路的驱动能力可以实现一定程度增强，可用于所有产品驱动，如分辨率为4K的显示产品、分辨率为8K的显示产品、COF(Chip On Flex或者Chip On Film，覆晶薄膜)产品等。
例如，在一些实施例中，可以只采用时钟信号的多阶电平设置，移位寄存器单元的驱动能力可以实现一定程度增强。
例如，在另一些示例中，可以在时序控制器300和多条信号线之间只串入电阻，可以有 效降低时钟信号线电流，大幅度降低显示面板转角处的温度，可适用于时钟信号线数量少，但充电率很足的产品。
例如，在另一些示例中，可以在时序控制器300和多条信号线之间只串入电感，电感值例如为10微亨～500微亨之间，可以较大幅度优化时钟信号线的延迟，提升移位寄存器单元驱动能力，适用于充电率需要提升，且GOE边缘不足的产品，对于画面有水平横纹的产品也可以适用。
需要注意的是，上述各实施例可任意组合，本公开的实施例对此不作限制。
例如，移位寄存器单元可以采用本领域的电路结构，例如，可以采用4T1C、10T4C、21T1C等，本公开的实施例对此不作限制，其具体驱动过程可以参考本领域的常规介绍，在此不再赘述。
图10为本公开一实施例提供的一种移位寄存器单元的示意图。如图10所示，该移位寄存器单元500包括输入电路110、输出电路120、第一节点N1和第一节点控制电路130。通过级联多个该移位寄存器单元500可以得到栅极驱动电路，该栅极驱动电路用于驱动显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
如图10所示，输入电路110与第一节点N1(例如，这里为上拉节点)连接，且配置为响应于输入信号对第一节点N1进行充电。例如，在一些示例中，输入电路110与输入信号端INT和第一节点N1连接，配置为在输入信号端INT提供的输入信号的控制下导通，使输入信号端INT和第一节点N1连接，从而使输入信号端INT提供的输入信号被输入到第一节点N1，将第一节点N1的电位充电(例如上拉)到工作电位。
输出电路120包括输出端OUT，与第一节点N1连接，且配置为在第一节点N1的电平信号的控制下，将输出信号在输出端OUT输出。例如，在一些示例中，输出电路120与时钟信号端CLK、第一节点N1以及输出端OUT连接，且配置为在第一节点N1的电平信号的控制下导通，将时钟信号端CLK提供的第二时钟信号传输至输出端OUT，并作为输出信号在输出端OUT输出。或者，在另一个示例中，输出电路120还与一个电压端连接，使用时钟信号端CLK提供的第二时钟信号作为控制信号以控制是否将该电压端与输出端OUT连接，从而控制是否将该电压端的电压信号传输至输出端OUT并作为输出信号在输出端OUT输出。
例如，时钟信号端CLK与时钟信号线CLK1-CLKm中一条连接以接收第二时钟信号，从而将第二时钟信号作为输出信号输出至输出端OUT。
例如，输出端OUT可以包括多个输出端，例如包括移位输出端和至少一个扫描信号输出端，从而将输出信号例如时钟信号端CLK提供的第二时钟信号输出至移位输出端和扫描信号输出端，以提高该移位寄存器单元500的驱动能力。例如，在本公开的至少一个实施例提供的移位寄存器单元中，至少一个扫描信号输出端包括一个扫描信号输出端。例如，移位输出端用于为下一级移位寄存器单元500提供输入信号以及复位信号，扫描信号输出端用 于为显示面板中一行像素单元的像素电路提供驱动信号。这样可以减少像素区中的负载和信号对级联的移位寄存器单元的影响。例如，移位输出端和扫描信号输出端输出相同的输出信号。需要注意的是，在其他示例中，当包括多个扫描信号输出端时，各个扫描信号输出端也可以输出不同的输出信号，具体的设置根据实际情况而定，本公开的实施例对此不作限制。
第一节点控制电路130分别与第二节点N2和第三节点N3连接，且配置为响应于输入信号，控制第二节点N2和第三节点N3的电平。例如，该第一节点控制电路130可以配置为和第二节点N2、第三节点N3、第二电压端VGL2(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及输入端INT连接，从而可以在输入端INT输入的输入信号的控制下，使得第二节点N2和第三节点N3和第二电压端VGL2或低电压端电连接，以保证在拉高第一节点N1的阶段，拉低第二节点N2和第三节点N3的电平至第二电压。
请注意，本公开实施例中提供的移位寄存器单元的“有效输出电平”指的是能够使得与之连接的显示面板的像素电路中的开关晶体管被导通从而可以向像素电路中写入数据信号的电平，相应地“无效输出电平”指的是不能使得与之连接的像素电路中的开关晶体管被导通(即，该开关晶体管被截止)的电平。根据像素电路中的开关晶体管的类型(N型或P型)等因素，有效输出电平可以比无效输出电平高或者低。通常，移位寄存器单元在工作期间于输出端输出方波脉冲信号，有效输出电平对应于该方波脉冲信号的方波脉冲部分的电平，而无效输出电平则对应于非方波脉冲部分的电平。
在一些示例中，如图10所示，该移位寄存器单元还包括第一节点复位电路150。
第一节点复位电路150与第一节点N1连接，配置为响应于复位信号对第一节点N1进行复位。例如，该第一节点复位电路150可以配置为和第一节点N1、第二电压端VGL2(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及复位端RST连接，从而可以在复位端RST输入的复位信号的控制下，使得第一节点N1和第二电压端VGL2或低电压端电连接，以对第一节点N1进行下拉复位。
如图10所示，在一些示例中，该移位寄存器单元500还包括第二节点控制电路160、第一节点降噪电路170和输出降噪电路180。
第二节点控制电路160与第一节点N1以及第二节点N2和第三节点N3连接，且配置为在第一节点N1的电平信号的控制下，对第二节点N2和第三节点N3的电平进行控制。例如，在一个示例中，第二节点控制电路160与第一节点N1、第二节点N2、第三节点N3、第二电压端VGL2、第三电压端VGH1以及第四电压端VGH2或另行提供的电压端(例如，高电压端)连接，从而将第二节点N2和第三节点N3下拉为低电平；在第一节点N1为低电平时，使得第二节点N2和第三节点N3与第三电压端VGH1或第四电压端VGH2其中一个连接，且配置为在第一节点N1例如为高电平时，使得第二节点N2和第三节点N3与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，从而将第二节点N2和第三节点N3下拉为低电平。
例如，在另一个示例中，第二节点N2的电平受第一节点N1的电平和第三电压端VGH1提供的第三电压控制，第三节点N3的电平受第一节点N1的电平和第四电压端VGH2提供的第四电压控制，具体的连接方式将在下面进行详细地介绍。
例如，在一个示例中，该第三电压端VGH1和第四电压端VGH2可以被设置为交替输入高电平，即第三电压端VGH1输入高电平时，第四电压端VGH1输入低电平，而第三电压端VGH1输入低电平时，第四电压端VGH2输入高电平，从而，第二节点N2和第三节点N3交替工作，以使得与其相连的晶体管可以交替工作，延长这些晶体管的使用寿命。例如，在另一个示例中，该第三电压端VGH1和第四电压端VGH2也可以用交替提供高电平(在实现的晶体管为P型时，则为直流低电平)的时钟信号端代替，本公开的实施例对此不作限制。
第一节点降噪电路170与第一节点N1以及第二节点N2、第三节点N3连接，且配置为在第二节点N2和第三节点N3的电平的控制下，对第一节点N1进行降噪。例如，第一节点降噪电路170与第一节点N1、第二节点N2、第三节点N3以及第二电压端VGL2连接，且配置为在第二节点N2和第三节点N3例如为高电平时导通，使得第一节点N1与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，将第一节N1的电位下拉至非工作电位，以实现对第一节点N1降噪。
输出降噪电路180与第二节点N2、第三节点N3以及输出端OUT连接，且配置为在第二节点N2和第三节点N3的电平的控制下，对输出端OUT进行降噪。例如，输出降噪电路180与第二节点N2、第三节点N3、第二电压端VGL2以及输出端OUT连接，且配置为在第二节点N2例如为高电平时导通，使得输出端OUT与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，以实现对输出端OUT降噪。
如图10所示，在另一些示例中，移位寄存器单元500还包括总复位电路190。
例如，总复位电路190与第一节点N1连接，配置为响应于总复位信号对第一节点N1进行复位。例如，该总复位电路190可以配置为和第一节点N1、第二电压端VGL2(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及总复位端TRST连接，从而可以在总复位端TRST输入的总复位信号的控制下，使得第一节点N1和第二电压端VGL2或低电压端电连接，以对第一节点N1进行下拉复位。
例如，第一电压端VGL1配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，这里将该直流低电平信号称为第一电压，例如，以下各实施例与此相同，不再赘述。
例如，第二电压端VGL2配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，这里将该直流低电平信号称为第二电压，例如，该第二电压可以小于或等于第一电压，以下各实施例与此相同，不再赘述。
例如，第三电压端VGH1配置为提供直流高电平信号，将其提供的信号称为第三电压，第四电压端VGH2也配置为提供直流高电平信号，将其提供的信号称为第四电压，例如， 第三电压和第四电压可以是相同的电压，且均大于第一电压和第二电压，以下各实施例与此相同，不再赘述。
图11为图10中所示的移位寄存器单元的一种具体实现示例的电路图。如图11所示，该移位寄存器单元500包括第二晶体管至第二十九晶体管T2-T29，以及还包括存储电容C。需要注意的是，在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
输入电路110可以实现为第四晶体管T4。第四晶体管T4的栅极和第一极彼此电连接，且配置为都和输入端INT连接以接收输入信号，第二极配置为和第一节点N1连接，从而当第四晶体管T4由于输入端INT接收到的导通信号(例如，高电平信号)导通时，使用该导通信号以对第一节点N1进行充电，使其处于高电平。例如，第四晶体管T4的栅极和第一极也可以分别和输入端INT或其他的高电压端(例如第三电压端VGH1或第四电压端VGH2)连接，本公开的实施例对此不作限制。
输出电路120可以实现为包括第二晶体管T2、第三晶体管T3和存储电容C。第二晶体管T2的栅极和第一节点N1连接，第二晶体管T2的第一极和时钟信号端CLK连接以接收第二时钟信号，第二晶体管T2的第二极和移位输出端CR连接。第三晶体管T3的栅极和第一节点N1连接，第三晶体管T3的第一极和时钟信号端CLK连接以接收第二时钟信号，第三晶体管T3的第二极和扫描信号输出端OUT1(即图3中所示的输出端Gout)连接。存储电容C的第一极和第一节点N1连接，存储电容C的第二极和扫描信号输出端OUT1连接。需要注意的是，不限于此，移位寄存器单元还可以包括更多的输出信号，以及与其对应的扫描信号输出端。
例如，时钟信号端CLK和图3所示的时钟信号线CLK1-CLKm连接以接收上述实施例中的第二时钟信号。
第一节点控制电路130可以实现为第十四晶体管T14和第二十四晶体管T24。第十四晶体管T14的栅极和输入端INT连接以接收输入信号，第十四晶体管T14的第一极和第一极和第二节点N2连接，第十四晶体管T14的第二极和第二电压端VGL2连接，第二十四晶体管T24的栅极和和输入端INT连接以接收输入信号，第二十四晶体管T24的第一极和第一极和第三节点N3连接，第二十四晶体管T24的第二极和第二电压端VGL2连接。
第一节点复位电路150可以实现为第五晶体管T5。第五晶体管T5的栅极配置为和复位端RST连接以接收复位信号，第一极和第一节点N1连接，第二极和第二电压端VGL2连接以接收第二电压。第五晶体管T5响应于复位信号而导通时，将第一节点N1和第二电压端VGL2电连接，从而可以对第一节点N1进行复位。例如，复位端RST和与其级联的移位寄存器的输出端连接，以实现在栅极扫描信号的移位输出的过程中对该级移位寄存器单元的第一节点N1进行实时复位，以避免输出端的误输出。
总复位电路190可以实现为第六晶体管T6。第六晶体管T6的栅极和总复位端TRST连接以接收总复位信号，第一极和第一节点N1连接，第二极和第二电压端VGL2连接以接收 第二电压。第六晶体管T6响应于总复位信号而导通时，将第一节点N1和第二电压端VGL2电连接，从而可以对第一节点N1进行复位。例如，该总复位电路190配置为在一帧图像的显示阶段的起始阶段或一帧图像的显示阶段的结束阶段，对所有级联的移位寄存器单元进行全局复位。例如，该总复位信号的时序早于控制一帧图像的显示阶段的起始时的触发信号(将在后面进行详细地介绍)，从而可以在一帧图像的显示阶段的起始阶段对所有的移位寄存器单元的第一节点N1进行复位，以避免显示画面出现异常。
例如，在一个示例中，第二节点控制电路160可以实现为第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。第七晶体管T7的栅极和第一控制节点CN1连接，第一极和第三电压端VGH1连接以接收第三电压，第二极和第二节点N2连接；第八晶体管T8的栅极和第一节点N1连接，第一极和第二节点N2连接，第二极和第二电压端VGL2连接以接收第二电压。第九晶体管T9的栅极和其自身的第一极彼此电连接，且配置为都和第三电压端VGH1连接以接收第三电压，第二极和第一控制节点CN1连接；第十晶体管T10的栅极和第一节点N1连接，第一极和第一控制节点CN1连接，第二极和第二电压端VGL2连接以接收第二电压。
例如，在另一个示例中，第二节点控制电路160还包括第二十七晶体管T27、第二十八晶体管T28、第二十九晶体管T29和第二十晶体管T20。第二十七晶体管T27的栅极和第二控制节点CN2连接，第一极和第四电压端VGH2连接以接收第四电压，第二极和第三节点N3连接；第二十八晶体管T28的栅极和第一节点N1连接，第一极和第三节点N3连接，第二极和第二电压端VGL2连接以接收第二电压。第二十九晶体管T29的栅极和其自身的第一极彼此电连接，且配置为都和第四电压端VGH2连接以接收第四电压，第二极和第二控制节点CN2连接；第二十晶体管T20的栅极和第一节点N1连接，第一极和第二控制节点CN2连接，第二极和第二电压端VGL2连接以接收第二电压。
第一节点降噪电路170可以实现为第十一晶体管T11和第二十一晶体管T21。第十一晶体管T11的栅极和第二节点N2连接，第一极和第一节点N1连接，第二极和第二电压端VGL2连接以接收第二电压。第十一晶体管T11在第二节点N2为高电位时导通，将第一节点N1和第二电压端VGL2连接，从而可以对第一节点N1下拉以实现降噪。第二十一晶体管T21的栅极和第三节点N3连接，第一极和第一节点N1连接，第二极和第二电压端VGL2连接以接收第二电压。第二十一晶体管T21在第三节点N3为高电位时导通，将第一节点N1和第二电压端VGL2连接，从而可以对第一节点N1下拉以实现降噪。例如，第十一晶体管T11和第二十一晶体管T21分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
例如，在一个示例中，输出端OUT包括移位输出端CR和一个扫描信号输出端OUT1(即栅极驱动电路的输出端Gout)，输出降噪电路180可以实现为第十二晶体管T12、第二十二晶体管T22、第十三晶体管T13和第二十三晶体管T23。第十二晶体管T12和第二十二晶体管T22用于对移位输出端CR降噪，第十三晶体管T13和第二十三晶体管T23用 于对扫描信号输出端OUT1降噪。当包括更多的扫描信号输出端时，该输出降噪电路180还可以包括更多的晶体管以实现对扫描信号输出端的降噪。
第十二晶体管T12的栅极和第二节点N2连接，第一极和移位输出端CR连接，第二极和第二电压端VGL2连接以接收第二电压。第十二晶体管T12在第二节点N2为高电位时导通，将移位输出端CR和第二电压端VGL2连接，从而可以对移位输出端CR降噪。第二十二晶体管T22的栅极和第三节点N3连接，第一极和移位输出端CR连接，第二极和第二电压端VGL2连接以接收第二电压。第二十二晶体管T22在第三节点N3为高电位时导通，将移位输出端CR和第二电压端VGL2连接，从而可以对移位输出端CR降噪。例如，第十二晶体管T12和第二十二晶体管T22分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
第十三晶体管T13的栅极和第二节点N2连接，第一极和扫描信号输出端OUT1连接，第二极和第一电压端VGL1连接以接收第一电压。第十三晶体管T13在第二节点N2为高电位时导通，将扫描信号输出端OUT1和第一电压端VGL1连接，从而可以对扫描信号输出端OUT1降噪。第二十三晶体管T23的栅极和第三节点N3连接，第一极和扫描信号输出端OUT1连接，第二极和第一电压端VGL1连接以接收第一电压。第二十三晶体管T23在第三节点N3为高电位时导通，将扫描信号输出端OUT1和第一电压端VGL1连接，从而可以对扫描信号输出端OUT1降噪。例如，第十三晶体管T13和第二十三晶体管T23分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一节点N1、第二节点N2、第三节点N3、第一控制节点CN1和第二控制节点CN2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元500中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
图12为本公开至少一实施例提供的一种移位寄存器单元的驱动时序图。图12中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号。
例如，在一个示例中，下面结合图12所示的信号时序图，对图11中所示的栅极驱动电路10的第N级移位寄存器单元500的工作原理进行说明。该移位寄存器单元500的工作原理如下。
在第一阶段1，输入端INT提供高电平，时钟信号端CLK提供第二时钟信号的低电平，因此，第四晶体管T4导通，第一节点N1被充电至第一高电平，同时，第十四晶体管T14和第二十四晶体管T24导通，使得第二节点N2和第三节点N3被下拉至低电平。在此阶段，第二晶体管T2和第三晶体管T3响应于第一节点N1的第一高电平导通，从而将时钟信号端CLK提供的第二时钟信号的低电平输出至移位输出端CR和扫描信号输出端OUT1。
在第二阶段2，输入端INT输入低电平，时钟信号端CLK提供第二时钟信号的高电平，存储电容C的第二极由低电平变为高电平，且根据电容两端的电压不能突变这一特性，存储电容C第一极(即第一节点N1)的电压被自举，因此，在此阶段，第一节点N1被充电至第二高电平，使得第二晶体管T2和第三晶体管T3响应于第一节点N1的第二高电平导通，同时，在此阶段，移位寄存器单元的移位输出端CR和扫描信号输出端OUT1输出高电平。
例如，在此阶段，当第二时钟信号采用图9所示的波形时，根据电容两端的电压不能突变这一特性，存储电容C第一极(即第一节点N1)的电压被自举，因此，在此阶段，第一节点N1被充电至第三子电平VGH5，使得第一节点N1的电压被自举的更高，从而可以使得第二晶体管T2和第三晶体管T3导通的更彻底，有利于第二时钟信号的输出。
在第三阶段3，时钟信号端CLK提供第二时钟信号的低电平，存储电容C的第二极由高电平变为低电平，且根据电容两端的电压不能突变这一特性，存储电容C第一极(即第一节点N1)的电压被变为第一高电平，因此，在此阶段，使得第二晶体管T2和第三晶体管T3响应于第一节点N1的第一高电平导通，移位寄存器单元的移位输出端CR和扫描信号输出端OUT1输出第二时钟信号的低电平。
在第四阶段4，复位端RST提供复位信号的高电平，因此，第五晶体管T5导通，使得第一节点N1与第二电压端VGL2连接，从而第一节点N1的电压被变为低电平，第二节点N2和第三节点N3变为高电平，因此，在此阶段，使得第二晶体管T2和第三晶体管T3响应于第一节点N1的低电平截止，第十二晶体管T12、第二十二晶体管T22、第十三晶体管T13和第二十三晶体管T23导通，使得移位寄存器单元的移位输出端CR和扫描信号输出端OUT1输出低电平。
在第一阶段1开始之前，总复位端TRST提供总复位信号的高电平，使得第六晶体管T6导通，从而可以对栅极驱动电路的所有移位寄存器单元的第一节点N1进行复位。
本公开至少一实施例还提供一种显示装置。图13为本公开至少一实施例提供的一种显示装置的示意图。例如，如图13所示，该显示装置100包括本公开任一实施例提供的显示面板1。
需要说明的是，本实施例中的显示装置100可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置100还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
本公开的实施例提供的显示装置100的技术效果可以参考上述实施例中关于显示面板的相应描述，这里不再赘述。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置100的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种显示面板，包括：栅极驱动电路、多条时钟信号线、时序控制器和多个防串行电路；其中，
    所述时序控制器配置为提供第一时钟信号；
    所述多个防串行电路与所述时序控制器和所述多条时钟信号线连接，且配置为将所述时序控制器提供的所述第一时钟信号调节为第二时钟信号，并将所述第二时钟信号输出至所述多条时钟信号线，其中，所述第二时钟信号的下降沿的下降时间小于所述第一时钟信号的下降沿的下降时间；
    所述栅极驱动电路包括多个级联的移位寄存器单元，分别和所述多条时钟信号线连接，所述栅极驱动电路配置为将所述第二时钟信号作为输出信号逐行输出；
    其中，所述多个防串行电路的每个包括至少一个电阻和至少一个电感。
  2. 根据权利要求1所述的显示面板，其中，所述至少一个电阻和所述至少一个电感串联连接或并联连接。
  3. 根据权利要求1或2所述的显示面板，其中，所述至少一个电阻的第一端和所述时序控制器连接，所述至少一个电阻的第二端和所述至少一个电感连接。
  4. 根据权利要求1-3任一所述的显示面板，其中，
    所述防串行电路的等效电阻的总阻值为1欧姆至1000欧姆；
    所述防串行电路的等效电感的总电感量为1微亨至1000微亨。
  5. 根据权利要求1或2所述的显示面板，其中，所述至少一个电阻包括第一电阻和第二电阻，所述至少一个电感包括第一电感和第二电感，
    所述第一电阻和所述第一电感并联形成第一元件，所述第二电阻和所述第二电感并联形成第二元件；
    所述第一元件和所述第二元件串联连接。
  6. 根据权利要求5所述的显示面板，其中，所述第一元件的等效电阻和所述第二元件的等效电阻的总阻值为1欧姆至1000欧姆；或者，
    所述第一元件的等效电感和所述第二元件的等效电感的总电感量为1微亨至1000微亨。
  7. 根据权利要求1-6任一所述的显示面板，其中，所述第一时钟信号包括在时域上按顺序排布的第一电平和第二电平，所述第二时钟信号包括在所述时域上按顺序排布的第三电平和第四电平；
    所述第一电平高于所述第二电平，所述第三电平高于所述第四电平；
    所述第四电平包括第一子电平和第二子电平；
    在所述时域上，所述第二子电平位于所述第三电平和所述第一子电平之间，
    其中，所述第二子电平低于所述第一子电平。
  8. 根据权利要求7所述的显示面板，其中，所述第一电平和所述第三电平相等，所述第一子电平和所述第二电平相等。
  9. 根据权利要求7或8所述的显示面板，其中，所述第三电平包括第三子电平和第四子电平，
    在所述时域上，所述第四子电平位于所述第三子电平和所述第二子电平之间，
    其中，所述第三子电平高于所述第四子电平。
  10. 根据权利要求9所述的显示面板，其中，所述第四子电平和所述第一电平相等。
  11. 根据权利要求1-6任一所述的显示面板，其中，所述第一时钟信号包括在时域上按顺序排布的第一电平和第二电平，所述第二时钟信号包括在时域上按顺序排布的第三电平和第四电平，所述第一电平高于所述第二电平，所述第三电平高于所述第四电平；
    其中，所述第二电平高于所述第四电平。
  12. 根据权利要求11所述的显示面板，其中，所述第三电平高于所述第一电平。
  13. 根据权利要求7-12任一所述的显示面板，还包括电平转换电路，配置为将所述第一时钟信号转换为所述第二时钟信号。
  14. 根据权利要求1-13任一所述的显示面板，其中，所述移位寄存器单元包括输入电路、输出电路和第一节点控制电路；其中，
    所述输入电路与第一节点连接，且配置为响应于输入信号对所述第一节点进行充电；
    所述输出电路与所述第一节点连接，且配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；
    所述第一节点控制电路分别与第二节点和第三节点连接，且配置为响应于所述输入信号，控制所述第二节点和所述第三节点的电平。
  15. 根据权利要求14所述的显示面板，其中，所述移位寄存器单元还包括：总复位电路，
    其中，所述总复位电路与所述第一节点和所述总复位端连接，且配置为从所述总复位端接收所述总复位信号并响应于所述总复位信号，对所述第一节点的电平进行控制。
  16. 根据权利要求14或15所述的显示面板，其中，所述移位寄存器单元还包括第一节点复位电路，
    其中，所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位。
  17. 根据权利要求14-16任一所述的显示面板，其中，所述移位寄存器单元还包括第二节点控制电路、第一节点降噪电路和输出降噪电路；其中，
    所述第二节点控制电路分别与所述第一节点以及所述第二节点和所述第三节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点和所述第三节点的电平进行控制；
    所述第一节点降噪电路与所述第一节点以及所述第二节点和所述第三节点连接，且配 置为在所述第二节点和所述第三节点的电平信号的控制下，对所述第一节点进行降噪；
    所述输出降噪电路与所述第二节点、所述第三节点以及所述输出端连接，且配置为在所述第二节点和所述第三节点的电平信号的控制下，对所述输出端进行降噪。
  18. 根据权利要求14-17任一所述的显示面板，其中，所述输出端包括移位输出端和至少一个扫描信号输出端。
  19. 根据权利要求18所述的显示面板，其中，所述至少一个扫描信号输出端包括一个扫描信号输出端，其中，所述输出电路包括第二晶体管、第三晶体管和存储电容；其中，
    所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第二极和所述移位输出端连接；
    所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述第二时钟信号，所述第三晶体管的第二极和所述扫描信号输出端连接；
    所述存储电容的第一极和所述第一节点连接，所述存储电容的第二极和所述扫描信号输出端连接；
    所述第二时钟信号被传输至所述输出端作为所述输出信号。
  20. 根据权利要求1-19任一所述的显示面板，还包括显示区域、围绕所述显示区域的周边区域和电路板；
    其中，所述显示区域包括阵列排布的多个像素，配置为接收所述栅极驱动电路的输出信号以进行显示；
    所述栅极驱动电路、所述多条时钟信号线位于所述周边区域，所述周边区域包括转角部分，所述转角部分包括所述栅极驱动电路中的部分移位寄存器单元和所述多条时钟信号线；
    所述时序控制器和所述防串行电路位于所述电路板上。
  21. 一种显示装置，包括如权利要求1-20任一所述的显示面板。
PCT/CN2021/126858 2021-05-28 2021-10-28 显示面板及显示装置 WO2022247135A1 (zh)

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