WO2020181966A1 - 阵列基板、显示装置及驱动方法 - Google Patents

阵列基板、显示装置及驱动方法 Download PDF

Info

Publication number
WO2020181966A1
WO2020181966A1 PCT/CN2020/075899 CN2020075899W WO2020181966A1 WO 2020181966 A1 WO2020181966 A1 WO 2020181966A1 CN 2020075899 W CN2020075899 W CN 2020075899W WO 2020181966 A1 WO2020181966 A1 WO 2020181966A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
signal
adjustment
type transistor
circuit
Prior art date
Application number
PCT/CN2020/075899
Other languages
English (en)
French (fr)
Inventor
赵晶
孙继刚
赵爽
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020181966A1 publication Critical patent/WO2020181966A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to an array substrate, a display device, and a driving method.
  • an array substrate including: a gate driving circuit, a plurality of adjustment circuits, and a plurality of rows of gate lines; wherein the adjustment circuit is connected to the gate lines in a one-to-one correspondence; the adjustment The circuits are respectively connected to the gate driving circuit, the adjusting signal input terminal, and the corresponding gate line, and the adjusting circuit is configured to receive the first gate driving signal input by the gate driving circuit, and the adjusting signal input After the first gate drive signal and the adjustment signal are logically processed for the adjustment signal input from the terminal, a second gate drive signal is output to the corresponding gate line; wherein, the second gate drive signal It is a square wave signal.
  • the adjustment signal is synchronized with the clock signal of the first gate driving signal and has the same pulse width.
  • the adjustment signal is a square wave signal.
  • the adjustment signal is a sine wave signal.
  • the adjustment circuit connected to the odd-numbered rows of gate lines and the adjustment circuit connected to the even-numbered rows of gate lines input the second input from the opposite ends of the plurality of rows of gate lines to the corresponding gate lines.
  • Gate drive signal; the adjustment signal received by the adjustment circuit connected to the odd-numbered row of gate lines, and the adjustment signal received by the adjustment circuit connected to the even-numbered row of gate lines has a duty ratio of 50%, and in the same clock interval, they are opposite to each other signal.
  • the adjustment circuit includes an AND gate logic circuit.
  • the AND gate logic circuit includes: a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, and a third N-type transistor;
  • the gate of the first P-type transistor is connected to the gate driving circuit, the first electrode is connected to the first electrode of the third P-type transistor, and the second electrode is respectively connected to the gate of the third P-type transistor.
  • the gate of the third N-type transistor is connected; the gate of the second P-type transistor is connected to the adjustment signal input terminal, the first electrode is connected to the ground potential, and the second electrode is connected to the first N-type transistor.
  • the first electrode of the transistor is connected; the second electrode of the third P-type transistor is connected to the corresponding gate line; the gate of the first N-type transistor is connected to the gate drive circuit, and the second electrode is connected to the The first electrode of the second N-type transistor is connected; the gate of the second N-type transistor is connected to the adjustment signal input terminal, and the second electrode is connected to the ground potential; the first electrode of the third N-type transistor is connected to The corresponding gate line is connected, and the second pole is connected to the ground potential.
  • a display device including any of the above-mentioned array substrates.
  • a driving method applied to any of the above-mentioned array substrates comprising: receiving a first gate driving signal input by the gate driving circuit, and receiving The adjustment signal input from the adjustment signal input terminal; logically process the first gate drive signal and the adjustment signal, and output a second gate drive signal to the corresponding gate line; wherein, the second The gate drive signal is a square wave signal.
  • the adjustment signal is synchronized with the clock signal of the first gate driving signal and has the same pulse width.
  • the adjustment signal is a square wave signal.
  • the adjustment signal is a sine wave signal.
  • FIG. 1 shows a schematic diagram of waveforms of gate signals at the start and end of an array substrate in the related art
  • FIG. 2 shows a schematic diagram of the principle of the display cross-color generation of the array substrate in the related art
  • FIG. 3 shows a schematic diagram of a line picture showing cross-color display of an array substrate in the related art
  • FIG. 4 shows a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of input and output signal waveforms of the adjustment circuit in the array substrate provided by the embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of input and output signal waveforms of a regulating circuit in another array substrate provided by an embodiment of the present disclosure
  • FIG. 8 shows a schematic structural diagram of an AND gate logic circuit provided by an embodiment of the present disclosure
  • FIG. 9 shows a flow chart of the steps of the driving method provided by an embodiment of the present disclosure.
  • the Gate signal at the beginning of the scan (such as gate1) is not deformed, and the source charge can be correctly charged to the pixel through the normal on and off of the source and Gate signals; but the Gate signal at the end of the scan (such as gate1920, etc.) Due to the influence of RC loading, delay deformation occurs when the gate signal is turned off.
  • the turn-off delay of the gate of the previous row also causes the source charge of the next row to be incorrectly charged into the pixel of the previous row.
  • the pixel in the upper row contains the source charges of the current row and the next row at the same time, so that cross-color occurs.
  • the gate signal at the end of the scan will be severely deformed, and the gate signal of the previous row and the source signal of the next row will overlap, which will cause the Pixel to charge.
  • the pixels of the previous row will incorrectly charge the data signal (source charge) of the next row, resulting in cross-color display on the display screen.
  • the resistance R in RC loading is mainly generated in the data line from the near end to the far end of the panel.
  • the capacitance C is mainly due to the overlapping area of each metal layer in the vertical and parallel directions, so RC loading cannot be avoided and can only be minimized.
  • the commonly used method to reduce the RC loading delay during layout is to widen the traces to reduce the resistance R.
  • the gate layer metal in the AA area avoids overlapping with other layers of metal to reduce C.
  • it is limited by the layout wiring area
  • the limitation of RC loading still cannot completely eliminate RC loading, and as the number of resolution lines increases, RC loading will become larger and larger.
  • the array substrate includes a gate driving circuit 10, a plurality of adjustment circuits 11, and Multiple rows of gate lines 12; wherein, the adjustment circuit 11 and the gate lines 12 are connected in a one-to-one correspondence.
  • the adjusting circuit 11 is connected to the gate driving circuit 10, the adjusting signal input terminal A, and the corresponding gate line 12, respectively.
  • the adjustment circuit 11 is configured to respectively receive the first gate drive signal gate input by the gate drive circuit 10 and the adjustment signal w input by the adjustment signal input terminal A, and perform logic processing on the first gate drive signal gate and the adjustment signal w , Output the second gate drive signal gate' to the corresponding gate line 12; wherein, the second gate drive signal gate' is a square wave signal.
  • the gate driving circuit 10 may be, for example, a GOA circuit capable of generating a first gate driving signal gate.
  • the GOA circuit may include multiple GOA cells, and the number of GOA cells may correspond to the gate lines 12 in a one-to-one manner. If the first gate driving signal gate is directly input to the corresponding gate line 12, a cross-color display problem caused by RC loading may occur.
  • the adjustment circuit 11 may include but is not limited to an AND gate logic circuit. As long as the adjustment circuit 11 that can logically process the first gate driving signal gate and the adjustment signal w and generate a square wave signal is within the protection scope of this embodiment.
  • the adjustment signal input terminal A may be, for example, an output terminal of the Driver IC for outputting the adjustment signal w.
  • the adjustment signal w can be determined according to the specific structure of the adjustment circuit 11, etc., which is not limited in this application.
  • the array substrate may include multiple adjustment signal input terminals A one-to-one corresponding to the gate lines 12, and may also include two adjustment signal input terminals A (each adjustment signal input terminal corresponds to a type of adjustment signal), respectively
  • the adjustment circuits connected to the odd-numbered gate lines and the even-numbered gate lines are connected. The latter can reduce wiring, reduce RC loading, and reduce process difficulty, which will be described in detail in subsequent embodiments.
  • the second gate drive signal gate' output by the adjustment circuit 11 cannot be an ideal square wave signal, it only needs the fall time (for the case of turning on the pixel transistor at a high level, and turning on the pixel at a low level). In the case of transistors, the rise time) is less than the specified threshold of the second gate drive signal gate', all within the protection scope of this embodiment.
  • the designated threshold may be, for example, the duration of the I area in FIG. 1.
  • the second gate drive signal output to the gate line is a square wave signal
  • the problem of the first gate drive signal falling delay caused by RC loading is eliminated, so that the second gate of the previous row There is no overlap between the driving signal and the data signal of the next row, which can prevent the data signal of the next row from being incorrectly charged to the previous row, thereby solving the problem of cross-color display.
  • the adjustment circuit may include an AND gate logic circuit.
  • the adjustment signal w may be a square wave signal that is synchronized with the clock signal CLK of the first gate driving signal gate and has the same pulse width.
  • the first gate drive signal gate generated by the GOA unit is input to the AND gate logic circuit, and the square wave signal Square wave generated by the drive IC is also input to the AND gate logic circuit.
  • the first gate drive signal gate and the square wave signal Square After the wave passes the AND gate logic circuit and performs the AND gate logic calculation, the second gate driving signal gate′ is obtained and output to the corresponding gate line 12.
  • 5 shows a schematic diagram of the waveforms of the first gate driving signal gate, the square wave signal Square wave, and the second gate driving signal gate'.
  • the adjustment signal w is not limited to a square wave signal, for example, it can also be a sine wave signal, as long as it is synchronized with the clock signal CLK of the first gate drive signal gate and has the same pulse width, it is within the protection scope of this application. Inside.
  • the adjusting circuit 11 connected to the odd-numbered gate lines and the adjusting circuit 11 connected to the even-numbered gate lines respectively extend from opposite ends of the multi-row gate lines to the corresponding gates.
  • Line 12 inputs the second gate driving signal gate'.
  • the duty ratio of the adjustment signal received by the adjustment circuit 11 connected to the odd-numbered gate line and the adjustment signal received by the adjustment circuit 11 connected to the even-numbered gate line is 50%, and in the same clock interval, they are opposite to each other Phase signal.
  • the adjustment signal received by the adjustment circuit 11 connected to the odd rows of gate lines may be a square wave signal Square wave1 that is synchronized with the clock signal CLK of the first gate drive signal gate of each odd row and has the same pulse width.
  • the adjustment signal received by the adjustment circuit 11 connected to the even rows of gate lines may be a square wave signal Square wave 2 that is synchronized with the clock signal CLK of the first gate drive signal gate of each even row and has the same pulse width.
  • a square wave signal Square wave1 and Square wave2 can be output from the left and right sides of the Driver IC (corresponding to the two adjustment signal input terminals), and the square wave signal Square wave1/Square wave2 width remains the same as the CLK width of the same row Consistent, and the duty cycle is 50%.
  • the Gate signal generated by the gate driving circuit 10 enters the gate line, the Gate signal and the Square wave signal are processed by an AND gate to output a Gate' signal.
  • the Gate' signal is a square wave signal and is used to control the conduction of each row of TFTs. And turn off.
  • the Gate’ signal will not be deformed due to the RC loading delay, so the problem of cross-color display will no longer occur.
  • the specific working process of the array substrate is as follows:
  • the left and right sides of the Driver IC each output a square wave signal Square wave1 and Square wave2, which are respectively input to the adjustment circuit 11 of the parity row.
  • the gate signal generated by the gate driving circuit 10 Due to the influence of RC loading, the gate signal generated by the gate driving circuit 10 has a drop delay problem for the odd-numbered and even-numbered gate signals actually generated.
  • the square wave signal Square wave1 and the odd-numbered gate signal are phase-anded, and the odd-numbered line Gate' square wave signal is output, and the square wave signal Square wave2 is phase-anded with the even-numbered gate signal, and the even-numbered line Gate' square wave signal is output. Control the on and off of each row of TFTs.
  • the odd-numbered Gate’ square wave signal and the even-numbered Gate’ square wave signal have no overlap, and each cooperates with the source signal to control the charge of the pixel, which completely solves the problem of display cross-color.
  • the AND gate logic circuit may include: a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, and a first N-type transistor N1, the second N-type transistor N2 and the third N-type transistor N3.
  • the gate of the first P-type transistor P1 is connected to the gate drive circuit (shown as B in FIG. 8), the first pole is connected to the first pole of the third P-type transistor P3, and the second pole is connected to the third pole respectively.
  • the gate of the P-type transistor P3 and the gate of the third N-type transistor N3 are connected.
  • the gate of the second P-type transistor P2 is connected to the adjustment signal input terminal (shown by A in FIG. 8), the first electrode is connected to the ground potential, and the second electrode is connected to the first electrode of the first N-type transistor N1.
  • the second pole of the third P-type transistor P3 is connected to the corresponding gate line (shown by Y in FIG. 8).
  • the gate of the first N-type transistor N1 is connected to the gate driving circuit, and the second electrode is connected to the first electrode of the second N-type transistor N2.
  • the gate of the second N-type transistor N2 is connected to the adjustment signal input terminal, and the second electrode is connected to the ground potential.
  • the first pole of the third N-type transistor N3 is connected to the corresponding gate line, and the second pole is connected to the ground potential.
  • a B Y AB 0 0 0 0 1 0 1 0 0 1 1 1
  • the first gate drive signal gate generated by each row of GOA is processed through an AND gate logic circuit.
  • This design will not affect the high-density circuits in the original Panel. The reasons can be explained from the following three aspects: 1
  • the entire panel design contains more
  • Each circuit is composed of TFT tubes, such as GOA unit, MUX unit, ESD, etc.
  • the design needs to cooperate with the driver IC timing to output a square wave signal at the left and right ends of the gate line.
  • LTPS TDDI/Normal Driver IC can be supported. Therefore, considering the driver IC, the technical solution of this application is feasible.
  • the technical solution of the present disclosure uses an adjustment circuit to logically process the first gate drive signal output by the gate drive circuit and the adjustment signal output by the Driver IC, and solves the gate signal deformation caused by the RC loading delay and the pixel mischarging data
  • the data brings about the problem of screen cross-color display.
  • the present disclosure also provides a display device, which may include any of the above-mentioned array substrates.
  • the display device in this embodiment may be any product or component with a display function, such as a display panel, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc.
  • Another embodiment of the present application also provides a driving method, which can be applied to any of the above-mentioned array substrates.
  • the driving method may include the following steps.
  • step 901 the first gate driving signal input by the gate driving circuit is received, and the adjustment signal input from the adjustment signal input terminal is received.
  • this step can be performed by a regulating circuit.
  • step 902 logic processing is performed on the first gate driving signal and the adjustment signal, and the second gate driving signal is output to the corresponding gate line; where the second gate driving signal is a square wave signal.
  • this step can be performed by a regulating circuit.
  • the adjustment signal may be a square wave signal synchronized with the clock signal of the first gate driving signal and having the same pulse width.
  • the present application provides an array substrate, a display device, and a driving method.
  • the array substrate includes: a gate driving circuit, a plurality of adjustment circuits, and a plurality of rows of gate lines; wherein the adjustment circuit is connected to the gate line in a one-to-one correspondence
  • the adjustment circuit is respectively connected to the gate drive circuit, the adjustment signal input terminal, and the corresponding gate line, the adjustment circuit is configured to receive the first gate drive signal input by the gate drive circuit, and the The adjustment signal input from the adjustment signal input terminal performs logical processing on the first gate drive signal and the adjustment signal, and then outputs a second gate drive signal to the corresponding gate line; wherein, the second gate drive signal
  • the gate drive signal is a square wave signal.
  • the second gate driving signal output to the gate line is a square wave signal, the problem of the first gate driving signal falling delay caused by RC loading is eliminated, and the data signal of the next row is prevented from being incorrectly charged to the previous row, thereby solving the problem of string Color display problem.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种阵列基板、显示装置及驱动方法，其中阵列基板包括：栅极驱动电路(10)、多个调节电路(11)和多行栅线(12)；其中，调节电路(11)与栅线(12)一一对应连接；调节电路(11)分别与栅极驱动电路(10)、调节信号输入端，以及对应的栅线(12)连接，调节电路(11)被配置为分别接收栅极驱动电路(10)输入的第一栅极驱动信号，及调节信号输入端输入的调节信号，将第一栅极驱动信号及调节信号进行逻辑处理后，向对应的栅线(12)输出第二栅极驱动信号；其中，第二栅极驱动信号为方波信号。

Description

阵列基板、显示装置及驱动方法
相关申请的交叉引用
本申请要求于2019年3月12日递交的中国专利申请201910185099.X的优先权。
技术领域
本公开涉及阵列基板、显示装置及驱动方法。
背景技术
目前科技的发展越来越迅速，伴随着科技的飞速发展手机行业也有了突飞猛进的发展，传统的功能性手机的仅有的通讯功能已经无法满足现在人们对手机的要求，人们对手机的要求增加了音视频播放等功能，但是视频播放时需要能显示更多的细节，这就需要手机显示屏的分辨率越来越高。
然而，在高分辨率显示装置中，经常出现串色显示的现象，严重影响显示效果。
因此，需要具有改进的显示效果的显示装置。
发明内容
根据本公开的一个方面，提供了一种阵列基板，包括：栅极驱动电路、多个调节电路和多行栅线；其中，所述调节电路与所述栅线一一对应连接；所述调节电路分别与栅极驱动电路、调节信号输入端，以及对应的栅线连接，所述调节电路被配置为分别接收所述栅极驱动电路输入的第一栅极驱动信号，及所述调节信号输入端输入的调节信号，将所述第一栅极驱动信号及所述调节信号进行逻辑处理后，向所述对应的栅线输出第二栅极驱动信号；其中，所述第二栅极驱动信号为方波信号。
在一个示例中，所述调节信号与所述第一栅极驱动信号的时钟信号同步且脉冲宽度相同。
在一个示例中，所述调节信号为方波信号。
在一个示例中，所述调节信号为正玄波信号。
在一个示例中，所述多行栅线中，奇数行栅线连接的调节电路和偶数行栅线连接的调节电路分别从所述多行栅线相对的两端向对应的栅线输入第二栅极驱动信号；奇数行栅线连接的调节电路接收的调节信号，与偶数行栅线连接的调节电路接收的调节信号的占空比为50％，且在同一时钟区间内，互为反相信号。
在一个示例中，所述调节电路包括与门逻辑电路。
在一个示例中，所述与门逻辑电路包括：第一P型晶体管、第二P型晶体管、第三P型晶体管、第一N型晶体管、第二N型晶体管和第三N型晶体管；所述第一P型晶体管的栅极与所述栅极驱动电路连接，第一极与所述第三P型晶体管的第一极连接，第二极分别与所述第三P型晶体管的栅极以及所述第三N型晶体管的栅极连接；所述第二P型晶体管的栅极与所述调节信号输入端连接，第一极与地电位连接，第二极与所述第一N型晶体管的第一极连接；所述第三P型晶体管的第二极与对应的栅线连接；所述第一N型晶体管的栅极与所述栅极驱动电路连接，第二极与所述第二N型晶体管的第一极连接；所述第二N型晶体管的栅极与所述调节信号输入端连接，第二极与地电位连接；所述第三N型晶体管的第一极与对应的栅线连接，第二极与地电位连接。
根据本公开的另一方面，提供了一种显示装置，包括任一以上所述的阵列基板。
在本公开的另一方面，还提供了了一种驱动方法，应用于任一以上所述的阵列基板，所述方法包括：接收所述栅极驱动电路输入的第一栅极驱动信号，接收所述调节信号输入端输入的调节信号；对所述第一栅极驱动信号及所述调节信号进行逻辑处理，向所述对应的栅线输出第二栅极驱动信号；其中，所述第二栅极驱动信号为方波信号。
在一个示例中，所述调节信号与所述第一栅极驱动信号的时钟信号同步且脉冲宽度相同。
在一个示例中，所述调节信号为方波信号。
在一个示例中，所述调节信号为正玄波信号。
附图说明
图1示出了相关技术中阵列基板起始端和结束端gate信号的波形示意图；
图2示出了相关技术中阵列基板显示串色产生原理的示意图；
图3示出了相关技术中阵列基板发生串色显示的H one line图片示意图；
图4示出了本公开实施例提供的阵列基板的结构示意图；
图5示出了本公开实施例提供的阵列基板中调节电路的输入、输出信号波形示意图；
图6示出了本公开实施例提供的另一阵列基板的结构示意图；
图7示出了本公开实施例提供的另一阵列基板中调节电路的输入、输出信号波形示意图；
图8示出了本公开实施例提供的与门逻辑电路的结构示意图；
图9示出了本公开实施例提供的驱动方法的步骤流程图。
具体实施方式
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细的说明。
研究发现，显示屏的分辨率越来越高，也就意味着显示屏的行数越来越多，由于显示屏内部存在RC loading，导致显示屏内部的Gate信号在扫描起始端和结束端信号差异很大，gate信号在末端时会发生严重的变形，参照图1，这样会导致末端Pixel在充电时，下一行的数据信号会错充入上一行中，造成了屏幕的串色显示，如图2所示，I区域为正常GOE(栅线输出能力，Gate Output Enable))时间，II区域为发生串色的区域。扫描起始端的Gate信号(如gate1)由于信号未发生变形，通过source和Gate信号的正常导通和关断可以正确地对pixel进行source电荷充电；但扫描结束端的Gate信号(如gate1920等)由于RC loading的影响，Gate信号关断时产生延时变形，当下一行Gate打开进行source电荷充电时，上一行Gate的关断延时也使得下一行的source电荷错充入上一行的pixel中，这样上一行的pixel中同时包含本行和下一行的source电荷，从而发生了串色。随着RC loading的持续增大，Gate信号末端变形越来越大，错充的source电荷越来越多，串色显示越来越严重。以H one line图片显示为例，source电压在0和+255二者之间变化，实际扫描显示末端White(+255)变为高灰阶显示，Black(0)变为低灰阶显示，如图3所示。
综上，由于显示屏内部RC loading延迟的原因，导致扫描末端的Gate信号会发生严重的变形，上一行的gate信号与下一行的source信号之间发生交叠，进而导致Pixel(像素)在充电时，上一行像素会把下一行的数据信号(source电荷)错充进去，导致显示屏的串色显示。
RC loading中的电阻R主要产生于panel近端到远端Data line走线中，电容C主要由于各金属层存在垂直和平行方向的交叠面积，故RC loading无法避免，只能尽量减小。目前常用的减小RC loading延迟的方法是在Layout时，走线加宽以减小电阻R，AA区Gate层金属避免与其他层金属交叠以减小C，但是，受限于Layout布线区域的限制，依然无法彻底消除RC loading，且随着分辨率行数的增加，RC loading会越来越大。
由于单纯依靠Array布线来解决RC loading延迟是不可能的，即RC loading无法避 免且分辨率越高RC loading越大，因此Gate信号的延迟变形必然存在，高分辨率显示的串色问题会更加严重，屏幕串色显示的问题亟待解决。
为了解决由于Gate信号的RC loading延迟产生的屏幕串色显示问题，本申请一实施例提供了一种阵列基板，参照图4，该阵列基板包括：栅极驱动电路10、多个调节电路11和多行栅线12；其中，调节电路11与栅线12一一对应连接。
调节电路11分别与栅极驱动电路10、调节信号输入端A，以及对应的栅线12连接。调节电路11被配置为分别接收栅极驱动电路10输入的第一栅极驱动信号gate及调节信号输入端A输入的调节信号w，将第一栅极驱动信号gate及调节信号w进行逻辑处理后，向对应的栅线12输出第二栅极驱动信号gate’；其中，第二栅极驱动信号gate’为方波信号。
栅极驱动电路10例如可以是能够产生第一栅极驱动信号gate的GOA电路等。GOA电路可以包括多个GOA单元，GOA单元的数量可以与栅线12一一对应。如果直接将第一栅极驱动信号gate输入给对应的栅线12，可能出现由于RC loading导致的串色显示问题。
调节电路11可以包括但不仅限于与门逻辑电路，只要能够将第一栅极驱动信号gate及调节信号w进行逻辑处理并生成方波信号的调节电路11均在本实施例保护范围之内。
调节信号输入端A例如可以是Driver IC的一个输出端，用于输出调节信号w。调节信号w可以根据调节电路11的具体结构等确定，本申请对其不作限定。在实际应用中，阵列基板可以包括多个与栅线12一一对应的调节信号输入端A，还可以包括两个调节信号输入端A(每个调节信号输入端对应一种调节信号)，分别与奇数行栅线连接的调节电路以及偶数行栅线连接的调节电路连接，由于后者可以减少布线，减小RC loading，降低工艺难度，后续实施例会详细介绍。
需要说明的是，由于调节电路11输出的第二栅极驱动信号gate’不可能为理想的方波信号，因此只要下降时间(对于高电平打开pixel晶体管的情况，而对于低电平打开pixel晶体管的情况则为上升时间)小于指定阈值的第二栅极驱动信号gate’均在本实施例保护范围之内。其中，指定阈值例如可以是图1中I区域的持续时间。
本实施例提供的阵列基板，由于向栅线输出的第二栅极驱动信号为方波信号，消除了RC loading引起的第一栅极驱动信号下降延迟的问题，使得上一行的第二栅极驱动信号与下一行的数据信号之间无交叠，可以避免下一行的数据信号错充到上一行，从而可以解决串色显示问题。
调节电路可以包括与门逻辑电路。调节信号w可以是与第一栅极驱动信号gate的时钟信号CLK同步且脉冲宽度相同的方波信号Square wave。
例如，GOA单元产生的第一栅极驱动信号gate输入至与门逻辑电路，同时驱动IC产生的方波信号Square wave也输入至与门逻辑电路，第一栅极驱动信号gate与方波信号Square wave经过与门逻辑电路进行与门逻辑计算后，得到第二栅极驱动信号gate’并输出至对应的栅线12。参照图5示出了第一栅极驱动信号gate、方波信号Square wave以及第二栅极驱动信号gate’的波形示意图。这样就可以消除由于RC loading产生的下降延迟，消除扫描起始端和结束端的第一栅极驱动信号gate差异过大的问题，使得所有行的第二栅极驱动信号gate’几乎没有变形(方波信号)，避免上一行的第二栅极驱动信号与下一行的数据信号之间发生交叠，从而使pixel充电时不会产生错充数据信号的问题，彻底解决由于RC loading延迟原因产生的高分辨率屏幕串色显示的问题。
需要说明的是，调节信号w不仅限于是方波信号，例如还可以是正玄波信号，只要与第一栅极驱动信号gate的时钟信号CLK同步且脉冲宽度相同的信号都在本申请保护范围之内。
一种实现方式中，参照图6，多行栅线12中，奇数行栅线连接的调节电路11和偶数行栅线连接的调节电路11分别从多行栅线相对的两端向对应的栅线12输入第二栅极驱动信号gate’。
参照图7，奇数行栅线连接的调节电路11接收的调节信号，与偶数行栅线连接的调节电路11接收的调节信号的占空比为50％，且在同一时钟区间内，互为反相信号。
奇数行栅线连接的调节电路11接收的调节信号可以是与各奇数行第一栅极驱动信号gate的时钟信号CLK同步且脉冲宽度相同的方波信号Square wave1。偶数行栅线连接的调节电路11接收的调节信号可以是与各偶数行第一栅极驱动信号gate的时钟信号CLK同步且脉冲宽度相同的方波信号Square wave2。
在实际应用中，可以由Driver IC的左右两侧(对应两个调节信号输入端)各输出一个方波信号Square wave1和Square wave2，方波信号Square wave1/Square wave2宽度保持跟同一行的CLK宽度一致，且占空比为50％。在栅极驱动电路10产生的Gate信号在进入栅线之前，Gate信号与Square wave信号经过一个与门处理输出Gate’信号，该Gate’信号为方波信号，用于控制每行TFT的导通和关断。Gate’信号不会受到RC loading延迟的影响而发生变形，因此不会再产生串色显示的问题。阵列基板的具体工作过程如下：
Driver IC的左右两侧各输出一个方波信号Square wave1和Square wave2，分别输 入奇偶行的调节电路11中。
栅极驱动电路10产生的Gate信号由于RC loading的影响，实际产生的奇数行和偶数行Gate信号均存在下降延迟问题。
方波信号Square wave1与奇数行Gate信号进行相与运算，输出奇数行Gate’方波信号，方波信号Square wave2与偶数行Gate信号进行相与运算，输出偶数行Gate’方波信号，用于控制每行TFT的导通关断。
奇数行Gate’方波信号与偶数行Gate’方波信号无交叠，各自与source信号配合控制对pixel的电荷的充电，彻底解决显示串色问题。
本实施例提供了一种与门逻辑电路，参照图8，该与门逻辑电路可以包括：第一P型晶体管P1、第二P型晶体管P2、第三P型晶体管P3、第一N型晶体管N1、第二N型晶体管N2和第三N型晶体管N3。
例如，第一P型晶体管P1的栅极与栅极驱动电路(图8中用B示出)连接，第一极与第三P型晶体管P3的第一极连接，第二极分别与第三P型晶体管P3的栅极以及第三N型晶体管N3的栅极连接。
第二P型晶体管P2的栅极与调节信号输入端(图8中用A示出)连接，第一极与地电位连接，第二极与第一N型晶体管N1的第一极连接。
第三P型晶体管P3的第二极与对应的栅线(图8中用Y示出)连接。
第一N型晶体管N1的栅极与栅极驱动电路连接，第二极与第二N型晶体管N2的第一极连接。
第二N型晶体管N2的栅极与调节信号输入端连接，第二极与地电位连接。
第三N型晶体管N3的第一极与对应的栅线连接，第二极与地电位连接。
采用与门逻辑电路进行与门逻辑计算的真值表如下表1所示。
A B Y＝AB
0 0 0
0 1 0
1 0 0
1 1 1
通过一个与门逻辑电路对每一行GOA产生的第一栅极驱动信号gate进行处理，这样的设计不会影响原本Panel中高密集电路，原因可以从以下三个方面解释：①整个panel设计中包含多个电路，均由TFT管组成，如GOA单元、MUX单元、ESD等，Array Layout (线路布置)中，由于各电路之间无交叠，故耦合电容几乎为0，因此panel设计中个电路不会相互影响；②手机扫描帧频为60Hz，这一量级的频率对于Panel设计中各电路电路的耦合电容几乎为0；③与门逻辑电路或调节电路与各行GOA不存在交叠，且与门逻辑电路或调节电路的输出作为栅线的输入信号，相当于在原本GOA电路的基础上进行改良，故无影响。因此，从Array方面考虑，本申请技术方案可行。
另外，设计中需要配合Driver IC时序，在栅线左右两端各输出一个方波信号，目前LTPS TDDI/Normal Driver IC均可支持，因此，从Driver IC方面考虑，本申请技术方案可行。
本公开的技术方案通过调节电路，对栅极驱动电路输出的第一栅极驱动信号和Driver IC输出的调节信号进行逻辑处理，解决了由于RC loading延迟产生的Gate信号变形，以及pixel错充数据资料带来屏幕串色显示的问题。
本公开还提供了一种显示装置，可以包括任一以上所述的阵列基板。
需要说明的是，本实施例中的显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请另一实施例还提供了一种驱动方法，可以应用于任一以上所述的阵列基板，参照图9，该驱动方法可以包括以下步骤。
在步骤901，接收栅极驱动电路输入的第一栅极驱动信号，接收调节信号输入端输入的调节信号。例如，该步骤可以由调节电路执行。
在步骤902中，对第一栅极驱动信号及调节信号进行逻辑处理，向对应的栅线输出第二栅极驱动信号；其中，第二栅极驱动信号为方波信号。例如，该步骤可以由调节电路执行。
调节信号可以是与第一栅极驱动信号的时钟信号同步且脉冲宽度相同的方波信号。
本申请提供了一种阵列基板、显示装置及驱动方法，其中阵列基板包括：栅极驱动电路、多个调节电路和多行栅线；其中，所述调节电路与所述栅线一一对应连接；所述调节电路分别与栅极驱动电路、调节信号输入端，以及对应的栅线连接，所述调节电路被配置为分别接收所述栅极驱动电路输入的第一栅极驱动信号，及所述调节信号输入端输入的调节信号，将所述第一栅极驱动信号及所述调节信号进行逻辑处理后，向所述对应的栅线输出第二栅极驱动信号；其中，所述第二栅极驱动信号为方波信号。由于向栅线输出的第二栅极驱动信号为方波信号，消除了RC loading引起的第一栅极驱动信号下降延迟的问题，避免下一行的数据信号错充到上一行，从而可以解决串色显示问题。
本公开提供的驱动方法的过程与前述实施例提供的阵列基板的工作过程相同，这里不再赘述。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种阵列基板、显示装置及驱动方法，进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (12)

  1. 一种阵列基板，包括：
    栅极驱动电路、多个调节电路和多行栅线；其中：
    所述调节电路与所述栅线一一对应连接；
    所述调节电路分别与栅极驱动电路、调节信号输入端以及对应的栅线连接，所述调节电路被配置为：分别接收所述栅极驱动电路输入的第一栅极驱动信号及所述调节信号输入端输入的调节信号，将所述第一栅极驱动信号及所述调节信号进行逻辑处理后，向所述对应的栅线输出第二栅极驱动信号，所述第二栅极驱动信号为方波信号。
  2. 根据权利要求1所述的阵列基板，其中所述调节信号与所述第一栅极驱动信号的时钟信号同步且脉冲宽度相同。
  3. 根据权利要求2所述的阵列基板，其中所述调节信号为方波信号。
  4. 根据权利要求2所述的阵列基板，其中所述调节信号为正玄波信号。
  5. 根据权利要求1所述的阵列基板，其中：
    所述多行栅线中，奇数行栅线连接的调节电路和偶数行栅线连接的调节电路分别从所述多行栅线相对的两端向对应的栅线输入第二栅极驱动信号；
    奇数行栅线连接的调节电路接收的调节信号，与偶数行栅线连接的调节电路接收的调节信号的占空比为50％，且在同一时钟区间内，互为反相信号。
  6. 根据权利要求1至5任一项所述的阵列基板，其中所述调节电路包括与门逻辑电路。
  7. 根据权利要求6所述的显示面板，其中所述与门逻辑电路包括：第一P型晶体管、第二P型晶体管、第三P型晶体管、第一N型晶体管、第二N型晶体管和第三N型晶体管；
    所述第一P型晶体管的栅极与所述栅极驱动电路连接，第一极与所述第三P型晶体管的第一极连接，第二极分别与所述第三P型晶体管的栅极以及所述第三N型晶体管的栅极连接；
    所述第二P型晶体管的栅极与所述调节信号输入端连接，第一极与地电位连接，第二极与所述第一N型晶体管的第一极连接；
    所述第三P型晶体管的第二极与对应的栅线连接；
    所述第一N型晶体管的栅极与所述栅极驱动电路连接，第二极与所述第二N型晶体 管的第一极连接；
    所述第二N型晶体管的栅极与所述调节信号输入端连接，第二极与地电位连接；
    所述第三N型晶体管的第一极与对应的栅线连接，第二极与地电位连接。
  8. 一种显示装置，包括权利要求1至7任一项所述的阵列基板。
  9. 一种驱动方法，用于驱动权利要求1至7任一项所述的阵列基板，所述方法包括：
    接收所述栅极驱动电路输入的第一栅极驱动信号；
    接收所述调节信号输入端输入的调节信号；
    对所述第一栅极驱动信号及所述调节信号进行逻辑处理，向所述对应的栅线输出第二栅极驱动信号；其中，所述第二栅极驱动信号为方波信号。
  10. 根据权利要求9所述的驱动方法，其中所述调节信号与所述第一栅极驱动信号的时钟信号同步且脉冲宽度相同。
  11. [根据细则91更正 20.02.2020]　
    根据权利要求10所述的驱动方法，其中所述调节信号为方波信号。
  12. [根据细则91更正 20.02.2020]　
    根据权利要求10所述的驱动方法，其中所述调节信号为正玄波信号。
PCT/CN2020/075899 2019-03-12 2020-02-19 阵列基板、显示装置及驱动方法 WO2020181966A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910185099.X 2019-03-12
CN201910185099.XA CN109767716B (zh) 2019-03-12 2019-03-12 一种阵列基板、显示装置及驱动方法

Publications (1)

Publication Number Publication Date
WO2020181966A1 true WO2020181966A1 (zh) 2020-09-17

Family

ID=66458815

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/075899 WO2020181966A1 (zh) 2019-03-12 2020-02-19 阵列基板、显示装置及驱动方法

Country Status (2)

Country Link
CN (1) CN109767716B (zh)
WO (1) WO2020181966A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109767716B (zh) * 2019-03-12 2022-09-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101408684A (zh) * 2007-10-12 2009-04-15 群康科技(深圳)有限公司 液晶显示装置及其驱动方法
CN101772801A (zh) * 2007-08-10 2010-07-07 夏普株式会社 显示装置、显示装置的控制装置、显示装置的驱动方法、液晶显示装置、及电视接收机
CN101908310A (zh) * 2009-06-04 2010-12-08 索尼公司 像素选择控制方法、驱动电路、显示装置以及电子设备
CN106023949A (zh) * 2016-08-12 2016-10-12 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN109767716A (zh) * 2019-03-12 2019-05-17 京东方科技集团股份有限公司 一种阵列基板、显示装置及驱动方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001108966A (ja) * 1999-10-13 2001-04-20 Sharp Corp 液晶パネルの駆動方法および駆動装置
JP4474821B2 (ja) * 2002-04-16 2010-06-09 セイコーエプソン株式会社 シフトレジスタ、データ線駆動回路および走査線駆動回路
JP3715967B2 (ja) * 2002-06-26 2005-11-16 キヤノン株式会社 駆動装置及び駆動回路及び画像表示装置
JP4266616B2 (ja) * 2002-11-13 2009-05-20 キヤノン株式会社 表示装置及びその駆動制御方法
CN102436788B (zh) * 2008-10-21 2014-02-05 华映视讯（吴江）有限公司 栅极驱动模块及扫描线的控制方法
US9118908B2 (en) * 2013-01-25 2015-08-25 Innolux Corporation Two dimensional/three dimensional switchable module and a method of driving the same
CN104240631B (zh) * 2014-08-18 2016-09-28 京东方科技集团股份有限公司 Goa电路及其驱动方法、显示装置
CN104269134B (zh) * 2014-09-28 2016-05-04 京东方科技集团股份有限公司 一种栅极驱动器、显示装置及栅极驱动方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101772801A (zh) * 2007-08-10 2010-07-07 夏普株式会社 显示装置、显示装置的控制装置、显示装置的驱动方法、液晶显示装置、及电视接收机
CN101408684A (zh) * 2007-10-12 2009-04-15 群康科技(深圳)有限公司 液晶显示装置及其驱动方法
CN101908310A (zh) * 2009-06-04 2010-12-08 索尼公司 像素选择控制方法、驱动电路、显示装置以及电子设备
CN106023949A (zh) * 2016-08-12 2016-10-12 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN109767716A (zh) * 2019-03-12 2019-05-17 京东方科技集团股份有限公司 一种阵列基板、显示装置及驱动方法

Also Published As

Publication number Publication date
CN109767716A (zh) 2019-05-17
CN109767716B (zh) 2022-09-06

Similar Documents

Publication Publication Date Title
US11328672B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US11749158B2 (en) Shift register unit, gate driving circuit, display device, and driving method
US11263942B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US11263953B2 (en) Shift register unit and drive method thereof, gate drive circuit and display device
US11302276B2 (en) Gate drive circuit, touch display device and driving method
US11011088B2 (en) Shift register unit, driving method, gate drive circuit, and display device
WO2017181647A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
EP3825994A1 (en) Shift register unit, driving method therefor, gate driving circuit and display device
US11295645B2 (en) Shift register and driving method thereof, gate driving circuit and display apparatus
US10121403B2 (en) Gate turn on voltage compensating circuit, display panel, driving method and display apparatus
US11443706B2 (en) Shift register having a compensation circuit, shift register circuit and display device
WO2017107285A1 (zh) 用于窄边框液晶显示面板的goa电路
WO2016101618A1 (zh) 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
EP3400593A1 (en) Shift register, driving method, and gate electrode drive circuit
CN112216249B (zh) 栅极驱动电路及显示装置
US20210209993A1 (en) Shift register, gate driver-on-array circuit and driving method thereof, display device
US11094389B2 (en) Shift register unit and driving method, gate driving circuit, and display device
WO2019010956A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US20230274680A1 (en) Shift register unit, driving method, gate driving circuit, and display device
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
WO2020181966A1 (zh) 阵列基板、显示装置及驱动方法
CN215834233U (zh) 显示面板及显示装置
EP4207151A1 (en) Display panel and display device
WO2020187043A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20769400

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20769400

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20769400

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11.05.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20769400

Country of ref document: EP

Kind code of ref document: A1