WO2022246909A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022246909A1
WO2022246909A1 PCT/CN2021/098763 CN2021098763W WO2022246909A1 WO 2022246909 A1 WO2022246909 A1 WO 2022246909A1 CN 2021098763 W CN2021098763 W CN 2021098763W WO 2022246909 A1 WO2022246909 A1 WO 2022246909A1
Authority
WO
WIPO (PCT)
Prior art keywords
nth
thin film
scanning line
film transistor
driving
Prior art date
Application number
PCT/CN2021/098763
Other languages
English (en)
French (fr)
Inventor
田超
管延庆
刘广辉
艾飞
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/430,058 priority Critical patent/US20240038130A1/en
Publication of WO2022246909A1 publication Critical patent/WO2022246909A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • display devices As a display component of electronic equipment, display devices have been widely used in various electronic products. Among them, various driving modules are an important part of the display device, and most of them are located in the peripheral area of the display device. Drive signals need to be transmitted through drive signal lines. to the display area of the display device.
  • the present application provides a display panel and a display device to alleviate the technical problem of scanning signal distortion caused by transmission delay in the display area.
  • the present application provides a display panel, which includes a first wiring, an Nth scanning line, and an Nth auxiliary unit; at least part of the Nth scanning line is located in the display area of the display panel, and is used to transmit the N-level scanning signal, N is a positive integer; the Nth auxiliary unit is located in the display area of the display panel, the output end of the Nth auxiliary unit is electrically connected to the Nth scanning line, and the input end of the Nth auxiliary unit is connected to the Nth scanning line.
  • a wire is electrically connected, and the control terminal of the Nth auxiliary unit is electrically connected with the N+M scanning line, where M is a positive integer.
  • the Nth auxiliary unit includes at least one thin film transistor, one of the source/drain of the thin film transistor is electrically connected to the Nth scanning line, and the other of the source/drain of the thin film transistor One is electrically connected to the first wiring, and the gate of the thin film transistor is electrically connected to the N+M scanning line.
  • the Nth scan line is electrically connected to one of the sources/drains of the multiple thin film transistors, so as to construct a plurality of corresponding connection nodes on the Nth scan line; the Nth scan line The signal is input from at least one end of the Nth scan line; wherein, if the Nth level scan signal is input from one end of the Nth scan line, the density of multiple connection nodes at the other end close to the Nth scan line is greater than the number The density of connected nodes at one end close to the Nth scan line.
  • the density of the multiple connection nodes in the middle of the Nth scanning line is greater than that of the multiple connection nodes near the Nth scanning line. Density at either end of the scanline.
  • the first wiring is used to transmit a constant-voltage low-potential signal.
  • the thin film transistor is an N-channel thin film transistor, when the thin film transistor is turned on, the first wiring is used to transmit a low potential signal.
  • the first routing is the N+Xth scanning line, and X is an integer greater than or equal to 2 ; If the control terminal of the Nth auxiliary unit is connected to the N+2th scanning line, the first routing is the N+Yth scanning line, and Y is equal to 1, or Y is an integer equal to or greater than 3.
  • the first wiring is used to transmit a constant-voltage high-potential signal.
  • the thin film transistor is a P-channel thin film transistor
  • the first wiring is used to transmit a high potential signal.
  • the first routing is the N+Xth scanning line, and X is an integer greater than or equal to 2 ; If the control terminal of the Nth auxiliary unit is connected to the N+2th scanning line, the first routing is the N+Yth scanning line, and Y is equal to 1, or Y is an integer equal to or greater than 3.
  • the present application provides a display device, which includes the display panel in any one of the above implementation manners.
  • the display panel and the display device provided by the present application are connected to the corresponding scanning lines through the auxiliary unit located in the display area, so that the falling edge of the scanning signal transmitted in the scanning line can be pulled down quickly or the rising edge of the scanning signal can be pulled high quickly,
  • the scanning signal distortion problem caused by the transmission delay in the display area can be alleviated.
  • FIG. 1 is a schematic diagram of a first structure of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a third structure of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a fourth structure of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fifth structure of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of comparison of different driving signals provided by the embodiment of the present application.
  • FIG. 7 is another schematic diagram of comparison of different driving signals provided by the embodiment of the present application.
  • this embodiment provides a display panel, which includes a first wiring DDL, an Nth scanning line, and an Nth auxiliary unit 210; at least part of the Nth scanning line is located on the display panel
  • the display area AA is used to transmit the Nth-level scanning signal, and N is a positive integer
  • the Nth auxiliary unit 210 is located in the display area AA of the display panel, and the output end of the Nth auxiliary unit 210 is electrically connected to the Nth scanning line , the input end of the Nth auxiliary unit 210 is electrically connected to the first wire DDL, the control end of the Nth auxiliary unit 210 is electrically connected to the N+M scanning line, and M is a positive integer.
  • the auxiliary unit located in the display area AA is connected to the corresponding scanning line, so that the falling edge of the scanning signal transmitted in the scanning line can be quickly pulled down or the rising edge of the scanning signal Pulling it high quickly can alleviate the scanning signal distortion problem caused by the transmission delay in the display area AA.
  • the N+M scan line when M is equal to 1, the N+M scan line may be the N+1 scan line. When M is equal to 2, the N+M scan line may be the N+2 scan line.
  • the Nth auxiliary unit 210 includes at least one thin film transistor, one of the source/drain of the thin film transistor is electrically connected to the Nth scanning line, and one of the source/drain of the thin film transistor The other is electrically connected to the first wiring DDL, and the gate of the thin film transistor is electrically connected to the N+1 scan line or the N+2 scan line.
  • the Nth scan line is connected to the sources or drains of multiple thin film transistors, so as to construct a plurality of corresponding connection nodes on the Nth scan line; the Nth scan signal is transmitted from the Nth scan line At least one end of the scanning line is input; wherein, if the Nth-level scanning signal is input from one end of the Nth scanning line, the density of multiple connection nodes at the other end close to the Nth scanning line is greater than that of multiple connection nodes near the Density at one end of the Nth scanline.
  • the density of the multiple connection nodes in the middle of the N-th scanning line is greater than that of the multiple connection nodes near the N-th scanning line. Density at either end of the scanline.
  • the transmission delay of the scanning signal becomes more serious. Therefore, in this embodiment, more thin film transistors are arranged at the end of the scanning signal transmission. To increase the pull-down effect of the scan signal in the end region, the falling edge of the scan signal can be further pulled down quickly.
  • the display panel may further include a driving module 100, and the driving module 100 may be a GOA circuit or a gate driving circuit. If the Nth scan signal is input from one end of the Nth scan line, the driving module 100 is located at one side of the display area AA. If the Nth scan signal is input from both ends of the Nth scan line, one of the driving modules 100 is located on one side of the display area AA, and the other of the driving modules 100 is located on the other side of the display area AA.
  • the first wiring DDL is used to transmit a constant-voltage low-potential signal.
  • the constant-voltage low-potential signal can be used to correspond to the falling edge of the low-scanning signal. Since the constant-voltage low-potential signal is used, its low potential has a constant holding effect, which has a constant effect on the decline of the scanning signal. The edge can have a better pull-down effect.
  • the thin film transistor is an N-channel thin film transistor
  • the first wiring DDL is used to transmit a low potential signal.
  • the first wiring DDL can also be used to transmit a pulse signal, and when the N-channel thin film transistor is turned on, the pulse signal is in a low potential state. Similarly, the falling edge of the scan signal can be pulled down.
  • the first wiring DDL is the N+Xth scanning line, and X is greater than or equal to 2 is an integer; if the control terminal of the Nth auxiliary unit 210 is connected to the N+2th scanning line, the first routing DDL is the N+Yth scanning line, Y is equal to 1, or Y is equal to or greater than 3 integer.
  • At least part of the first wiring DDL is located in the display area AA.
  • the first wiring DDL is used to transmit a constant voltage high potential signal.
  • a constant-voltage high-potential signal can be used to correspond to the rising edge of the pull-up scan signal. Due to the use of a constant-voltage high-potential signal, its high potential has a constant holding effect, which has a constant effect on the rise of the scan signal. The edge can have a better pull-up effect.
  • the thin film transistor is a P-channel thin film transistor
  • the first wiring DDL is used to transmit a high potential signal.
  • the first wiring DDL can also be used to transmit a pulse signal, and when the P-channel thin film transistor is turned on, the pulse signal is in a high potential state. Similarly, the rising edge of the scan signal can be pulled high.
  • the present embodiment provides a display device, which includes the display panel in any of the above embodiments.
  • the auxiliary unit located in the display area AA is connected to the corresponding scanning line, so that the falling edge of the scanning signal transmitted in the scanning line can be quickly pulled down or the rising edge of the scanning signal can be quickly pulled down. Pulling it high quickly can alleviate the scanning signal distortion problem caused by the transmission delay in the display area AA.
  • this embodiment provides a display panel, and the display panel further includes a driving module 100, a plurality of driving lines SL and an auxiliary module 200; the driving module 100 is located in a non-display area of the display panel, and the driving module 100 includes multiple cascaded driving units, wherein the Nth level driving unit 110 is used to output the Nth level driving signal G(N); the driving line SL is located in the display area AA of the display panel, wherein the Nth level driving line and the Nth level The output end of the driving unit 110 is connected; the auxiliary module 200 is located in the display area AA, and the auxiliary module 200 includes a plurality of auxiliary units, wherein the output end of the Nth auxiliary unit 210 is connected to the Nth driving line to pull down the Nth level The falling edge of the driving signal G(N) or the rising edge of the N-th stage driving signal G(N) is pulled high.
  • the auxiliary module 200 located in the display area AA is connected to the corresponding driving line SL, so that the falling edge of the driving signal transmitted in the driving line SL can be quickly pulled down or the driving signal The rising edge of AA is quickly pulled high, which can alleviate the problem of distortion of the driving signal that exists when the driving module 100 in the non-display area transmits the driving signal to the display area AA.
  • the non-display area is located at the periphery of the display area AA, and the non-display area may include a first non-display sub-area NA1, a second non-display sub-area NA2, and a third non-display sub-area NA3. and the fourth non-display sub-area NA4.
  • the first non-display sub-area NA1 can be located on the upper side of the display area AA
  • the second non-display sub-area NA2 can be located on the lower side of the display area AA
  • the third non-display sub-area NA3 can be located on the display area AA.
  • the fourth non-display sub-area NA4 may be located on the right side of the display area AA.
  • the display panel may further include a source driver 300 and a plurality of data lines DL, and the source driver 300 is electrically connected to the plurality of data lines DL.
  • the source driver 300 is located in the second non-display sub-area NA2, and the data line DL may extend from the second non-display sub-area NA2 to the display area AA.
  • the source driver 300 may be a source driver integrated circuit for outputting corresponding data signals.
  • the display panel may include one or more driving modules 100, and when the display panel includes one driving module 100, the driving module 100 may be located in the third non-display sub-area NA3 or the fourth non-display sub-area NA4.
  • the display panel includes two driving modules 100, one of the driving modules 100 can be located in one of the third non-display sub-area NA3 and the fourth non-display sub-area NA4, and the other driving module 100 can be located in the third non-display sub-area NA3.
  • one driving line SL can be electrically connected with one or more driving units, for example, one driving line SL can be electrically connected with two driving units, and the two driving units can be in different driving modules. drive unit.
  • one driving unit can be electrically connected with one or more driving lines SL, for example, one driving unit can be electrically connected with two driving lines SL, and one driving unit can also be connected with four driving lines SL.
  • the line SL is electrically connected.
  • the driving unit may be one driving unit in the driving module 100, and one driving line SL may be one scanning line.
  • each cascaded driving unit can output driving signals with the same frequency and different phases.
  • the falling edge of the Nth-level driving signal G(N) is the same as the ), or the rising edge of the N+1-th stage driving signal G(N+1) slightly lags behind the falling edge of the N-th stage driving signal G(N).
  • N can be a positive integer.
  • the rising edge of the Nth-level drive signal G(N) is synchronized with the falling edge of the N+1-th level drive signal G(N+1), or the falling edge of the N+1-th level drive signal G(N+1) The edge lags slightly behind the rising edge of the Nth-level drive signal G(N).
  • N can be a positive integer.
  • the driving module 100 may be, but not limited to, a GOA (Gate Driver On Array, line scanning technology integrated on an array substrate) circuit, correspondingly, the driving unit may be a GOA unit, and the driving line SL may be The scanning line, the driving signal can scan the signal, and is used to control whether the data signal is written or not.
  • GOA Gate Driver On Array, line scanning technology integrated on an array substrate
  • the driving module 100 can also be a lighting control circuit, correspondingly, the driving unit can be a lighting control unit, the driving line SL can be a lighting control signal line, and the driving signal can be a lighting control signal for controlling lighting. Whether the device emits light or not.
  • the driving module 100 may include an Nth level driving unit 110, an N+1st level driving unit 120, and an N+2th level driving unit 130;
  • the Nth-level drive unit 110 is connected to the N-th drive line;
  • the N+1-th level drive unit 120 is used to output the N+1-th level drive signal G(N +1), the output terminal of the N+1th driving unit 120 is connected to the N+1 driving line;
  • the N+2th driving unit 130 is used to output the N+2th driving signal G(N+2),
  • the output end of the N+2th driving unit 130 is connected to the N+2th driving line.
  • the output end of the Nth auxiliary unit 210 is electrically connected to the Nth driving line.
  • the output end of the N+1th auxiliary unit 220 is electrically connected to the N+1th driving line.
  • control terminal of the Nth auxiliary unit 210 is connected to the N+1th driving line; the falling edge of the Nth driving signal G(N) is connected to the rising edge of the N+1th driving signal G(N+1) At the same moment, or, the rising edge of the N+1th stage driving signal G(N+1) lags behind the falling edge of the Nth stage driving signal G(N).
  • the control terminal of the N+1th auxiliary unit 220 is connected to the N+2th driving line; the falling edge of the N+1th driving signal G(N+1) is connected to the ) at the same moment, or, the rising edge of the N+2th driving signal G(N+2) lags behind the falling edge of the N+1th driving signal G(N+1).
  • the display panel may further include a first wiring DDL connected to the input end of the Nth auxiliary unit 210 and/or the input end of the N+1th auxiliary unit 220 . It can be understood that a low potential signal may be transmitted in the first wiring DDL, and the low potential signal has at least a partial low potential state.
  • the driving module 100 may include an Nth level driving unit 110, an N+1th level driving unit 120, an N+2th level driving unit 130, an N+3th level driving unit 140 and the N+4th stage driving unit 150.
  • the Nth level driving unit 110 is configured to output the Nth level driving signal G(N), and the output end of the Nth level driving unit 110 is connected to the Nth driving line.
  • the N+1th level driving unit 120 is configured to output the N+1th level driving signal G(N+1), and the output end of the N+1th level driving unit 120 is connected to the N+1th driving line.
  • the N+2th level driving unit 130 is configured to output the N+2th level driving signal G(N+2), and the output end of the N+2th level driving unit 130 is connected to the N+2th driving line.
  • the N+3th level driving unit 140 is configured to output the N+3th level driving signal G(N+3), and the output end of the N+3th level driving unit 140 is connected to the N+3th driving line.
  • the N+4th level driving unit 150 is configured to output the N+4th level driving signal G(N+4), and the output end of the N+4th level driving unit 150 is connected to the N+4th driving line.
  • the output end of the Nth auxiliary unit 210 is electrically connected to the Nth driving line.
  • the output end of the N+1th auxiliary unit 220 is electrically connected to the N+1th driving line.
  • the output end of the N+2th auxiliary unit 230 is electrically connected to the N+2th driving line.
  • the output end of the N+3 th auxiliary unit 240 is electrically connected to the N+3 th driving line.
  • control terminal of the Nth auxiliary unit 210 is connected to the N+2th driving line; the falling edge of the Nth level driving signal G(N) and the rising edge of the N+2th level driving signal G(N+2) At the same moment, or, the rising edge of the N+2th stage driving signal G(N+2) lags behind the falling edge of the Nth stage driving signal G(N).
  • the control terminal of the N+1th auxiliary unit 220 is connected to the N+3th driving line; the falling edge of the N+1th level driving signal G(N+1) is connected to the ) at the same moment, or, the rising edge of the N+3-th stage driving signal G(N+3) lags behind the falling edge of the N+1-th stage driving signal G(N+1).
  • the control terminal of the N+2th auxiliary unit 230 is connected to the N+4th driving line; the falling edge of the N+2th driving signal G(N+2) is connected to the N+4th driving signal G(N+4 ) at the same moment, or, the rising edge of the N+4th driving signal G(N+4) lags behind the falling edge of the N+2th driving signal G(N+2).
  • the control terminal of the N+3th auxiliary unit 240 is connected to the N+5th driving line; the falling edge of the N+3th level driving signal G(N+3) is at the same level as the rising edge of the N+5th level driving signal time, or, the rising edge of the N+5th stage driving signal lags behind the falling edge of the N+3th stage driving signal G(N+3).
  • the first routing DDL and the input of the Nth auxiliary unit 210, the input of the N+1th auxiliary unit 220, the input of the N+2th auxiliary unit 230, and the input of the N+3th auxiliary unit 240 end connection.
  • a low potential signal may be transmitted in the first wiring DDL, and the low potential signal has at least a partial low potential state.
  • the driving module 100 may include an Nth level driving unit 110, an N+1th level driving unit 120, an N+2th level driving unit 130, an N+3th level driving unit 140 and the N+4th stage driving unit 150.
  • the Nth level driving unit 110 is configured to output the Nth level driving signal G(N), and the output end of the Nth level driving unit 110 is connected to the Nth driving line.
  • the N+1th level driving unit 120 is configured to output the N+1th level driving signal G(N+1), and the output end of the N+1th level driving unit 120 is connected to the N+1th driving line.
  • the N+2th level driving unit 130 is configured to output the N+2th level driving signal G(N+2), and the output terminal of the N+2th level driving unit 130 is connected to the N+2th driving line.
  • the N+3th level driving unit 140 is configured to output the N+3th level driving signal G(N+3), and the output end of the N+3th level driving unit 140 is connected to the N+3th driving line.
  • the N+4th level driving unit 150 is configured to output the N+4th level driving signal G(N+4), and the output end of the N+4th level driving unit 150 is connected to the N+4th driving line.
  • the output end of the Nth auxiliary unit 210 is electrically connected to the Nth driving line.
  • the output end of the N+1th auxiliary unit 220 is electrically connected to the N+1th driving line.
  • the output end of the N+2th auxiliary unit 230 is electrically connected to the N+2th driving line.
  • the output end of the N+3 th auxiliary unit 240 is electrically connected to the N+3 th driving line.
  • control terminal of the Nth auxiliary unit 210 is connected to the N+1th driving line; the falling edge of the Nth driving signal G(N) is connected to the rising edge of the N+1th driving signal G(N+1) At the same moment, or, the rising edge of the N+1th stage driving signal G(N+1) lags behind the falling edge of the Nth stage driving signal G(N).
  • the control terminal of the N+1th auxiliary unit 220 is connected to the N+2th driving line; the falling edge of the N+1th driving signal G(N+1) is connected to the ) at the same moment, or, the rising edge of the N+2th driving signal G(N+2) lags behind the falling edge of the N+1th driving signal G(N+1).
  • the control terminal of the N+2th auxiliary unit 230 is connected to the N+3th driving line; the falling edge of the N+2th driving signal G(N+2) is connected to the ) at the same moment, or, the rising edge of the N+3th stage driving signal G(N+3) lags behind the falling edge of the N+2th stage driving signal G(N+2).
  • the control terminal of the N+3th auxiliary unit 240 is connected to the N+4th driving line; the falling edge of the N+3rd driving signal G(N+3) is connected to the ) at the same moment, or, the rising edge of the N+4th driving signal G(N+4) lags behind the falling edge of the N+3th driving signal G(N+3).
  • the input end of the Nth auxiliary unit 210 is connected to the N+2th driving line.
  • the input end of the N+1th auxiliary unit 220 is connected to the N+3th driving line.
  • the input end of the N+2th auxiliary unit 230 is connected to the N+4th driving line.
  • the input end of the N+3th auxiliary unit 240 is connected to the N+5th driving line.
  • the driving module 100 may include an Nth level driving unit 110, an N+1th level driving unit 120, and an N+2th level driving unit 130; To output the Nth-level drive signal G(N), the output end of the N-level drive unit 110 is connected to the N-th drive line; the N+1-th level drive unit 120 is used to output the N+1-th level drive signal G(N +1), the output terminal of the N+1th driving unit 120 is connected to the N+1 driving line; the N+2th driving unit 130 is used to output the N+2th driving signal G(N+2), The output end of the N+2th driving unit 130 is connected to the N+2th driving line.
  • the output end of the N-1 auxiliary unit 209 is electrically connected to the N-1 driving line.
  • the output end of the Nth auxiliary unit 210 is electrically connected to the Nth driving line.
  • the output end of the N+1th auxiliary unit 220 is electrically connected to the N+1th driving line.
  • control terminal of the N-1th auxiliary unit 209 is connected to the Nth driving line; the falling edge of the N-1th level driving signal is at the same moment as the rising edge of the Nth level driving signal G(N), or, The rising edge of the Nth level driving signal G(N) lags behind the falling edge of the N ⁇ 1th level driving signal.
  • the control terminal of the Nth auxiliary unit 210 is connected to the N+1th driving line; the falling edge of the Nth driving signal G(N) is at the same level as the rising edge of the N+1th driving signal G(N+1). time, or, the rising edge of the N+1th stage driving signal G(N+1) lags behind the falling edge of the Nth stage driving signal G(N).
  • the control terminal of the N+1th auxiliary unit 220 is connected to the N+2th driving line; the falling edge of the N+1th driving signal G(N+1) is connected to the ) at the same moment, or, the rising edge of the N+2th driving signal G(N+2) lags behind the falling edge of the N+1th driving signal G(N+1).
  • the first wiring DDL may be a constant-voltage low-potential line VGL, and the constant-voltage low-potential line VGL is used to receive a constant-voltage low-potential signal.
  • the constant voltage low potential line VGL is connected to the input end of the N ⁇ 1th auxiliary unit 209 , the input end of the Nth auxiliary unit 210 , and the input end of the N+1th auxiliary unit 220 .
  • the N-1th auxiliary unit 209 may include a first transistor T1 and a second transistor T2; a constant voltage low potential line VGL and one of the source/drain of the first transistor T1 and the source of the second transistor T2 One of the /drains is connected; the Nth driving line is connected to the gate of the first transistor T1 and the gate of the second transistor T2; the N-1th driving line is connected to the source/drain of the first transistor T1 The other one is connected to the other one of the source/drain of the second transistor T2.
  • the N+1th auxiliary unit 220 may include a fifth transistor T5 and a sixth transistor T6; the constant voltage low potential line VGL and one of the source/drain of the fifth transistor T5 and the source of the sixth transistor T6 One of the /drains is connected; the N+2 drive line is connected to the gate of the fifth transistor T5 and the gate of the sixth transistor T6; the N+1 drive line is connected to the source/drain of the fifth transistor T5 The other of the electrodes is connected to the other of the source/drain of the sixth transistor T6.
  • an auxiliary unit may include two transistors or multiple transistors, and the multiple transistors may be one of three transistors, four transistors, five transistors, or six transistors,
  • the two transistors or the plurality of transistors may be thin film transistors, which are convenient for fabrication and display area AA on the array substrate.
  • the thin film transistor may be, but not limited to, an N-channel thin film transistor, or a P-channel thin film transistor.
  • the auxiliary module 200 may include one or more Nth auxiliary units 210, and the plurality of Nth auxiliary units 210 may be two Nth auxiliary units 210, three One of the Nth auxiliary unit 210 , four Nth auxiliary units 210 or five Nth auxiliary units 210 .
  • each Nth auxiliary unit 210 may include one or more thin film transistors.
  • the plurality of Nth auxiliary units 210 are two Nth auxiliary units 210
  • one of the Nth auxiliary units 210 may include a third transistor T3, and the other Nth auxiliary unit 210 may include a fourth Transistor T4.
  • the constant voltage low potential line VGL is connected to one of the source/drain of the third transistor T3 and one of the source/drain of the fourth transistor T4; the N+1th driving line is connected to the gate of the third transistor T3 The pole is connected to the gate of the fourth transistor T4; the Nth driving line is connected to the other of the source/drain of the third transistor T3 and the other of the source/drain of the fourth transistor T4.
  • the first wiring DDL may be at least one of the N+1th driving line and the N+2th driving line; when the control terminal of the Nth auxiliary unit 210 is connected to the N+1th driving line When the driving lines are connected, the input terminal of the Nth auxiliary unit 210 is connected to the N+2th driving line; or, when the control terminal of the Nth auxiliary unit 210 is connected to the N+2th driving line, the Nth The input end of the auxiliary unit 210 is connected to the N+1th driving line.
  • the Nth auxiliary unit 210 includes at least one thin film transistor; one of the source/drain of the at least one thin film transistor is connected to the Nth driving line.
  • the gate of at least one thin film transistor is connected to the N+1th driving line or the N+2th driving line.
  • the display panel further includes at least one first wiring DDL; the first wiring DDL is connected to the other of the source/drain of at least one thin film transistor; wherein, the first wiring DDL is used for Access the constant voltage low potential signal.
  • any one of the at least one first wiring DDL is at least partially located in the display area AA.
  • the Nth auxiliary unit 210 includes a first thin film transistor and a second thin film transistor; the Nth driving line is connected to one of the source/drain of the first thin film transistor to drive the Nth
  • the first connection node is constructed on the line;
  • the Nth driving line is connected to one of the source/drain of the second thin film transistor to construct the second connection node on the Nth driving line;
  • one end of the Nth driving line is connected to At least two of the distance from the first connection node, the distance from the first connection node to the second connection node, and the distance from the second connection node to the other end of the Nth driving line are equal or approximately equal.
  • the distance between two adjacent connection nodes can be equal to the different connection nodes constructed by the Nth driving line. Or approximately equal, at the same time, the distance between one end of the Nth driving line and its adjacent connection node can also be equal to or approximately equal to the distance between two adjacent connection nodes, and the other end of the Nth driving line The distance to its adjacent connection nodes may also be equal to or approximately equal to the distance between two adjacent connection nodes.
  • one end of the Nth drive line may be, but not limited to, the output end of the Nth level drive unit, or a point where the Nth drive line is located at the junction of one of the non-display areas and the display area ;
  • the other end of the Nth driving line may be a point at the junction of another non-display area and the display area.
  • the falling edges of the Nth-level driving signal can be pulled down simultaneously at equal distances, and the falling edges of the Nth-level driving signal can be pulled down more quickly and uniformly.
  • the corresponding driving line SL will also increase accordingly, and the corresponding driving signal will be subjected to increasingly larger capacitive reactance and/or Impedance, then the waveform of the driving signal will also have a corresponding delay.
  • the falling edge of the driving signal will be extended from a certain moment to a certain period of time.
  • the falling edge will also change from a straight line state to a curve state, resulting in The falling edge of the driving signal cannot be pulled down quickly. Based on this, it is necessary to compare different falling edges to understand the technical improvements brought about by different embodiments of the present application.
  • Figure 6 shows the ideal waveform diagram P1, the traditional waveform diagram P2 and the improved waveform diagram P3 of different embodiments of the application, in the ideal waveform diagram P1, the traditional waveform diagram P2 and In the improved waveform diagram P3, the waveform diagrams of the Nth level driving signal G(N), the N+1st level driving signal G(N+1) and the N+2th level driving signal G(N+2) are respectively provided .
  • the rising edge or falling The edges are all in a straight line state, or they all rise or fall at the same time.
  • This waveform is the ideal waveform required by the display panel, but limited by the influence of capacitive reactance and/or impedance, there will always be a certain delay.
  • the comparison between the traditional waveform diagram P2 and the improved waveform diagram P3 shows that in the traditional waveform diagram P2, the drive signal G(N) of level N, the driving signal G(N+1) of level N+1 and the level N+
  • the falling edge ratio of the 2-level drive signal G(N+2) corresponds to the N-level drive signal G(N), the N+1-th level drive signal G(N+1) and the N+2-th level in the improved waveform diagram P3
  • the falling edge of the stage driving signal G(N+2) takes a longer time before being pulled down to a low potential.
  • the above-mentioned embodiment can quickly pull down the falling edge of the driving signal to improve the delay caused by the capacitive reactance and/or impedance of the driving signal in the display area AA.
  • the inventive concept of the present application overcomes the long-standing technical prejudice in this field to a certain extent, and can significantly improve the pull-down speed of the falling edge of the driving signal in the display area AA or the rising edge of the driving signal in the display area AA. pull-up speed.
  • the present application provides a schematic diagram of waveform comparison of another driving signal, wherein the driving signal S1 is the driving signal in the traditional technical solution, the driving signal S2 is the driving signal in the above-mentioned embodiment, and the driving signal S3 is A driving signal in an ideal state; the horizontal axis can be expressed as time T, and its unit can be microseconds ( ⁇ s), and the vertical axis can be expressed as voltage value U, and its unit can be volts (V).
  • the rising speed of the rising edge of the driving signal S3 is significantly higher than the rising speed of the rising edge of the driving signal S1 and the rising speed of the driving signal S2, and the rising speed of the rising edge of the driving signal S1 is the same as the rising speed of the driving signal S2.
  • the rising speed of the edge is similar or approximate.
  • the falling speed of the falling edge of the driving signal S3 is obviously higher than the falling speed of the falling edge of the driving signal S1 and the falling speed of the falling edge of the driving signal S2; while the falling speed of the falling edge of the driving signal S1 is obviously lower than the falling speed of the driving signal S2
  • the low potential state of the driving signal S1 has not received the continuous pull-down effect of the auxiliary module 200, some potential states slightly higher than the low potential state will easily appear, which will Further, the waveform of the driving signal S1 deteriorates, thereby affecting the stability of the display panel.
  • this embodiment provides a display device, which includes the display panel in any one of the above embodiments.
  • the auxiliary module located in the display area is connected to the corresponding driving line, so that the falling edge of the driving signal transmitted in the driving line can be pulled down quickly, and the problem in the non-display area can be alleviated.
  • the drive signal distortion problem exists when the drive module transmits the drive signal to the display area.
  • the display device may further include a pixel circuit, the pixel circuit is located in the display area of the display device, and the pixel circuit is electrically connected to the driving module through a driving line.

Abstract

本申请公开了一种显示面板及显示装置，该显示面板的第N个辅助单元位于显示面板的显示区，第N个辅助单元的输出端与第N条扫描线连接，通过位于显示区中的辅助单元与对应的扫描线连接，可以使扫描线中传输的扫描信号的下降沿快速拉低或者扫描信号的上升沿快速拉高，能够缓解显示区中传输延时导致的扫描信号失真问题。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
显示装置作为电子设备的显示部件已经广泛应用于各种电子产品中，其中，各种驱动模块作为显示装置的一个重要组成部分，其大多位于显示装置的外围区域，需要通过驱动信号线传输驱动信号至显示装置的显示区。
随着当前显示应用的不断发展，显示面板的外观、尺寸也在不断的突破。越来越多的应用场景对显示面板的需求也越发多样。然而，随着显示面板的尺寸不断扩大，这些驱动信号的传输延时也越来越大，驱动信号的失真也愈发严重，难以保证显示品质。
 技术问题
本申请提供一种显示面板及显示装置，以缓解显示区中传输延时导致的扫描信号失真的技术问题。
 技术解决方案
第一方面，本申请提供一种显示面板，其包括第一走线、第N条扫描线以及第N个辅助单元；第N条扫描线的至少部分位于显示面板的显示区，用于传输第N级扫描信号，N为正整数；第N个辅助单元位于显示面板的显示区，第N个辅助单元的输出端与第N条扫描线电性连接，第N个辅助单元的输入端与第一走线电性连接，第N个辅助单元的控制端与第N+M条扫描线电性连接，M为正整数。
在其中一些实施方式中，第N个辅助单元包括至少一个薄膜晶体管，薄膜晶体管的源极/漏极中的一个与第N条扫描线电性连接，薄膜晶体管的源极/漏极中的另一个与第一走线电性连接，薄膜晶体管的栅极与第N+M条扫描线电性连接。
在其中一些实施方式中，第N条扫描线与多个薄膜晶体管的源极/漏极中的一个电性连接，以在第N条扫描线上构造对应的多个连接节点；第N级扫描信号从第N条扫描线的至少一端输入；其中，若第N级扫描信号从第N条扫描线的一端输入，则多个连接节点在靠近第N条扫描线的另一端的密度，大于多个连接节点在靠近第N条扫描线的一端的密度。
在其中一些实施方式中，若第N级扫描信号从第N条扫描线的两端输入，则多个连接节点在第N条扫描线的中部的密度，大于多个连接节点在靠近第N条扫描线的任一端的密度。
在其中一些实施方式中，若薄膜晶体管为N沟道型薄膜晶体管，第一走线用于传输恒压低电位信号。
在其中一些实施方式中，若薄膜晶体管为N沟道型薄膜晶体管，薄膜晶体管打开时，第一走线用于传输低电位信号。
在其中一些实施方式中，若第N个辅助单元的控制端与第N+1条扫描线电性连接，则第一走线为第N+X条扫描线，X为大于或者等于2的整数；若第N个辅助单元的控制端与第N+2条扫描线连接，第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
在其中一些实施方式中，若薄膜晶体管为P沟道型薄膜晶体管，第一走线用于传输恒压高电位信号。
在其中一些实施方式中，若薄膜晶体管为P沟道型薄膜晶体管，薄膜晶体管打开时，第一走线用于传输高电位信号。
在其中一些实施方式中，若第N个辅助单元的控制端与第N+1条扫描线电性连接，则第一走线为第N+X条扫描线，X为大于或者等于2的整数；若第N个辅助单元的控制端与第N+2条扫描线连接，第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
第二方面，本申请提供一种显示装置，其包括上述任一实施方式中的显示面板。
 有益效果
本申请提供的显示面板及显示装置，通过位于显示区中的辅助单元与对应的扫描线连接，可以使扫描线中传输的扫描信号的下降沿快速拉低或者扫描信号的上升沿快速拉高，能够缓解显示区中传输延时导致的扫描信号失真问题。
 附图说明
图1为本申请实施例提供的显示面板的第一种结构示意图。
图2为本申请实施例提供的显示面板的第二种结构示意图。
图3为本申请实施例提供的显示面板的第三种结构示意图。
图4为本申请实施例提供的显示面板的第四种结构示意图。
图5为本申请实施例提供的显示面板的第五种结构示意图。
图6为本申请实施例提供的不同驱动信号的一种对比示意图。
图7为本申请实施例提供的不同驱动信号的另一种对比示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1至图7，本实施例提供一种显示面板，其包括第一走线DDL、第N条扫描线以及第N个辅助单元210；第N条扫描线的至少部分位于显示面板的显示区AA，用于传输第N级扫描信号，N为正整数；第N个辅助单元210位于显示面板的显示区AA，第N个辅助单元210的输出端与第N条扫描线电性连接，第N个辅助单元210的输入端与第一走线DDL电性连接，第N个辅助单元210的控制端与第N+M条扫描线电性连接，M为正整数。
可以理解的是，本实施例提供的显示面板，通过位于显示区AA中的辅助单元与对应的扫描线连接，可以使扫描线中传输的扫描信号的下降沿快速拉低或者扫描信号的上升沿快速拉高，能够缓解显示区AA中传输延时导致的扫描信号失真问题。
其中，当M等于1时，第N+M条扫描线可以为第N+1条扫描线。当M等于2时，第N+M条扫描线可以为第N+2条扫描线。
在其中一些实施例中，第N个辅助单元210包括至少一个薄膜晶体管，薄膜晶体管的源极/漏极中的一个与第N条扫描线电性连接，薄膜晶体管的源极/漏极中的另一个与第一走线DDL电性连接，薄膜晶体管的栅极与第N+1条扫描线或者第N+2条扫描线电性连接。
在其中一些实施例中，第N条扫描线与多个薄膜晶体管的源极或者漏极连接，以在第N条扫描线上构造对应的多个连接节点；第N级扫描信号从第N条扫描线的至少一端输入；其中，若第N级扫描信号从第N条扫描线的一端输入，则多个连接节点在靠近第N条扫描线的另一端的密度，大于多个连接节点在靠近第N条扫描线的一端的密度。
在其中一些实施例中，若第N级扫描信号从第N条扫描线的两端输入，则多个连接节点在第N条扫描线的中部的密度，大于多个连接节点在靠近第N条扫描线的任一端的密度。
需要进行说明的是，随着扫描信号在对应的扫描线中传输的距离越远，扫描信号的传输延迟也愈发严重，因此，本实施例在扫描信号传输的末端配置较多的薄膜晶体管，以增加末端区域中扫描信号的下拉作用，能够进一步快速地拉低扫描信号的下降沿。
需要进行说明的是，显示面板还可以包括驱动模块100，该驱动模块100可以为GOA电路或者栅极驱动电路。如果第N级扫描信号从第N条扫描线的一端输入，则该驱动模块100位于显示区AA的一侧。如果第N级扫描信号从第N条扫描线的两端输入，则其中一个驱动模块100位于显示区AA的一侧，同时，其中另一个驱动模块100位于显示区AA的另一侧。
在其中一些实施例中，若薄膜晶体管为N沟道型薄膜晶体管，第一走线DDL用于传输恒压低电位信号。
可以理解的是，在本实施例中，可以采用恒压低电位信号去对应拉低扫描信号的下降沿，由于采用了恒压低电位信号，其低电位具有恒定保持作用，对扫描信号的下降沿可以具有更好的下拉作用。
在其中一些实施例中，若薄膜晶体管为N沟道型薄膜晶体管，薄膜晶体管打开时，第一走线DDL用于传输低电位信号。
可以理解的是，在本实施例中，第一走线DDL也可以用于传输脉冲信号，当N沟道型薄膜晶体管打开时，脉冲信号处于低电位状态。同理可以拉低扫描信号的下降沿。
在其中一些实施例中，若第N个辅助单元210的控制端与第N+1条扫描线电性连接，则第一走线DDL为第N+X条扫描线，X为大于或者等于2的整数；若第N个辅助单元210的控制端与第N+2条扫描线连接，第一走线DDL为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
在其中一些实施例中，第一走线DDL的至少部分位于显示区AA。
在其中一些实施例中，若薄膜晶体管为P沟道型薄膜晶体管，第一走线DDL用于传输恒压高电位信号。
可以理解的是，在本实施例中，可以采用恒压高电位信号去对应拉高扫描信号的上升沿，由于采用了恒压高电位信号，其高电位具有恒定保持作用，对扫描信号的上升沿可以具有更好的上拉作用。
在其中一些实施例中，若薄膜晶体管为P沟道型薄膜晶体管，薄膜晶体管打开时，第一走线DDL用于传输高电位信号。
可以理解的是，在本实施例中，第一走线DDL也可以用于传输脉冲信号，当P沟道型薄膜晶体管打开时，脉冲信号处于高电位状态。同理可以拉高扫描信号的上升沿。
在其中一些实施例中，本实施例提供一种显示装置，其包括上述任一实施例中的显示面板。
可以理解的是，本实施例提供的显示装置，通过位于显示区AA中的辅助单元与对应的扫描线连接，可以使扫描线中传输的扫描信号的下降沿快速拉低或者扫描信号的上升沿快速拉高，能够缓解显示区AA中传输延时导致的扫描信号失真问题。
如图1所示，本实施例提供了一种显示面板，显示面板还包括驱动模块100、多条驱动线SL以及辅助模块200；驱动模块100位于显示面板的非显示区，驱动模块100包括多个级联的驱动单元，其中，第N级驱动单元110用于输出第N级驱动信号G（N）；驱动线SL位于显示面板的显示区AA，其中，第N条驱动线与第N级驱动单元110的输出端连接；辅助模块200位于显示区AA，辅助模块200包括多个辅助单元，其中，第N个辅助单元210的输出端与第N条驱动线连接，以拉低第N级驱动信号G（N）的下降沿或者拉高第N级驱动信号G（N）的上升沿。
可以理解的是，本实施例提供的显示面板，通过位于显示区AA中的辅助模块200与对应的驱动线SL连接，可以使驱动线SL中传输的驱动信号的下降沿快速拉低或者驱动信号的上升沿快速拉高，能够缓解非显示区中驱动模块100传输驱动信号至显示区AA时存在的驱动信号失真问题。
需要进行说明的是，在该显示面板中，非显示区位于显示区AA的外围，非显示区可以包括第一非显示子区NA1、第二非显示子区NA2、第三非显示子区NA3以及第四非显示子区NA4。当正面俯视该显示面板时，第一非显示子区NA1可以位于显示区AA的上侧，第二非显示子区NA2可以位于显示区AA的下侧，第三非显示子区NA3可以位于显示区AA的左侧，第四非显示子区NA4可以位于显示区AA的右侧。
其中，该显示面板还可以包括源极驱动器300和多条数据线DL，源极驱动器300与多条数据线DL电性连接。该源极驱动器300位于第二非显示子区NA2，数据线DL可以从第二非显示子区NA2延伸至显示区AA。其中，该源极驱动器300可以为源极驱动集成电路，用于输出对应的数据信号。
其中，该显示面板可以包括一个或者多个驱动模块100，当该显示面板包括一个驱动模块100时，该驱动模块100可以位于第三非显示子区NA3或者第四非显示子区NA4。当该显示面板包括两个驱动模块100时，其中一个驱动模块100可以位于第三非显示子区NA3和第四非显示子区NA4中的一个，其中另一个驱动模块100可以位于第三非显示子区NA3和第四非显示子区NA4中的另一个。
在其中一个实施例中，一条驱动线SL可以与一个或者多个驱动单元电性连接，例如，一条驱动线SL可以与两个驱动单元电性连接，该两个驱动单元可以为不同驱动模块中的驱动单元。
在其中一个实施例中，一个驱动单元可以与一条或者多条驱动线SL电性连接，例如，一个驱动单元可以但不限于与两条驱动线SL电性连接，一个驱动单元还可以与四条驱动线SL电性连接。对应地，该驱动单元可以为驱动模块100中一个驱动单元，一条驱动线SL可以为一条扫描线。
可以理解的是，级联的每个驱动单元可以输出频率相同且相位不同的驱动信号，例如，第N级驱动信号G（N）的下降沿与第N+1级驱动信号G（N+1）的上升沿同步，或者第N+1级驱动信号G（N+1）的上升沿略微滞后于第N级驱动信号G（N）的下降沿。其中，N可以为正整数。或者，第N级驱动信号G（N）的上升沿与第N+1级驱动信号G（N+1）的下降沿同步，或者第N+1级驱动信号G（N+1）的下降沿沿略微滞后于第N级驱动信号G（N）的上升沿。其中，N可以为正整数。
在其中一个实施例中，该驱动模块100可以但不限于为GOA（Gate Driver On Array，集成在阵列基板上的行扫描技术）电路，对应地，驱动单元可以为GOA单元，驱动线SL可以为扫描线，驱动信号可以扫描信号，用于控制数据信号的写入与否。
在其中一个实施例中，该驱动模块100还可以为发光控制电路，对应地，驱动单元可以为发光控制单元，驱动线SL可以为发光控制信号线，驱动信号可以发光控制信号，用于控制发光器件的发光与否。
如图2所示，在其中一个实施例中，驱动模块100可以包括第N级驱动单元110、第N+1级驱动单元120以及第N+2级驱动单元130；第N级驱动单元110用于输出第N级驱动信号G（N），第N级驱动单元110的输出端与第N条驱动线连接；第N+1级驱动单元120用于输出第N+1级驱动信号G（N+1），第N+1级驱动单元120的输出端与第N+1条驱动线连接；第N+2级驱动单元130用于输出第N+2级驱动信号G（N+2），第N+2级驱动单元130的输出端与第N+2条驱动线连接。
其中，第N个辅助单元210的输出端与第N条驱动线电性连接。第N+1个辅助单元220的输出端与第N+1条驱动线电性连接。
其中，第N个辅助单元210的控制端与第N+1条驱动线连接；第N级驱动信号G（N）的下降沿与第N+1级驱动信号G（N+1）的上升沿位于同一时刻，或者，第N+1级驱动信号G（N+1）的上升沿滞后于第N级驱动信号G（N）的下降沿。第N+1个辅助单元220的控制端与第N+2条驱动线连接；第N+1级驱动信号G（N+1）的下降沿与第N+2级驱动信号G（N+2）的上升沿位于同一时刻，或者，第N+2级驱动信号G（N+2）的上升沿滞后于第N+1级驱动信号G（N+1）的下降沿。
该显示面板还可以包括第一走线DDL，该第一走线DDL与第N个辅助单元210的输入端和/或第N+1个辅助单元220的输入端连接。可以理解的是，该第一走线DDL中可以传输低电位信号，该低电位信号至少存在部分的低电位状态。
如图3所示，在其中一个实施例中，驱动模块100可以包括第N级驱动单元110、第N+1级驱动单元120、第N+2级驱动单元130、第N+3级驱动单元140以及第N+4级驱动单元150。第N级驱动单元110用于输出第N级驱动信号G（N），第N级驱动单元110的输出端与第N条驱动线连接。第N+1级驱动单元120用于输出第N+1级驱动信号G（N+1），第N+1级驱动单元120的输出端与第N+1条驱动线连接。第N+2级驱动单元130用于输出第N+2级驱动信号G（N+2），第N+2级驱动单元130的输出端与第N+2条驱动线连接。第N+3级驱动单元140用于输出第N+3级驱动信号G（N+3），第N+3级驱动单元140的输出端与第N+3条驱动线连接。第N+4级驱动单元150用于输出第N+4级驱动信号G（N+4），第N+4级驱动单元150的输出端与第N+4条驱动线连接。
其中，第N个辅助单元210的输出端与第N条驱动线电性连接。第N+1个辅助单元220的输出端与第N+1条驱动线电性连接。第N+2个辅助单元230的输出端与第N+2条驱动线电性连接。第N+3个辅助单元240的输出端与第N+3条驱动线电性连接。
其中，第N个辅助单元210的控制端与第N+2条驱动线连接；第N级驱动信号G（N）的下降沿与第N+2级驱动信号G（N+2）的上升沿位于同一时刻，或者，第N+2级驱动信号G（N+2）的上升沿滞后于第N级驱动信号G（N）的下降沿。第N+1个辅助单元220的控制端与第N+3条驱动线连接；第N+1级驱动信号G（N+1）的下降沿与第N+3级驱动信号G（N+3）的上升沿位于同一时刻，或者，第N+3级驱动信号G（N+3）的上升沿滞后于第N+1级驱动信号G（N+1）的下降沿。第N+2个辅助单元230的控制端与第N+4条驱动线连接；第N+2级驱动信号G（N+2）的下降沿与第N+4级驱动信号G（N+4）的上升沿位于同一时刻，或者，第N+4级驱动信号G（N+4）的上升沿滞后于第N+2级驱动信号G（N+2）的下降沿。第N+3个辅助单元240的控制端与第N+5条驱动线连接；第N+3级驱动信号G（N+3）的下降沿与第N+5级驱动信号的上升沿位于同一时刻，或者，第N+5级驱动信号的上升沿滞后于第N+3级驱动信号G（N+3）的下降沿。第一走线DDL与第N个辅助单元210的输入端、第N+1个辅助单元220的输入端、第N+2个辅助单元230的输入端以及第N+3个辅助单元240的输入端连接。该第一走线DDL中可以传输低电位信号，该低电位信号至少存在部分的低电位状态。
如图4所示，在其中一个实施例中，驱动模块100可以包括第N级驱动单元110、第N+1级驱动单元120、第N+2级驱动单元130、第N+3级驱动单元140以及第N+4级驱动单元150。第N级驱动单元110用于输出第N级驱动信号G（N），第N级驱动单元110的输出端与第N条驱动线连接。第N+1级驱动单元120用于输出第N+1级驱动信号G（N+1），第N+1级驱动单元120的输出端与第N+1条驱动线连接。第N+2级驱动单元130用于输出第N+2级驱动信号G（N+2），第N+2级驱动单元130的输出端与第N+2条驱动线连接。第N+3级驱动单元140用于输出第N+3级驱动信号G（N+3），第N+3级驱动单元140的输出端与第N+3条驱动线连接。第N+4级驱动单元150用于输出第N+4级驱动信号G（N+4），第N+4级驱动单元150的输出端与第N+4条驱动线连接。
其中，第N个辅助单元210的输出端与第N条驱动线电性连接。第N+1个辅助单元220的输出端与第N+1条驱动线电性连接。第N+2个辅助单元230的输出端与第N+2条驱动线电性连接。第N+3个辅助单元240的输出端与第N+3条驱动线电性连接。
其中，第N个辅助单元210的控制端与第N+1条驱动线连接；第N级驱动信号G（N）的下降沿与第N+1级驱动信号G（N+1）的上升沿位于同一时刻，或者，第N+1级驱动信号G（N+1）的上升沿滞后于第N级驱动信号G（N）的下降沿。第N+1个辅助单元220的控制端与第N+2条驱动线连接；第N+1级驱动信号G（N+1）的下降沿与第N+2级驱动信号G（N+2）的上升沿位于同一时刻，或者，第N+2级驱动信号G（N+2）的上升沿滞后于第N+1级驱动信号G（N+1）的下降沿。第N+2个辅助单元230的控制端与第N+3条驱动线连接；第N+2级驱动信号G（N+2）的下降沿与第N+3级驱动信号G（N+3）的上升沿位于同一时刻，或者，第N+3级驱动信号G（N+3）的上升沿滞后于第N+2级驱动信号G（N+2）的下降沿。第N+3个辅助单元240的控制端与第N+4条驱动线连接；第N+3级驱动信号G（N+3）的下降沿与第N+4级驱动信号G（N+4）的上升沿位于同一时刻，或者，第N+4级驱动信号G（N+4）的上升沿滞后于第N+3级驱动信号G（N+3）的下降沿。
第N个辅助单元210的输入端与第N+2条驱动线连接。第N+1个辅助单元220的输入端与第N+3条驱动线连接。第N+2个辅助单元230的输入端与第N+4条驱动线连接。第N+3个辅助单元240的输入端与第N+5条驱动线连接。
如图5所示，在其中一个实施例中，驱动模块100可以包括第N级驱动单元110、第N+1级驱动单元120以及第N+2级驱动单元130；第N级驱动单元110用于输出第N级驱动信号G（N），第N级驱动单元110的输出端与第N条驱动线连接；第N+1级驱动单元120用于输出第N+1级驱动信号G（N+1），第N+1级驱动单元120的输出端与第N+1条驱动线连接；第N+2级驱动单元130用于输出第N+2级驱动信号G（N+2），第N+2级驱动单元130的输出端与第N+2条驱动线连接。
其中，第N-1个辅助单元209的输出端与第N-1条驱动线电性连接。第N个辅助单元210的输出端与第N条驱动线电性连接。第N+1个辅助单元220的输出端与第N+1条驱动线电性连接。
其中，第N-1个辅助单元209的控制端与第N条驱动线连接；第N-1级驱动信号的下降沿与第N级驱动信号G（N）的上升沿位于同一时刻，或者，第N级驱动信号G（N）的上升沿滞后于第N-1级驱动信号的下降沿。第N个辅助单元210的控制端与第N+1条驱动线连接；第N级驱动信号G（N）的下降沿与第N+1级驱动信号G（N+1）的上升沿位于同一时刻，或者，第N+1级驱动信号G（N+1）的上升沿滞后于第N级驱动信号G（N）的下降沿。第N+1个辅助单元220的控制端与第N+2条驱动线连接；第N+1级驱动信号G（N+1）的下降沿与第N+2级驱动信号G（N+2）的上升沿位于同一时刻，或者，第N+2级驱动信号G（N+2）的上升沿滞后于第N+1级驱动信号G（N+1）的下降沿。
在本实施例中，第一走线DDL可以为恒压低电位线VGL，该恒压低电位线VGL用于接入恒压低电位信号。该恒压低电位线VGL与第N-1个辅助单元209的输入端、第N个辅助单元210的输入端以及第N+1个辅助单元220的输入端。
其中，第N-1个辅助单元209可以包括第一晶体管T1和第二晶体管T2；恒压低电位线VGL与第一晶体管T1的源极/漏极中的一个和第二晶体管T2的源极/漏极中的一个连接；第N条驱动线与第一晶体管T1的栅极和第二晶体管T2的栅极连接；第N-1条驱动线与第一晶体管T1的源极/漏极中的另一个和第二晶体管T2的源极/漏极中的另一个连接。
其中，第N+1个辅助单元220可以包括第五晶体管T5和第六晶体管T6；恒压低电位线VGL与第五晶体管T5的源极/漏极中的一个和第六晶体管T6的源极/漏极中的一个连接；第N+2条驱动线与第五晶体管T5的栅极和第六晶体管T6的栅极连接；第N+1条驱动线与第五晶体管T5的源极/漏极中的另一个和第六晶体管T6的源极/漏极中的另一个连接。
可以理解的是，在该实施例中，一个辅助单元可以包括两个晶体管或者多个晶体管，该多个晶体管可以为三个晶体管、四个晶体管、五个晶体管或者六个晶体管中的一种，该两个晶体管或者多个晶体管可以为薄膜晶体管，便于制作与阵列基板上的显示区AA。其中，该薄膜晶体管可以但不限于为N沟道型薄膜晶体管，也可以为P沟道型薄膜晶体管。
如图5所示，在其中一个实施例中，辅助模块200可以包括一个或者多个第N个辅助单元210，多个第N个辅助单元210可以为两个第N个辅助单元210、三个第N个辅助单元210、四个第N个辅助单元210或者五个第N个辅助单元210中的一种。其中，每个第N个辅助单元210可以包括一个或者多个薄膜晶体管。例如，当多个第N个辅助单元210为两个第N个辅助单元210时，其中一个第N个辅助单元210可以包括第三晶体管T3，其中另一个第N个辅助单元210可以包括第四晶体管T4。恒压低电位线VGL与第三晶体管T3的源极/漏极中的一个和第四晶体管T4的源极/漏极中的一个连接；第N+1条驱动线与第三晶体管T3的栅极和第四晶体管T4的栅极连接；第N条驱动线与第三晶体管T3的源极/漏极中的另一个和第四晶体管T4的源极/漏极中的另一个连接。
在其中一个实施例中，第一走线DDL可以为第N+1条驱动线和第N+2条驱动线中的至少一个；当第N个辅助单元210的控制端与第N+1条驱动线连接时，第N个辅助单元210的输入端与第N+2条驱动线连接；或者，当第N个辅助单元210的控制端与第N+2条驱动线连接时，第N个辅助单元210的输入端与第N+1条驱动线连接。
在其中一个实施例中，第N个辅助单元210包括至少一个薄膜晶体管；至少一个薄膜晶体管的源极/漏极中的一个与第N条驱动线连接。
在其中一个实施例中，至少一个薄膜晶体管的栅极与第N+1条驱动线或者第N+2条驱动线连接。
在其中一个实施例中，显示面板还包括至少一条第一走线DDL；第一走线DDL与至少一个薄膜晶体管的源极/漏极中的另一个连接；其中，第一走线DDL用于接入恒压低电位信号。
在其中一个实施例中，至少一条第一走线DDL中的任一第一走线DDL至少部分位于显示区AA。
在其中一个实施例中，第N个辅助单元210包括第一薄膜晶体管和第二薄膜晶体管；第N条驱动线与第一薄膜晶体管的源极/漏极中的一个连接以在第N条驱动线上构造第一连接节点；第N条驱动线与第二薄膜晶体管的源极/漏极中的一个连接以在第N条驱动线上构造第二连接节点；第N条驱动线的一端至第一连接节点的距离、第一连接节点至第二连接节点的距离以及第二连接节点至第N条驱动线的另一端的距离中的至少两个是相等或者近似相等的。
需要进行说明的是，在同一个和/或不同的第N个辅助单元210中的所有薄膜晶体管在第N条驱动线构造出来的不同连接节点，相邻两个连接节点之间的距离可以相等或者近似相等，同时，第N条驱动线的一端至与其相邻的连接节点之间的距离也可以等于或者近似等于相邻两个连接节点之间的距离，以及第N条驱动线的另一端至与其相邻的连接节点之间的距离也可以等于或者近似等于相邻两个连接节点之间的距离。
需要进行说明的是，第N条驱动线的一端可以但不限于为第N级驱动单元的输出端，也可以为第N条驱动线位于其中一个非显示区与显示区的交界处的一个点；第N条驱动线的另一端可以为其中另一个非显示区与显示区的交界处的一个点。
可以理解的是，如此可以等距离同时拉低第N级驱动信号的下降沿，能够更快速且均匀地拉低第N级驱动信号的下降沿。
可以理解的是，随着显示面板的长度或者宽度的增加，对应的驱动线SL也会随之增长，对应的驱动信号在驱动线SL中传输也会受到越来越大的容抗和/或阻抗，那么驱动信号的波形也会产生对应的延迟，例如，驱动信号的下降沿会从某一时刻延长至某一时间段，对应地，下降沿也将从直线状态改变为曲线状态，进而致使驱动信号的下降沿不能够快速下拉，基于此，有必要通过不同下降沿的对比，可以更为明了本申请不同的实施例所带来的技术改进。
如图6所示，图6展示出了驱动信号的理想型波形图P1、传统型波形图P2以及本申请不同实施例改进型波形图P3，在理想型波形图P1、传统型波形图P2以及改进型波形图P3中，分别提供了第N级驱动信号G（N）、第N+1级驱动信号G（N+1）以及第N+2级驱动信号G（N+2）的波形图。
在理想型波形图P1中，第N级驱动信号G（N）、第N+1级驱动信号G（N+1）以及第N+2级驱动信号G（N+2）的上升沿或者下降沿均是直线状态，或者均是在同一时刻进行的上升或者下降，这种波形是显示面板所需的理想型波形，但是受限于容抗和/或阻抗的影响，总是会存在一定的延时。
例如，传统型波形图P2与改进型波形图P3的对比可知，传统型波形图P2中第N级驱动信号G（N）、第N+1级驱动信号G（N+1）以及第N+2级驱动信号G（N+2）的下降沿比改进型波形图P3中对应的第N级驱动信号G（N）、第N+1级驱动信号G（N+1）以及第N+2级驱动信号G（N+2）的下降沿经历了更长时间后才得以下拉至低电位。换句话说，上述实施例可以使得驱动信号的下降沿快速拉低，已改善驱动信号在显示区AA中受到容抗和/或阻抗导致的延迟。
可以理解的是，虽然对应的驱动单元中也可能存在对应的下拉电路，但是由于对应的下拉电路所在的驱动单元位于非显示区，所以这种具有下拉电路的驱动单元甚至驱动模块100也不可能达到与上述实施例相同的技术效果，而且本领域所属的技术人员普遍认为这些驱动模块100应该位于非显示区，因此，通常情况下，本领域所属的技术人员不容易想到可以将本实施例中的辅助模块200设置在显示区AA，且可以取得意料不到的技术效果。因此，本申请的发明构思在一定程度上克服了本领域长期以来形成的技术偏见，并且可以明显改善驱动信号的下降沿在显示区AA中的下拉速度或者驱动信号的上升沿在显示区AA中的上拉速度。
如图7所示，本申请提供了另一种驱动信号的波形对比示意图，其中，驱动信号S1为传统技术方案中的驱动信号，驱动信号S2为上述实施例中的驱动信号，驱动信号S3为较为理想状态的驱动信号；横轴可以表示为时间T，其单位可以为微秒（μs），纵轴可以表示电压值U，其单位可以为伏特（V）。
其中，驱动信号S3的上升沿的上升速度明显高于驱动信号S1的上升沿的上升速度和驱动信号S2的上升沿的上升速度，而驱动信号S1的上升沿的上升速度与驱动信号S2的上升沿的上升速度相近或者近似。驱动信号S3的下降沿的下降速度明显高于驱动信号S1的下降沿的下降速度和驱动信号S2的下降沿的下降速度；而驱动信号S1的下降沿的下降速度明显低于驱动信号S2的下降沿的下降速度；同时，在一些可能的情况下，驱动信号S1的低电位状态由于未收到辅助模块200的持续下拉作用，会容易出现一些比低电位状态稍高的一些电位状态，这会更加重驱动信号S1的波形恶化，进而影响显示面板的稳定性。
在其中一个实施例中，本实施例提供一种显示装置，其包括上述任一实施例中的显示面板。
可以理解的是，本实施例提供的显示装置，通过位于显示区中的辅助模块与对应的驱动线连接，可以使驱动线中传输的驱动信号的下降沿快速拉低，能够缓解非显示区中驱动模块传输驱动信号至显示区时存在的驱动信号失真问题。
需要进行说明的是，该显示装置还可以包括像素电路，该像素电路位于该显示装置的显示区，且该像素电路通过驱动线与驱动模块电性连接。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    第一走线；
    第N条扫描线，所述第N条扫描线的至少部分位于所述显示面板的显示区，用于传输第N级扫描信号，N为正整数；以及
    第N个辅助单元，所述第N个辅助单元位于所述显示面板的显示区，所述第N个辅助单元的输出端与所述第N条扫描线电性连接，所述第N个辅助单元的输入端与所述第一走线电性连接，所述第N个辅助单元的控制端与第N+M条扫描线电性连接，M为正整数。
  2. 根据权利要求1所述的显示面板，其中，所述第N个辅助单元包括：
    至少一个薄膜晶体管，所述薄膜晶体管的源极/漏极中的一个与所述第N条扫描线电性连接，所述薄膜晶体管的源极/漏极中的另一个与所述第一走线电性连接，所述薄膜晶体管的栅极与所述第N+M条扫描线电性连接。
  3. 根据权利要求2所述的显示面板，其中，所述第N条扫描线与多个所述薄膜晶体管的源极/漏极中的一个电性连接，以在所述第N条扫描线上构造对应的多个连接节点；
    所述第N级扫描信号从所述第N条扫描线的至少一端输入；
    其中，若所述第N级扫描信号从所述第N条扫描线的一端输入，则所述多个连接节点在靠近所述第N条扫描线的另一端的密度，大于所述多个连接节点在靠近所述第N条扫描线的一端的密度。
  4. 根据权利要求3所述的显示面板，其中，若所述第N级扫描信号从所述第N条扫描线的两端输入，则所述多个连接节点在所述第N条扫描线的中部的密度，大于所述多个连接节点在靠近所述第N条扫描线的任一端的密度。
  5. 根据权利要求2所述的显示面板，其中，若所述薄膜晶体管为N沟道型薄膜晶体管，所述第一走线用于传输恒压低电位信号。
  6. 根据权利要求2所述的显示面板，其中，若所述薄膜晶体管为N沟道型薄膜晶体管，所述薄膜晶体管打开时，所述第一走线用于传输低电位信号。
  7. 根据权利要求6所述的显示面板，其中，若所述第N个辅助单元的控制端与第N+1条扫描线电性连接，则所述第一走线为第N+X条扫描线，X为大于或者等于2的整数；
    若所述第N个辅助单元的控制端与第N+2条扫描线连接，所述第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
  8. 根据权利要求2所述的显示面板，其中，若所述薄膜晶体管为P沟道型薄膜晶体管，所述第一走线用于传输恒压高电位信号。
  9. 根据权利要求2所述的显示面板，其中，若所述薄膜晶体管为P沟道型薄膜晶体管，所述薄膜晶体管打开时，所述第一走线用于传输高电位信号。
  10. 根据权利要求9所述的显示面板，其中，若所述第N个辅助单元的控制端与第N+1条扫描线电性连接，则所述第一走线为第N+X条扫描线，X为大于或者等于2的整数；
    若所述第N个辅助单元的控制端与第N+2条扫描线连接，所述第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
  11. 一种显示装置，包括如权利要求1所述的显示面板。
  12. 根据权利要求11所述的显示装置，其中，所述第N个辅助单元包括：
    至少一个薄膜晶体管，所述薄膜晶体管的源极/漏极中的一个与所述第N条扫描线电性连接，所述薄膜晶体管的源极/漏极中的另一个与所述第一走线电性连接，所述薄膜晶体管的栅极与所述第N+M条扫描线电性连接。
  13. 根据权利要求12所述的显示装置，其中，所述第N条扫描线与多个所述薄膜晶体管的源极/漏极中的一个电性连接，以在所述第N条扫描线上构造对应的多个连接节点；
    所述第N级扫描信号从所述第N条扫描线的至少一端输入；
    其中，若所述第N级扫描信号从所述第N条扫描线的一端输入，则所述多个连接节点在靠近所述第N条扫描线的另一端的密度，大于所述多个连接节点在靠近所述第N条扫描线的一端的密度。
  14. 根据权利要求13所述的显示装置，其中，若所述第N级扫描信号从所述第N条扫描线的两端输入，则所述多个连接节点在所述第N条扫描线的中部的密度，大于所述多个连接节点在靠近所述第N条扫描线的任一端的密度。
  15. 根据权利要求12所述的显示装置，其中，若所述薄膜晶体管为N沟道型薄膜晶体管，所述第一走线用于传输恒压低电位信号。
  16. 根据权利要求12所述的显示装置，其中，若所述薄膜晶体管为N沟道型薄膜晶体管，所述薄膜晶体管打开时，所述第一走线用于传输低电位信号。
  17. 根据权利要求16所述的显示装置，其中，若所述第N个辅助单元的控制端与第N+1条扫描线电性连接，则所述第一走线为第N+X条扫描线，X为大于或者等于2的整数；
    若所述第N个辅助单元的控制端与第N+2条扫描线连接，所述第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
  18. 根据权利要求12所述的显示装置，其中，若所述薄膜晶体管为P沟道型薄膜晶体管，所述第一走线用于传输恒压高电位信号。
  19. 根据权利要求12所述的显示装置，其中，若所述薄膜晶体管为P沟道型薄膜晶体管，所述薄膜晶体管打开时，所述第一走线用于传输高电位信号。
  20. 根据权利要求19所述的显示装置，其中，若所述第N个辅助单元的控制端与第N+1条扫描线电性连接，则所述第一走线为第N+X条扫描线，X为大于或者等于2的整数；
    若所述第N个辅助单元的控制端与第N+2条扫描线连接，所述第一走线为第N+Y条扫描线，Y为等于1，或者Y为等于或者大于3的整数。
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