WO2022244837A1 - 半導体装置の製造方法およびレーザアニール装置 - Google Patents

半導体装置の製造方法およびレーザアニール装置 Download PDF

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Publication number
WO2022244837A1
WO2022244837A1 PCT/JP2022/020813 JP2022020813W WO2022244837A1 WO 2022244837 A1 WO2022244837 A1 WO 2022244837A1 JP 2022020813 W JP2022020813 W JP 2022020813W WO 2022244837 A1 WO2022244837 A1 WO 2022244837A1
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Prior art keywords
annealing step
region
regions
laser light
beam spot
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English (en)
French (fr)
Japanese (ja)
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和彦 長谷川
暢彦 大森
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023522713A priority Critical patent/JP7618030B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing

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  • the present disclosure relates to a semiconductor device manufacturing method and a laser annealing apparatus.
  • a laser annealing process is performed in which a semiconductor substrate is irradiated with laser light to anneal an impurity region for the purpose of activating an impurity region formed in the semiconductor substrate.
  • a semiconductor substrate is divided into a plurality of irradiation areas, and beam spots of laser light are sequentially formed on each irradiation area.
  • an overlap rate is generally set between adjacent irradiation regions, and adjacent regions with the set overlap rate are generally set.
  • the two matching irradiation regions are continuously irradiated with laser light.
  • Patent Document 1 In International Publication No. WO 2019/244665 (Patent Document 1), two irradiation regions with consecutive incident orders do not have overlapping portions, but two irradiation regions with non-sequential incident orders have overlapping portions with each other. discloses a technique for setting the irradiation order and arrangement of a plurality of irradiation areas. If the process of sequentially irradiating each of the plurality of irradiation regions with laser light is regarded as one laser annealing process, each overlapping portion is formed within the one laser annealing process.
  • the time difference between the first laser light irradiation and the second laser light irradiation for forming each overlapped portion is equal to the time difference between the two adjacent irradiations for which the overlap rate is set. Although it is longer than the time when the regions are continuously irradiated with the laser light, it is set shorter than the time required to sequentially irradiate each of the plurality of irradiation regions with the laser light once.
  • each of the plurality of irradiation regions has an overlapping portion, and the time difference between the two irradiations for forming each overlapping portion is relatively short. Therefore, in the conventional technology, the semiconductor substrate heated by the first laser beam irradiation is reheated by the second laser beam irradiation, and the temperature of the semiconductor substrate tends to rise relatively high. .
  • An example of such a structure is a protective film which is formed on the surface of the semiconductor substrate opposite to the laser beam irradiation surface before the laser annealing process and which is removed after the laser annealing process.
  • a main object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of suppressing temperature rise of a semiconductor substrate as compared with the conventional technology while preventing formation of an impurity region that is not sufficiently annealed, and the manufacturing method.
  • An object of the present invention is to provide a laser annealing apparatus for realizing the method.
  • a method for manufacturing a semiconductor device has a first surface extending along a first direction and a second direction orthogonal to the first direction, and a plurality of element formation regions are arranged on the first surface. preparing a semiconductor substrate in which a first impurity region is formed in each of a plurality of element formation regions; and sequentially irradiating each of the plurality of element formation regions with a laser beam to anneal the first impurity region. and a first annealing step.
  • the first width in the first direction of the beam spot formed on the first surface by the laser light is narrower than the second width in the second direction of the beam spot.
  • the relative movement distance of the beam spot in the first direction is the first width
  • the beam spot in the second direction is The second width is the relative movement distance of the spot.
  • a laser annealing apparatus has a first surface extending along a first direction and a second direction orthogonal to the first direction, and holds a semiconductor substrate in which a first impurity region is formed. irradiating a first surface of a semiconductor substrate held by the holding portion with a laser beam, and one of a plurality of regions of the first surface arranged side by side in at least one of the first direction and the second direction; An optical system for forming beam spots in two regions, and a scanning unit for scanning one of the semiconductor substrate and the optical system with respect to the other.
  • the optical system is provided to form a beam spot on the first surface, the first width in the first direction being narrower than the second width in the second direction.
  • the scanning unit scans the first surface with respect to the optical system by a first width in the first direction, and scans the first surface with respect to the optical system in the first direction. After scanning by the first width, the first surface is scanned by the second width in the second direction with respect to the optical system.
  • a method for manufacturing a semiconductor device and a method for manufacturing a semiconductor device, which can suppress temperature rise of a semiconductor substrate as compared with conventional techniques while preventing formation of an impurity region that is not sufficiently annealed. It is possible to provide a laser annealing apparatus for realizing
  • FIG. 1 is a partial cross-sectional view showing an example of a semiconductor device according to Embodiment 1;
  • FIG. 4 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Embodiment 1;
  • 4A and 4B are diagrams showing examples of the shape of a beam spot of laser light and the intensity distribution of laser light along each of the first direction and the second direction in the method of manufacturing the semiconductor device according to the first embodiment;
  • FIG. 3 is a diagram for explaining a scanning path of a beam spot in the first laser annealing step shown in FIG. 2; 7 is a diagram for more specifically explaining the scanning path of the beam spot shown in FIG. 6;
  • FIG. 1 is a block diagram showing an example of a laser annealing apparatus according to Embodiment 1;
  • FIG. 8 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Embodiment 2; 10 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Embodiment 3; 13 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Embodiment 4; 14 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Embodiment 5;
  • a semiconductor device 101 according to the first embodiment is obtained by dicing a plurality of chips formed on a semiconductor substrate 1 by a method for manufacturing the semiconductor device 101, which will be described later.
  • the semiconductor device 101 is, for example, a reverse conducting IGBT (RC-IGBT: Reverse Conducting Insulated Gate Bipolar Transistor), and includes a trench gate IGBT and a trench gate IGBT connected in anti-parallel with this IGBT.
  • RC-IGBT Reverse Conducting Insulated Gate Bipolar Transistor
  • the semiconductor substrate 1 has a first surface 1A and a second surface 1B opposite to the first surface 1A.
  • first surface 1A is the bottom surface of the semiconductor substrate 1 .
  • a second surface 1B is the upper surface of the semiconductor substrate 1 .
  • a semiconductor device 101 shown in FIG. 1 includes an IGBT region 101A that is an IGBT operating region and an FWD region 101B that is an FWD operating region.
  • IGBT region 101A and FWD region 101B are arranged in parallel in an active region on the same semiconductor substrate 1 .
  • the active region is the region through which current flows when in the ON state.
  • the IGBT 101A includes an n ⁇ type drift layer 2, a p type base layer 3, a p + type contact layer 4, an n + type emitter layer 5, a gate insulating film 6, a gate electrode 7, an n type buffer layer 8, a p type collector layer 9, an interlayer It has an insulating film 10, a barrier metal 11, a plug 12, an emitter electrode 13A and a collector electrode 14A.
  • the p-type base layer 3 is arranged on the top surface of the n ⁇ type drift layer 2 .
  • Each of p + -type contact layer 4 and n + -type emitter layer 5 is arranged on the upper surface of p-type base layer 3 .
  • the n + -type emitter layer 5 is arranged so as to surround the p + -type contact layer 4 .
  • the n-type buffer layer 8 is arranged on the lower surface of the n ⁇ type drift layer 2 .
  • P-type collector layer 9 is arranged on the lower surface of n ⁇ type drift layer 2 .
  • a plurality of trenches T are formed in the IGBT region 101A.
  • each of trenches T extends from the upper surface of n + -type emitter layer 5 through n + -type emitter layer 5 and p-type base layer 3 to reach n ⁇ -type drift layer 2 .
  • the gate insulating film 6 and the gate electrode 7 are embedded inside the trench T.
  • Gate insulating film 6 is arranged along the inner wall surface of trench T.
  • Gate electrode 7 faces p-type base layer 3 with gate insulating film 6 interposed therebetween.
  • Each of the plurality of trenches T is arranged at intervals in a direction in which the IGBT region 101A and the FWD region 101B are arranged (horizontal direction in FIG. 1), for example, in plan view.
  • Each of the plurality of trenches T extends, for example, in a direction (depth direction in FIG. 1) perpendicular to the direction in which the IGBT regions 101A and the FWD regions 101B are arranged.
  • the plurality of trenches T are arranged in stripes, for example, in a plan view.
  • n + -type emitter layer 5 is arranged between adjacent trenches T (mesa regions), it is not limited to this.
  • the n + -type emitter layer 5 may be arranged in at least one mesa region between adjacent trenches T (mesa region). There may be a mesa region where the n + -type emitter layer 5 is not arranged. Also, a plurality of n + -type emitter layers 5 may be arranged at predetermined intervals in the direction in which the trenches T extend in stripes (the depth direction in FIG. 1).
  • the interlayer insulating film 10 covers the top surface of the gate electrode 7 .
  • Interlayer insulating film 10 is provided so as to electrically insulate gate electrode 7 arranged under interlayer insulating film 10 and emitter electrode 13A arranged on interlayer insulating film 10 .
  • a contact hole is formed in the interlayer insulating film 10, and the p + -type contact layer 4 and the n + -type emitter layer 5 are exposed in the contact hole.
  • the barrier metal 11 is arranged so as to cover the surfaces of the interlayer insulating film 10 and the contact holes. Barrier metal 11 is in contact with the upper surfaces of p + -type contact layer 4 and n + -type emitter layer 5 exposed in the contact hole. A plug 12 is embedded on the barrier metal 11 in the contact hole.
  • the emitter electrode 13A is arranged on the barrier metal 11 and the plug 12.
  • An aluminum alloy is generally used for the emitter electrode 13A.
  • Emitter electrode 13A is connected to each of n + -type emitter layer 5 and p + -type contact layer 4 via barrier metal 11 and plug 12 .
  • Collector electrode 14A is in contact with p-type collector layer 9 .
  • the FWD region 101B of the semiconductor device 101 includes an n ⁇ type drift layer 2, a p type anode layer 15, a p + type anode layer 16, a gate insulating film 6, a dummy gate electrode 17, an n type buffer layer 8, an n + type cathode layer 18, It has an electrode 13B and a cathode electrode 14B.
  • the p-type anode layer 15 is arranged on the upper surface of the n ⁇ type drift layer 2 .
  • the p + -type anode layer 16 is arranged on the upper surface of the p-type anode layer 15 .
  • the n-type buffer layer 8 is arranged on the lower surface of the n ⁇ type drift layer 2 .
  • the n + -type cathode layer 18 is arranged on the bottom surface of the n-type buffer layer 8 .
  • a plurality of trenches T are formed in each of the FWD regions 101B.
  • each of trenches T extends from the upper surface of p + -type anode layer 16 through p + -type anode layer 16 and p-type anode layer 15 to reach n ⁇ -type drift layer 2 .
  • the gate insulating film 6 and the dummy gate electrode 17 are embedded inside the trench T. As shown in FIG.
  • the FWD region 101B includes an n-type drift layer 2, a gate insulating film 6, and an n-type buffer layer 8 in common with the IGBT region 101A.
  • the top surface of the dummy gate electrode 17 is covered with the interlayer insulating film 10 .
  • Dummy gate electrode 17 is electrically insulated by interlayer insulating film 10 from electrode 13B arranged on interlayer insulating film 10 .
  • the electrode 13B is provided integrally with the emitter electrode 13A.
  • the second electrode 13 as a single member is formed over both the IGBT region 101A and the FWD region 101B. 13 constitutes the electrode 13B.
  • the dummy gate electrode 17 may be electrically connected to the electrode 13B.
  • Cathode electrode 14B is joined to n+ type cathode layer 18 .
  • the cathode electrode 14B is provided integrally with the collector electrode 14A.
  • the first electrode 14 as a single member is formed over both the IGBT region 101A and the FWD region 101B. 14 constitutes the cathode electrode 14B.
  • n ⁇ type drift layer 2 the p type base layer 3, the p + type contact layer 4, the n + type emitter layer 5, the gate insulating film 6, the gate electrode 7, the n type buffer layer 8, and the p type collector layer 9 are formed on a semiconductor substrate.
  • 1 is arranged between the first surface 1A and the second surface 1B.
  • Collector electrode 14A is arranged on first surface 1A.
  • Interlayer insulating film 10, barrier metal 11, plug 12, and emitter electrode 13A are arranged on second surface 1B.
  • the semiconductor device 101 may have a breakdown voltage structure such as a guard ring provided in the edge termination region arranged so as to surround the active region.
  • the method for manufacturing a semiconductor device 101 includes a step of preparing a semiconductor substrate 1 having a first impurity region formed thereon (S10), and irradiating the first surface with a laser beam to perform the first step. and a first annealing step (S20) of annealing the one impurity region.
  • the first impurity region includes an impurity region to form n-type buffer layer 8 , an impurity region to form p-type collector layer 9 , and an impurity region to form n + type cathode layer 18 .
  • the semiconductor substrate 1 on which the p-type collector layer 9 and the n+ type cathode layer 18 are formed is prepared as an object to be laser-annealed in the first annealing step (S20).
  • the semiconductor substrate 1 is manufactured by, for example, sequentially performing the following steps (S1) to (S4).
  • step (S1) element structures are formed on the second surface 1B side of the semiconductor substrate 1 in each of the IGBT region 101A and the FWD region 101B.
  • a semiconductor substrate 1 is prepared.
  • the semiconductor substrate 1 has a third surface and a second surface 1B opposite to the third surface.
  • Each of the third surface and the second surface 1B extends along the first direction X and the second direction Y orthogonal to the first direction X.
  • the material constituting the semiconductor substrate 1 may be any semiconductor material, such as silicon (Si) or silicon carbide (SiC).
  • the conductivity type of the semiconductor substrate 1 is n ⁇ type.
  • a p-type base layer 3, a p-type anode layer 15, a p+-type contact layer 4, and an n+-type emitter layer 5 are formed on the upper surface (second surface 1B) of the semiconductor substrate 1.
  • Each of p-type base layer 3, p + -type contact layer 4 and n + -type emitter layer 5 is formed by ion implantation using a mask pattern formed by photolithography. For example, a set of a process of forming a mask pattern using photolithography, an ion implantation process using the mask pattern, and a process of removing the mask pattern is repeatedly performed under different conditions.
  • the p-type base layer 3 and the p-type anode layer 15 are formed by one ion implantation process, for example. In other words, p-type base layer 3 and p-type anode layer 15 are formed such that one of p-type base layer 3 and p-type anode layer 15 serves as the other.
  • the p + -type contact layer 4 and the n + -type emitter layer 5 are selectively formed inside the p-type base layer 3 in the IGBT region 101A.
  • a field oxide film covering the second surface 1B is formed in the edge termination region.
  • the field oxide film is formed by thermally oxidizing the second surface 1B of the semiconductor substrate 1, for example.
  • a plurality of trenches T are formed in each of IGBT region 101A and FWD region 101B. As described above, the plurality of trenches T are formed in stripes, for example, in plan view.
  • step (S1) next, a gate insulating film 6 is formed inside a plurality of trenches T in each of the IGBT regions 101A and the FWD regions 101B. Gate insulating film 6 is formed along the inner wall surface of each trench T. As shown in FIG. The gate insulating film 6 is formed by thermally oxidizing the inner wall surface of each trench T, for example.
  • step (S1) next, gate electrodes 7 and dummy gate electrodes 17 are formed inside the plurality of trenches T in each of the IGBT regions 101A and the FWD regions 101B.
  • the polysilicon film on second surface 1B is removed by an etch back process. As a result, the polysilicon film left inside each trench T becomes the gate electrode 7 and the dummy gate electrode 17, respectively.
  • a MOS gate having a trench gate structure composed of the n ⁇ type drift layer 2, the p type base layer 3, the p+ type contact layer 4, the n+ type emitter layer 5, the gate insulating film 6, and the gate electrode 7 is formed. It is formed. Note that the p + -type contact layer 4 and the n + -type emitter layer 5 may be formed after forming the gate electrode 7 .
  • interlayer insulating film 10 barrier metal 11, plug 12, and second electrode 13 are formed in each of IGBT region 101A and FWD region 101B.
  • Interlayer insulating film 10 is formed on second surface 1B.
  • a plurality of contact holes are formed in the interlayer insulating film 10 .
  • Each contact hole penetrates interlayer insulating film 10 in a direction perpendicular to second surface 1B.
  • the p + -type contact layer 4 and the n + -type emitter layer 5 are exposed.
  • Barrier metal 11 is formed on the upper surface of p + -type contact layer 4 and n + -type emitter layer 5 exposed from each contact hole, the inner wall surface of each contact hole, and the upper surface of interlayer insulating film 10 .
  • a plug 12 is formed on the barrier metal 11 so as to fill the inside of each contact hole.
  • a second electrode 13 is formed on the barrier metal 11 and the plug 12 .
  • an element structure is formed on the second surface 1B side of semiconductor substrate 1 in each of IGBT region 101A and FWD region 101B.
  • a protective film is formed on the second surface 1B (step (S2)).
  • the protective film is formed so as to cover the structures.
  • Materials constituting the protective film include at least one selected from the group consisting of, for example, polyimide, resist, and silicon oxide.
  • the protective film may be a film or tape-like member.
  • the protective film may be a coating film.
  • the temperature at which the protective film is not deformed, degraded, or the like is referred to as the heat resistant temperature of the protective film.
  • the heat-resistant temperature of the protective film is higher than the reaching temperature of the protective film in the post-process of this step (S2).
  • the heat resistance temperature of the protective film is, for example, lower than the glass transition temperature (Tg) of the material forming the protective film.
  • the semiconductor substrate 1 is ground (back ground) from the third surface side to thin the semiconductor substrate 1 (step (S3)).
  • step (S3) the thickness of the semiconductor substrate 1 is the thickness of the semiconductor substrate 1 in the semiconductor device 101 .
  • a first surface 1A is formed on the side of the semiconductor substrate 1 opposite to the second surface 1B.
  • an impurity region to be the n-type buffer layer 8 an impurity region to be the p-type collector layer 9, and an n + -type impurity region are formed on the first surface 1A side of the semiconductor substrate 1.
  • Impurity regions to be cathode layers 18 are formed (step (S4)).
  • an impurity region that will become the n-type buffer layer 8, an impurity region that will become the p-type collector layer 9, and an impurity region that will become the n+ type cathode layer 18 are formed in this order.
  • Each impurity region is formed by, for example, repeating under different conditions a set of steps of forming a mask pattern using photolithography, ion implantation using the mask pattern, and removing the mask pattern. ,It is formed.
  • n-type ions for forming n-type buffer layer 8 are implanted into semiconductor substrate 1 using a mask pattern that exposes first surface 1A of each of IGBT region 101A and FWD region 101B.
  • An n-type ion is, for example, phosphorus (P).
  • p-type ions for forming p-type collector layer 9 are implanted into semiconductor substrate 1 using a mask pattern that exposes first surface 1A of IGBT region 101A.
  • a p-type ion is, for example, boron (B).
  • n-type ions for forming the n+-type cathode layer 18 are implanted into the semiconductor substrate 1 .
  • An n-type ion is P, for example.
  • the semiconductor substrate 1 is prepared in which an impurity region that will form the n-type buffer layer 8, an impurity region that will form the p-type collector layer 9, and an impurity region that will form the n+ type cathode layer 18 are formed.
  • the prepared semiconductor substrate 1 is subjected to a first annealing step (S20).
  • laser light is applied to each of the impurity region that will form the n-type buffer layer 8, the impurity region that will form the p-type collector layer 9, and the impurity region that will form the n+ type cathode layer 18.
  • the impurity region to be the n-type buffer layer 8, the impurity region to be the p-type collector layer 9, and the impurity region to be the n + -type cathode layer 18 are annealed. Impurities in the impurity regions are activated.
  • An example of a laser annealing apparatus for performing this step (S20) will be described later.
  • the width (first width) in the first direction X of the beam spot S of the laser light irradiated onto the first surface 1A in step (S20) is the width in the second direction Y of the beam spot S. Narrower than the width (second width).
  • the beam spot S has an elongated shape in which the first direction X is the lateral direction and the second direction Y is the longitudinal direction.
  • the shape of the beam spot S may be any long shape, such as a rectangular shape.
  • the beam profile P1 of the laser light in the first direction X and the beam profile P2 of the laser light L in the second direction Y with which the first surface 1A is irradiated in step (S20) are top-flat. have a shape.
  • the beam spot S shown in FIG. 3 can be formed by irradiating the first surface 1A with laser light shaped by a beam homogenizer.
  • the first surface 1A is arranged side by side in each of the first direction X and the second direction Y, and has a first width in the first direction X and a second width in the second direction Y. It has an illuminated area.
  • the first surface 1A is divided into a plurality of irradiated areas having the same size as the beam spot.
  • the plurality of irradiated regions includes a first group of irradiated regions, a second group of irradiated regions, and a third group of irradiated regions.
  • Each of the first group of irradiation regions, the second group of irradiation regions, and the third group of irradiation regions includes a plurality of irradiation regions arranged side by side in the first direction X, and They are arranged side by side in the Y direction.
  • each of the plurality of irradiated regions may or may not be associated with each of the plurality of element forming regions of the semiconductor substrate 1 described above.
  • Each irradiated region may be a region that overlaps with an element formation region and an inner peripheral region of a dicing region (dicing line) arranged to surround it.
  • Each irradiated region may overlap with a plurality of element forming regions and a part of a dicing region (dicing line) arranged in a lattice to surround them.
  • an irradiation step of forming a beam spot in one of the plurality of irradiation regions is performed a plurality of times, and a laser beam is emitted during each of the plurality of irradiation steps.
  • a first step of scanning the first surface of the optical system by a first width in the first direction X, a second step of scanning the first surface of the optical system by a second width in the second direction Y, or A third step of scanning the first surface by the first width in the direction opposite to the first direction X with respect to the optical system is performed.
  • FIG. 4 is a diagram for explaining the path along which the beam spot is scanned with respect to the first surface 1A. In FIG. 4, illustration of the irradiated area is omitted.
  • the step (S20) first, among the plurality of irradiated regions, positioned at one end in the second direction Y (upper end toward the paper surface of FIG. 4), The above-described irradiation step is sequentially performed on the first group of irradiated regions arranged in line with X. As shown in FIG. Specifically, first, of the first group of irradiated regions, one irradiated region located at one end of the first surface 1A in the first direction X (the left end when facing the paper surface of FIG. 4) is , the irradiation step is performed. After that, the first step and the irradiation step are repeated. This scanning path is along line segment 61 in FIG. In the final irradiation step, one irradiated region located at the other end of the first surface 1A in the first direction X (the right end when facing the paper surface of FIG. 4) among the irradiated regions of the first group done.
  • a second step is then performed.
  • This scanning path is along line segment 62 in FIG.
  • the irradiation steps are sequentially performed. Specifically, first, of the second group of irradiated regions, one irradiated region positioned at the other end of the first surface 1A in the first direction X (the right end as viewed from the paper surface of FIG. 4) is , the irradiation step is performed. After that, the third step and the irradiation step are repeated.
  • This scanning path is along line segment 63 in FIG. In the last irradiation step, one irradiated region located at one end of the first surface 1A in the first direction X (the left end when facing the paper surface of FIG. 4) among the second group of irradiated regions done.
  • a second step is then performed.
  • This scanning path is along line segment 64 in FIG.
  • the irradiation steps are sequentially performed. Specifically, first, among the irradiation regions of the third group, for one irradiation region located at one end of the first surface 1A in the first direction X (the left end when facing the paper surface of FIG. 4) , the irradiation step is performed. After that, the first step and the irradiation step are repeated.
  • This scanning path is along line segment 65 in FIG.
  • one irradiation region located at the other end of the first surface 1A in the first direction X (the right end as viewed from the paper surface of FIG. 4) is irradiated with done. At least a part of the irradiated regions in the third group is in contact with each of the irradiated regions in the second group.
  • FIGS. 5(a) to (h) are diagrams for explaining the scanning path in more detail.
  • FIGS. 5A to 5H among the plurality of irradiation regions, each of the irradiation regions arranged in four rows in the first direction X and two rows in the second direction Y, and each coordinate, and 1 A beam spot S formed on one irradiated area is shown.
  • the irradiation process is performed on the irradiated region with coordinates (0, 0) among the eight irradiated regions. As a result, a beam spot S is formed on the irradiated region at coordinates (0, 0).
  • a first step is performed.
  • the irradiation process is performed on the irradiated region with coordinates (1, 0) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (1, 0).
  • This beam spot S is formed so as not to overlap with the irradiated region of coordinates (0, 0) in which the beam spot S was formed immediately before, but to be in contact therewith.
  • the beam spot S is formed such that its long side is in contact with the long side of the irradiated region of coordinates (0, 0) in which the beam spot S was formed immediately before.
  • a first step is performed.
  • the irradiation process is performed on the irradiated region at coordinates (2, 0) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (2, 0).
  • This beam spot S is formed so as not to overlap with the irradiated region of coordinates (1, 0) in which the beam spot S was formed immediately before, but to be in contact therewith.
  • the beam spot S is formed such that its long side is in contact with the long side of the irradiated region of coordinates (1, 0) in which the beam spot S was formed immediately before.
  • a first step is performed.
  • the irradiation process is performed on the irradiated region at coordinates (3, 0) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (3, 0).
  • This beam spot S is formed so as not to overlap with the irradiated region of coordinates (2, 0) in which the beam spot S was formed immediately before, but to be in contact therewith.
  • the beam spot S is formed such that its long side is in contact with the long side of the irradiated region at the coordinates (2, 0) where the beam spot S was formed immediately before.
  • the second step is performed.
  • the first step and the second step may be performed at least once, and the third step may be performed at least once in this order.
  • the beam spot when the beam spot is scanned in the second direction Y, the beam spot may be scanned outside the end of the first surface 1A in the first direction X.
  • the irradiation process is performed on the irradiated region at coordinates (3, 1) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (3, 1).
  • This beam spot S is formed so as not to overlap with the irradiated region of coordinates (3, 0) in which the beam spot S was formed immediately before, but to be in contact therewith.
  • the beam spot S is formed such that its short side is in contact with the short side of the irradiated region at the coordinates (3, 0) where the beam spot S was formed immediately before.
  • a third step is performed.
  • the irradiation process is performed on the irradiated region at coordinates (2, 1) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (2, 1).
  • This beam spot S overlaps the irradiated region with coordinates (2, 0) in which the beam spot S was previously formed and the irradiated region with coordinates (3, 1) in which the beam spot S was formed immediately before. instead, they are formed so as to touch each other.
  • the long side of the beam spot S is in contact with the long side of the irradiated area at the coordinates (3, 1) where the beam spot S was formed immediately before, and the short side is at the coordinates ( 2, 0) in contact with the short side of the irradiated region.
  • a third step is performed.
  • the irradiation process is performed on the irradiated region with coordinates (1, 1) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (1, 1).
  • This beam spot S overlaps the irradiated region with coordinates (1, 0) in which the beam spot S was previously formed and the irradiated region with coordinates (2, 1) in which the beam spot S was formed immediately before. instead, they are formed so as to touch each other.
  • the long side of the beam spot S is in contact with the long side of the irradiated area at the coordinates (2, 1) where the beam spot S was formed immediately before, and the short side is at the coordinates ( 1, 0) so as to be in contact with the short side of the irradiated region.
  • a third step is performed.
  • the irradiation process is performed on the irradiated region with coordinates (0, 1) among the eight irradiated regions.
  • a beam spot S is formed on the irradiated region at coordinates (0, 1).
  • This beam spot S overlaps the irradiated region with coordinates (0, 0) in which the beam spot S was previously formed and the irradiated region with coordinates (1, 1) in which the beam spot S was formed immediately before. instead, they are formed so as to touch each other.
  • the long side of the beam spot S is in contact with the long side of the irradiated area at the coordinates (1, 1) where the beam spot S was formed immediately before, and the short side is at the coordinates (1) where the beam spot S was formed first. 0, 0) in contact with the short side of the irradiated region.
  • the first annealing step (S20) is repeated twice.
  • the scanning path in the second first annealing step (S20) is the same as the scanning path in the first first annealing step (S20).
  • the second first annealing step (S20) is continuously performed after the first first annealing step (S20) is completed.
  • the intensity of the laser light in each of the first and second first annealing steps (S20) is set to be, for example, the same as the intensity of the laser light in the first first annealing step (S20).
  • a method for removing the protective film is, for example, at least one of a dry etching method and a wet etching method.
  • the first electrode 14 is formed on the first surface 1A (step (S40)).
  • a plurality of semiconductor devices 101 are obtained by singulating (dicing) each of the plurality of element forming regions of the semiconductor substrate 1 .
  • a laser annealing apparatus 200 shown in FIG. 6 is used in the above step (S20).
  • the laser annealing apparatus 200 mainly includes an optical system 30 , a holding section 31 , a scanning section 32 and a control section 33 .
  • the optical system 30 mainly includes a first laser oscillator 40 , a second laser oscillator 41 , a plurality of mirrors 42 , a coupling optical system 43 , a beam homogenizer 44 and a condenser lens 45 .
  • Each of the first laser oscillator 40 and the second laser oscillator 41 outputs pulsed laser light.
  • the pulsed laser output from the first laser oscillator 40 is called first pulsed laser light
  • the pulsed laser output from the second laser oscillator 41 is called second pulsed laser light.
  • the second laser oscillator 41 outputs the second pulsed laser beam after a predetermined delay time has elapsed since the first laser oscillator 40 output the first pulsed laser beam.
  • the first pulsed laser beam enters the coupling optical system 43 via the mirror 42 .
  • the second pulsed laser beam enters the coupling optical system 43 via the mirror 42 .
  • the coupling optical system 43 combines the first pulsed laser beam and the second pulsed laser beam into one laser beam. For example, the first pulsed laser beam is reflected by the coupling optical system 43 and the second pulsed laser beam is transmitted through the coupling optical system 43 . The first pulsed laser beam reflected by the coupling optical system 43 is coupled with the second pulsed laser beam transmitted through the coupling optical system 43 .
  • the laser beams combined by the coupling optical system 43 pass through the mirror 42 and enter the beam homogenizer 44 .
  • the beam homogenizer 44 shapes the beam spot shape and beam profile of the laser light on the first surface 1A.
  • the laser light shaped by the beam homogenizer 44 is condensed by the condensing lens 45 and then irradiated as the laser light L onto the first surface 1A.
  • the holding part 31 holds the semiconductor substrate 1 .
  • the holding part 31 horizontally holds the first surface 1A of the semiconductor substrate 1, for example.
  • Each of the first direction X and the second direction Y is a direction along the horizontal direction.
  • the semiconductor substrate 1 is arranged on the holding portion 31 such that the protective film formed on the second surface 1 ⁇ /b>B, for example, is in contact with the upper surface of the holding portion 31 .
  • the scanning unit 32 moves the semiconductor substrate 1 held by the holding unit 31 in the first direction X and the second direction Y respectively.
  • the scanning unit 32 is an XY stage that can move in the first direction X and the second direction Y, respectively.
  • the control unit 33 controls the intensity of the pulsed laser light output from each of the first laser oscillator 40 and the second laser oscillator 41 , the delay time described later, and the movement distance of the semiconductor substrate 1 by the scanning unit 32 .
  • the control unit 33 reads a signal from an encoder attached to the holding unit 31 and obtains position information of the semiconductor substrate 1 .
  • One shot of pulsed laser light is output from each of the first laser oscillator 40 and the second laser oscillator 41 based on the positional information of the semiconductor substrate 1, and the laser light is emitted from the optical system 30 to the target irradiation area. . Thereby, the beam spot is formed in the region.
  • FIG. 7 is a diagram for explaining how the intensity of each of the first pulsed laser beam, the second pulsed laser beam, and the laser beam combined by the coupling optical system 43 changes over time. is.
  • the horizontal axis of FIG. 7 indicates time, and the vertical axis indicates intensity.
  • waveform 201 indicates the intensity waveform of the first pulsed laser beam
  • waveform 202 indicates the intensity waveform of the second pulsed laser beam
  • waveform 210 indicates the intensity waveform of the laser beam irradiated from the optical system 30. show.
  • the laser light consists of a first pulsed laser beam and a second pulsed laser beam output after a delay time td has elapsed since the first pulsed laser beam was output from the first laser oscillator 40. It is generated by being combined with light.
  • the laser light By generating the laser light as described above, it is possible to sufficiently secure the time te in which the intensity of the laser light reaches the intensity P1 or more while suppressing the intensity of the laser light to the intensity P2 or less.
  • Intensity P1 is the intensity required to activate impurities in each of the impurity region to form n-type buffer layer 8, the impurity region to form p-type collector layer 9, and the impurity region to form n+ type cathode layer 18. is.
  • the strength P2 is a strength that can alter the quality of the protective film formed on the second surface 1B.
  • the delay time td can be arbitrarily set by adjusting the output timing of the trigger signal from the control section 33. Also, the time te can be adjusted to an arbitrary value by changing the delay time td, the intensity of each of the first pulsed laser beam and the second pulsed laser beam, and the like.
  • the waveform 210 of the laser light has a first peak and a second peak.
  • the delay time Td, the first pulsed laser light and the 2, each intensity of the pulsed laser light is set.
  • Each of the first pulsed laser light and the second pulsed laser light is visible light.
  • Each wavelength of the first pulsed laser light and the second pulsed laser light is set to 400 nm or more and less than 600 nm.
  • Each of the first pulsed laser light and the second pulsed laser light is, for example, a second harmonic of an Nd:YLF laser, a second harmonic of an Nd:YAG laser, or a second harmonic of an Nd:YVO4 laser. be.
  • the pulse half width of each of the first pulsed laser light and the second pulsed laser light is 100 ns or more and less than 5 ⁇ s.
  • the heat may not sufficiently reach a region with a depth of about 1 ⁇ m from the first surface 1A of the semiconductor substrate 1, and the impurities present in this region may not be sufficiently activated. Further, when the pulse half-value width is 5 ⁇ s or more, heat may be transmitted to the second surface 1B of the semiconductor substrate 1, and the structure on the second surface 1B may be thermally damaged.
  • the delay time td also depends on the pulse half width of each of the first pulsed laser beam and the second pulsed laser beam, preferably the delay time td is 200 ns or more, and the first peak value PP1 is the first It is set according to the pulse half width and intensity ratio of each of the first pulsed laser beam and the second pulsed laser beam so as to be 2 peak values PP2 or less.
  • the pulse repetition frequency is set between the order of kHz and the order of 10 kHz. If the pulse repetition frequency becomes too high, the pulse generation interval becomes short, and sufficient cooling time for the semiconductor substrate cannot be ensured, causing heat accumulation in the semiconductor substrate, which may melt the semiconductor substrate. On the other hand, if the pulse repetition frequency is too low, the activation processing time becomes long.
  • the first surface 1A is oriented in the first direction X with respect to the optical system 30 between each of the plurality of irradiation steps.
  • a first step of scanning by one width or a second step of scanning the first surface 1A in the second direction Y with respect to the optical system 30 by a second width is performed.
  • the beam spots S formed on the first surface 1A by each of the plurality of irradiation steps are sequentially formed on the entire surface of each of the plurality of irradiated regions without overlapping each other.
  • each irradiated region is irradiated with the laser light once. Therefore, in the semiconductor device manufacturing method according to the present embodiment, the beam profile of the laser light is the same as that of the semiconductor device manufacturing method according to the present embodiment, and the beam spots are formed on the entire surface of the plurality of irradiation regions.
  • the temperature rise of the semiconductor substrate 1 is suppressed as compared with the conventional technique in which each beam spot is formed so as to overlap each other in one annealing process for sequentially forming the .
  • each irradiated region of first surface 1A is irradiated with a laser beam having an intensity sufficient to activate the first impurity region in each of the plurality of irradiation steps. be. Therefore, in each irradiation step, the first surface 1A, which is the irradiation surface, is heated, and the heat generated on the first surface 1A side is conducted from the first surface 1A in the depth direction and reaches the second surface 1B. , the temperature of the entire irradiated region in the depth direction rises.
  • the beam spots do not overlap each other in one annealing step. Therefore, if the laser beam irradiation conditions are the same, the heat storage amount in the present embodiment is relatively smaller than the heat storage amount in the conventional technology, so the temperature of the second surface 1B, which is the non-irradiation surface, increases. The temperature is relatively low, and the structural body such as the protective film formed on the second surface 1B is less likely to deteriorate. As a result, residues are less likely to occur in the step of removing the protective film (S30), for example.
  • the first impurity region can be sufficiently activated compared to the case where the first annealing step (S20) is performed only once.
  • the time until one irradiated region irradiated with laser light in the first annealing step (S20) for the first time is irradiated with laser light in the first annealing step (S20) for the second time is It is long compared to the time between the first and second shots to form the beam spot overlap in the prior art.
  • the temperature reached by the second surface 1B in the second first annealing step (S20) is also the same as the temperature reached by the non-irradiated surface in the conventional technique. can be kept relatively low.
  • the method for manufacturing the semiconductor device according to the second embodiment has basically the same configuration as the method for manufacturing the semiconductor device according to the first embodiment, but the second first annealing step The method differs from the semiconductor device manufacturing method according to the first embodiment in that the intensity of the laser light in (S20) is set lower than the intensity of the laser light in the first annealing step (S20).
  • the semiconductor substrate 1 When the semiconductor substrate 1 becomes amorphous in the first annealing step (S20) of the first time, the semiconductor substrate 1 easily absorbs the laser beam, so the intensity of the laser beam in the second first annealing step (S10) is reduced. Even if it is lower than the first annealing step (S20), the first impurity region can be sufficiently activated. Furthermore, since the intensity of the laser light in the second first annealing step (S10) is lower than that in the first first annealing step (S20), the second first annealing step (S10) is lower than the first annealing step (S20). Also during the annealing step (S20), the temperature reached by second surface 1B is relatively low, and the structure such as the protective film formed on second surface 1B is less likely to deteriorate.
  • the semiconductor device 100 can also be manufactured by the semiconductor device manufacturing method according to the second embodiment.
  • the method for manufacturing a semiconductor device according to the third embodiment has basically the same configuration as the method for manufacturing a semiconductor device according to the first embodiment, except that a first annealing step (S20) is performed. is repeated three times, which is different from the manufacturing method of the semiconductor device according to the first embodiment. Differences from the first embodiment will be mainly described below.
  • the intensity E3 of the laser beam in the third first annealing step (S20) is set, for example, to be equal to the intensities E1 and E2 of the laser beams in the first and second first annealing steps (S20).
  • the third first annealing step (S20) can be performed. By doing so, the first impurity region can be sufficiently activated.
  • the semiconductor device manufacturing method according to the third embodiment may have the same configuration as the semiconductor device manufacturing method according to the second embodiment except that the first annealing step (S20) is repeated three times. good. That is, the intensity of the laser beam in the third first annealing step (S20) is lower than the intensity of the laser beam in the first annealing step (S20), for example, and the intensity of the laser beam in the second first annealing step (S20) It may be set equal to or lower than the intensity of the laser light in (S20). By doing so, the same effects as in the second embodiment can be obtained.
  • the semiconductor device 100 can also be manufactured by the semiconductor device manufacturing method according to the third embodiment.
  • Embodiment 4 The semiconductor device manufacturing method according to the fourth embodiment has basically the same configuration as the semiconductor device manufacturing method according to the first embodiment, but the first impurity region is annealed as shown in FIG.
  • the second annealing step (S50) of annealing the second impurity region is provided, which is different from the method of manufacturing the semiconductor device according to the first embodiment. Differences from the first embodiment will be mainly described below.
  • the first impurity region includes an impurity region to become the n-type buffer layer 8 .
  • the second impurity region includes an impurity region to form p-type collector layer 9 and an impurity region to form n + -type cathode layer 18 .
  • step (S5) a first impurity region that will become the n-type buffer layer 8 is formed (step (S5)).
  • Step (S5) is performed in the same manner as the step of forming an impurity region to become n-type buffer layer 8 in the first embodiment. Thereby, the semiconductor substrate 1 having the first impurity region to be the n-type buffer layer 8 is prepared.
  • a first annealing step (S20) is performed on the first impurity region.
  • the first annealing step (S20) is performed in the same manner as the first annealing step (S20) in the first embodiment. This activates the first impurity region.
  • step (S6) After the first annealing step (S20), an impurity region that will become the p-type collector layer 9 and an impurity region that will become the n+ type cathode layer 18 are formed (step (S6)).
  • This step (S6) is performed in the same manner as the step of forming the impurity region to be the p-type collector layer 9 and the impurity region to be the n+ type cathode layer 18 in the first embodiment.
  • an impurity region to form the p-type collector layer 9 and a second impurity region to form the n + -type cathode layer 18 are formed in the semiconductor substrate 1 .
  • a second annealing step (S50) is performed to irradiate the first surface 1A with laser light emitted from the optical system 30 to anneal the second impurity regions.
  • the second annealing step (S50) is performed in the same manner as the first annealing step (S20).
  • the laser annealing apparatus 200 shown in FIG. 3 is also used in the second annealing step (S50).
  • the scanning shown in FIGS. 4 and 5 is also performed in the second annealing step (S50).
  • the second annealing step (S50) is repeated, for example, twice.
  • the laser beam intensity E5 in the second second annealing step (S50) is set to be, for example, equal to the laser beam intensity E4 in the first second annealing step (S50).
  • the step of removing the protective film (S30) and the step of forming the first electrode 14 (S40) are performed.
  • the first annealing step (S20) for the first impurity region among the plurality of impurity regions formed on the first surface 1A side and the second annealing step for the second impurity region ( S50) are performed as separate steps.
  • the semiconductor device 100 can also be manufactured by the semiconductor device manufacturing method according to the fourth embodiment.
  • the second annealing step (S50) may be repeated three times or more.
  • the intensity of the laser beam in the third second annealing step (S50) is lower than, for example, the intensity of the laser beam in the first second annealing step (S50), and the second annealing step (S50 ) may be set equal to or lower than the intensity of the laser light.
  • the first annealing step (S20) may be performed similarly to the first annealing step (S20) in the second or third embodiment.
  • each of the first annealing step (S20) and the second annealing step (S50) may be performed only once.
  • the method for manufacturing the semiconductor device according to the fifth embodiment has basically the same configuration as the method for manufacturing the semiconductor device according to the first embodiment, but the second first annealing step is performed.
  • This method is different from the semiconductor device manufacturing method according to the first embodiment in that the delay time td2 of the laser light in (S20) is different from the delay time td1 of the laser light in the first annealing step (S20). Differences from the first embodiment will be mainly described below.
  • the laser beams used in the first annealing step (S20) for the first time are the first pulsed laser beam output from the first laser oscillator 40 and the first pulsed laser beam output from the first laser oscillator 40 with a delay. After the elapse of time td1, it is generated by being coupled with the second pulsed laser beam output from the second laser oscillator.
  • the laser beams used in the second first annealing step (S20) are the first pulsed laser beam output from the first laser oscillator 40 and the delay after the first pulsed laser beam is output from the first laser oscillator 40. After the elapse of time td2, it is generated by being coupled with the second pulsed laser beam output from the second laser oscillator.
  • the laser light delay time td2 in the second first annealing step (S20) is different from the laser light delay time td1 in the first first annealing step (S20).
  • the laser light delay time td2 in the second first annealing step (S20) may be longer than the laser light delay time td1 in the first first annealing step (S20).
  • the delay time td2 of the laser light in the second first annealing step (S20) is set to is longer than the delay time td1 of the laser light.
  • the intensity of the laser beam in the second first annealing step (S20) is less than or equal to the intensity of the laser beam in the first first annealing step (S20).
  • the intensity of the laser light in the second first annealing step (S20) may be the same as the intensity of the laser light in the first first annealing step (S20).
  • the intensity of the laser light in the first and second first annealing steps (S20) is equal to each other, and the shorter the delay time of the laser light, the easier it is to activate the impurity region, the second first annealing Even if the laser light delay time td2 in the step (S20) is longer than the laser light delay time td1 in the first annealing step (S20), the first impurity region can be sufficiently activated. This is because when the semiconductor substrate 1 becomes amorphous by the first annealing step (S20), the semiconductor substrate 1 easily absorbs the laser light.
  • the second first annealing step (S20) compared to the case where the intensity and delay time of the laser light are the same in the first and second first annealing steps (S20), the second first annealing step (S20) , the temperature reached by the second surface 1B becomes relatively low, and the structure such as the protective film formed on the second surface 1B is less likely to deteriorate.
  • the intensity of the laser light in the second first annealing step (S20) may be lower than the intensity of the laser light in the first first annealing step (S20).

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JP2001044136A (ja) * 1999-08-02 2001-02-16 Sumitomo Heavy Ind Ltd 精密レーザ照射装置及び制御方法
JP2003045820A (ja) * 2001-07-30 2003-02-14 Semiconductor Energy Lab Co Ltd レーザ照射装置およびレーザ照射方法、並びに半導体装置の作製方法
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