WO2022242754A1 - 电路板及电子装置 - Google Patents

电路板及电子装置 Download PDF

Info

Publication number
WO2022242754A1
WO2022242754A1 PCT/CN2022/094166 CN2022094166W WO2022242754A1 WO 2022242754 A1 WO2022242754 A1 WO 2022242754A1 CN 2022094166 W CN2022094166 W CN 2022094166W WO 2022242754 A1 WO2022242754 A1 WO 2022242754A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
slit
area
region
metal layer
Prior art date
Application number
PCT/CN2022/094166
Other languages
English (en)
French (fr)
Inventor
黎明权
许文钦
孙平如
Original Assignee
深圳市聚飞光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市聚飞光电股份有限公司 filed Critical 深圳市聚飞光电股份有限公司
Priority to JP2023571840A priority Critical patent/JP2024518628A/ja
Publication of WO2022242754A1 publication Critical patent/WO2022242754A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits

Definitions

  • the present application relates to the technical field of chip packaging, in particular to a circuit board and an electronic device.
  • SMT Surface Mounted Technology, surface mount technology
  • SMC Surface Mounted for short
  • Components, Surface Mount Components)/SMD Surface Mounted Devices, surface mount devices
  • PCB Printed Circuit Board, printed circuit board
  • PCB Printed Circuit Board, printed circuit board
  • the stencil is a special mold for surface mount technology. Its main function is to help the deposition of solder paste. The purpose is to transfer an accurate amount of solder paste to the position of the corresponding pad on the printed circuit board.
  • a gap is set on the metal layer of the substrate to divide the metal layer into a plurality of mutually insulated metal sheets to form corresponding lines, and pads are set at corresponding positions on the lines and the Solder resist ink layer covered by lines (pad exposed to solder resist ink layer).
  • the printed circuit board shown in FIG. 1 has a slot C1 extending in the transverse direction and a slot C2 extending in the longitudinal direction.
  • the slit C2 extending in the longitudinal direction continuously crosses a plurality of metal sheets in the longitudinal direction to form a longer slit in the longitudinal direction.
  • the steel net is easily deformed and sinks due to the lack of strong support and clings to the surface of the substrate.
  • the soldering process once the stencil is damaged, the accuracy of solder coating cannot be guaranteed.
  • the purpose of this application is to provide a circuit board and an electronic device, which can reduce the degree of stencil depression during the process of printing solder paste on the circuit board, and prolong the service life of the stencil.
  • the present application provides a circuit board, which includes at least one substrate, a metal layer disposed on the front and/or back of the substrate, the metal layer has an area array, and the area array includes At least two first regions and second regions formed by division, the first regions and the second regions are alternately distributed in the row direction and the column direction of the region array and are insulated from each other;
  • Each of the first area and the second area has at least two mutually insulated metal sheets formed by dividing and forming through the second slit, and each of the first area and the second area is adjacent to two of the metal sheets.
  • the metal sheet is correspondingly provided with a pad for connecting with an electronic component; the pads in each of the first region and the second region are arranged in a multi-row and multi-column array on the substrate to form pad array;
  • the present application also provides an electronic device, which includes an electronic component and the above-mentioned circuit board, the electronic component is arranged on the circuit board and soldered to the corresponding pad .
  • the metal sheet in each of the first regions has a first extension extending along the column direction of the pad array, and the solder pads in each of the first regions In each row direction of the pad array, the second slit is interrupted by the first extension; at least a part of the metal sheet in each second region has a second slot extending along the row direction of the pad array.
  • the second slit is interrupted by the second extension part.
  • the metal layer on the substrate is divided into at least two first regions and second regions that are alternately distributed in the row direction and the column direction through the first slit and are insulated from each other to form an area array, and each first region and the second region are separated through the second slit.
  • the metal layer in the second area is divided to form at least two mutually insulated metal sheets, and corresponding pads are provided on the two adjacent metal sheets for connecting with an electronic component, thereby forming the circuit of the circuit board, and the circuit of the circuit
  • the formation method is simple and efficient;
  • the bonding pads in each first region and the second region are arranged in multi-row and multi-column arrays on the substrate to form a bonding pad array, and at least some of the metal sheets in each first region have The first extension part extending in the column direction of the array, in each row direction of the pad array in each first region, the second slit is interrupted by the first extension part, so that in each row direction, the first extension part forms a pair of The supporting point for the support of the steel mesh; at least a part of the metal sheets in each second area has a second extension extending along the row direction of the pad array, and each of the pad arrays in each second area In the column direction, the second slit is interrupted by the second extension, so that in each column direction, the second extension forms a support point for supporting the stencil, which can ensure that the solder pad array is in each row direction and each column direction.
  • the distribution of the second slit on the circuit board can reduce the degree of deformation of the stencil at the position of the second slit during the process of printing solder, thereby avoiding the stencil as much as possible.
  • the position of the second gap is damaged due to excessive sag, thereby ensuring the accuracy of the solder printed by the stencil, and improving the reliability and yield of the circuit board and electronic devices.
  • Fig. 1 is the structural representation of existing printed circuit board
  • Fig. 2 is a top view 1 of the front of the circuit board provided by the embodiment of the present application.
  • FIG. 3 is a first cross-sectional schematic diagram of a circuit board provided in an embodiment of the present application.
  • FIG. 4 is a second schematic cross-sectional view of the circuit board provided in the embodiment of the present application.
  • Fig. 5 is a schematic cross-sectional view three of the circuit board provided by the embodiment of the present application.
  • Fig. 6 is the second top view of the front of the circuit board provided by the embodiment of the present application.
  • FIG. 7 is a third top view of the front of the circuit board provided by the embodiment of the present application.
  • FIG. 8 is a top view of a circuit board provided with LED chips according to an embodiment of the present application.
  • FIG. 2 is a top view of the front of the circuit board
  • FIG. 3 is a schematic cross-sectional view including two adjacent metal sheets in FIG. 2
  • the circuit board includes a substrate 10 and a metal layer 20 disposed on the substrate 10.
  • the metal layer 20 is provided, or the metal layer 20 is provided on the front and back of the substrate 10 at the same time.
  • the metal layer 20 on the front of the substrate 10 is taken as an example for description below.
  • the substrate 10 in this embodiment is an insulating substrate, and the material of the substrate 10 can be determined according to the use scenario of the circuit board.
  • the substrate 10 when the circuit board needs to be bent, can be made of flexible materials, such as epoxy resin, which has good heat dissipation and is ultra-thin, and can be bent, folded, wound, and moved and stretched arbitrarily in three-dimensional space , so a three-dimensional circuit board can be formed.
  • the substrate 10 when the circuit board is required to have a certain supporting effect, can be made of a rigid material, such as a ceramic substrate, so as to have a certain mechanical strength for support.
  • the metal layer 20 in this embodiment may be a conductive layer such as copper foil or aluminum foil, and the metal layer 20 is provided with a gap 21 .
  • the slit 21 includes the first slit 211 that divides the metal layer 20 into at least two first regions 221 and at least two second regions 222, the first slit 211 runs through the front and back of the metal layer 20 (that is, the first slit 211
  • the bottom of the substrate 10 is the surface of the substrate 10.
  • the first slit is not specifically drawn in FIG. 2 , and reference numeral 211 in FIG. 2 is an example of the position of the first slit).
  • the formed at least two first regions 221 and at least two second regions 222 form an area array of the metal layer 20, as shown in FIG.
  • the X direction in FIG. 2, which can also be referred to as the horizontal direction) and the column direction (the Y direction in FIG. 2, which can also be referred to as the vertical direction) are distributed alternately and are insulated from each other.
  • the area array is a 2*2 array
  • the first area 221 and the second area 222 are sequentially arranged in the first row of the area array
  • the second area 222 and the second area 222 are sequentially arranged in the second row of the area array.
  • the first region 221 is provided with the first region 221 and the second region 222 in sequence in the first row of the region array
  • the second region 222 and the first region 221 are arranged in turn in the second row of the region array, and are adjacent to each other.
  • the first region 221 and the second region 222 are separated by the first gap 21 and insulated from each other.
  • the area array shown in FIG. 2 is only an example for easy understanding. In practical applications, the area array can be set as an N*M array, where N and M are both greater than or equal to 2, and the number of N and M Values can be equal or unequal.
  • the slit 21 also includes a second slit 212 that divides the metal layer 20 in each of the first region 221 and the second region 222 into at least two metal sheets 22.
  • the second slit 212 It also runs through the front and back of the metal layer 20 (that is, the bottom of the second slit 212 is the surface of the substrate 10, and reference numeral 212 in FIG. 2 is an example of the planar structure of the second slit), so that are insulated from each other.
  • each of the two adjacent metal sheets 22 in the first region 221 and the second region 222 is located on both sides of the second gap 212 and is respectively provided with a corresponding welding pad 23, for example, it can be on the two adjacent metal sheets 2
  • a welding pad 23 is provided on the edge or near the edge, and the corresponding two welding pads 23 can be a positive electrode pad and a negative electrode pad respectively, and are used to connect with the positive and negative pins of the same electronic component.
  • the pads 23 in each first region 221 and each second region 222 are combined on the substrate 10 into a multi-row and multi-column array of pads. In the example shown in FIG.
  • the pad array formed by the pads 23 in each of the first region 221 and the second region 222 is a 12*8 array, that is, 12 rows and 8 columns. It should be understood that the pad array shown in FIG. 2 is only an example for easy understanding. In practical applications, the area array can be set as an n*m array, where n and m are both greater than or equal to 2, and n and The values of m can be equal or unequal.
  • At least a part of the metal sheets 22 in each first region 221 has a first extension A1 extending along the column direction of the pad array, and in each first region 221 In each row direction of the pad array in 221, the second slit 212 is interrupted by each first extension part A1, so that in each row direction, the first extension part A1 forms a support point for supporting the stencil; each second area At least a part of the metal sheets 22 in the metal sheet 222 has a second extension A2 extending along the row direction of the pad array, and in each second region 222 in each column direction of the pad array, the second slits 212 are formed.
  • Each second extension part A2 is interrupted, so that in each column direction, the second extension part A2 forms a support point for supporting the stencil, which can ensure that there are sufficient pad arrays in each row direction and each column direction.
  • the supporting points form a support for the stencil, so as to minimize the deformation of the stencil at the second gap 212 in the process of printing solder, prolong the service life of the stencil, improve the accuracy of solder coating and reduce the stencil loss and cost; and in the example shown in FIG. 2 , only the distribution of the second slit 212 needs to be adjusted ingeniously, no additional components or processes are required, and the fabrication is simple, versatile and low in cost.
  • At least one of the first slit 211 and the second slit 212 can be formed by, but not limited to, etching the metal layer 20 , the etching process is simple and mature, and the efficiency and yield are high.
  • each of the pads 23 provided at corresponding positions on the edges of two adjacent metal sheets 22 in each first region 221 and each second region 22 can be arranged symmetrically along the X direction. , so that the pads 23 are arranged in a multi-row multi-column array.
  • the pads 23 correspondingly arranged on two adjacent metal sheets 22 are not limited to being symmetrically arranged, and may also be asymmetrically arranged according to requirements.
  • the number of pads 23 contained in each of the first region 221 and the second region 222 is equal.
  • the number of pads 23 contained in each of the first region 221 and the second region 222 may also be set to be different.
  • the same column direction Y since the second slit 212 in the second region 222 is interrupted by the second extension A2 of the metal sheet 22 in the second region 222 along the row direction, the same column direction
  • the length D2 of a second slit 212 on Y in the same column direction Y is smaller than the length D1 of a second slit 212 in the first region 221 in the same column direction Y (wherein D1 and D2 are shown in FIG. 2, in FIG. 2
  • the second slit 212 extending along the column direction in the first region 221 spans a plurality of metal sheets 22 ).
  • each second extension part A2 serves as a support point to increase the support strength of the stencil in the same straight line direction as the row direction.
  • the same row direction X since the second slit 212 in the first region 221 is interrupted by the first extension A1 of the metal sheet 22 in the first region 221 along the column direction, the same row direction X
  • the length D3 of the last second slit 212 in the same row direction X is smaller than the length D4 of a second slit 212 in the second region 222 in the same row direction X (where D3 and D4 are shown in FIG. 2 , in FIG. 2
  • the second slits 212 extending along the row direction in the second region 222 span the plurality of metal sheets 22 ).
  • the length D3 of the second slit 212 of the first region 221 is different from the length D4 of the second slit 212 of the second region 222 (that is, the length D4 of the second slit 212 in the first region 221 is set in each row direction.
  • the second slit 212 is interrupted by the first extension A1 of the metal sheet 22 in the first region 221 along the column direction, while the second slit 212 in the second region 222 spans a plurality of metal sheets 22), when using a steel mesh
  • each first extension part A1 serves as a support point to increase the support strength of the stencil in the same straight line direction in the row direction, thereby reducing the degree of depression of the stencil in the process of printing solder in both the row direction and the column direction, Extend the service life of the stencil.
  • the length D1 of the second slit 212 of the first region 221 may also be shorter than the length D2 of the second slit 212 of the second region 222, and the length D3 of the second slit 212 of the first region 221 It can also be greater than the length D4 of the second slit 212 of the second region 222 .
  • FIG. 6 Compared with FIG. 2 , in FIG. 6 , the order in which the first regions 221 and the second regions 222 are alternately arranged in FIG. 2 is reversed.
  • the row direction and the column direction in this embodiment are two relative concepts.
  • the circuit board shown in FIG. 2 is rotated to obtain FIG. 7, so that the row in FIG. 2 becomes the column in FIG. 7 , the columns in Figure 2 become the rows in Figure 7. That is, in other embodiments, after the column direction in FIG. 2 is rotated to the row direction in FIG. 7, then in FIG. (corresponding to D1 in FIG. 2 ) greater than the length D6 of the second slit 212 in the second region 222 (corresponding to D2 in FIG. 2 ), along the same column direction Y, the length of the second slit 212 in the first region 221 D7 (corresponding to D3 in FIG. 2 ) is smaller than the length D8 (corresponding to D4 in FIG. 2 ) of the second slit 212 of the second region 222 .
  • the second slit 212 in the second region 222 is extended along the row direction by the second slit 212 in the second region 222 A2 breaks, so the number of second slits 212 extending along the column direction Y in the first region 221 is less than the number of second slits 212 extending along the column direction Y in the second region 222 .
  • the second slit 212 in the first region 221 in the same column direction Y (taking the first column from left to right as an example), the second slit 212 in the first region 221 (see K1 in FIG. 2 )
  • the number of the second slits 212 in the second region 222 is 3.
  • the second slits 212 in the first area 221 and the second area 222 include several trunk slits and several branch slits, wherein the main slits are along the row direction X or the column direction Y.
  • the branch gap separates the pads 23 between adjacent metal sheets 22 and connects to the trunk gap, and one trunk gap is connected to at least two branch gaps respectively.
  • the trunk slits in the first region 221 are not parallel to the extending direction of the trunk slits in the second region 222 .
  • the first area 221 has six trunk gaps extending along the column direction Y, namely Z11, Z12, Z13, Z14, Z15, and Z16, and each trunk gap is connected to one side with three branches.
  • the gaps for example, the three branch gaps connected by the trunk gap of Z16 are x11, x12, and x13 respectively, and at least a part of each branch gap is perpendicular to the trunk gap; and there are four in the second area 222 extending along the row direction X
  • the trunk gaps are Z21, Z22, Z23, and Z24 respectively.
  • the trunk gap has a part parallel to the trunk gap and a part perpendicular to the trunk gap, and a turning angle is formed at the junction of the part parallel to the trunk gap and the part perpendicular to the trunk gap.
  • the trunk slit in the first region 221 is perpendicular to the extension direction of the trunk slit in the second region 222, so that there is more in the extending direction of the trunk slit between the first region 221 and the second region 222.
  • Multiple support points can reduce the degree of stencil depression during the process of printing solder paste on the circuit board and prolong the service life of the stencil.
  • FIG. 2 there is a supporting area 24 between the adjacent first area 221 and the second area 222.
  • the scraper moves on the steel mesh, the scraper passes through the adjacent first area 221 and the second area.
  • the support area 24 can provide support to the stencil, thereby reducing the size of the stencil between the adjacent first area 221 and the second area 222.
  • the degree of depression and deformation of the area can further prevent the steel mesh from being damaged, thereby further prolonging the practical life of the steel mesh.
  • the first slit 211 is located at the edge of the first area 221
  • the second slit 212 is located inside the first area 221
  • the first slit 211 and the second slit 212 are connected to each other. connected to enclose the first region 221 .
  • the first slit 211 isolates the first area 221 from external circuits outside the first area 221
  • the second slit 212 isolates two adjacent metal sheets in the first area 221 .
  • the first slit 211 is located at the edge of the second area 222
  • the second slit 212 is located inside the second area 221
  • the first slit 211 and the second slit 212 are connected to each other to form a first slit.
  • the first gap 211 isolates the second area 222 from external circuits outside the second area 222
  • the second gap 212 isolates two adjacent metal sheets in the second area 222 .
  • the width of the second slit 212 located in the first area 221 and the second area 222 can be determined according to the spacing between the pins of the electronic device soldered to the pads 23 on both sides and the size of the metal sheet 22.
  • the width of the first gap 211 at the edge of the area 221 and the second area 222 is set according to actual requirements (such as voltage and current on the circuit board, etc.).
  • the width of the first slit 211 is smaller than the width of the second slit 212.
  • the first area 221 and the second area 222 can be The circuit is isolated from the external circuit outside the first area 221 and the second area 222, and by setting the second gap 212 inside the first area 221 and the second area 222, the adjacent metal sheets can be isolated, thereby The required circuit is formed, and the direction and width of the first slit 211 and the second slit 212 can be reasonably designed in combination with the circuit requirements, so as to maximize the use of the support function of the metal layer 20 to further reduce the degree of stencil depression.
  • the extending direction of at least one of the first slit 211 and the second slit 212 shown in FIG. 2 is the same as the row direction and column direction of the pad array, which can also be understood as the The X and Y directions shown in 2 are the same.
  • the second slit 212 extends zigzagging, for example, the second slit 212 extends zigzagging along the row direction X and the column direction Y, and at the corner of the extension path, the second slit 212 is at a right angle (of course, it can also be replaced be rounded corners or other types of corners).
  • a plurality of metal sheets 22 or a combination of the plurality of metal sheets 22 form a rectangle, which facilitates the layout design of electronic components during the packaging process.
  • the second slit 212 can also meander and extend in other directions, so as to divide the metal layer 20 into metal sheets of other shapes, such as circular, trapezoidal, rhombus, triangular, etc., so as to be suitable for different The shape or size of an electronic component.
  • the first slit 211 also extends in a zigzag manner, and the first slit 211 extends in a zigzag manner along the row direction X and the column direction Y, so as to enclose the rectangular first region 221 and The second region 222 facilitates the layout design of the electronic components during the packaging process. It can be understood that, in other embodiments, the first slit 211 can also extend in other directions according to the extension path of the second slit 212, so as to form a circular, trapezoidal, rhombus, triangular and other arbitrary shapes surrounded by the second slit 212. The first area 221 and the second area 222 .
  • the solder resist layer 30 is filled in the gap 21 (that is, the first gap 211 and the second gap 212 ), and in the direction perpendicular to the substrate 10 , the solder resist layer The height of 30 is less than the height of metal sheet 22 .
  • the solder resist layer 30 has the functions of insulation and solder resistance.
  • the material of the solder resist layer 30 is solder resist ink.
  • the solder resist layer 30 can also be made of solder resist, solder resist glue, etc. to make.
  • the solder resist layer 30 also has the function of preventing solder from overflowing and avoiding circuit short circuit.
  • the setting of the welding-building layer 30 makes the stencil even when it deforms and sags at the positions of the first slit 211 and the second slit 212, its maximum depression can only be against the welding-building layer 30.
  • the first gap 211 and the second gap 212 are not provided with the structure of the welding layer 30, which can further reduce the degree of depression of the stencil and prolong the service life of the stencil.
  • metal layers are provided on the front and back of the substrate, and the metal layers on the front and back can both be the structure of the metal layer 20 shown in FIG. 2 , or only one of them can be used.
  • One is the structure of the metal layer 20 shown in FIG. 2 .
  • FIG. 4 FIG. 4 is also a schematic cross-sectional view including two adjacent metal sheet parts
  • the front of the substrate 10 is the first surface 11
  • the back of the substrate 10 is the second surface 12.
  • the first surface 11 is provided with a first metal layer 201
  • the second surface 12 is provided with a second metal layer 202.
  • the opposite first surface 11 and the second surface 12 of the substrate 10 can be provided with circuits and electronic components.
  • the first metal The structure of at least one metal layer among the layer 201 and the second metal layer 202 is the same as that of the metal layer 20 shown in FIG. 2 .
  • the structures of the metal layers of the first metal layer 201 and the second metal layer 202 are the same as that of the metal layer 20 shown in FIG.
  • the purpose of the stencil depression It can be understood that the structure of at least one of the first metal layer 201 and the second metal layer 202 is the same as that of the metal layer 20, specifically including: only the structure of the first metal layer 201 is the same as that of the metal layer 20 provided in the embodiment of the present application.
  • the same structure, or only the structure of the second metal layer 202 is the same as the structure of the metal layer 20 provided in the embodiment of the present application, or the structure of the first metal layer 201 and the second metal layer 202 is the same as that provided in the embodiment of the present application.
  • the structure of the metal layer 20 is the same.
  • there may be no circuit connection between the first metal layer 201 and the second metal layer 202 or a circuit connection may be made as required.
  • a circuit connection may be made as required.
  • the substrate 10 is provided with a via hole 13 , the via hole 13 runs through the first surface 11 and the second surface 12 of the substrate 10 , and the first metal layer 201 and the second metal layer 202 are connected through the via hole 13 (That is, the metal layers on the front and back of the substrate 10 are electrically connected through the via hole 13 ).
  • the via hole 13 to connect the circuits on the first metal layer 201 and the second metal layer 202.
  • electroless plating and electroplating can be used to conduct the circuits on both sides of the via hole 13. It is also possible to pass the wire through the via hole 13, and connect the circuits on both sides of the via hole 13 through the wire.
  • the via hole 13 It is also possible to fill the via hole 13 with a conductive substance, which is simultaneously connected to the first metal layer 201 and the second metal layer 202. Contact to achieve conduction.
  • the conductive substance includes conductive paste, conductive ink, solder and the like.
  • the circuit board includes at least two stacked substrates, each of which is provided with a metal layer. That is, in this example, the circuit board can be a multi-layer circuit board structure having at least two substrates and metal layers disposed on the substrates. Wherein, it should be understood that, in this example, the metal layers provided on each substrate may all have the metal layer 20 structure shown in FIG. 2 , or a part of the metal layers may have the metal layer 20 structure shown in FIG. 2 , Some are other structures.
  • the circuit board when the circuit board includes at least two substrates stacked, adjacent substrates can be bonded together through but not limited to an adhesive layer, and the bonding method is simple and reliable. It should be understood that, in this example, there may be no direct electrical connection between the metal layers on the substrates, and at least some of the metal layers between the substrates may be electrically connected according to requirements, and the electrical connection may be through But it is not limited to providing corresponding via holes on the substrate or providing connection lines on the surface of the substrate or outside the substrate for electrical connection, which is not limited in this example.
  • the board structure includes two substrates 10 , referred to here as a first substrate 101 and a second substrate 102 respectively, and the first substrate 101 and the second substrate 102 are bonded by an adhesive layer 40 .
  • the first substrate 101 is provided with a first metal layer 201 and pads 23 to form a first sub-circuit board
  • the second substrate 102 is provided with a second metal layer 202 and pads 23 to form a second sub-circuit board.
  • the first metal layer At least one of the metal layer 201 and the second metal layer 202 is the structure of the metal layer 20 shown in FIG.
  • the circuit board shown in FIG. 5 includes two substrates 10, and an adhesive layer 40 bonding the two substrates 10 together, and the two substrates 10 are provided on the side away from the adhesive layer 40 as shown in FIG. metal layer.
  • the circuit board shown in FIG. 5 further includes a via hole 13 passing through at least the first substrate 101 , the adhesive layer 4 and the second substrate 102 , and the via hole 13 electrically connects the first metal layer 201 and the second metal layer 202 .
  • the number of the substrate 10 and the number of the metal layer 20 can also be other combinations, which are not limited here.
  • the embodiment of the present application provides an electronic device, the electronic device includes electronic components and the circuit board as shown above, the electronic components are arranged on the circuit board and welded with the corresponding pads, for example, the electronic components can be directly soldered on the pads 23 superior.
  • the electronic components in this embodiment can be at least one of capacitors, resistors, and LED chips, etc., and the electronic components include positive and negative pins.
  • the pole pins are fixed on the pads 23 by solder paste welding (or fixed by conductive glue).
  • the degree of deformation of the stencil at the position of the second slit can be reduced during the process of printing solder, thereby avoiding the stencil as much as possible in the second slit.
  • the position of the gap is damaged due to excessive depression, thereby ensuring the accuracy of the solder printed by the stencil, which can improve the reliability and yield of the circuit board and electronic devices, and save the production cost of the electronic devices.
  • the circuit board provided in this embodiment can be used in a display screen of an electronic device as a circuit board for a backlight source of the display screen.
  • LED chips can be soldered to each pad in each first area and second area on the circuit board, and all LED chips in each first area and second area are connected in series.
  • the LED chips in a first area are combined into an LED chip array, and the LED chips in a second area are also combined into an LED chip array.
  • the LED chips in each first area and the LED chips in each second area are on the substrate The upper combination forms a large LED chip array.
  • the following is an example of soldering LED chips on the circuit board shown in FIG. 2. Referring to FIG. There are LED chips L. Wherein, referring to FIG.
  • each LED chip L in the first region 221 forms a series circuit through each metal sheet 22 in the first region 221 , and the current flow of the series circuit is shown by the dotted line I1 in FIG. 8 .
  • the bonding pad in the upper right corner is the positive electrode bonding pad H+
  • the bonding pad in the lower left corner is the negative electrode bonding pad (not marked in the figure)
  • the second region 222 Each LED chip L in the second area 222 forms a series circuit through each metal sheet 22 in the second region 222 , and the current flow of the series circuit is shown by the dotted line I2 in FIG. 8 .
  • At least two first regions 221 and second regions 222 are arranged alternately on the circuit board both horizontally and vertically, and the display screen can be divided into at least two sub-regions. Therefore, the LED chips in the same area (for example, in a certain first area 221 or a certain second area 222) can be controlled at the same time, and the LED chips in the same area can be controlled individually as a whole, that is, they can be individually controlled. Control the light and shade of LED chips in a certain area to adjust the light and shade of a certain sub-area of the display screen, realize the effect of local area dimming, and improve the display effect of the display screen.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本申请涉及一种电路板及电子装置，通过第一缝隙将基板上的金属层分割成至少两个在行方向和列方向交替分布且相互绝缘的第一区域和第二区域，且第一区域各行方向上的第二缝隙被第一区域内的至少一部分金属片沿列方向延伸的第一延伸部打断；第二区域各列方向上的第二缝隙被第二区域内的至少一部分金属片沿行方向延伸的第二延伸部打断。

Description

电路板及电子装置 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种电路板及电子装置。
 背景技术
SMT(Surface Mounted Technology，表面贴装技术)是电子组装行业里最流行的一种技术和工艺，它是一种将无引脚或短引线表面组装元器件(简称SMC（Surface Mounted Components，表面组装元件）/SMD（Surface Mounted Devices，表面组装器件)）安装在PCB(Printed Circuit Board，印制电路板)的表面或其它基板的表面上，通过再流焊或浸焊等方法加以焊接组装的电路装连技术。随着电子装置小型化的发展，SMT越来越广泛地应用到电子装置的制作中。
钢网是一种表面贴装技术专用模具，其主要功能是帮助锡膏的沉积，目的是将准确数量的锡膏转移到印制电路板上的对应焊盘的位置。针对目前的印制电路板结构，通常都会在其基板的金属层上设置缝隙以将金属层划分成多个相互绝缘的金属片从而形成相应的线路，并在线路上的对应位置设置焊盘以及将线路覆盖的阻焊油墨层（焊盘外露于阻焊油墨层）。具体的，如图1所示的印制电路板，其具有沿横向延伸的缝隙C1和沿纵向延伸的缝隙C2。其中沿纵向延伸的缝隙C2在纵向上连续跨越多个金属片，形成在纵向上较长的缝隙，在对印制电路板印刷焊料的工艺中，在钢网上涂敷焊料之后，使刮刀在钢网上移动的过程中，经过纵向上的缝隙C2时，钢网由于缺少有力支撑而容易变形下沉并紧贴基板表面，当钢网凹陷程度过大时，则容易导致钢网损坏；在涂敷焊料过程中，钢网一旦损坏，则不能保证焊料涂覆的精准性。
 技术问题
鉴于上述现有技术的不足，本申请的目的在于提供一种电路板及电子装置，能减小在电路板上印刷锡膏的过程中钢网凹陷的程度，延长钢网的使用寿命。
 技术解决方案
为实现申请的目的，本申请提供了如下的技术方案：
本申请提供一种电路板，所述电路板包括至少一块基板，设置在所述基板的正面和/或背面上的金属层，所述金属层具有区域阵列，所述区域阵列包括通过第一缝隙分割形成的至少两个第一区域和第二区域，所述第一区域和所述第二区域在所述区域阵列的行方向和列方向上均交替分布且相互绝缘；
各所述第一区域和所述第二区域内分别具有通过第二缝隙分割形成的至少两个相互绝缘的金属片，各所述第一区域和所述第二区域内相邻两个所述金属片对应的设有用于与一个电子元件连接的焊盘；各所述第一区域和所述第二区域内的所述焊盘在所述基板上呈多行多列式阵列排布以形成焊盘阵列；
基于同样的发明构思，本申请还提供一种电子装置，所述电子装置包括电子元件和如上所述的电路板，所述电子元件设于所述电路板上并与对应的所述焊盘焊接。
 有益效果
本申请提供的电路板，在各所述第一区域内的至少一部分所述金属片具有沿所述焊盘阵列的列方向延伸的第一延伸部，在各所述第一区域内所述焊盘阵列的各行方向上，所述第二缝隙被所述第一延伸部打断；各所述第二区域内的至少一部分所述金属片具有沿所述焊盘阵列的行方向延伸的第二延伸部，在各所述第二区域内所述焊盘阵列的各列方向上，所述第二缝隙被所述第二延伸部打断。
通过第一缝隙将基板上的金属层分割成至少两个在行方向和列方向交替分布且相互绝缘的第一区域和第二区域形成区域阵列，并通过第二缝隙将各第一区域和第二区域内的金属层分割形成的至少两个相互绝缘的金属片，且在相邻两个金属片上对应的设有焊盘以用于与一个电子元件连接，从而形成电路板的线路，线路的形成方式简单且高效；
另外，各第一区域和第二区域内的焊盘在基板上呈多行多列式阵列排布以形成焊盘阵列，各第一区域内的金属片中的至少一部分金属片具有沿焊盘阵列的列方向延伸的第一延伸部，在各第一区域内所述焊盘阵列的各行方向上，第二缝隙被第一延伸部打断，使得各行方向上，该第一延伸部形成对钢网进行支撑的支撑点；各第二区域内的金属片中的至少一部分金属片具有沿焊盘阵列的行方向延伸的第二延伸部，在各第二区域内所述焊盘阵列的各列方向上，第二缝隙被第二延伸部打断，使得各列方向上，该第二延伸部形成对钢网进行支撑的支撑点，这样可以保证在焊盘阵列的各行方向和各列方向上都有足够的支撑点，从而尽可能减小印刷焊料的过程中钢网在第二缝隙位置处的变形程度，例如可尽可能减小钢网在第二缝隙位置处的凹陷程度，延长钢网的使用寿命，提升焊料涂覆的精准性并降低钢网损耗和成本；且本申请只需要对第二缝隙的分布进行巧妙的改进，不需要额外增加其他部件或工艺，制作简单，通用性好且成本低。
本申请提供的电子装置采用的上述电路板，该电路板上的第二缝隙的分布可以在印刷焊料的过程中减小钢网在第二缝隙位置处的变形程度，从而尽可能避免钢网在第二缝隙位置处因凹陷程度过大而损坏，进而保证使用钢网所印刷的焊料精准性，提升电路板和电子装置的可靠性和良品率。
 附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有印制电路板的结构示意图；
图2为本申请实施例提供的电路板正面的俯视图一；
图3为本申请实施例提供的电路板的截面示意图一；
图4为本申请实施例提供的电路板的截面示意图二；
图5为本申请实施例提供的电路板的截面示意图三；
图6为本申请实施例提供的电路板正面的俯视图二；
图7为本申请实施例提供的电路板正面的俯视图三；
图8为本申请实施例提供的电路板上设有LED芯片的俯视图。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
本实施例提供的一种电路板示意图请参考图2和图3，其中图2为电路板正面的俯视图，图3为图2中包括相邻两个金属片部分的截面示意图。本实施例提供该电路板包括基板10和设置在基板10上的金属层20，图2和图3所示为在基板的正面设有金属层，当然应当理解的是也可在基板10的背面设置金属层20，或在基板10的正面和背面同时设置金属层20，为了便于理解，下面以在基板10的正面设有金属层20为例进行说明。本实施例中的基板10为绝缘基板，基板10的材料可根据电路板的使用场景而定。例如当需要对电路板进行弯折时，基板10可选用柔性材料，如环氧树脂等，它散热性好，超薄，既可弯曲、折叠、卷绕，又可在三维空间任意移动和伸缩，因此可形成三维空间的立体线路板。当需要电路板具有一定支撑作用时，基板10可选用刚性材料，如陶瓷基板等，以具有一定的机械强度进行支撑。
本实施例中的金属层20可以为铜箔或铝箔等具有导电性能的导电层，且金属层20上开设有缝隙21。其中缝隙21包括将金属层20分割成至少两个第一区域221和至少两个第二区域222的第一缝隙211，第一缝隙211贯穿金属层20的正面和背面（也即第一缝隙211的底部为基板10的表面，需要说明的是，图2中并未具体画出第一缝隙，图2中附图标记211所示的是第一缝隙所设置的位置示例）。所形成的至少两个第一区域221和至少两个第二区域222构成金属层20的区域阵列，参见图2所示，第一区域221和第二区域222在区域阵列的行方向（图2中的X方向，也可称之为横向）和列方向（图2中的Y方向，也可称之为纵向）上均交替分布且相互绝缘。例如图2中，区域阵列为2*2阵列，在区域阵列的第一行中依次设有第一区域221和第二区域222，在区域阵列的第二行中依次设有第二区域222和第一区域221，在区域阵列的第一列中依次设有第一区域221和第二区域222，在区域阵列的第二列中依次设有第二区域222和第一区域221，且相邻的第一区域221和第二区域222之间被第一缝隙21分割并相互绝缘。应当理解的是，图2所示的区域阵列仅仅是便于理解的一种示例，在实际应用中，区域阵列可设置为N*M阵列,其中N和M都大于等于2，且N和M的值可以相等，也可不等。
参见图2所示，在本实施例中，缝隙21还包括将各第一区域221和第二区域内222的金属层20分割成至少两个金属片22的第二缝隙212，第二缝隙212也贯穿金属层20的正面和背面（也即第二缝隙212的底部为基板10的表面，图2中附图标记212所示为第二缝隙的平面结构示例），使得相邻金属片22之间相互绝缘。且各第一区域221和第二区域内222内相邻的两个金属片22位于第二缝隙212的两侧各对应的设有一焊盘23，例如可以在相邻的两个金属片2的边缘或靠近边缘的区域各对应设置一焊盘23，该对应的两个焊盘23可分别为正极焊盘和负极焊盘，用于与同一个电子元件的正负极引脚连接。参见图2所示，本实施例中各第一区域221和各第二区域222内的焊盘23在基板10上组合成多行多列的焊盘阵列。在图2所示的示例中，各第一区域221和第二区域222内的焊盘23形成的焊盘阵列为12*8阵列，也即12行8列。应当理解的是，图2所示的焊盘阵列也仅仅是便于理解的一种示例，在实际应用中，区域阵列可设置为n*m阵列,其中n和m都大于等于2，且n和m的值可以相等，也可不等。
参见图2所示，在本实施例中，各第一区域221内的金属片22中的至少一部分金属片22具有沿焊盘阵列的列方向延伸的第一延伸部A1,在各第一区域221内在焊盘阵列的各行方向上，第二缝隙212被各第一延伸部A1打断，使得在各行方向上，该第一延伸部A1形成对钢网进行支撑的支撑点；各第二区域222内的金属片22中的至少一部分金属片22具有沿焊盘阵列的行方向延伸的第二延伸部A2，在各第二区域222内在焊盘阵列的各列方向上，第二缝隙212被各第二延伸部A2打断，使得在各列方向上，该第二延伸部A2形成对钢网进行支撑的支撑点，这样可以保证在焊盘阵列的各行方向和各列方向上都有足够的支撑点对钢网形成支撑，从而尽可能减小印刷焊料的过程中钢网在第二缝隙212位置处的变形程度，延长钢网的使用寿命，提升焊料涂覆的精准性并降低钢网损耗和成本；且在图2所示的示例中，只需要对第二缝隙212的分布进行巧妙的调整，不需要额外增加其他部件或工艺，制作简单，通用性好且成本低。
在本实施例的一些示例中，第一缝隙211和第二缝隙212中的至少之一可以通过但不限于对金属层20刻蚀而形成，刻蚀工艺简单成熟，且效率和良品率高。
在本实施例的一些示例中，各第一区域221和各第二区域22内相邻两个金属片22的边缘对应位置上各设有的一焊盘23可在沿X方向上呈对称设置，从而使得焊盘23呈多行多列式阵列排布。但应当理解的是，本实施例中相邻两个金属片22上对应设置的焊盘23并不限于对称设置，也可根据需求采用非对称的方式。在本实施例中，各第一区域221和第二区域222包含的焊盘23的数量相等。当然，应当理解的是，也可设置各第一区域221和第二区域222包含的焊盘23的数量不同。
本实施例中，在同一列方向Y上，由于第二区域222内的第二缝隙212被第二区域222内的金属片22沿行方向上的第二延伸部A2打断，因此在同一列方向Y上一条第二缝隙212在同一列方向Y上的长度D2，小于同一列方向Y第一区域221内的一条第二缝隙212的长度D1（其中D1和D2参见图2所示，在图2中第一区域221内沿列方向延伸的第二缝隙212跨越多个金属片22）。通过设置同一列方向Y上，第一区域221的第二缝隙212的长度D1与第二区域222的第二缝隙212的长度D2不同的结构（也即在各列方向上设置第二区域222内的第二缝隙212被第二区域222内的金属片22沿行方向上的第二延伸部A2打断，而第一区域221内的第二缝隙212跨越多个金属片22），当使用钢网印刷焊料时，各第二延伸部A2作为支撑点增加了钢网在列方向的同一直线方向上的支撑强度。同样的，在同一行方向X上，由于第一区域221内的第二缝隙212被第一区域221内的金属片22沿列方向上的第一延伸部A1打断，因此在同一行方向X上一条第二缝隙212在同一行方向X上的长度D3，小于同一行方向X上第二区域222内的一条第二缝隙212的长度D4（其中D3和D4参见图2所示，在图2中第二区域222内沿行方向延伸的第二缝隙212跨越多个金属片22）。通过设置同一行方向X上，第一区域221的第二缝隙212的长度D3与第二区域222的第二缝隙212的长度D4不同的结构（也即在各行方向上设置第一区域221内的第二缝隙212被第一区域221内的金属片22沿列方向上的第一延伸部A1打断，而第二区域222内的第二缝隙212跨越多个金属片22），当使用钢网印刷焊料时，各第一延伸部A1作为支撑点增加了钢网在行方向的同一直线方向上的支撑强度，从而在行方向和列方向均可减少印刷焊料的过程中钢网凹陷的程度，延长钢网的使用寿命。
可以理解的是，其他实施例中，第一区域221的第二缝隙212的长度D1也可以小于第二区域222的第二缝隙212的长度D2，第一区域221的第二缝隙212的长度D3也可以大于第二区域222的第二缝隙212的长度D4。例如参见图6所示，图6相对于图2而言，则是将图2中所示的第一区域221和第二区域222交替设置的顺序进行了对调。
可以理解的是，本实施例中的行方向和列方向为相对的两个概念，例如将图2中所示的电路板进行旋转得到图7，使得图2中的行变为图7中列，图2中的列变为图7中的行。也即在其他实施例中，将图2中的列方向旋转变为图7中的行方向后，则在图7中，沿同一行方向X上第一区域221的第二缝隙212的长度D5（对应于图2中的D1）大于第二区域222的第二缝隙212的长度D6（对应于图2中的D2），沿同一列方向Y上，第一区域221的第二缝隙212的长度D7（对应于图2中的D3）小于第二区域222的第二缝隙212的长度D8（对应于图2中的D4）。
在本实施例中，请参考图2和图3，在同一列方向Y上，由于第二区域222内的第二缝隙212被第二区域222内的金属片22沿行方向上的第二延伸部A2打断，因此第一区域221中沿列方向Y延伸的第二缝隙212的数量少于第二区域222中沿列方向Y延伸的第二缝隙212的数量。在图2所示的示例中，在同一列方向Y上（以从左往右的方向第一列为例），第一区域221内的第二缝隙212（参见图2中的K1所示）的数量为1，第二区域222的第二缝隙212（参见图2中的K2、K3、K4所示）的数量为3。
在本实施例中，如图2所示，第一区域221和第二区域222内的第二缝隙212，包括若干主干缝隙和若干支干缝隙，其中主干缝隙沿行方向X或列方向Y的直线延伸，支干缝隙分隔相邻金属片22之间的焊盘23并连接于主干缝隙，一个主干缝隙与至少两个支干缝隙分别连接。第一区域221内的主干缝隙与第二区域222内的主干缝隙的延伸方向不平行。具体如图2所示中第一区域221的有6条沿列方向Y延伸的主干缝隙，分别为Z11、Z12、Z13、Z14、Z15、Z16，各主干缝隙一侧均连接有3条支干缝隙，例如Z16这一条主干缝隙连接的3条支干缝隙分别为x11、x12、x13，各支干缝隙至少有一部分与主干缝隙垂直；而第二区域222中有4条沿行方向X延伸的主干缝隙，分别为Z21、Z22、Z23、Z24，各主干缝隙一侧均连接有3条支干缝隙，例如Z24这一条主干缝隙连接的3条支干缝隙分别为x21、x22、x23，各支干缝隙具有与主干缝隙平行的部分和与主干缝隙垂直的部分，与主干缝隙平行的部分和与主干缝隙垂直的部分的连接处形成转折角。由图2可以看出，第一区域221内的主干缝隙与第二区域222内的主干缝隙的延伸方向垂直，使得第一区域221和第二区域222之间的主干缝隙的延方向上有更多支撑点，能减小在电路板上印刷锡膏的过程中钢网凹陷的程度，延长钢网的使用寿命。
在本实施例中，例如参见图2所示，相邻第一区域221和第二区域222之间具有支撑区域24，当刮刀在钢网上移动时，刮刀经过相邻第一区域221和第二区域222之间的区域时当对钢网施加垂直基板10向下的力，支撑区域24能对钢网提供支撑，从而达到减小钢网在相邻第一区域221和第二区域222之间的区域凹陷变形的程度，可进一步防止钢网损坏，从而进一步延长钢网的实用寿命。
在本实施例中，对于单个的第一区域221而言，第一缝隙211位于第一区域221的边缘，第二缝隙212位于第一区域221的内部，第一缝隙211与第二缝隙212相互连接以围合形成第一区域221。第一缝隙211将第一区域221与第一区域221之外的外部电路隔绝，第二缝隙212将第一区域221内相邻的两个金属片隔绝。对于单个的第二区域222而言，第一缝隙211位于第二区域222的边缘，第二缝隙212位于第二区域221的内部，第一缝隙211与第二缝隙212相互连接以围合形成第二区域222。第一缝隙211将第二区域222与第二区域222之外的外部电路隔绝，第二缝隙212将第二区域222内相邻的两个金属片隔绝。
在本实施例中，位于第一区域221和第二区域222内的第二缝隙212的宽度可根据其两侧焊盘23焊接的电子器件引脚间隔和金属片22的尺寸确定，位于第一区域221和第二区域222边缘的第一缝隙211的宽度根据实际需求(如电路板上的电压、电流等)进行设定。本实施例中，第一缝隙211的宽度小于第二缝隙212的宽度，通过在第一区域221和第二区域222的边缘设置第一缝隙211，可以将第一区域221和第二区域222内的线路与第一区域221和第二区域222之外的外部电路隔绝，通过在第一区域221和第二区域222的内部设置第二缝隙212，可以将相邻金属片之间进行隔绝，从而形成所需电路，并可结合电路需求对第一缝隙211和第二缝隙212的走向和宽度等进行合理设计，从而最大化利用金属层20的支撑作用达到进一步减少钢网凹陷程度的目的。
在本实施例的一些示例中，图2中所示的第一缝隙211和第二缝隙212中的至少之一的延伸方向与焊盘阵列的行方向和列方向相同，也可以理解为与图2中所示的X方向和Y方向相同。在图2所示的示例中，第二缝隙212曲折延伸，例如第二缝隙212沿行方向X和列方向Y曲折延伸，在延伸路径的拐角处，第二缝隙212成直角（当然也可替换为圆角或其他类型的角）。通过使第二缝隙212沿行方向X和列方向Y曲折延伸，以使多个金属片22或多个金属片22的组合构成矩形，便于封装过程中对电子元件的布局设计。
可以理解的是，其他实施例中，第二缝隙212也可以沿其他方向曲折延伸，以将金属层20分割成其他形状的金属片，如圆形、梯形、菱形、三角形等，以适用于不同形状或大小的电子元件。
又例如，在图2所示的示例中，第一缝隙211也曲折延伸，第一缝隙211沿行方向X和列方向Y曲折延伸，以将多个金属片22围城矩形的第一区域221和第二区域222，从而便于封装过程中对电子元件的布局设计。可以理解的是，其他实施例中，第一缝隙211也可以根据第二缝隙212的延伸路径沿其他方向延伸，以与第二缝隙212围合形成圆形、梯形、菱形、三角形等任意形状的第一区域221和第二区域222。
在本实施例的另一些示例中，请参考图3，缝隙21（也即第一缝隙211和第二缝隙212）内填充有阻焊层30，在垂直于基板10的方向上，阻焊层30的高度小于金属片22的高度。阻焊层30具有绝缘和防焊的作用，例如，本实施例中，阻焊层30的材料为阻焊油墨，其他实施例中，阻焊层30也可以由阻焊剂、阻焊胶等制成。由于电路板封装过程中，需要在焊盘23上镀锡以将电子器件固定于焊盘23上，相邻焊盘23之间的间隔较小，通过在缝隙21内部填充阻焊层30隔绝不同金属片22，可以防止相邻两个焊盘23之间出现锡桥造成不同电子元件之间相互影响。此外，在回流焊过程中，阻焊层30还具有防止焊锡外溢，避免电路短路的作用。另外，组焊层30的设置，使得钢网即使在第一缝隙211和第二缝隙212位置处变形凹陷时，其最大程度的凹陷也只能是抵靠在组焊层30上，相对于在第一缝隙211和第二缝隙212不设置组焊层30的结构，可进一步减小钢网凹陷的程度，延长钢网的使用寿命。
在本实施例的又一示例中，基板的正面和背面均设有金属层，且正面和背面所设置的金属层可都为图2所示的金属层20的结构，也可为只有其中之一为图2所示的金属层20的结构。例如参见图4所示（图4所示也为包括相邻两个金属片部分的截面示意图），基板10的正面为第一表面11，基板10的背面为第二表面12，应当理解的是此处基板10的正面和背面是相对而言的。第一表面11设有第一金属层201，第二表面12设有第二金属层202，基板10相背的第一表面11和第二表面12均可设置电路以及安装电子元件，第一金属层201和第二金属层202中至少一个金属层的结构与图2所示的金属层20结构相同。例如第一金属层201和第二金属层202的金属层的结构与图2所示的金属层20结构都相同时，在对电路板印刷焊料的过程中，在其正面和背面均可以达到减少钢网凹陷的目的。可以理解的是，第一金属层201和第二金属层202中至少一个金属层的结构与金属层20结构相同具体包括：只有第一金属层201的结构与本申请实施例提供的金属层20的结构相同，或者只有第二金属层202的结构与本申请实施例提供的金属层20的结构相同，也可以为第一金属层201和第二金属层202的结构均与本申请实施例提供的金属层20的结构相同。在本示例中，第一金属层201和第二金属层202之间可以无电路连接，也可根据需求进行电路连接。例如，请参考图4的示例，基板10设有过孔13，过孔13贯穿基板10的第一表面11和第二表面12，第一金属层201和第二金属层202通过过孔13连接（也即基板10正面和背面上的金属层通过过孔13进行电连接）。应当理解的是，采用过孔13连通第一金属层201和第二金属层202上的电路可有多种方式，例如，可以通过化学镀再加电镀，使过孔13两面的电路导通，也可以使导线穿设于过孔13，通过导线将过孔13两面的电路连通，还可通过在过孔13内填充导电物质，该导电物质同时与第一金属层201和第二金属层202接触，实现导通作用。其中，导电物质包括导电浆、导电油墨、焊锡等。通过在基板10上开设过孔3以连通第一金属层201和第二金属层202上的电路，可以达到简化电路结构，避免导线缠绕、节省空间等目的。
在本实施例的其他示例中，电路板包括至少两个层叠设置基板，各基板上均设有金属层。也即在本示例中电路板可为具有至少两个基板以及设于基板上的金属层的多层电路板结构。其中，应当理解的是，在本示例中，各基板上设置的金属层可均为图2所示的金属层20结构，也可为其中一部分金属层为图2所示的金属层20结构，一部分则为其他结构。
在本示例中，电路板包括层叠设置的至少两个基板时，相邻基板之间可以通过但不限于粘接层粘接在一起，粘接方式简单可靠。应当理解的是，在本示例中，各基板上的金属层之间可无直接的电连接关系，也可根据需求将其中的至少一部分基板之间的金属层进行电连接，电连接方式可以通过但不限于在基板上设置对应的过孔或在基板的表面或基板之外设置连接线路进行电连接，本示例对其不做限制。
为了便于理解，本示例下面结合图5（图5所示也为包括相邻两个金属片部分的截面示意图）所示的一种多层电路板结构进行便于理解性的说明，该多层电路板结构包括两个基板10，此处分别称之为第一基板101和第二基板102，第一基板101和第二基板102通过粘接层40粘接。第一基板101上设有第一金属层201和焊盘23形成第一子电路板，第二基板102上设有第二金属层202和焊盘23形成第二子电路板，第一金属层201和第二金属层202中的至少之一为图2所示的金属层20结构。也即图5所示电路板包括两个基板10，以及将两个基板10粘接在一起的粘接层40，两个基板10远离粘接层40的一面上均设有图2所示的金属层。图5所示的电路板还包括至少贯穿第一基板101、粘接层4和第二基板102的过孔13，且过孔13将第一金属层201和第二金属层202电连接。
应当理解的是，当电子产品多功能化要求较高时，需要的布线层数也较多，通过设置至少两个基板10和至少两个金属层20组成的电路板结构，可以避免多层布线结构中不同线路传输信号之间的干扰，且通过在多层电路板中采用本申请实施例提供的电路板，有利于减少钢网印刷过程中的生产成本。且可以理解的是，其他示例中，基板10和金属层20的数量还可以为其他数量的组合，此处不作过多限定。
本申请实施例提供一种电子装置，所述电子装置包括电子元件和如上所示的电路板，电子元件设于电路板上并与对应的焊盘焊接，例如电子元件可直接焊接在焊盘23上。本实施例中的电子元件可以为电容、电阻和LED芯片等中的至少之一，电子元件包括正负极引脚，当采用钢网在焊盘23上印刷锡膏之后，电子元件的正负极引脚通过锡膏焊接（也可替换为通过导电胶固定）固定于焊盘23上。通过采用本申请实施例提供的电路板，由于电路板上第二缝隙的分布可以在印刷焊料的过程中减小钢网在第二缝隙位置处的变形程度，从而尽可能避免钢网在第二缝隙位置处因凹陷程度过大而损坏，进而保证使用钢网所印刷的焊料精准性，可提升电路板和电子装置的可靠性和良品率，节省了电子装置的生产成本。
本实施例提供的电路板在可用于电子装置的显示屏作为显示屏背光源的电路板。在该应用场景中，电路板上各第一区域和第二区域中的各焊盘可以焊接LED芯片，且各第一区域和第二区域内的所有LED芯片串联连接。一个第一区域内的LED芯片组合成一个LED芯片阵列，一个第二区域内的LED芯片也组合成一个LED芯片阵列，各第一区域内的LED芯片和各第二区域内的LED芯片在基板上组合成一个大的LED芯片阵列。为了便于理解，下面以在图2所示的电路板上焊接LED芯片为示例进行说明，参见图8所示,电路板上的各第一区域221和第二区域222内的焊盘23上焊接有LED芯片L。其中，参见图8所示，对于第一区域221内的LED芯片L所组成的LED芯片阵列中，右上角的焊盘为正极焊盘H+，左下角的焊盘为负极焊盘H-，该第一区域221内的各LED芯片L通过第一区域221内的各金属片22组成串联电路，其中该串联电路的电流流向请参见图8中I1所示的虚线。对于第二区域222内的LED芯片L所组成的LED芯片阵列中，右上角的焊盘为正极焊盘H+，左下角的焊盘为负极焊盘（图中未标记），该第二区域222内的各LED芯片L通过第二区域222内的各金属片22组成串联电路，其中该串联电路的电流流向请参见图8中I2所示的虚线。
在图2所示的示例中，电路板上横向和纵向均设有至少两个交替排布的第一区域221和第二区域222，可将显示屏划分为至少两个子区域。故在同一区域内（例如在某个第一区域221或某个第二区域222内）的LED芯片可以同时受到控制，且同一区域内的LED芯片作为一个整体，可以单独受到控制，即可以单独控制某一个区域内的LED芯片的明暗从而调节显示屏的某一个子区域的明暗，实现局部区域调光的效果，可以提高显示屏的显示效果。
以上所揭露的仅为本申请一种较佳实施例而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于本申请所涵盖的范围。

Claims (15)

  1. 一种电路板，其特征在于，所述电路板包括至少一块基板，设置在所述基板的正面和/或背面上的金属层，所述金属层具有区域阵列，所述区域阵列包括通过第一缝隙分割形成的至少两个第一区域和至少两个第二区域，所述第一区域和所述第二区域在所述区域阵列的行方向和列方向上均交替分布且相互绝缘；
    各所述第一区域和所述第二区域内分别具有通过第二缝隙分割形成的至少两个相互绝缘的金属片，各所述第一区域和所述第二区域内相邻两个所述金属片对应的设有用于与一个电子元件连接的焊盘；各所述第一区域和所述第二区域内的所述焊盘在所述基板上呈多行多列式阵列排布以形成焊盘阵列；
    各所述第一区域内的至少一部分所述金属片具有沿所述焊盘阵列的列方向延伸的第一延伸部，在各所述第一区域内所述焊盘阵列的各行方向上，所述第二缝隙被所述第一延伸部打断；各所述第二区域内的至少一部分所述金属片具有沿所述焊盘阵列的行方向延伸的第二延伸部，在各所述第二区域内所述焊盘阵列的各列方向上，所述第二缝隙被所述第二延伸部打断。
  2. 如权利要求1所述的电路板，其特征在于，所述第一缝隙和/或所述第二缝隙的延伸方向与所述焊盘阵列的行方向和列方向相同。
  3. 如权利要求1所述的电路板，其特征在于，所述第一缝隙的宽度小于所述第二缝隙的宽度。
  4. 如权利要求1所述的电路板，其特征在于，所述第一区域和所述第二区域内的所述焊盘数量相等。
  5. 如权利要求1所述的电路板，其特征在于，所述第一缝隙和/或所述第二缝隙曲折延伸。
  6. 如权利要求1所述的电路板，其特征在于，所述第一缝隙和所述第二缝隙内填充有阻焊层，在垂直于所述基板的方向上，所述阻焊层的高度小于所述金属片的高度。
  7. 如权利要求1所述电路板，其特征在于，所述基板的正面和背面均设有所述金属层。
  8. 如权利要求7所述的电路板，其特征在于，所述基板上还设有贯穿其正面和背面的过孔，以将所述正面和所述背面上的所述金属层电连接。
  9. 如权利要求1所述的电路板，其特征在于，所述电路板包括至少两个层叠设置所述基板，各所述基板上均设有所述金属层。
  10. 如权利要求9所述的电路板，其特征在于，所述电路板包括两个所述基板，以及将两个所述基板粘接在一起的粘接层，所述两个基板远离所述粘接层的一面上均设有所述金属层。
  11. 如权利要求10所述的电路板，其特征在于，所述电路板还包括贯穿两个所述基板和所述粘接层的过孔，两个所述基板上的所述金属层通过所述过孔电连接。
  12. 如权利要求1所述的电路板，其特征在于，相邻所述第一区域和所述第二区域之间具有支撑区域。
  13. 如权利要求1所述的电路板，其特征在于，所述第一区域和所述第二区域内的所述第二缝隙包括主干缝隙和支干缝隙，所述主干缝隙沿所述焊盘阵列的行方向或列方向延伸，所述支干缝隙分隔相邻的所述金属片之间的所述焊盘并连接于所述主干缝隙，一个所述主干缝隙与多个所述支干缝隙分别连接，且所述第一区域内的所述主干缝隙与所述第二区域内的所述主干缝隙的延伸方向垂直。
  14. 一种电子装置，其特征在于，所述电子装置包括电子元件和如权利要求1所述的电路板，所述电子元件设于所述电路板上并与对应的所述焊盘焊接。
  15. 如权利要求14所述的电子装置，其特征在于，所述电子元件包括LED芯片。
PCT/CN2022/094166 2021-05-20 2022-05-20 电路板及电子装置 WO2022242754A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023571840A JP2024518628A (ja) 2021-05-20 2022-05-20 回路基板及び電子機器

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202121096883.2 2021-05-20
CN202121096883.2U CN216146514U (zh) 2021-05-20 2021-05-20 电路板及电子装置

Publications (1)

Publication Number Publication Date
WO2022242754A1 true WO2022242754A1 (zh) 2022-11-24

Family

ID=80799444

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/094166 WO2022242754A1 (zh) 2021-05-20 2022-05-20 电路板及电子装置

Country Status (3)

Country Link
JP (1) JP2024518628A (zh)
CN (1) CN216146514U (zh)
WO (1) WO2022242754A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN216146514U (zh) * 2021-05-20 2022-03-29 深圳市聚飞光电股份有限公司 电路板及电子装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234657A (ja) * 2006-02-27 2007-09-13 Kyocera Corp 多数個取り配線基板
JP2008192655A (ja) * 2007-01-31 2008-08-21 Kyocera Corp 複数個取り配線基台、配線基台および電子装置、ならびに複数個取り配線基台の分割方法
CN110277378A (zh) * 2019-04-25 2019-09-24 深圳市聚飞光电股份有限公司 一种集合基板、发光装置及其制造方法
CN111615257A (zh) * 2020-06-30 2020-09-01 华勤通讯技术有限公司 一种pcb板及pcb板上的屏蔽罩的焊接方法
CN216146514U (zh) * 2021-05-20 2022-03-29 深圳市聚飞光电股份有限公司 电路板及电子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234657A (ja) * 2006-02-27 2007-09-13 Kyocera Corp 多数個取り配線基板
JP2008192655A (ja) * 2007-01-31 2008-08-21 Kyocera Corp 複数個取り配線基台、配線基台および電子装置、ならびに複数個取り配線基台の分割方法
CN110277378A (zh) * 2019-04-25 2019-09-24 深圳市聚飞光电股份有限公司 一种集合基板、发光装置及其制造方法
CN111615257A (zh) * 2020-06-30 2020-09-01 华勤通讯技术有限公司 一种pcb板及pcb板上的屏蔽罩的焊接方法
CN216146514U (zh) * 2021-05-20 2022-03-29 深圳市聚飞光电股份有限公司 电路板及电子装置

Also Published As

Publication number Publication date
JP2024518628A (ja) 2024-05-01
CN216146514U (zh) 2022-03-29

Similar Documents

Publication Publication Date Title
US6760227B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
US10381286B2 (en) Power module
US5095407A (en) Double-sided memory board
CN112242476B (zh) 一种led显示单元组及显示面板
KR20010076213A (ko) 반도체 장치 및 그 배선 방법
WO2022242754A1 (zh) 电路板及电子装置
US20230276572A1 (en) Display device and manufacturing method thereof
JP7321009B2 (ja) 配線基板、接合型配線基板及び配線基板の製造方法
US10847695B2 (en) Light emitting device
JPH0529537A (ja) 半導体モジユール構造
JP3426988B2 (ja) 多数個取り配線基板
CN111048560B (zh) 显示装置
JPH0563346A (ja) チツプ型電子部品を搭載した装置
US10231335B2 (en) Electronic module with embedded jumper conductor
TW201806456A (zh) 電子裝置
JPS59138355A (ja) 記憶装置の多層実装構造
JPH0685465A (ja) Ｓｍｄモジュール用基板及びその製造方法
CN205029965U (zh) 电路板
US20230307586A1 (en) Mounting arrangements for semiconductor packages and related methods
CN217034453U (zh) 一种简化线路的调控式led背光模组结构
TWI764760B (zh) 電子裝置
WO2012129118A1 (en) Circuit protection device
JPH05275612A (ja) 電子部品組立構体
JP2023156805A (ja) プリント回路板の製造方法、プリント回路板及びプリント回路板用構造体
KR0135036Y1 (ko) 2중 저항을 갖는 2중 구조의 박막형 칩 부품

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22804073

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18561288

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2023571840

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22804073

Country of ref document: EP

Kind code of ref document: A1