WO2022237197A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2022237197A1
WO2022237197A1 PCT/CN2021/143228 CN2021143228W WO2022237197A1 WO 2022237197 A1 WO2022237197 A1 WO 2022237197A1 CN 2021143228 W CN2021143228 W CN 2021143228W WO 2022237197 A1 WO2022237197 A1 WO 2022237197A1
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WIPO (PCT)
Prior art keywords
layer
array substrate
substrate according
thin film
area
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Ceased
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PCT/CN2021/143228
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English (en)
French (fr)
Inventor
邬可荣
郑在纹
康报虹
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HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
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HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
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Application filed by HKC Co Ltd, Changsha HKC Optoelectronics Co Ltd filed Critical HKC Co Ltd
Publication of WO2022237197A1 publication Critical patent/WO2022237197A1/zh
Priority to US18/067,494 priority Critical patent/US20230123248A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs

Definitions

  • the present application relates to the technical field of display screens, in particular to an array substrate and a display panel.
  • the cathode is thin, the resistance of the cathode increases, which in turn makes the distribution of the cathode voltage uneven, resulting in low brightness uniformity of the display panel.
  • the main purpose of the present application is to provide an array substrate and a display panel, aiming at solving the technical problem of low brightness uniformity of the display panel in the prior art.
  • an array substrate proposed in this application includes:
  • a pixel definition layer is disposed in the non-via area of the non-opening area of the TFT device layer, and the non-opening area includes a via area and a non-via area;
  • a barrier wall the barrier wall is arranged at the via hole area, wherein the barrier wall is in an inverted trapezoidal shape;
  • organic light emitting diode layer is arranged on the upper end of the barrier wall and part of the auxiliary electrode in the via hole area;
  • a cathode is arranged on the upper end of a part of the auxiliary electrode in the via hole area.
  • the array substrate further includes an inorganic thin film disposed under the pixel definition layer and the barrier wall, and the inorganic thin film includes a silicon dioxide thin film and a silicon nitride thin film.
  • a first side engraved space is formed on both sides of the barrier wall and the edge of the inorganic thin film in the via hole area.
  • a second side engraving space is formed between the pixel definition layer and the edge of the inorganic thin film in the non-via region.
  • the thickness range of the inorganic thin film is 500-3000 angstroms.
  • the organic light emitting diode layer is further disposed on the upper end of the pixel definition layer.
  • the cathode is further disposed on the upper end of the OLED layer.
  • the organic light emitting diode layer is also disposed on a part of the upper end of the anode in the opening area.
  • the TFT device layer includes an auxiliary electrode, an anode and a thin film transistor structure.
  • the present application further provides a display panel, which includes the array substrates with the above structures.
  • the array substrate provided by the present application includes: a TFT device layer; a pixel definition layer, the pixel definition layer is arranged in the non-via area of the non-opening area of the TFT device layer, and the non-opening area includes a via area and a non-via area region; a barrier wall, the barrier wall is arranged at the via hole area, wherein the barrier wall is in an inverted trapezoidal shape; an organic light emitting diode layer, the organic light emitting diode layer is arranged on the top of the barrier wall, and the The upper end of part of the auxiliary electrode in the via hole area; the cathode, the cathode is arranged on the upper end of the part of the auxiliary electrode in the via hole area.
  • the array substrate provided by this application uses an inverted trapezoidal barrier wall, when evaporating the organic light emitting diode layer, there will be a gap space on both sides of the bottom of the barrier wall to make the cathode contact with the auxiliary electrode, so the cathode voltage can be improved uneven distribution.
  • FIG. 1 is a schematic diagram of the hardware structure of one embodiment of the array substrate of the present application.
  • FIG. 2 is a schematic diagram of the hardware structure of one embodiment of the array substrate of the present application.
  • Fig. 3 is a schematic diagram of the module structure of the TFT device layer of the present application.
  • Fig. 4 is a schematic diagram of the hardware structure of the TFT device layer of the present application.
  • FIG. 5 is a region division diagram of the TFT device layer of the present application.
  • the pixels of the organic light emitting diode (OLED) TFT device layer can be divided into bottom emitting (bottom emitting) and top emitting (top emitting) emitting) two kinds.
  • the pixel design of the array substrate mostly adopts the bottom emission design
  • the anode is a transparent electrode
  • the cathode uses aluminum as the reflective layer of the organic light-emitting diode, and the light needs to pass through the TFT array and the glass TFT device layer to be emitted.
  • the aperture ratio can only reach a maximum of about 40%.
  • the top-emitting OLED design uses a transparent or semi-transparent cathode, while the anode is an opaque metal. Therefore, even though TFTs and capacitors occupy most of the area of the pixel, because the OLED emits light upwards, its luminous area is not large. Affected by the TFT and capacitor area in the pixel.
  • it needs to be made very thin, and its sheet resistance cannot be reduced, which makes the cathode voltage distribution uneven, resulting in low brightness uniformity of the display panel.
  • the array substrate provided by the present application includes: a TFT device layer; a pixel definition layer, the pixel definition layer is arranged in the non-via area of the non-opening area of the TFT device layer, and the non-opening area includes a via area and a non-via area region; a barrier wall, the barrier wall is arranged at the via hole area, wherein the barrier wall is in an inverted trapezoidal shape; an organic light emitting diode layer, the organic light emitting diode layer is arranged on the top of the barrier wall, and the The upper end of part of the auxiliary electrode in the via hole area; the cathode, the cathode is arranged on the upper end of the part of the auxiliary electrode in the via hole area.
  • the array substrate provided by this application uses an inverted trapezoidal barrier wall, when evaporating the organic light emitting diode layer, there will be a gap space on both sides of the bottom of the barrier wall to make the cathode contact with the auxiliary electrode, so the cathode voltage can be improved uneven distribution.
  • FIG. 1 is a schematic diagram of a hardware structure of an embodiment of an array substrate of the present application. It includes: a TFT device layer 1; a pixel definition layer 4, the pixel definition layer 4 is arranged in the non-via area of the non-opening area of the TFT device layer 1, and the non-opening area includes a via area and a non-via area; A barrier wall 5, the barrier wall 5 is arranged at the via hole area, wherein the barrier wall is in an inverted trapezoidal shape; an organic light emitting diode layer 7, the organic light emitting diode layer 7 is arranged on the top of the barrier wall, and The upper end of part of the auxiliary electrodes 2 in the via area; the cathode 8, the cathode 8 is arranged on the upper end of the part of the auxiliary electrodes 2 in the via area.
  • the above-mentioned array substrate includes a TFT device layer 1, wherein the TFT device layer 1 includes an auxiliary electrode 2, an anode 3, and a thin film transistor structure 30.
  • the module structure of the TFT device layer 1 can refer to FIG. 3
  • the hardware structure of TFT device layer 1 can refer to FIG. GI (gate insulating layer 16), ACT (active layer 17), Buffer (buffer layer 18), Bottom Shield Metal (shading layer 19) and Substrate (substrate 20).
  • the above TFT device layer 1 is prepared by thin film transistor manufacturing process and positive electrode manufacturing process.
  • the upper end of the TFT device layer 1 can be divided into an opening area (B) and a non-opening area (A), wherein the non-opening area includes a via area (A2) and a non-via area (A1),
  • the open area is also referred to as the light emitting area.
  • the organic light emitting diode layer 7 and the cathode 8 are vapor-deposited sequentially above the anode 3 in the light-emitting area, so light can be successfully emitted; for the division of the upper end of the TFT device layer 1, refer to FIG. 5 .
  • the above-mentioned pixel definition layer 4 is arranged in the non-via area of the non-opening area of the TFT device layer 1.
  • the above-mentioned non-opening area includes a via area and a non-via area, and a barrier wall 5 is arranged in the middle of the via area.
  • the barrier wall 5 The upper end is provided with an organic light emitting diode layer 7 and a cathode 8 in sequence, wherein the barrier wall 5 is in an inverted trapezoidal shape.
  • the pixel definition layer 4 and the anode of the light-emitting area is also evaporated; further, when the cathode 8 is evaporated at a preset angle ⁇ , the gap space 6 where the organic light emitting diode layer 7 is not evaporated can be successfully evaporated, thereby realizing the cathode 8
  • the auxiliary electrode 2 below the gap space 6 for example: take the TFT device layer 1 as the plane, and tilt the evaporation cathode downward at a preset angle ⁇ , so that the cathode 8 can enter the gap space 6 more easily, thereby connecting with the gap space 6
  • the lower auxiliary electrode 2 contacts, specifically, the thickness of the evaporated organic light emitting diode layer 7 and the cathode 8 is not limited here, and can be preset according to specific circumstances.
  • the above preset angle ⁇ is preferably 30 degrees to 89 degrees
  • the array substrate uses an inverted trapezoidal barrier wall, when evaporating the organic light emitting diode layer, a gap space 6 that makes the cathode contact with the auxiliary electrode will be left, so the cathode voltage distribution can be improved. uneven.
  • FIG. 2 is a schematic diagram of the hardware structure of one embodiment of the array substrate of the present application, including: the array substrate further includes an inorganic thin film 9, and the inorganic thin film 9 is disposed on the pixel definition layer 4 and Below the barrier wall 5 , the inorganic film 9 includes a silicon dioxide film and a silicon nitride film.
  • the above-mentioned array substrate further includes an inorganic thin film 9, wherein the above-mentioned inorganic thin film 9 is arranged under the pixel definition layer 4 and the barrier wall 5, and then the side of the inorganic thin film 9 is etched, so that the pixel definition layer 4 And both sides of the bottom of the barrier wall 5 and the edge of the inorganic film 9 are formed with a first side carved space 10 and a second side carved space 11, the width of the first side carved space 10 and the second side carved space 11 is preferably 1 to 3 nanometers,
  • the last side etching process may be a wet etching process, and preferably, the above-mentioned inorganic film 9 is a silicon dioxide film or a silicon nitride film.
  • the thickness of the above-mentioned inorganic thin film 9 is preferably between 500 and 3000 angstroms.
  • the cathode 8 and the auxiliary electrode 2 can be in contact with the first side engraved space 10 and the second side engraved space 11 , which in turn can make the contact area between the cathode 8 and the auxiliary electrode 2 wider, and further improve the uneven distribution of the cathode voltage.
  • the present application also provides a display panel, which includes the above-mentioned array substrate. Since this display panel adopts all the technical solutions of all the above-mentioned embodiments, it has at least the technical solutions of the above-mentioned embodiments All the beneficial effects brought about will not be described one by one here.
  • the embodiments of the present application may be provided as methods or systems. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供了一种阵列基板及显示面板，阵列基板包括：TFT器件层（1）；像素定义层（4），像素定义层（4）设置于TFT器件层（1）非开口区域（A）的非过孔区域（A1），非开口区域（A）包括过孔区域（A2）以及非过孔区域（A1）；阻隔墙（5），阻隔墙（5）设置于过孔区域处，其中，阻隔墙（5）呈倒梯形；有机发光二极管层（7），有机发光二极管层（7）设置于阻隔墙（5）上端、以及过孔区域（A2）的部分辅助电极（2）上端；阴极（8），阴极（8）设置于过孔区域（A2）的部分辅助电极（2）上端。本申请可以改善阴极电压分布不均，以提高显示面板亮度均一性。

Description

阵列基板及显示面板
本申请要求于2021年5月14日申请的、申请号为202110533073.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示屏技术领域，特别涉及一种阵列基板及显示面板。
 背景技术
对于顶发光的阵列基板，由于阴极较薄，会导致阴极电阻增加，进而使得阴极电压分布不均，导致显示面板亮度均一性低。
 技术问题
本申请的主要目的是提供一种阵列基板及显示面板，旨在解决现有技术中，显示面板亮度均一性低的技术问题。
 技术解决方案
为实现上述目的，本申请提出的一种阵列基板，包括：
TFT器件层；
像素定义层，所述像素定义层设置于所述TFT器件层非开口区域的非过孔区域，所述非开口区域包括过孔区域以及非过孔区域；
阻隔墙，所述阻隔墙设置于所述过孔区域处，其中，所述阻隔墙呈倒梯形；
有机发光二极管层，所述有机发光二极管层设置于所述阻隔墙上端、以及所述过孔区域的部分辅助电极上端；
阴极，所述阴极设置于所述过孔区域的部分辅助电极上端。
在一实施例中，所述阵列基板还包括无机薄膜，所述无机薄膜设置于所述像素定义层以及所述阻隔墙下方，所述无机薄膜包括二氧化硅薄膜以及氮化硅薄膜。
在一实施例中，所述阻隔墙两侧与所述过孔区域的无机薄膜边缘形成有第一侧刻空间。
在一实施例中，所述像素定义层与所述非过孔区域的无机薄膜边缘形成有第二侧刻空间。
在一实施例中，所述无机薄膜的厚度区间为500~3000埃米。
在一实施例中，所述有机发光二极管层还设置于所述像素定义层上端。
在一实施例中，所述阴极还设置于所述有机发光二极管层上端。
在一实施例中，所述有机发光二极管层还设置于所述开口区域的部分阳极上端。
在一实施例中，所述TFT器件层包括辅助电极、阳极以及薄膜晶体管结构。
为了实现上述目的，本申请还提供一种显示面板，所述显示面板包括以上各个架构的阵列基板。
本申请提供的阵列基板包括：TFT器件层；像素定义层，所述像素定义层设置于所述TFT器件层非开口区域的非过孔区域，所述非开口区域包括过孔区域以及非过孔区域；阻隔墙，所述阻隔墙设置于所述过孔区域处，其中，所述阻隔墙呈倒梯形；有机发光二极管层，所述有机发光二极管层设置于所述阻隔墙上端、以及所述过孔区域的部分辅助电极上端；阴极，所述阴极设置于所述过孔区域的部分辅助电极上端。
 有益效果
由于本申请提供的阵列基板使用倒梯形的阻隔墙，因此，在蒸镀有机发光二极管层时，会在阻隔墙底部的两侧留下使得阴极与辅助电极接触的缝隙空间，因此可以改善阴极电压分布不均。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请阵列基板其中一个实施例的硬件结构示意图；
图2为本申请阵列基板其中一个实施例的硬件结构示意图；
图3为本申请TFT器件层的模块结构示意图；
图4为本申请TFT器件层的硬件结构示意图；
图5为本申请TFT器件层的区域划分图。
附图标号说明：
标号 名称 标号 名称
1 TFT器件层 2 辅助电极
3 阳极 4 像素定义层
5 阻隔墙 6 缝隙空间
7 有机发光二极管层 8 阴极
9 无机薄膜 10 第一侧刻空间
11 第二侧刻空间 12 平坦化层
13 源漏极 14 绝缘层
15 栅极 16 栅绝缘层
17 有缘层 18 缓冲层
19 遮光层 20 基板
30 薄膜晶体管结构    
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
有机发光二极管（OLED）TFT器件层的像素可以分成底部发光(bottom emitting)与上部发光(top emitting)两种。以往阵列基板的像素设计大多采用底部发光设计，其阳极为透明的电极，而阴极则以铝作为有机发光二极管发光的反射层，而光则需透过TFT数组与玻璃TFT器件层才能发射出去。由于发光面积与像素中的薄膜晶体管(TFT)与电容数目和面积有关，因为OLED所发出的光会被TFT与电容中的不透明金属导线所阻挡，因此开口率最大只能到达约40%。顶发光OLED设计则是采用透明或者半透的阴极，而阳极则为不透明的金属，因此即使TFT与电容占去像素中的大部分面积，但因为OLED是往上发光，所以其可发光面积不受像素中的TFT与电容面积影响。但是顶发光阴极金属为了维持透明，需要做的很薄，其方块电阻无法降低，进而使得阴极电压分布不均，导致显示面板亮度均一性低。
本申请提供的阵列基板包括：TFT器件层；像素定义层，所述像素定义层设置于所述TFT器件层非开口区域的非过孔区域，所述非开口区域包括过孔区域以及非过孔区域；阻隔墙，所述阻隔墙设置于所述过孔区域处，其中，所述阻隔墙呈倒梯形；有机发光二极管层，所述有机发光二极管层设置于所述阻隔墙上端、以及所述过孔区域的部分辅助电极上端；阴极，所述阴极设置于所述过孔区域的部分辅助电极上端。
由于本申请提供的阵列基板使用倒梯形的阻隔墙，因此，在蒸镀有机发光二极管层时，会在阻隔墙底部的两侧留下使得阴极与辅助电极接触的缝隙空间，因此可以改善阴极电压分布不均。
如图1所示，图1为本申请阵列基板其中一个实施例的硬件结构示意图。包括：TFT器件层1；像素定义层4，所述像素定义层4设置于所述TFT器件层1非开口区域的非过孔区域，所述非开口区域包括过孔区域以及非过孔区域；阻隔墙5，所述阻隔墙5设置于所述过孔区域处，其中，所述阻隔墙呈倒梯形；有机发光二极管层7，所述有机发光二极管层7设置于所述阻隔墙上端、以及所述过孔区域的部分辅助电极2上端；阴极8，所述阴极8设置于所述过孔区域的部分辅助电极2上端。
在本实施例中，上述阵列基板包括TFT器件层1，其中，TFT器件层1包括辅助电极2、阳极3以及薄膜晶体管结构30，具体的，TFT器件层1的模块架构可参考图3，进一步的，TFT器件层1的硬件架构可参考图4，上述薄膜晶体管结构30由OC (平坦化层12)、SD（源漏极13）、ILD（绝缘层14）、Gate（栅极15）、GI（栅绝缘层16）、ACT(有缘层17)、Buffer（缓冲层18）、Bottom Shield Metal (遮光层19)以及Substrate（基板20）组成。
可选的，通过薄膜晶体管制程以及正极制程制备上述TFT器件层1。具体的，如图5，TFT器件层1的上端可分为开口区域（B）以及非开口区域（A），其中，非开口区域包括过孔区域（A2）和非过孔区域（A1），开口区域也称为发光区域。其中，发光区域的阳极3上方依次蒸镀了有机发光二极管层7以及阴极8，因此可成功发光；对于TFT器件层1上端的区域划分，可参考图5所示。
进一步的，上述像素定义层4设置于TFT器件层1非开口区域的非过孔区域，上述非开口区域包括过孔区域以及非过孔区域，过孔区域中部设置有阻隔墙5，阻隔墙5上端依次设置有机发光二极管层7以及阴极8，其中，阻隔墙5呈倒梯形，容易理解的是，当存在倒梯形的阻隔墙5时，在垂直蒸镀有机发光二极管层7后，阻隔墙5底部的两侧不会被蒸镀上有机发光二极管层7，反而会形成缝隙空间6，容易理解的，在完成了有机发光二极管层7的蒸镀工艺后，像素定义层4以及发光区域的阳极上也蒸镀了像素定义层7；进一步的，当以预设角度θ蒸镀阴极8时，可使得未被蒸镀有机发光二极管层7的缝隙空间6成功蒸镀阴极8，从而实现阴极8与缝隙空间6下方的辅助电极2接触，例如：以TFT器件层1为平面，以预设角度θ向下倾斜蒸镀阴极，即可使得阴极8更容易进入缝隙空间6，从而与缝隙空间6下方的辅助电极2接触，具体的，蒸镀的有机发光二极管层7以及阴极8的厚度，在此不做限定，可视具体情况预设，优选的，上述预设角度θ优选30度至89度（30°-89°）。
在本实施例的技术方案中，由于阵列基板使用倒梯形的阻隔墙，因此，在蒸镀有机发光二极管层时，会留下使得阴极与辅助电极接触的缝隙空间6，因此可以改善阴极电压分布不均。
可选的，参照图2，图2为本申请阵列基板其中一个实施例的硬件结构示意图，包括：所述阵列基板还包括无机薄膜9，所述无机薄膜9设置于所述像素定义层4以及所述阻隔墙5下方，所述无机薄膜9包括二氧化硅薄膜以及氮化硅薄膜。
在本实施例中，上述阵列基板还包括无机薄膜9，其中，上述无机薄膜9设置于像素定义层4以及阻隔墙5的下方，然后再对无机薄膜9进行侧刻，从而使得像素定义层4以及阻隔墙5底部的两侧与无机薄膜9边缘形成有第一侧刻空间10以及第二侧刻空间11，第一侧刻空间10以及第二侧刻空间11的宽度优选1至3纳米，优选的，上次侧刻工艺可为湿法刻蚀工艺，优选的，上述无机薄膜9为二氧化硅薄膜或者氮化硅薄膜。优选的，上述无机薄膜9的厚度优选500至3000埃米之间。
在本实施例的技术方案中，由于增加了第一侧刻空间10以及第二侧刻空间11，可使得阴极8与辅助电极2在第一侧刻空间10以及第二侧刻空间11进行接触，进而可使得阴极8与辅助电极2之间的接触面积更广，更进一步的改善了阴极电压分布不均。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。
为了实现上述目的，本申请还提供一种显示面板，所述显示面板包括如上所述的阵列基板，由于本显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
本领域内的技术人员应明白，本申请的实施例可提供为方法或系统。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。
应当注意的是，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的单词“一”或“一个”不排除存在多个这样的部件。本申请可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。本领域的技术人员也可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，在不脱离本申请构思的前提下，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种阵列基板，其中，包括：
    TFT器件层（1）；
    像素定义层（4），所述像素定义层（4）设置于所述TFT器件层（1）非开口区域（A）的非过孔区域（A1），所述非开口区域（A）包括过孔区域（A2）以及非过孔区域（A1）；
    阻隔墙（5），所述阻隔墙（5）设置于所述过孔区域（A2）处，其中，所述阻隔墙（5）呈倒梯形；
    有机发光二极管层（7），所述有机发光二极管层（7）设置于所述阻隔墙上端、以及所述过孔区域（A2）的部分辅助电极（2）上端；
    阴极（8），所述阴极（8）设置于所述过孔区域（A2）的部分辅助电极（2）上端。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括无机薄膜（9），所述无机薄膜（9）设置于所述像素定义层（4）以及所述阻隔墙（5）下方。
  3. 如权利要求2所述的阵列基板，其中，所述阻隔墙（5）两侧与所述过孔区域（A2）的无机薄膜（9）边缘形成有第一侧刻空间（10）。
  4. 如权利要求3所述的阵列基板，其中，所述第一侧刻空间（10）的宽度为1至3纳米。
  5. 如权利要求2所述的阵列基板，其中，所述像素定义层（4）与所述非过孔区域（A1）的无机薄膜（9）边缘形成有第二侧刻空间（11）。
  6. 如权利要求5所述的阵列基板，其中，所述第二侧刻空间（11）的宽度为1至3纳米。
  7. 如权利要求2所述的阵列基板，其中，所述无机薄膜（9）的厚度区间为500~3000埃米。
  8. 如权利要求2所述的阵列基板，其中，所述无机薄膜（9）包括二氧化硅薄膜以及氮化硅薄膜。
  9. 如权利要求1所述的阵列基板，其中，所述有机发光二极管层（7）还设置于所述像素定义层（4）上端。
  10. 如权利要求1所述的阵列基板，其中，所述阴极（8）还设置于所述有机发光二极管层（7）上端。
  11. 如权利要求1所述的阵列基板，其中，所述有机发光二极管层（7）还设置于所述开口区域的部分阳极（3）上端。
  12. 如权利要求1所述的阵列基板，其中，所述TFT器件层（1）包括辅助电极（2）、阳极（3）以及薄膜晶体管结构（30）。
  13. 如权利要求12所述的阵列基板，其中，所述薄膜晶体管结构（30）由平坦化层（12）、源漏极（13）、绝缘层（14）、栅极（15）、栅绝缘层（16）、有缘层（17）、缓冲层（18）、遮光层（19）以及基板（20）组成。
  14. 如权利要求1所述的阵列基板，其中，所述阻隔墙（5）上端依次设置所述有机发光二极管层（7）以及所述阴极（8）。
  15. 一种显示面板，其中，包括如权利要求1所述的阵列基板。
PCT/CN2021/143228 2021-05-14 2021-12-30 阵列基板及显示面板 Ceased WO2022237197A1 (zh)

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