US20230123248A1 - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
US20230123248A1
US20230123248A1 US18/067,494 US202218067494A US2023123248A1 US 20230123248 A1 US20230123248 A1 US 20230123248A1 US 202218067494 A US202218067494 A US 202218067494A US 2023123248 A1 US2023123248 A1 US 2023123248A1
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United States
Prior art keywords
array substrate
layer
via area
thin film
barrier wall
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Pending
Application number
US18/067,494
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English (en)
Inventor
Kerong WU
Chung Jae Moon
Baohong KANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
Original Assignee
HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
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Filing date
Publication date
Application filed by HKC Co Ltd, Changsha HKC Optoelectronics Co Ltd filed Critical HKC Co Ltd
Assigned to CHANGSHA HKC OPTOELECTRONICS CO., LTD., HKC Corporation Limited reassignment CHANGSHA HKC OPTOELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, Baohong, MOON, CHUNG JAE, WU, KERONG
Publication of US20230123248A1 publication Critical patent/US20230123248A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs

Definitions

  • This application relates to the technical field of display screens, and in particular to an array substrate and a display panel.
  • the cathode is thin, which will cause the increase of cathode resistance and in turn the uneven distribution of cathode voltage, resulting in low brightness uniformity of the display panel.
  • a main object of this application is to provide an array substrate and a display panel, aiming at solving the technical problem of low brightness uniformity of the display panel in the related art.
  • an array substrate including:
  • TFT thin film transistor
  • a pixel definition layer arranged in a non-via area of a non-opening area of the TFT device layer, in particular the non-opening area includes a via area and the non-via area;
  • barrier wall arranged at the via area, in particular the barrier wall is in an inverted trapezoid shape
  • an organic light emitting diode layer arranged on an upper end of the barrier wall and an upper end of part of auxiliary electrodes in the via area;
  • a cathode arranged on the upper end of the part of the auxiliary electrode in the via area.
  • a display panel including an array substrate according to above each embodiment.
  • the array substrate provided by this application includes a TFT device layer; a pixel definition layer arranged in a non-via area of a non-opening area of the TFT device layer, in particular the non-opening area includes a via area and the non-via area; a barrier wall arranged at the via area, in particular the barrier wall is in an inverted trapezoid shape; an organic light emitting diode layer arranged on an upper end of the barrier wall and an upper end of part of an auxiliary electrode in the via area; and a cathode arranged on the upper end of part of the auxiliary electrode in the via area.
  • the array substrate provided by this application uses the inverted trapezoidal barrier wall, thus when the organic light emitting diode layer is evaporated, a gap that makes the cathode contact with the auxiliary electrode will be left on both sides of the bottom of the barrier wall, so that the uneven distribution of cathode voltage may be alleviated.
  • FIG. 1 is a schematic diagram of a hardware structure of an array substrate according to an embodiment of this application.
  • FIG. 2 is a schematic diagram of the hardware structure of the array substrate according to another embodiment of this application.
  • FIG. 3 is a schematic diagram of a module structure of a TFT device layer according to this application.
  • FIG. 4 is a schematic diagram of a hardware structure of the TFT device layer according to this application.
  • FIG. 5 is an area division diagram of the TFT device layer according to this application.
  • first and second in this application are only used for descriptive purposes, and should not be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may comprise at least one of these features explicitly or implicitly.
  • technical solutions of various embodiments may be combined with each other, but which should be based on the implementation for those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions neither exists nor falls within the protection scope of this application.
  • Pixels of the organic light emitting diode (OLED) TFT device layer may be divided into bottom emitting and top emitting.
  • the pixel design of the array substrate mostly adopted the bottom emitting design, in which the anode was a transparent electrode and the cathode was aluminum being used as a reflective layer of the organic light emitting diodes, and the light could only be emitted through the TFT array and the glass TFT device layer. Since the light emitting area is related to the number and area of thin film transistors (TFTs) and the capacitors in pixels, the light emitted by OLED will be blocked by opaque metal wires in the TFTs and the capacitors, so the opening ratio may only reach about 40% at the maximum.
  • TFTs thin film transistors
  • the top emitting OLED design uses transparent or semi-transparent cathode, while the anode is an opaque metal. Therefore, even the TFTs and the capacitors take up most of area in the pixels, the luminous area of the OLED is not affected by the area of TFTs and the capacitors in the pixels because the OLED emits light upwards.
  • the metal of the cathode for the top emitting needs to be very thin, and its sheet resistance cannot be reduced, which in turn causes the uneven distribution of the cathode voltage, resulting in low brightness uniformity of the display panel.
  • the array substrate provided by this application includes:
  • a pixel definition layer arranged in a non-via area of a non-opening area of the TFT device layer, the non-opening area including a via area and the non-via area;
  • a barrier wall arranged at the via area and in an inverted trapezoid shape
  • an organic light emitting diode layer arranged on an upper end of the barrier wall and an upper end of part of auxiliary electrodes in the via area;
  • a cathode arranged on the upper end of part of the auxiliary electrodes in the via area.
  • the array substrate provided by this application uses the inverted trapezoidal barrier wall, thus when the organic light emitting diode layer is evaporated, a gap that makes the cathode contact with the auxiliary electrodes will be left on both sides of the bottom of the barrier wall, so that the uneven distribution of the cathode voltage may be alleviated.
  • FIG. 1 is a schematic diagram of the hardware structure of an array substrate according to an embodiment of this application.
  • the array substrate includes:
  • a TFT device layer 1 a TFT device layer 1 ;
  • a pixel definition layer 4 arranged in a non-via area of a non-opening area of the TFT device layer 1 , the non-opening area including a via area and the non-via area;
  • barrier wall 5 arranged at the via area and in an inverted trapezoid shape
  • an organic light emitting diode layer 7 arranged on an upper end of the barrier wall and an upper end of part of auxiliary electrodes 2 in the via area;
  • a cathode 8 arranged on the upper end of part of the auxiliary electrodes 2 in the via area.
  • the array substrate includes a TFT device layer 1
  • the TFT device layer 1 includes an auxiliary electrode 2 , an anode 3 , and a thin film transistor structure 30 .
  • the module architecture of the TFT device layer 1 is shown in FIG. 3
  • the hardware architecture of the TFT device layer 1 is shown in FIG. 4 .
  • the thin film transistor structure 30 is composed of a planarization layer (OC) 12 , a source/drain (SD) 13 , an insulation layer (ILD) 14 , a gate 15 , a gate insulation layer (GI) 16 , an active layer (ACT) 17 , a buffer layer 18 , a bottom shield metal (light shield layer) 19 and an substrate 20 .
  • the TFT device layer 1 is prepared by a thin film transistor process and a positive electrode process.
  • the upper end of the TFT device layer 1 may be divided into an opening area (B) and a non-opening area (A).
  • the non-opening area includes a via area (A 2 ) and a non-via area (A 1 ), and the opening area is also called a light emitting area.
  • the organic light emitting diode layer 7 and the cathode 8 are sequentially evaporated on the anode 3 in the light emitting area, so the light emitting area may emit the light successfully.
  • An area division of the upper end of the TFT device layer 1 is shown in FIG. 5 .
  • the pixel definition layer 4 is arranged in a non-via area of a non-opening area of the TFT device layer 1 , and the non-opening area includes a via area and the non-via area.
  • the via area is provided with a barrier wall 5 in a middle, and an upper end of the barrier wall 5 is sequentially provided with an organic light emitting diode layer 7 and a cathode 8 .
  • the barrier wall 5 is in an inverted trapezoid shape.
  • the cathode 8 when to evaporate to form the cathode 8 at a preset angle ⁇ , the cathode 8 may be successfully deposited in the gap 6 where the organic light emitting diode layer 7 is not deposited, thus achieving the contact between the cathode 8 and the auxiliary electrode 2 below the gap 6 .
  • the cathode 8 may enter the gap 6 more easily, thus contacting the auxiliary electrode 2 below the gap 6 .
  • the thicknesses of the deposited organic light emitting diode layer 7 and the cathode 8 are not limited here, but may be preset according to specific conditions.
  • the preset angle ⁇ is preferably 30 to 89 degrees (30°-89°).
  • the array substrate uses the inverted trapezoidal barrier wall, thus when the organic light emitting diode layer is evaporated, the gap 6 that makes the cathode contact with the auxiliary electrode will be reserved, so that the uneven distribution of cathode voltage may be alleviated.
  • the array substrate further includes an inorganic thin film 9 .
  • the inorganic thin film 9 is arranged below the pixel definition layer 4 and the barrier wall 5 and includes a silicon dioxide thin film or a silicon nitride thin film.
  • the array substrate further includes an inorganic thin film 9 .
  • the inorganic thin film 9 is arranged below the pixel definition layer 4 and the barrier wall 5 , and then the inorganic thin film 9 is side-etched, so that a first side etching space 10 and a second side etching space 11 are formed among both sides of the bottom of the pixel definition layer 4 , both sides of the bottom of the barrier wall 5 and edges of the inorganic thin film 9 .
  • Widths of the first side etching space 10 and the second side etching space 11 are preferably 1 to 3 nanometers.
  • the side etching process may be a wet etching process.
  • the inorganic thin film 9 is a silicon dioxide thin film or a silicon nitride thin film.
  • the thickness of the inorganic thin film 9 is preferably between 500 and 3000 angstroms.
  • the cathode 8 may be brought into contact with the auxiliary electrode 2 in the first side etching space 10 and the second side etching space 11 , which in turn causes the contact area between the cathode 8 and the auxiliary electrode 2 to be larger, and further alleviate the uneven distribution of cathode voltage.
  • this application also provides a display panel, which includes the above-mentioned array substrate.
  • this display panel adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.
  • any reference signs in parentheses shall not be construed as limiting the claims.
  • the wordings “comprise”, “comprising”, “include”, “including” or the like do not exclude the presence of components or steps not listed in the claims.
  • the wording “a” or “an” preceding a component does not exclude the presence of a plurality of such components.
  • This application may be implemented by means of hardware including several different components and by means of a suitably programmed computer. In a unit claim enumerating several devices, several of these devices may be embodied by the same item of hardware.
  • the use of the wordings, such as first, second, third, and the like does not indicate any order. These wordings may be interpreted as names.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
US18/067,494 2021-05-14 2022-12-16 Array substrate and display panel Pending US20230123248A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202110533073.7A CN113270426B (zh) 2021-05-14 2021-05-14 阵列基板及显示面板
CN202110533073.7 2021-05-14
PCT/CN2021/143228 WO2022237197A1 (zh) 2021-05-14 2021-12-30 阵列基板及显示面板

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PCT/CN2021/143228 Continuation WO2022237197A1 (zh) 2021-05-14 2021-12-30 阵列基板及显示面板

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WO (1) WO2022237197A1 (zh)

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CN113270426B (zh) * 2021-05-14 2022-07-22 长沙惠科光电有限公司 阵列基板及显示面板

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JP5008606B2 (ja) * 2007-07-03 2012-08-22 キヤノン株式会社 有機ｅｌ表示装置及びその製造方法
KR20120092386A (ko) * 2011-02-11 2012-08-21 삼성디스플레이 주식회사 유기발광표시장치 및 그 제조방법
US20130056784A1 (en) * 2011-09-02 2013-03-07 Lg Display Co., Ltd. Organic Light-Emitting Display Device and Method of Fabricating the Same
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KR102020805B1 (ko) * 2012-12-28 2019-09-11 엘지디스플레이 주식회사 투명 유기 발광 표시 장치 및 투명 유기 발광 표시 장치 제조 방법
KR101548304B1 (ko) * 2013-04-23 2015-08-28 엘지디스플레이 주식회사 유기 전계 발광 표시장치 및 그 제조방법
KR20150061921A (ko) * 2013-11-28 2015-06-05 엘지디스플레이 주식회사 유기전계발광표시장치
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KR102378460B1 (ko) * 2015-02-09 2022-03-24 삼성디스플레이 주식회사 유기 발광 표시 장치
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CN113270426B (zh) * 2021-05-14 2022-07-22 长沙惠科光电有限公司 阵列基板及显示面板

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WO2022237197A1 (zh) 2022-11-17
CN113270426A (zh) 2021-08-17

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