WO2022237111A1 - 采样电路及驱动方法、像素采样电路、显示装置 - Google Patents

采样电路及驱动方法、像素采样电路、显示装置 Download PDF

Info

Publication number
WO2022237111A1
WO2022237111A1 PCT/CN2021/131519 CN2021131519W WO2022237111A1 WO 2022237111 A1 WO2022237111 A1 WO 2022237111A1 CN 2021131519 W CN2021131519 W CN 2021131519W WO 2022237111 A1 WO2022237111 A1 WO 2022237111A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
circuit
coupled
input terminal
sub
Prior art date
Application number
PCT/CN2021/131519
Other languages
English (en)
French (fr)
Inventor
韩新斌
殷新社
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/015,394 priority Critical patent/US12027085B2/en
Publication of WO2022237111A1 publication Critical patent/WO2022237111A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a sampling circuit and a driving method, a pixel sampling circuit, and a display device.
  • Self-luminous display devices such as organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panels have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, good color reproduction, sensitive response and wide viewing angle, etc., and have broad development prospects. prospect.
  • organic light-emitting diode Organic Light-Emitting Diode, OLED
  • a sampling circuit including: a first input terminal, a second input terminal, a first voltage acquisition sub-circuit, and a current integration sub-circuit.
  • the first voltage collection subcircuit is coupled to the first input terminal and the current integration subcircuit, and is configured to collect a first voltage at the first input terminal and transmit the first voltage to The current integration subcircuit.
  • the current integration sub-circuit is also coupled to the second input terminal and is configured to generate and outputting a second voltage; and outputting the first voltage in response to an integral control signal.
  • the second input is configured to be coupled to the first input.
  • the first voltage acquisition sub-circuit includes a first voltage follower, the input terminal of the first voltage follower is coupled to the first input terminal; and/or, the current integrator
  • the circuit includes an integrator and a first switching device, the integrator includes: a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal of the integrator is coupled to the first voltage acquisition sub-circuit, and the integrating The inverting input terminal of the device is coupled to the second input terminal.
  • a first switching device is connected in parallel between the non-inverting input of the integrator and the inverting input of the integrator and is configured to close in response to the integration control signal.
  • the first voltage acquisition sub-circuit further includes: a first capacitor and a second switching device.
  • the first plate of the first capacitor is coupled to the output end of the first voltage follower, the second plate of the first capacitor is grounded; the second switching device is coupled to the first capacitor between the first plate and the current integration sub-circuit.
  • the sampling circuit further includes a difference subcircuit coupled to the current integration subcircuit and configured to obtain the difference between the first voltage and the second voltage, to get the third voltage.
  • the difference subcircuit includes: a subtractor, a second voltage follower and a third voltage follower.
  • the subtractor includes a non-inverting input terminal, an inverting input terminal and an output terminal; the input terminal of the second voltage follower is coupled to the current integration sub-circuit, and the output terminal of the second voltage follower is connected to the The positive-phase input terminal of the subtractor is coupled; the input terminal of the third voltage follower is coupled to the current integration sub-circuit, and the output terminal of the third voltage follower is coupled to the inverting input of the subtractor terminal coupling.
  • the current integration subcircuit includes a voltage output terminal, and the current integration subcircuit is configured to output the first voltage and the second voltage through the voltage output terminal; the difference The subcircuit also includes a storage subcircuit coupled to the voltage output terminal of the current integration subcircuit and configured to store the received first voltage in response to a third control signal, and to store the received first voltage in response to a fourth control signal. control signal to store the second voltage.
  • the storage sub-circuit includes: a second capacitor, a third capacitor, a third switching device and a fourth switching device.
  • the first plate of the second capacitor is coupled to the voltage output end, the second plate of the second capacitor is grounded; the first plate of the third capacitor is coupled to the voltage output end, The second plate of the third capacitor is grounded; the third switching device is coupled between the voltage output terminal and the first plate of the second capacitor; the fourth switching device is coupled between the between the voltage output terminal and the first plate of the third capacitor.
  • the sampling circuit further includes: a sampling output terminal and a fifth switching device.
  • the fifth switching device is coupled between the difference subcircuit and the sampling output terminal.
  • the sampling circuit further includes: a second voltage acquisition subcircuit coupled to the third input terminal and configured to collect and output the fourth voltage provided by the third input terminal. Voltage.
  • the second voltage acquisition sub-circuit includes: a fourth voltage follower and a fourth capacitor.
  • the input end of the fourth voltage follower is coupled to the third input end; the first plate of the fourth capacitor is coupled to the output end of the fourth voltage follower, and the fourth capacitor The second plate is grounded.
  • the sampling circuit further includes a sampling output.
  • the third voltage acquisition sub-circuit further includes a sixth switch device coupled between the first plate of the fourth capacitor and the sampling output terminal.
  • a pixel sampling circuit includes: the sampling circuit and the pixel driving circuit described in any one of the above embodiments.
  • the pixel driving circuit includes a driving transistor, and the driving transistor includes a first stage, a second electrode and a control electrode.
  • the pixel driving circuit is configured to transmit the driving current flowing through the first stage and the second pole of the driving transistor to the second input terminal of the sampling circuit, and to transmit the driving current flowing through the second pole of the driving transistor The voltage is transmitted to the first input terminal of the sampling circuit.
  • the pixel driving circuit further includes a sensing transistor, the control electrode of the sensing transistor is coupled to the scanning signal end, and the first electrode of the sensing transistor is coupled to the first input end , the second pole of the sensing transistor is coupled to the second input terminal.
  • the pixel driving circuit further includes a voltage terminal, wherein the pixel driving circuit is further configured to transmit the voltage of the voltage terminal to the third input terminal of the sampling circuit.
  • a display device in a third aspect, includes the sampling circuit described in any of the above embodiments, or the display device includes the pixel sampling circuit described in any of the above embodiments.
  • the display device further includes a processor, the processor is coupled to the sampling circuit or the pixel sampling circuit, and is configured to calculate the driving current according to the difference between the first voltage and the second voltage .
  • a driving method of a sampling circuit comprising:
  • the first voltage collection sub-circuit collects the first voltage at the first input terminal, and transmits the first voltage to the current integration sub-circuit; the current integration sub-circuit transmits the first voltage and the second input terminal to the The driving current of the current integration sub-circuit is integrated with time to generate and output the second voltage; and, in response to the integration control signal, output the first voltage.
  • the driving method further includes: the difference finding subcircuit calculates the difference between the first voltage and the second voltage to obtain and output a third voltage.
  • FIG. 1 is a structural diagram of a sampling circuit provided by some embodiments of the present disclosure
  • FIG. 2 is a circuit diagram of another sampling circuit provided by some embodiments of the present disclosure.
  • Fig. 3 is a signal transmission diagram of the sampling circuit shown in Fig. 2;
  • FIG. 4 is a structural diagram of another sampling circuit provided by some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of another sampling circuit provided by some embodiments of the present disclosure.
  • Fig. 6 is a top view of a display panel provided by some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of a pixel sampling circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of another pixel sampling circuit provided by some embodiments of the present disclosure.
  • FIG. 9 is a timing control diagram of the pixel sampling circuit shown in FIG. 8.
  • FIG. 10A is a signal transmission diagram of the pixel sampling circuit shown in FIG. 8 in the display stage
  • FIG. 10B is a signal transmission diagram of the pixel sampling circuit shown in FIG. 8 in the acquisition phase
  • FIG. 11 is a structural diagram of another pixel sampling circuit provided by some embodiments of the present disclosure.
  • Fig. 12 is a flowchart of a driving method of a sampling circuit provided by some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • the luminous intensity of the sub-pixel in the OLED display panel is proportional to the driving current flowing through the light-emitting device, and in the sub-pixel, the driving current flowing through the light-emitting device is controlled by the driving transistor in the pixel driving circuit of the sub-pixel.
  • the driving transistor in the pixel driving circuit of the sub-pixel Under the influence of the manufacturing process of the driving transistors, there are differences in the threshold voltage Vth of each driving transistor in the OLED display panel, so that when an equal data signal (such as an initial voltage) is written to the gate of each driving transistor, it flows through each driving transistor. There is a difference in the driving current of the transistors, which causes the problem of display unevenness in the OLED display panel.
  • the threshold voltage of the drive transistor is compensated by using an electrical external compensation method
  • the electrical external compensation method includes sampling the anode voltage of the light emitting device by using a voltage sampling circuit, and calculating the compensation voltage according to the sampled anode voltage .
  • the sampling circuit is an analog circuit, there is common-mode noise, so that the voltage output by the sampling circuit includes a common-mode noise value, that is, the voltage output by the sampling circuit is not an accurate anode voltage.
  • embodiments of the present disclosure provide a sampling circuit for accurately collecting electrical signals in a pixel driving circuit.
  • the sampling circuit refers to a circuit capable of collecting electrical signals in a target circuit and outputting the collected electrical signals.
  • the target circuit refers to a circuit in which electrical signals are to be collected.
  • the target circuit may be a pixel driving circuit in a display panel.
  • the electrical signals that the sampling circuit can collect include voltage, current, etc.
  • the sampling circuit can be coupled to the node to be collected in the target circuit, and configured to collect the electrical signal of the node to be collected, for example, the sampling circuit is configured To collect the voltage of the node to be collected, or configured to collect the current flowing through the node to be collected.
  • the sampling circuit may include a plurality of electronic components and a plurality of wires coupling the electronic components.
  • the electronic components in the sampling circuit may include operational amplifiers, capacitors, switches, resistors and the like.
  • the operational amplifier can realize specific operational functions, for example, the inverting terminal of the operational amplifier is coupled to the output terminal to form a voltage follower, so as to output the voltage input from the non-inverting terminal through the output terminal.
  • the operational amplifier can also be combined with other electronic components to achieve other operational functions.
  • the combination of the operational amplifier and capacitor constitutes an integrator
  • the combination of operational amplifier and resistor constitutes a subtractor.
  • FIG. 1 shows a sampling circuit provided by some embodiments of the present disclosure.
  • the sampling circuit 100 includes: a first input terminal Iput1 , a second input terminal Iput2 , a first voltage acquisition sub-circuit 110 and a current integration sub-circuit 120 .
  • the input end of the sampling circuit 100 is coupled to the node to be sampled in the target circuit, and is configured to receive the electrical signal of the node to be sampled.
  • the sampling circuit includes at least one input terminal, and each input terminal may be respectively coupled to a different node in the target circuit, and the electrical signals received by each input terminal may be different. Exemplarily, referring to FIG.
  • the sampling circuit 100 includes a first input terminal Iput1 and a second input terminal Iput2, and the first input terminal Iput1 is configured to receive a voltage signal in a target circuit, for example, the first input terminal Iput1 and the target circuit
  • the first to-be-mined node in is coupled, configured to receive the first voltage V1 of the first to-be-mined node
  • the second input terminal Iput2 is configured to receive the current signal in the target circuit, for example, the second input terminal Iput2 is connected to the target
  • the second mining node in the circuit is coupled and configured to receive the driving current Id flowing through the second mining node.
  • the first voltage collection sub-circuit 110 is coupled to the first input terminal Iput1 and the current integration sub-circuit 120, and is configured to collect the first voltage V1 of the first input terminal Iput1, and transmit the first voltage V1 to the current integration sub-circuit 120 .
  • the first voltage acquisition sub-circuit 110 can read the first voltage V1 of the first input terminal Iput1 , and transmit the read first voltage V1 to the current integration sub-circuit 120 .
  • the current integration sub-circuit 120 is also coupled to the second input terminal Iput2, and is configured to generate and output a second voltage V1 according to the integral of the driving current Id transmitted to the current integration sub-circuit 120 by the first voltage V1 and the second input terminal Iput2 with respect to time. voltage V2; and, in response to the integral control signal, outputting the first voltage V1.
  • the current integration sub-circuit 120 may integrate the received electric signal, for example, the current integration sub-circuit 120 integrates the received driving current Id with respect to time to generate a charge amount.
  • the current integration sub-circuit 120 can also output a second voltage V2 according to the generated charge amount and the first voltage V1.
  • the current integration sub-circuit 120 may be coupled to the integration control signal terminal and configured to receive the integration control signal from the integration control signal terminal Inc.
  • the integration control signal can control the output of the current integration sub-circuit 120.
  • the integration control signal is a signal output within a specific time period.
  • the current integration sub-circuit 120 receives the first voltage acquisition sub-circuit The first voltage V1 transmitted by 110, within the time period of the output signal of the integral control signal, the current integration sub-circuit 120 directly outputs the received first voltage V1;
  • the sub-circuit 120 can generate and output the second voltage V2 according to the first voltage V1 and the time-integrated drive current Id transmitted to the current integration sub-circuit 120 by the second input terminal Iput2.
  • the integral control signal is a signal controlled alternately by a valid signal and an invalid signal.
  • the current integral sub-circuit 120 directly outputs the received first voltage V1; when the integral control signal In the case of outputting an invalid signal, the current integration sub-circuit 120 generates and outputs the second voltage V2 according to the first voltage V1 and the time integration of the driving current Id transmitted to the current integration sub-circuit 120 by the second input terminal Iput2.
  • the current integration sub-circuit 120 may further include a voltage output terminal Oput_V configured to output the first voltage V1 and the second voltage V2 through the voltage output terminal Oput_V.
  • some embodiments of the present disclosure provide a sampling circuit, which may include: a first voltage follower 111 , an integrator 121 and a first switching device SW1 .
  • the sampling circuit can be used as a specific implementation of the sampling circuit provided in FIG. 1 , and is not limited to realizing the functions that can be realized by each sub-circuit in FIG. 1 .
  • the input terminal 111a of the first voltage follower is coupled to the first input terminal Iput1.
  • the voltage follower includes an operational amplifier OP, the inverting terminal of the operational amplifier OP is coupled to the output terminal, so that the signal output by the output terminal of the operational amplifier OP is the same as the signal input by the non-inverting terminal, for example, the positive phase terminal of the operational amplifier OP
  • the phase terminal inputs the first voltage V1
  • the output terminal of the operational amplifier OP also outputs the first voltage V1.
  • the inverting terminal of the operational amplifier OP is coupled to the output terminal to form a voltage follower
  • the input terminal 111a of the voltage follower is the non-inverting terminal of the operational amplifier
  • the output terminal 111b of the voltage follower is the output terminal of the operational amplifier OP.
  • the integrator 121 includes: a non-inverting input terminal 121a, an inverting input terminal 121b and an output terminal 121c, the non-inverting input terminal 121a of the integrator is coupled to the first voltage acquisition sub-circuit 110, and the inverting input terminal 121b of the integrator is connected to the first voltage acquisition sub-circuit 110.
  • the two input terminals Iput2 are coupled.
  • the integrator 121 includes an operational amplifier OP and a capacitor Cf, wherein one plate of the capacitor Cf is coupled to the inverting terminal of the operational amplifier OP, and the other plate of the capacitor Cf is coupled to the output terminal of the operational amplifier OP , when the operational amplifier OP and the capacitor Cf form an integrator 121, the non-inverting input terminal 121a of the integrator is the non-inverting terminal of the operational amplifier OP, the inverting input terminal 121b of the integrator is the inverting terminal of the operational amplifier, and the integrator The output terminal 121c is the output terminal of the operational amplifier OP.
  • the first switching device SW1 is connected in parallel between the non-inverting input terminal 121a of the integrator and the inverting input terminal 121b of the integrator, and is configured to close in response to the integration control signal.
  • the first switching device SW1 is controlled by the integral control signal.
  • the first switching device SW1 may be a normally open or normally closed switch.
  • the first switching device SW1 is a normally open switch.
  • the first switching device SW1 is in an open state, and when the integral control signal is received, the first switching device SW1 is closed.
  • the first switching device SW1 is a timing-controlled switching device.
  • the first switching device SW1 may be a transistor, or other switching devices.
  • the first switching device SW1 is controlled by a valid signal and an invalid signal. When the integral control signal controlling the first switching device SW1 outputs a valid signal, the first switching device SW1 is closed to form a path. When the integral control signal controlled by SW1 outputs an invalid signal, the first switching device SW1 is turned off to cut off the path.
  • the embodiments of the present disclosure all take the switch devices (including the first switch device SW1 and the switch devices SW2 - SW6 to be described later) as normally open switches that are closed in response to corresponding control signals as an example for illustration.
  • the embodiment of the present disclosure does not limit the type of the switching device.
  • the switching device described in the embodiment of the present disclosure may be a normally closed switch that is turned off only in response to a corresponding control signal, or, the present disclosure
  • the switching device described in the embodiment is a switch controlled alternately by a valid signal and an invalid signal. Under the control of the valid signal, the switch is closed, and under the control of the invalid signal, the switch is opened.
  • the first voltage acquisition sub-circuit 110 includes a first voltage follower 111
  • the current integration sub-circuit 120 includes an integrator 121 and a first switching device SW1.
  • Fig. 3 is a signal transmission diagram of the sampling circuit shown in Fig. 2 at different stages, wherein (a) in Fig. 3 is a signal transmission diagram of the sampling circuit shown in Fig. 2 in the first stage of the acquisition stage, in Fig. 3 (b) is a signal transmission diagram of the second stage of the sampling circuit in the acquisition stage shown in FIG. 2 .
  • the first input terminal Iput1 receives the first voltage V1 in the target circuit, and transmits the first voltage V1 to the integrator 121 through the first voltage follower 111 The non-inverting terminal of the operational amplifier OP.
  • the first switching device SW1 is closed in response to the integral control signal, so that the inverting terminal of the operational amplifier OP in the integrator 121 is coupled to the output terminal to form a voltage follower, and the first The voltage V1 is output through the inverting terminal of the operational amplifier OP, so that the voltage output terminal Oput_V outputs the first voltage V1.
  • the integrator 121 works, the positive phase input terminal 121a of the integrator inputs the first voltage V1, and the negative phase input terminal 121a of the integrator Terminal 121b inputs the driving current Id that the second input terminal Iput receives, and the output terminal of integrator 121 is according to the operational formula of integrator
  • the second voltage V2 is output, where T is the charging time of the capacitor, that is, the time from when the first switching device SW1 is turned off to when the integrator 121 outputs a stable second voltage V2.
  • the value of the driving current Id' calculated according to the first voltage V1 and the second voltage V2 is the driving current Id in the target circuit collected by the sampling circuit 100 .
  • the voltage output terminal Oput_V of the sampling circuit 100 may be coupled to an analog-to-digital converter and configured to convert the received analog signal into a digital signal.
  • the voltage output terminal Oput_V is The first stage and the second stage output the first voltage V1 and the second voltage V2 respectively. Since the sampling circuit 100 is an analog circuit, the output first voltage V1 and the second voltage V2 are analog signals.
  • the first voltage V1 and the second voltage V2 are successively received by the analog-to-digital converter, so that the first voltage V1 and the second voltage V2 are converted into digital signals, for example, the analog-to-digital converter is also coupled to the processor, and the converted The digital signal can be directly used by the processor, and the driving current Id' can be calculated by the processor.
  • the sampling circuit respectively outputs the first voltage V1 and the second voltage V2, wherein both the first voltage V1 and the second voltage V2 include common-mode noise caused by the sampling circuit, and when the first voltage V1 and the second voltage V2 After the difference between the two voltages V2 is calculated, the common mode noise included in the first voltage V1 and the second voltage V2 can be canceled out.
  • the difference between the first voltage V1 and the second voltage V2 is a function of the driving current received by the second input terminal, therefore, the driving current in the target circuit can be effectively extracted through the sampling circuit, and, because the first The difference between the voltage V1 and the second voltage V2 does not include common-mode noise, so the extracted driving current also filters out the common-mode noise, thereby ensuring the accuracy of extracting the driving current.
  • the first voltage V1 and the second voltage V2 are respectively output through the sampling circuit, which is beneficial to the subsequent difference between the first voltage V1 and the second voltage V2, and the difference between the first voltage V1 and the second voltage V2 The included common-mode noise value cancels out.
  • the first voltage V1 and the second voltage V2 can also be used as the basis for calculating the electrical signal collected in the target circuit, so as to accurately collect the electrical signal to be collected from the target circuit, thereby ensuring the accuracy of sampling.
  • the sampling circuit 100 it is usually necessary to connect a longer wire between the second input terminal Iput2 and the current integration sub-circuit 120, so as to transmit the driving current Id to the current integration sub-circuit 120, so that the second input terminal Iput2 and the current integration sub-circuit 120 A parasitic capacitance Cs exists between the sub-circuits 120 .
  • the second input terminal Iput2 is configured to be coupled to the first input terminal Iput1.
  • the second input terminal Iput2 of the sampling circuit 100 is coupled to the first input terminal Iput1.
  • the first input terminal Iput1 receives the first voltage V1 of a node to be sampled in the target circuit.
  • a voltage V1 can be transmitted to the current integration sub-circuit 120 through the second voltage V2; in the second stage of sampling, the first input terminal Iput1 receives the driving current Id of the node to be sampled, and the driving current Id can be transmitted through the second input terminal Iput2 to the current integration sub-circuit 120.
  • the second input terminal Iput2 and the first input terminal Iput1 may be coupled through a transistor, and the transistor may control the transmission of the electrical signal received by the first input terminal Iput1 to the second input terminal Iput2.
  • the sampling circuit 100 is only coupled to a node to be sampled in the target circuit, so that the sampling circuit 100 can collect the voltage of the node to be sampled , and the driving current flowing through this node can be collected.
  • the first voltage acquisition sub-circuit 120 further includes: a first capacitor C1 and a second switching device SW2 .
  • the first plate of the first capacitor C1 is coupled to the output terminal 111b of the first voltage follower, the second plate of the first capacitor C1 is grounded; the second switching device SW2 is coupled to the first plate of the first capacitor C1 Between the current integration sub-circuit 120.
  • the first capacitor C1 can be used to store the signal output by the first voltage follower 111
  • the second switching device SW2 can be used to control the transmission of the electrical signal output by the first voltage follower 111 to the current integration sub-circuit 120
  • the first capacitor C1 stores the first voltage V1 from the first voltage follower 111 , and transmits the first voltage V1 to the current integration sub-circuit 120 under the control of the second switching device SW2 .
  • the second switching device SW2 can be closed at an appropriate time according to the needs of the sampling circuit 100 , so as to transmit the electrical signal stored in the first capacitor C1 to the current integration sub-circuit 120 at a specific time.
  • the sampling circuit 100 further includes a difference sub-circuit 130 .
  • the difference subcircuit 130 is coupled to the current integration subcircuit 120 and is configured to calculate the difference between the first voltage V1 and the second voltage V2 to obtain a third voltage V3.
  • the differential subcircuit 130 includes two input terminals: a first differential input terminal and a second differential input terminal, wherein the first differential input terminal and the second differential input terminal are respectively connected to a current integrator
  • the circuit 120 is coupled, and the first difference input terminal receives the first voltage V1, and the second difference input terminal receives the second voltage V2.
  • FIG. 5 provides a sampling circuit for some embodiments of the present disclosure.
  • the sampling circuit can be used as a specific implementation of the sampling circuit provided in FIG. 4 , and it is not limited to realizing the functions that can be realized by each sub-circuit in FIG. 4 .
  • the electronic components and the coupling relationship included in the first voltage acquisition sub-circuit 110 and the current integration sub-circuit 120 may be the same as those of the sampling circuit shown in FIG. 1 or FIG. 2 , and will not be repeated here.
  • the difference subcircuit 130 includes: a subtractor 131 , a second voltage follower 132 , and a third voltage follower 133 .
  • the subtractor 131 includes a non-inverting input terminal 131a, an inverting input terminal 131b, and an output terminal 131c.
  • the input terminal 132a of the second voltage follower is coupled to the current integration sub-circuit 120, and the output terminal 132b of the second voltage follower is coupled to the non-inverting input terminal 131a of the subtractor.
  • the input terminal 133a of the third voltage follower is coupled to the current integration sub-circuit 120, and the output terminal 133b of the third voltage follower is coupled to the inverting input terminal 131b of the subtractor.
  • the input terminal 132a of the second voltage follower in the difference subcircuit 130 receives the first voltage V1 transmitted by one current integration subcircuit 120
  • the input terminal 133a of the third voltage follower receives the other current integration subcircuit 120
  • the transmitted second voltage V2 the first voltage V1 and the second voltage V2 are respectively transmitted to the non-inverting input terminal 131a and the inverting input terminal 131b of the subtractor 131 through the second voltage follower 132 and the third voltage follower 133 .
  • the sampling circuit 100 includes the difference sub-circuit 130
  • the sampling circuit directly outputs the third voltage V3, wherein the third voltage V3 is the difference between the first voltage V1 and the second voltage V2, that is, the third voltage V3 does not include common-mode noise caused by the sampling circuit, thereby making the electrical signal (third voltage) output by the sampling circuit more accurate.
  • the difference subcircuit 130 may be coupled with the analog-to-digital conversion unit and the processor.
  • the third voltage V3 output by the difference sub-circuit 130 is converted into a digital signal by an analog-to-digital converter, and then directly transmitted to the processor for subsequent processing, without requiring the processor to perform a difference operation on the first voltage V1 and the second voltage V2, In turn, the power consumption of the processor can be reduced.
  • the current integration sub-circuit 120 includes a voltage output terminal Oput_V, and the current integration sub-circuit 120 is configured to output the first voltage V1 and the second voltage V2 through the voltage output terminal Oput_V.
  • the difference sub-circuit 130 also includes a storage sub-circuit 134, which is coupled to the voltage output terminal Oput_V of the current integration sub-circuit 120, configured to store the received first voltage V1 in response to the third control signal, and respond to According to the fourth control signal, the second voltage V2 is stored.
  • a storage sub-circuit 134 which is coupled to the voltage output terminal Oput_V of the current integration sub-circuit 120, configured to store the received first voltage V1 in response to the third control signal, and respond to According to the fourth control signal, the second voltage V2 is stored.
  • the current integration sub-circuit 120 respectively outputs the first voltage V1 and the second voltage V2 at different times through the voltage output terminal Oput_V
  • the storage sub-circuit 134 integrates the current when the current integration sub-circuit 120 outputs the first voltage V1
  • the first voltage V2 output by the sub-circuit 120 is stored, and the storage sub-circuit 134 stores the second voltage V2 output by the current integration sub-circuit 120 while the current integration sub-circuit 120 is outputting the second voltage V2.
  • the storage subcircuit 134 includes a second capacitor C2 , a third capacitor C3 , a third switching device SW3 and a fourth switching device SW4 .
  • the first plate of the second capacitor C2 is coupled to the voltage output terminal Oput_V, and the second plate of the second capacitor C2 is grounded.
  • the first plate of the third capacitor C3 is coupled to the voltage output terminal Oput_V, and the second plate of the third capacitor C3 is grounded.
  • the third switching device SW3 is coupled between the voltage output terminal Oput_V and the first plate of the second capacitor C2.
  • the fourth switching device SW4 is coupled between the voltage output terminal Oput_V and the first plate of the third capacitor C3.
  • the first voltage V1 output from the voltage output terminal Oput_V may be stored in the second capacitor C2, and the second voltage V2 output from the voltage output terminal Oput_V may be stored in the third capacitor C3.
  • the third switching device SW3 is closed in response to the third control signal, and the storage sub-circuit 134 transmits and stores the first voltage V1 in the second capacitor C2; in the second stage of sampling, the first The four switching device SW4 is turned on in response to the fourth control signal, and the storage sub-circuit 134 transmits and stores the second voltage V2 in the third capacitor C3.
  • the current integration sub-circuit 120 includes only one voltage output terminal Oput_V
  • the difference sub-circuit 130 includes a storage sub-circuit 134
  • the first voltage V1 and the second voltage V2 can be divided through the voltage output terminal Oput_V
  • the stored first voltage V1 and second voltage V2 are simultaneously transmitted to the subtractor for difference calculation to obtain the third voltage V3, which avoids the need for a subtractor to be coupled to two current integration sub-circuits 120 at the same time. situation, thereby reducing the volume of the sampling circuit 100 .
  • the sampling circuit 100 further includes a sampling output terminal Oput_S and a fifth switching device SW5, wherein the fifth switching device SW5 is coupled between the difference sub-circuit 130 and the sampling output terminal Oput_S between.
  • the sampling circuit 100 includes a fifth switching device SW5
  • the fifth switching device SW5 can control the transmission of the third voltage V3 output by the difference sub-circuit 130 to the sampling output terminal Oput_S, so as to output The terminal Oput_S outputs the third voltage V3.
  • the sampling circuit 100 further includes a second voltage acquisition sub-circuit 140, the second voltage acquisition sub-circuit 140 is coupled to the third input terminal Iput3, and is configured to collect and output the fourth voltage provided by the third input terminal Iput3. Voltage V4.
  • the third input terminal Iput3 is configured to receive the voltage signal in the target circuit, for example, the third input terminal Iput3 is coupled to the third node to be sampled in the target circuit, and is configured to receive the voltage signal of the third node to be sampled The fourth voltage V4.
  • the embodiment of the present disclosure does not limit the time for the third input terminal Iput3 to collect the fourth voltage V4, which can be designed according to needs, for example, the time for the third input terminal Iput3 to collect the fourth voltage V4 can be compared with the time for the first input terminal The time for Iput1 to collect the first voltage V1 and the second input terminal Iput2 to collect the driving current Id are different.
  • the second voltage collection sub-circuit includes: a fourth voltage follower 141 and a fourth capacitor C4.
  • the input terminal 141a of the fourth voltage follower is coupled to the third input terminal Iput3.
  • the first plate of the fourth capacitor C4 is coupled to the output terminal 141b of the fourth voltage follower, and the second plate of the fourth capacitor C4 is grounded.
  • the third voltage acquisition sub-circuit 140 further includes a sixth switching device SW6, and the sixth switching device SW6 is coupled between the first plate of the fourth capacitor C4 and the sampling output terminal Oput_S. Wherein, the sixth switching device SW6 is configured to control the transmission of the fourth voltage V4 to the sampling output terminal Oput_S.
  • the fourth voltage V4 received by the third input terminal Iput3 is transmitted to the fourth capacitor C4 through the fourth voltage follower, and the fourth capacitor C4 stores the received fourth voltage V4.
  • the sixth switching device SW6 responds to the first When the six control signals are closed, the fourth voltage V4 stored in the fourth capacitor C4 can be output through the sampling output terminal Oput_S.
  • Embodiments of the present disclosure also provide a display device.
  • a display device refers to a product with an image display function. Exemplarily, it can be: a monitor, a TV, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (Personal Digital Assistant, PDA), Digital cameras, portable camcorders, viewfinders, monitors, navigators, vehicles, large-area walls, home appliances, information query equipment (such as business query equipment for e-government, banks, hospitals, electric power and other departments, monitors, etc.
  • PDA Personal Digital Assistant
  • the display device includes a display panel 20 and a sampling circuit 100 .
  • the display panel may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) display panel, a micro LED (including: miniLED or microLED) display panel, etc.
  • the sampling circuit 100 may be an integrated circuit (integrated circuit, IC for short), or the sampling circuit 100 is an analog circuit including several electronic components.
  • the display device may further include other components, such as a printed circuit board (PCB) and a flexible circuit board (FPC) coupled with the display panel, a power system for supplying power to the display panel, and the like.
  • PCB printed circuit board
  • FPC flexible circuit board
  • FIG. 6 shows a top view of the display panel 20 provided by some embodiments of the present disclosure.
  • the display panel 20 has a display area (Active Area, referred to as AA) and a peripheral area S located on at least one side of the display area AA.
  • the peripheral area S can be set around the display area AA.
  • the display panel includes: a plurality of sub-pixels P arranged in the area AA, each sub-pixel P includes a pixel driving circuit 200 and a light emitting device EL (such as OLED) coupled to each other.
  • FIG. 6 only exemplarily shows the coupling relationship between the pixel driving circuit 200 in the sub-pixel P and the light emitting device EL, but the size of the light emitting device is not limited thereto.
  • the size of the light emitting device EL is not limited. 1.
  • the positions of the pixel driving circuit 200 and the light emitting device EL are not limited thereto, for example, the light emitting device EL and the coupled pixel driving circuit 200 may overlap in the thickness direction of the display panel.
  • the pixel driving circuit is composed of electronic devices such as transistors and capacitors (Capacitance, C for short).
  • the pixel driving circuit may include three transistors (two switching transistors and one driving transistor) and a capacitor to form a 3T1C structure; of course, the pixel driving circuit may also include more than three transistors (multiple switching transistors and one driving transistor ) and at least one capacitor, for example, the pixel driving circuit may include a capacitor and four transistors to form a 4T1C structure.
  • the transistor may be a thin film transistor (Thin Film Transistor, TFT for short), a field effect transistor (metal oxide semiconductor, MOS for short), or other switching devices with the same characteristics, and the embodiments of the present disclosure all take the thin film transistor as an example for illustration.
  • TFT Thin Film Transistor
  • MOS metal oxide semiconductor
  • the control electrode of the thin film transistor is the gate, the first electrode of the thin film transistor is one of the source electrode and the drain electrode, and the second electrode of the thin film transistor is the other one of the source electrode and the drain electrode. Since the source and the drain of the thin film transistor can have the same function in the thin film transistor, there is no special distinction between the source and the drain. In one example, when the thin film transistor is a P-type transistor, the first pole of the thin film transistor is a source, and the second pole of the thin film transistor is a drain. In another example, when the thin film transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.
  • the description of the pixel driving circuit is described by taking a P-type transistor as an example. It should be noted that the embodiments of the present disclosure include but are not limited thereto.
  • one or more thin film transistors in the pixel driving circuit can also use N-type transistors, only need to connect the poles of the selected type of thin film transistors with reference to the poles of the corresponding thin film transistors in the embodiments of the present disclosure, and It is enough to make the corresponding control electrode supply the corresponding high-level voltage or low-level voltage.
  • the pixel driving circuit 200 in the display device can be coupled with the sampling circuit 100 to form a pixel sampling circuit 30 .
  • the target circuit sampled by the sampling circuit 100 is the pixel driving circuit 200 .
  • the pixel driving circuit 200 in the pixel sampling circuit 30 is located in the display panel, and the sampling circuit 100 may be located on a printed circuit board or a flexible circuit board coupled with the display panel.
  • the embodiments of the present disclosure are described with a 4T1C pixel driving circuit, and other types of pixel driving circuits, such as 3T1C and 7T1C driving methods, can refer to the embodiments of the present disclosure.
  • the pixel driving circuit 200 includes a driving transistor T1, and the driving transistor T1 includes a first stage T1a, a second electrode T1b and a control electrode T1c.
  • the second pole T1b of the driving transistor is coupled to the first input terminal Iput1 and the second input terminal Iput2 of the sampling circuit 100, and the pixel driving circuit 200 is configured to pass the flow through the first stage T1a and the second pole T1b of the driving transistor
  • the driving current Id is transmitted to the second input terminal Iput2 of the sampling circuit 100, for example, the driving current Id flowing through the first stage T1a and the second pole T1b of the driving transistor is transmitted to the second input terminal through the first input terminal Iput1 Iput2 ; and transmitting the voltage of the second pole T1b of the driving transistor to the first input terminal Iput1 of the sampling circuit 100 .
  • the pixel driving circuit 200 further includes a sensing transistor T4, wherein the control electrode T4c of the sensing transistor is coupled to the scanning signal Sn terminal, configured to be turned on under the control of the sensing signal Sn, and the first transistor T4c of the transistor
  • the diode T4b is coupled to the second input terminal Iput2 of the sampling circuit 100, and the first terminal T4a of the sensing transistor is coupled to the first input terminal Iput1.
  • the pixel driving circuit 200 further includes a scan transistor T2, a light emission control transistor T3, and a capacitor C.
  • the scanning transistor T2 is turned on under the control of the scanning signal Gate, and transmits the data signal Data to the control electrode T1c of the driving transistor. device EL, so that the light emitting device EL emits light.
  • the symbol Gate can represent both the scanning signal terminal and the scanning signal
  • the symbol Data can represent the data signal terminal, and can also represent the data signal
  • the symbol EM can represent the light emission control signal terminal, may also represent a light-emitting control signal
  • the symbol Sn may represent a sensing signal terminal, and may also represent a sensing signal.
  • sampling process of the pixel sampling circuit 30 is divided into a display stage and an acquisition stage, wherein the display stage includes a data writing stage D1 and a light emitting stage D2, and the acquisition stage includes a first stage S1, a second stage S2 and a third stage. Stage S3.
  • Figure 10A and Figure 10B show the signal transmission diagram of the sampling circuit at different stages, wherein Figure 10A is the signal transmission diagram of the pixel sampling circuit shown in Figure 8 in the sampling display stage, and Figure 10B is the pixel shown in Figure 8 Signal transfer diagram of the sampling circuit during the acquisition phase of sampling. Wherein, the direction of the arrow represents the transmission direction of the signal at this stage.
  • the pixel driving circuit 200 turns on the scanning transistor T2 in response to the scanning signal Gate, so that the data signal Data is transmitted to the control electrode T1c of the driving transistor.
  • the driving transistor T1 controls the magnitude of the driving current Id flowing through the driving transistor T1 according to the voltage of the control electrode T1c.
  • the pixel driving circuit 200 turns on the light emitting control transistor T3 in response to the light emitting control signal EM, so that the driving current Id flows through the light emitting device EL, and the light emitting device EL emits light.
  • the voltage of the second pole T1b of the driving transistor ie, the first voltage V1
  • the first voltage V1 is read by the first voltage follower 111 of the first voltage acquisition sub-circuit 110 and stored in the first capacitor C1 .
  • the pixel driving circuit 200 turns on the scanning transistor T2 again in response to the scanning signal Gate, so that the data signal Data is transmitted to the control electrode T1c of the driving transistor again. It should be noted that in the first stage S1 of the acquisition stage, the data signal transmitted by the data signal terminal Data is the same as the data signal transmitted by the data writing stage D1.
  • the pixel circuit turns on the sensing transistor T4 in response to the sensing signal Sn.
  • the second switching device SW2 of the first voltage acquisition sub-circuit 110, the first switching device SW1 of the current integration sub-circuit 120, and the third switching device SW3 of the storage sub-circuit 134 respectively respond to the first control signal, the integration control signal and The third control signal is closed, so that the first voltage V1 stored in the first capacitor C1 is transmitted to the storage sub-circuit 134 through the current integration sub-circuit 120, and stored in the second capacitor C2.
  • the sensing transistor T4 is continuously turned on, so that the driving current Id flowing through the first pole T1a to the second pole T1b of the driving transistor is transmitted to the current integration sub-circuit 120, and since the first switching device SW1 is continuously closed
  • the first voltage V1 stored in the first capacitor C1 can also be transmitted to the current integration sub-circuit 120, so that the current integration sub-circuit 120 generates and outputs the second voltage V2 according to the integration of the first voltage V1 and the driving current Id with respect to time.
  • the third switching device SW3 of the storage sub-circuit 134 is turned off, and the fourth switching device SW is closed in response to the fourth control signal, so that the second voltage V2 output by the current integration sub-circuit 120 is transmitted to the storage sub-circuit 134 and stored in the third capacitor C3.
  • a display device generally includes a coupled analog-to-digital converter and a processor.
  • the analog-to-digital converter is coupled to the sampling circuit and configured to receive the third voltage V3 output by the sampling circuit.
  • the third voltage V3 can be converted into a digital signal through the analog-to-digital converter, and the converted digital signal is further transmitted to the processor for processing, and then the magnitude of the driving current Id' in the pixel driving circuit can be obtained.
  • the embodiment of the present disclosure can output the third voltage V3 through the pixel sampling circuit, and the third voltage V3 is a linear function of the driving current in the pixel driving circuit, therefore, the third voltage V3 collected by the pixel sampling circuit can be further used as The basis for calculating the compensation voltage of the pixel driving circuit.
  • the processor calculates the driving current Id' according to the third voltage V3, and then calculates the compensation voltage through the driving current Id'.
  • the pixel driving circuit 200 further includes a voltage terminal ELVDD, wherein the pixel driving circuit 200 is further configured to transmit the voltage of the voltage terminal ELVDD to the third input terminal Iput3 of the sampling circuit 100 .
  • the sampling circuit 100 reads the voltage of the voltage terminal ELVDD (that is, the fourth voltage V4 ) through the fourth voltage follower 141 , and stores the read fourth voltage V4 in the fourth capacitor C4 .
  • the sixth switching device SW6 is turned on during the display phase in response to the sixth control signal to output the fourth voltage V4 during the display phase.
  • the fourth voltage V4 output by the sampling circuit 100 is the real voltage of the first electrode T1a of the driving transistor in the pixel driving circuit 200 in the display stage, and the fourth voltage V4 can also be further converted into a digital signal by an analog-to-digital converter, and transmitted to The processor of the display device is used as a basis for calculating the compensation voltage, thereby improving the accuracy of compensation voltage calculation.
  • the display area AA can be divided into multiple blocks (also referred to as sub-areas) B, and one block B can include multiple sub-pixels.
  • Sub-pixels in a block B can share one or several sampling circuits 100 (or sub-circuits in the sampling circuit), for example, referring to FIG.
  • the first voltage acquisition sub-circuit 110 is coupled, and the first voltage acquisition sub-circuit 110 is configured to acquire a first voltage V1 for the pixel driving circuit 200 of at least one sub-pixel coupled to each other, and the acquired first voltage V1 will be used as the reference voltage of all the current integration sub-circuits 120 coupled to the sub-pixels in the block B, that is, all the current integration sub-circuits 120 coupled to the sub-pixels in the block B use the first voltage collected above According to V1, the second voltage V2 is output; as another example, a column of sub-pixels in a block B is coupled to a current integration sub-circuit 120, and the current integration sub-circuit 120 is configured to collect The drive current Id, and output the second voltage V2 according to the collected drive current Id.
  • the pixel driving circuit 200 of only one sub-pixel is coupled to the first voltage acquisition sub-circuit 110 , and a column of sub-pixels in the block B shares one current integration sub-circuit 120 .
  • a current integration sub-circuit 120 can sequentially output multiple second voltages V2, wherein each second voltage V2 corresponds to a voltage collected from the pixel driving circuit 200. electric signal.
  • multiple current integration sub-circuits 120 output multiple second voltages V2 at the same time, for example, the multiple second voltages V2 can be sequentially transmitted to the modulus through the control of the multiplex switch MUX processing in the conversion unit.
  • a block B may include only one second voltage acquisition sub-circuit 140 , and the second voltage acquisition sub-circuit 140 only collects the fourth voltage V4 for one pixel driving circuit 200 in the block B. For the entire display device, a plurality of fourth voltages V4 will be collected, and the processor may further calculate an average value of the received plurality of fourth voltages V4 as a basis for calculating the subsequent compensation voltage.
  • the number of sampling circuits in the display device can be greatly reduced, and further It is beneficial to the small size design of the display device.
  • Embodiments of the present disclosure also provide a driving method of a sampling circuit, referring to FIG. 12 , the driving method includes:
  • Step S1 the first voltage collection sub-circuit collects the first voltage at the first input terminal, and transmits the first voltage to the current integration sub-circuit.
  • the first voltage collection sub-circuit collects and stores the first voltage during the display phase, and transmits the first voltage to the current integration sub-circuit during the first phase of the collection phase.
  • Step S2 the current integration sub-circuit generates and outputs a second voltage according to the first voltage and the time integral of the driving current transmitted from the second input terminal to the current integration sub-circuit; and, in response to the integral control signal, outputs the first Voltage.
  • the current integration sub-circuit outputs the received first voltage in the first acquisition phase, and generates and outputs the second voltage according to the integration of the first voltage and the driving current with respect to time in the second acquisition phase.
  • the driving method also includes:
  • Step S3 The difference subcircuit calculates the difference between the first voltage and the second voltage to obtain the third voltage.
  • the difference subcircuit calculates the difference between the first voltage and the second voltage in the third stage of acquisition to obtain a third voltage, and outputs the third voltage.
  • the driving method may also include:
  • a processor is used to calculate the driving current according to the converted first voltage and the second voltage.
  • the driving method may also include:
  • a processor is used to calculate the driving current according to the converted third voltage.
  • the driving method further includes: the second voltage collection sub-circuit collects and outputs the fourth voltage provided by the third input terminal.
  • the second voltage collection sub-circuit collects and outputs the fourth voltage during the display phase.
  • Each step in the above driving method of the sampling circuit can be realized by referring to the description of each sub-circuit in the sampling circuit, and will not be repeated here.
  • the effect achieved by the driving method of the above sampling circuit is the same as the effect achieved by the sampling circuit, and will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electronic Switches (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种采样电路，包括：第一输入端、第二输入端、第一电压采集子电路和电流积分子电路。其中，第一电压采集子电路与第一输入端以及电流积分子电路耦接，被配置为采集第一输入端的第一电压，并将第一电压传输至电流积分子电路。电流积分子电路还与第二输入端耦接，被配置为根据第一电压和第二输入端传输至电流积分子电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。

Description

采样电路及驱动方法、像素采样电路、显示装置
本申请要求于2021年5月10日提交的、申请号为202110506648.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种采样电路及驱动方法、像素采样电路、显示装置。
背景技术
自发光显示装置例如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有自发光、视角广、对比度高、功耗低、色彩还原度好、反应灵敏以及广视角等优点，具有广阔的发展前景。
发明内容
第一方面，提供一种采样电路，包括：第一输入端、第二输入端、第一电压采集子电路和电流积分子电路。
其中，所述第一电压采集子电路与所述第一输入端以及所述电流积分子电路耦接，被配置为采集所述第一输入端的第一电压，并将所述第一电压传输至所述电流积分子电路。所述电流积分子电路还与所述第二输入端耦接，被配置为根据所述第一电压和所述第二输入端传输至所述电流积分子电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。
在一些实施例中，所述第二输入端被配置为与所述第一输入端耦接。
在一些实施例中，所述第一电压采集子电路包括第一电压跟随器，所述第一电压跟随器的输入端与所述第一输入端耦接；和/或，所述电流积分子电路包括积分器和第一开关器件，所述积分器包括：正相输入端、反相输入端，所述积分器的正相输入端与所述第一电压采集子电路耦接，所述积分器的反相输入端与所述第二输入端耦接。第一开关器件并联在所述积分器的正相输入端与所述积分器的反相输入端之间，被配置为响应于所述积分控制信号闭合。
在一些实施例中，所述第一电压采集子电路还包括：第一电容器和第二开关器件。所述第一电容器的第一极板与所述第一电压跟随器的输出端耦接，所述第一电容器的第二极板接地；所述第二开关器件耦接在所述第一电容器的第一极板与所述电流积分子电路之间。
在一些实施例中，采样电路还包括求差子电路，所述求差子电路与所述 电流积分子电路耦接，被配置为求取所述第一电压和所述第二电压之差，得到第三电压。
在一些实施例中，所述求差子电路包括：减法器、第二电压跟随器和第三电压跟随器。所述减法器包括正相输入端、反相输入端和输出端；所述第二电压跟随器的输入端与所述电流积分子电路耦接，所述第二电压跟随器的输出端与所述减法器的正相输入端耦接；所述第三电压跟随器的输入端与所述电流积分子电路耦接，所述第三电压跟随器的输出端与所述减法器的反相输入端耦接。
在一些实施例中，所述电流积分子电路包括一个电压输出端，所述电流积分子电路被配置为通过所述电压输出端输出所述第一电压和所述第二电压；所述求差子电路还包括存储子电路，所述存储子路与所述电流积分子电路的电压输出端耦接，被配置为响应于第三控制信号，存储接收到的所述第一电压，响应于第四控制信号，存储所述第二电压。
在一些实施例中，所述存储子电路包括：第二电容器、第三电容器、第三开关器件和第四开关器件。所述第二电容器的第一极板与所述电压输出端耦接，所述第二电容器的第二极板接地；所述第三电容器的第一极板与所述电压输出端耦接，所述第三电容器的第二极板接地；所述第三开关器件耦接在所述电压输出端与所述第二电容器的第一极板之间；所述第四开关器件耦接在所述电压输出端与所述第三电容器的第一极板之间。
在一些实施例中，采样电路还包括：采样输出端和第五开关器件。所述第五开关器件耦接在所述求差子电路与所述采样输出端之间。
在一些实施例中，采样电路还包括：第二电压采集子电路，所述第二电压采集子电路与第三输入端耦接，被配置为采集并输出所述第三输入端提供的第四电压。
在一些实施例中，所述第二电压采集子电路包括：第四电压跟随器和第四电容器。所述第四电压跟随器的输入端与所述第三输入端耦接；所述第四电容器的第一极板与所述第四电压跟随器的输出端耦接，所述第四电容器的第二极板接地。
在一些实施例中，采样电路还包括采样输出端。所述第三电压采集子电路还包括第六开关器件，所述第六开关器件耦接在所述第四电容器的第一极板与所述采样输出端之间。
第二方面，提供一种像素采样电路，所述像素采样电路包括：上述任一实施例所述的采样电路和像素驱动电路。所述像素驱动电路包括驱动晶体管， 所述驱动晶体管包括第一级、第二极和控制极。
其中，所述像素驱动电路被配置为将流经所述驱动晶体管的第一级和第二极的驱动电流传输到所述采样电路的第二输入端，以及将所述驱动晶体管的第二极的电压传输到所述采样电路的第一输入端。
在一些实施例中，所述像素驱动电路还包括感测晶体管，所述感测晶体管的控制极与扫描信号端耦接，所述感测晶体管的第一极与所述第一输入端耦接，所述感测晶体管的第二极与所述第二输入端耦接。
在一些实施例中，所述像素驱动电路还包括电压端，其中，所述像素驱动电路还被配置为将所述电压端的电压传输到所述采样电路的所述第三输入端。
第三方面，提供一种显示装置，所述显示装置包括上述任一实施例所述的采样电路，或者，所述显示装置包括上述任一实施例所述的像素采样电路。
在一些实施例中，显示装置还包括处理器，所述处理器与所述采样电路或者所述像素采样电路耦接，被配置为根据所述第一电压和第二电压的差值计算驱动电流。
第四方面，提供一种采样电路的驱动方法，所述驱动方法包括：
第一电压采集子电路采集第一输入端的第一电压，并将所述第一电压传输至电流积分子电路；所述电流积分子电路根据所述第一电压和第二输入端传输至所述电流积分子电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。
在一些实施例中，所述驱动方法还包括：求差子电路求取第一电压和第二电压之差，得到并输出第三电压。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开的一些实施例提供的一种采样电路的结构图；
图2为本公开的一些实施例提供的另一种采样电路的电路图；
图3为图2所示的采样电路的信号传输图；
图4为本公开的一些实施例提供的又一种采样电路的结构图；
图5为本公开的一些实施例提供的又一种采样电路的电路图；
图6为本公开的一些实施例提供的显示面板的俯视图；
图7为本公开的一些实施例提供的一种像素采样电路的结构图；
图8为本公开的一些实施例提供的另一种像素采样电路的电路图；
图9为图8所示的像素采样电路的时序控制图；
图10A为图8所示的像素采样电路在显示阶段的信号传输图；
图10B为图8所示的像素采样电路在采集阶段的信号传输图；
图11为本公开的一些实施例提供的又一种像素采样电路的结构图；
图12为本公开的一些实施例提供的采样电路的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以 上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
OLED显示面板中子像素的发光强度与流经发光器件的驱动电流成正比，而在子像素中，流经发光器件的驱动电流由子像素的像素驱动电路中的驱动晶体管控制。在驱动晶体管的制程工艺影响下，OLED显示面板中各个驱动晶体管的阈值电压Vth存在差异，使得在对每个驱动晶体管的栅极写入相等的数据信号(例如初始电压)时，流经各个驱动晶体管的驱动电流存在差异，从而导致OLED显示面板中的显示不均问题。
在相关技术中，采用电学外补偿方法对驱动晶体管的阈值电压进行补偿，所述电学外补偿方法包括使用电压采样电路对发光器件的阳极电压进行采样，并根据所采样到的阳极电压计算补偿电压。然而，由于采样电路为模拟电路，存在共模噪声，使得采样电路输出的电压中包括共模噪声值，即采样电路输出的电压不是准确的阳极电压。
为了解决上述问题，本公开的实施例提供一种采样电路，用于精确地采集像素驱动电路中的电信号。
采样电路是指能够将目标电路中的电信号采集出来并将所采集到的电信号输出的电路。其中，目标电路是指待被采集其中电信号的电路，示例性地，当采样电路应用于显示装置时，目标电路可以是显示面板中的像素驱动电路。采样电路能够采集的电信号包括电压、电流等，示例性地，采样电路可以与目标电路中的待采节点耦接，被配置为采集所述待采节点的电信号，例如，采样电路被配置为采集所述待采节点的电压，或者被配置为采集流经所述待采节点的电流。
采样电路可以包括多个电子元件以及多条将电子元件耦接的导线。示例性地，采样电路中的电子元件可以包括运算放大器、电容器、开关、电阻等。其中，运算放大器可以实现特定的运算功能，例如，运算放大器的反相端与输出端耦接形成电压跟随器，以将正相端输入的电压通过输出端输出。此外，运算放大器还可以与其他电子元件组合实现其他的运算功能，例如，运算放大器与电容器组合构成积分器，运算放大器与电阻组合构成减法器等。
图1示出了本公开的一些实施例提供的采样电路。其中，采样电路100包括：第一输入端Iput1、第二输入端Iput2、第一电压采集子电路110和电流积分子电路120。
其中，采样电路100的输入端与目标电路中的待采节点耦接，被配置为接收所述待采节点的电信号。采样电路包括至少一个输入端，每个输入端可以分别与目标电路中的不同节点耦接，并且，每个输入端所接收的电信号可以不相同。示例性地，参见图1，采样电路100包括第一输入端Iput1和第二输入端Iput2，第一输入端Iput1被配置为接收目标电路中的电压信号，例如，第一输入端Iput1与目标电路中的第一待采节点耦接，被配置为接收第一待采节点的第一电压V1，第二输入端Iput2被配置为接收目标电路中的电流信号，例如，第二输入端Iput2与目标电路中的第二待采节点耦接，被配置为接收流经第二待采节点的驱动电流Id。
第一电压采集子电路110与第一输入端Iput1以及电流积分子电路120耦接，被配置为采集第一输入端Iput1的第一电压V1，并将第一电压V1传输至电流积分子电路120。
示例性地，第一电压采集子电路110可以将第一输入端Iput1的第一电压V1读取出来，并将所读取出来的第一电压V1传输至电流积分子电路120。
电流积分子电路120还与第二输入端Iput2耦接，被配置为根据第一电压V1和第二输入端Iput2传输至电流积分子电路120的驱动电流Id对时间的积分，生成并输出第二电压V2；以及，响应于积分控制信号，输出所第一电压 V1。
其中，电流积分子电路120可以将所接收的电信号进行积分，示例性地，电流积分子电路120将接收到的驱动电流Id对时间积分，生成电荷量。电流积分子电路120根据所生成的电荷量以及第一电压V1还可以输出第二电压V2。
示例性地，电流积分子电路120可以与积分控制信号端耦接，被配置为接收积分控制信号端Inc的积分控制信号。
其中，积分控制信号可以对电流积分子电路120的输出进行控制，示例性地，积分控制信号是在特定的时间段内输出的信号，例如，电流积分子电路120接收到第一电压采集子电路110传输的第一电压V1，在积分控制信号的输出信号的时间段内，电流积分子电路120将接收到的第一电压V1直接输出；在积分控制信号未输出信号的时间段内，电流积分子电路120可以根据第一电压V1和第二输入端Iput2传输至电流积分子电路120的驱动电流Id对时间的积分，生成并输出第二电压V2。
又示例性地，积分控制信号是有效信号和无效信号交替控制的信号，在积分控制信号输出有效信号的情况下，电流积分子电路120将接收到的第一电压V1直接输出；在积分控制信号输出无效信号的情况下，电流积分子电路120根据第一电压V1和第二输入端Iput2传输至电流积分子电路120的驱动电流Id对时间的积分，生成并输出第二电压V2。
此外，电流积分子电路120还可以包括一个电压输出端Oput_V，被配置为将第一电压V1和第二电压V2通过电压输出端Oput_V输出。
参见图2，本公开的一些实施例提供了一种采样电路，该采样电路可以包括：第一电压跟随器111、积分器121以及第一开关器件SW1。该采样电路可以作为图1提供的采样电路的一种具体实现方式，也可以不限于实现图1中各子电路所能实现的功能。
其中，第一电压跟随器的输入端111a与第一输入端Iput1耦接。
电压跟随器包括一个运算放大器OP，该运算放大器OP的反相端与输出端耦接，使得该运算放大器OP的输出端输出的信号与正相端输入的信号相同，例如该运算放大器OP的正相端输入第一电压V1，那么，该运算放大器OP的输出端也输出第一电压V1。当运算放大器OP的反相端与输出端耦接形成电压跟随器时，电压跟随器的输入端111a为运算放大器的正相端，电压跟随器的输出端111b为运算放大器OP的输出端。
积分器121包括：正相输入端121a、反相输入端121b和输出端121c，积 分器的正相输入端121a与第一电压采集子电路110耦接，积分器的反相输入端121b与第二输入端Iput2耦接。
其中，积分器121包括一个运算放大器OP和一个电容器Cf，其中，电容器Cf的一个极板与运算放大器OP的反相端耦接，电容器Cf的另一个极板与运算放大器OP的输出端耦接，当运算放大器OP与电容器Cf形成积分器121时，积分器的正相输入端121a为运算放大器OP的正相端，积分器的反相输入端121b为运算放大器的反相端，积分器的输出端121c为运算放大器OP的输出端。
第一开关器件SW1并联在积分器的正相输入端121a与积分器的反相输入端121b之间，被配置为响应于积分控制信号闭合。
第一开关器件SW1受控于积分控制信号，示例性地，第一开关器件SW1可以是一个常开或者常闭的开关，例如，第一开关器件SW1是一个常开的开关，在未接收到积分控制信号时，第一开关器件SW1处于断开状态，当接收到积分控制信号时，第一开关器件SW1闭合。又示例性地，第一开关器件SW1是受时序控制的开关器件。例如，第一开关器件SW1可以是晶体管，也可以是其他开关器件。第一开关器件SW1受有效信号和无效信号的控制，在对第一开关器件SW1进行控制的积分控制信号输出有效信号的情况下，第一开关器件SW1闭合，形成通路，在对第一开关器件SW1进行控制的积分控制信号输出无效信号的情况下，第一开关器件SW1断开，切断通路。
需要说明的是，本公开的实施例均以开关器件(包括第一开关器件SW1以及后续所要描述的开关器件SW2～SW6)为响应于相应控制信号才闭合的常开型开关为例进行说明。但是，本公开的实施例对开关器件的类型并不做限制，例如，本公开的实施例中所述的开关器件可以是仅响应于相应控制信号才断开的常闭开关，或者，本公开的实施例中所述的开关器件是受有效信号和无效信号交替控制的开关，在有效信号的控制下，开关闭合，在无效信号的控制下，开关断开。
示例性地，在采样电路100中，第一电压采集子电路110包括第一电压跟随器111，电流积分子电路120包括积分器121和第一开关器件SW1。
图3为图2所示的采样电路在不同阶段的信号传输图，其中，图3中的(a)为图2所示的采样电路处于采集阶段的第一阶段的信号传输图，图3中的(b)为图2所示的采样电路处于采集阶段的第二阶段的信号传输图。
下面结合图3所示的信号传输图对采样电路100的驱动原理进行说明。在采集阶段的第一阶段，参见图3中的(a)，第一输入端Iput1接收目标电 路中的第一电压V1，并将第一电压V1通过第一电压跟随器111传输至积分器121中的运算放大器OP的正相端。此时，第一开关器件SW1响应于积分控制信号闭合，使得积分器121中的运算放大器OP的反相端与输出端耦接形成电压跟随器，将传入运算放大器OP的正相端的第一电压V1通过运算放大器OP的反相端输出，进而使电压输出端Oput_V输出第一电压V1。
在采集阶段的第二阶段，参见图3中的(b)，第一开关器件SW1断开，积分器121工作，积分器的正相输入端121a输入第一电压V1，积分器的反相输入端121b输入第二输入端Iput接收的驱动电流Id，积分器121的输出端根据积分器的运算公式
Figure PCTCN2021131519-appb-000001
输出第二电压V2，其中,T为电容器的充电时间，即第一开关器件SW1断开至积分器121输出稳定的第二电压V2的时间。考虑到目标电路中待采集的驱动电流Id为恒定电流，因此，电压输出端Oput_V输出的第二电压V2为：V2＝V1-Id*T/Cf。
采样电路100在采集阶段的第一阶段和第二阶段分别输出第一电压V1和第二电压V2之后，可以通过处理器进一步计算第一电压V1与第二电压V2之差，即V1-V2＝Id*T/Cf，进而求解出驱动电流Id’的值。其中，根据第一电压V1和第二电压V2求解出的驱动电流Id’的值即为采样电路100所采集到的目标电路中的驱动电流Id。
示例性地，参见图1，采样电路100的电压输出端Oput_V可以与模数转换器耦接，被配置为将接收到的模拟信号转化为数字信号，例如，电压输出端Oput_V在采集阶段的第一阶段和第二阶段分别输出第一电压V1和第二电压V2，由于采样电路100是模拟电路，因此输出的第一电压V1和第二电压V2均为模拟信号。第一电压V1和第二电压V2相继被模数转换器接收，使得第一电压V1和第二电压V2被转换为数字信号，例如，模数转换器还与处理器耦接，上述转换后的数字信号可以被处理器直接使用，并通过处理器计算驱动电流Id’。
在上述实施例中，采样电路分别输出第一电压V1和第二电压V2，其中，第一电压V1和第二电压V2均包括由采样电路引起的共模噪声，在对第一电压V1和第二电压V2求差后，可以将第一电压V1和第二电压V2中所包括的共模噪声值抵消。此外，第一电压V1与第二电压V2的差值为第二输入端接收的驱动电流的函数，因此，通过采样电路，可以有效地将目标电路中的驱 动电流提取出来，并且，由于第一电压V1与第二电压V2的差值不包括共模噪声，那么提取出来的驱动电流也滤除了共模噪声，从而保证了提取驱动电流的准确性。
本公开的实施例通过采样电路分别输出第一电压V1和第二电压V2，这样就有利于后续对第一电压V1和第二电压V2求差，将第一电压V1和第二电压V2中所包括的共模噪声值抵消。此外，第一电压V1和第二电压V2还可以作为目标电路中被采集的电信号的计算依据，以将待采集的电信号从目标电路中准确地采集出来，保证了采样的准确性。
在采样电路100中，第二输入端Iput2与电流积分子电路120之间通常需要接入较长的导线，以将驱动电流Id传输至电流积分子电路120，使得第二输入端Iput2与电流积分子电路120之间存在一个寄生电容Cs。
在一些实施例中，第二输入端Iput2被配置为与第一输入端Iput1耦接。示例性地，采样电路100的第二输入端Iput2与第一输入端Iput1耦接，在采集阶段的第一阶段，第一输入端Iput1接收目标电路中一个待采节点的第一电压V1，第一电压V1可以通过第二电压V2传输至电流积分子电路120；在采样的第二阶段，第一输入端Iput1接收上述待采节点的驱动电流Id，驱动电流Id可以通过第二输入端Iput2传输至电流积分子电路120。示例性地，第二输入端Iput2与第一输入端Iput1可以通过一个晶体管耦接，在上述晶体管可以控制第一输入端Iput1接收的电信号向第二输入端Iput2的传输。
在第二输入端Iput2与第一输入端Iput1耦接的情况下，采样电路100仅与目标电路中的一个待采节点耦接，这样，采样电路100可以既采集到这一待采节点的电压，又可以采集到流经这一节点的驱动电流。
在一些实施例中，参见图2，第一电压采集子电路120还包括：第一电容器C1和第二开关器件SW2。
第一电容器C1的第一极板与第一电压跟随器的输出端111b耦接，第一电容器C1的第二极板接地；第二开关器件SW2耦接在第一电容器C1的第一极板与电流积分子电路120之间。
其中，第一电容器C1可以用来存储第一电压跟随器111输出的信号，第二开关器件SW2可以用来控制由第一电压跟随器111输出的电信号向电流积分子电路120的传输，例如，第一电容器C1将来自第一电压跟随器111的第一电压V1存储起来，并在第二开关器件SW2的控制下将第一电压V1传输至电流积分子电路120。第二开关器件SW2可以根据采样电路100的需要在适当的时间闭合，以在特定的时间将第一电容器C1中存储的电信号传输至电 流积分子电路120。
在一些实施例中，参见图4，采样电路100还包括求差子电路130。求差子电路130与电流积分子电路120耦接，被配置为求取第一电压V1和第二电压V2之差，得到第三电压V3。
示例性地，求差子电路130包括两个输入端：第一求差输入端和第二求差输入端，其中，第一求差输入端和第二求差输入端分别与一个电流积分子电路120耦接，并且第一求差输入端接收第一电压V1，第二求差输入端接收第二电压V2。
图5为本公开的一些实施例提供了一种采样电路，该采样电路可以作为图4提供的采样电路的一种具体实现方式，也可以不限于实现图4中各子电路所能实现的功能。其中，第一电压采集子电路110、电流积分子电路120中所包括的电子元件及耦接关系可以与图1或图2所示的采样电路相同，不再赘述。
参见图5，求差子电路130包括：减法器131、第二电压跟随器132、第三电压跟随器133。
减法器131包括正相输入端131a、反相输入端131b和输出端131c。其中，减法器131包括一个运算放大器OP和4个电阻R1、R2、R3和R4，减法器的输出可以根据减法运算公式得到，例如，减法器的反相输入端提供的电压为Vi1，减法器的正相输入端提供的电压为Vi2，减法器的输出端输出的电压
Figure PCTCN2021131519-appb-000002
当R1＝R2＝R3＝R4时，Vo＝Vi2-Vi1，即减法器的输出电压等于正相输入端提供的电压与反相输入端提供的电压之差。
第二电压跟随器的输入端132a与电流积分子电路120耦接，第二电压跟随器的输出端132b与减法器的正相输入端131a耦接。
第三电压跟随器的输入端133a与电流积分子电路120耦接，第三电压跟随器的输出端133b与减法器的反相输入端131b耦接。
示例性地，求差子电路130中第二电压跟随器的输入端132a接收一个电流积分子电路120传输的第一电压V1，第三电压跟随器的输入端133a接收另一个电流积分子电路120传输的第二电压V2，第一电压V1和第二电压V2分别通过第二电压跟随器132和第三电压跟随器133传输至减法器131的正相输入端131a和反相输入端131b。根据减法器的计算公式，减法器131输出 第三电压V3＝V1-V2，其中，第三电压V3可以通过减法器的输出端131c输出。
在采样电路100包括求差子电路130的情况下，采样电路直接输出第三电压V3，其中，第三电压V3为第一电压V1与第二电压V2的差值，也就是说，第三电压V3是不包括采样电路引起的共模噪声，进而使得采样电路输出的电信号(第三电压)更加准确。
此外，参见图4，求差子电路130可以与模数转换单元以及处理器耦接。求差子电路130输出第三电压V3通过模数转换器转换为数字信号后，直接传输至处理器进行后续处理，而不需要处理器对第一电压V1和第二电压V2做求差运算，进而可以降低处理器的功耗。
在一些实施例中，参见图5，电流积分子电路120包括一个电压输出端Oput_V，电流积分子电路120被配置为通过电压输出端Oput_V输出第一电压V1和第二电压V2。
求差子电路130还包括存储子电路134，存储子电路134与电流积分子电路120的电压输出端Oput_V耦接，被配置为响应于第三控制信号，存储接收到的第一电压V1，响应于第四控制信号，存储第二电压V2。
示例性地，电流积分子电路120通过电压输出端Oput_V在不同时刻分别输出第一电压V1和第二电压V2，并且在电流积分子电路120输出第一电压V1的同时存储子电路134将电流积分子电路120输出的第一电压V2存储起来，在电流积分子电路120输出第二电压V2的同时存储子电路134将电流积分子电路120输出的第二电压V2存储起来。
在一些实施例中，参见图5，存储子电路134包括第二电容器C2、第三电容器C3、第三开关器件SW3和第四开关器件SW4。
其中，第二电容器C2的第一极板与电压输出端Oput_V耦接，第二电容器C2的第二极板接地。
第三电容器C3的第一极板与电压输出端Oput_V耦接，第三电容器C3的第二极板接地。
第三开关器件SW3耦接在电压输出端Oput_V与第二电容器C2的第一极板之间。
第四开关器件SW4耦接在电压输出端Oput_V与第三电容器C3的第一极板之间。
示例性地，电压输出端Oput_V输出的第一电压V1可以存储在第二电容器C2中，电压输出端Oput_V输出的第二电压V2可以存储在第三电容器C3 中。
例如，在采集阶段的第一阶段，第三开关器件SW3响应于第三控制信号闭合，存储子电路134将第一电压V1传输并存储在第二电容器C2中；在采样的第二阶段，第四开关器件SW4响应于第四控制信号闭合，存储子电路134将第二电压V2传输并存储在第三电容器C3中。
在电流积分子电路120仅包括一个电压输出端Oput_V，且求差子电路130包括存储子电路134的情况下，通过时序控制，可以将第一电压V1和第二电压V2通过电压输出端Oput_V分时输出并存储，存储起来的第一电压V1和第二电压V2同时传输至减法器进行求差运算，得到第三电压V3，避免了一个减法器需要同时耦接两个电流积分子电路120的情况，进而减小采样电路100的体积。
在一些实施例中，参见图4和图5，采样电路100还包括采样输出端Oput_S和第五开关器件SW5，其中，第五开关器件SW5耦接在求差子电路130与采样输出端Oput_S之间。
在采样电路100包括第五开关器件SW5的情况下，第五开关器件SW5可以对求差子电路130输出的第三电压V3向采样输出端Oput_S的传输进行控制，以在需要的时刻通过采样输出端Oput_S输出第三电压V3。
在一些实施例中，采样电路100还包括第二电压采集子电路140，第二电压采集子电路140与第三输入端Iput3耦接，被配置为采集并输出第三输入端Iput3提供的第四电压V4。
示例性地，第三输入端Iput3被配置为接收目标电路中的电压信号，例如，第三输入端Iput3与目标电路中的第三待采节点耦接，被配置为接收第三待采节点的第四电压V4。其中，本公开的实施例对第三输入端Iput3采集第四电压V4的时间不做限制，可以根据需要进行设计，例如，第三输入端Iput3采集第四电压V4的时间可以与第一输入端Iput1采集第一电压V1、第二输入端Iput2采集驱动电流Id的时间均不相同。
在一些实施例中，参见图5，第二电压采集子电路包括：第四电压跟随器141和第四电容C4。
其中，第四电压跟随器的输入端141a与第三输入端Iput3耦接。
第四电容器C4的第一极板与第四电压跟随器的输出端141b耦接，第四电容器C4的第二极板接地。
在一些实施例中，第三电压采集子电路140还包括第六开关器件SW6，第六开关器件SW6耦接在第四电容器C4的第一极板与采样输出端Oput_S之 间。其中，第六开关器件SW6被配置为控制第四电压V4向采样输出端Oput_S的传输。
例如，第三输入端Iput3接收的第四电压V4通过第四电压跟随器传输至第四电容器C4，第四电容器C4将接收到的第四电压V4存储起来，当第六开关器件SW6响应于第六控制信号闭合时，第四电容器C4中存储的第四电压V4可以通过采样输出端Oput_S输出。
本公开的实施例还提供一种显示装置。显示装置是指具有图像显示功能的产品，示例性地，可以是：显示器，电视，广告牌，数码相框，具有显示功能的激光打印机，电话，手机，个人数字助理(Personal Digital Assistant，PDA)，数码相机，便携式摄录机，取景器，监视器，导航仪，车辆，大面积墙壁、家电、信息查询设备(如电子政务、银行、医院、电力等部门的业务查询设备，监视器等。
显示装置包括显示面板20和采样电路100。示例性地，显示面板可以是OLED(Organic Light Emitting Diode，有机发光二极管)显示面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板、微LED(包括：miniLED或microLED)显示面板等。采样电路100可以是集成电路(integrated circuit，简称IC)，或者，采样电路100是包括若干电子元件的模拟电路。此外，显示装置还可以包括其他部件，例如，与显示面板耦接的印刷电路板(PCB)和柔性电路板(FPC)、对显示面板供电的电源系统等。
图6示出了本公开的一些实施例提供的显示面板20的俯视图。参见图6，该显示面板20具有显示区(Active Area，简称为AA)和位于显示区AA的至少一侧的周边区S，例如，周边区S可以围绕显示区AA一周设置。
显示面板包括：设置在AA区中的多个子像素P，每个子像素P均包括相耦接的一个像素驱动电路200和一个发光器件EL(例如OLED)。值得注意的是，图6仅示例性地示出了子像素P中的像素驱动电路200与发光器件EL的耦接关系，但是发光器件的尺寸不限于此，例如，发光器件EL的尺寸大小不一；像素驱动电路200与发光器件EL的位置也不限于此，例如，发光器件EL与相耦接的像素驱动电路200在显示面板的厚度方向上可以有重叠部分。
像素驱动电路的结构可以根据实际情况进行设计。示例性地，像素驱动电路由晶体管、电容器(Capacitance，简称C)等电子器件组成。例如，像素驱动电路可以包括三个晶体管(两个开关晶体管和一个驱动晶体管)和一个电容器，构成3T1C结构；当然，像素驱动电路还可以包括三个以上的晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容器，例如，像素驱动 电路可以包括一个电容器和四个晶体管，构成4T1C结构。
其中，晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(metal oxide semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
薄膜晶体管的控制极为栅极，该薄膜晶体管的第一极为源极和漏极中一者，该薄膜晶体管的第二极为源极和漏极中另一者。由于薄膜晶体管的源极和漏极在薄膜晶体管中能产生的作用相同，因此源极和漏极可以不作特别区分。在一种示例中，在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极为源极，第二极为漏极。在另一种示例中，在薄膜晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例中，对像素驱动电路的说明均以P型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，像素驱动电路中的一个或多个薄膜晶体管也可以采用N型晶体管，只需将选定类型的薄膜晶体管的各极参照本公开的实施例中的相应薄膜晶体管的各极相应连接，并且使相应的控制极供对应的高电平电压或低电平电压即可。
显示装置中的像素驱动电路200可以与采样电路100耦接构成像素采样电路30。在像素采样电路30中，采样电路100采样的目标电路为像素驱动电路200。示例性地，像素采样电路30中的像素驱动电路200位于显示面板中，而采样电路100可以位于与显示面板耦接的印刷电路板或柔性电路板上。
本公开的实施例以4T1C的像素驱动电路进行说明，其他类型的像素驱动电路，例如3T1C、7T1C的驱动方法可以参照本公开的实施例。
参见图7，像素驱动电路200包括驱动晶体管T1，驱动晶体管T1包括第一级T1a、第二极T1b和控制极T1c。其中，驱动晶体管的第二极T1b与采样电路100的第一输入端Iput1和第二输入端Iput2耦接，像素驱动电路200被配置为将流经驱动晶体管的第一级T1a和第二极T1b的驱动电流Id传输到采样电路100的第二输入端Iput2，示例性地，流经驱动晶体管的第一级T1a和第二极T1b的驱动电流Id通过第一输入端Iput1传输至第二输入端Iput2；以及将驱动晶体管的第二极T1b的电压传输到采样电路100的第一输入端Iput1。
在一些实施例中，像素驱动电路200还包括感测晶体管T4，其中，感测晶体管的控制极T4c与扫描信号Sn端耦接，被配置为在感测信号Sn的控制下打开，晶体管的第二极T4b与采样电路100的第二输入端Iput2耦接，感测晶体管的第一极T4a与第一输入端Iput1耦接。
此外，像素驱动电路200还包括扫描晶体管T2、发光控制晶体管T3、以 及电容C。示例性地，扫描晶体管T2在扫描信号Gate的控制下打开，将数据信号Data传输至驱动晶体管的控制极T1c，发光控制晶体管T3在发光控制信号EM的控制下打开，控制驱动电流Id流经发光器件EL，以使发光器件EL发光。
需要说明的是，在本公开实施例的说明中，符号Gate既可以表示扫描信号端，还可以表示扫描信号，符号Data可以表示数据信号端，还可以表示数据信号，符号EM可以表示发光控制信号端，还可以表示发光控制信号，符号Sn可以表示感测信号端，还可以表示感测信号。
下面结合图9中的时序对图8所示的像素采样电路30的采样原理进行说明。需要说明的是，像素采样电路30的采样过程分为显示阶段和采集阶段，其中，显示阶段包括数据写入阶段D1和发光阶段D2，采集阶段包括第一阶段S1、第二阶段S2以及第三阶段S3。
图10A和图10B示出了采样电路在不同阶段的信号传输图，其中，图10A为图8所示的像素采样电路在采样的显示阶段的信号传输图，图10B为图8所示的像素采样电路在采样的采集阶段的信号传输图。其中，箭头的指向代表该阶段下信号的传输方向。
参见图10A，在数据写入阶段D1，像素驱动电路200响应于扫描信号Gate，将扫描晶体管T2打开，使得数据信号Data传输至驱动晶体管的控制极T1c。驱动晶体管T1根据控制极T1c的电压控制流经驱动晶体管T1的驱动电流Id的大小。
在发光阶段D2，像素驱动电路200响应于发光控制信号EM，将发光控制晶体管T3打开，使得驱动电流Id流经发光器件EL，发光器件EL发出光。同时，驱动晶体管的第二极T1b电压(即第一电压V1)通过第一电压采集子电路110的第一电压跟随器111被读取出来并存储在第一电容器C1中。
此时，显示阶段完成，进入采集阶段。
参见图10B，在第一阶段S1，像素驱动电路200再次响应于扫描信号Gate，将扫描晶体管T2打开，使得数据信号Data再次传输至驱动晶体管的控制极T1c。需要注意的是，在采集阶段的第一阶段S1，数据信号端Data传输的数据信号与数据写入阶段D1传输的数据信号相同。像素电路响应于感测信号Sn，将感测晶体管T4打开。同时，第一电压采集子电路110的第二开关器件SW2、电流积分子电路120的第一开关器件SW1以及存储子电路134的第三开关器件SW3分别响应于第一控制信号、积分控制信号和第三控制信号闭合，使得存储在第一电容器C1中的第一电压V1通过电流积分子电路120传输至 存储子电路134，并存储在第二电容器C2中。
在第二阶段S2，感测晶体管T4持续打开，使得流经驱动晶体管的第一极T1a至第二极T1b的驱动电流Id传输至电流积分子电路120，并且，由于第一开关器件SW1持续闭合，第一电容器C1中存储的第一电压V1也能够传输至电流积分子电路120，使得电流积分子电路120根据第一电压V1和驱动电流Id对时间的积分，生成并输出第二电压V2。同时，存储子电路134的第三开关器件SW3断开，第四开关器件SW响应于第四控制信号闭合，使得电流积分子电路120输出的第二电压V2传输至存储子电路134，并存储在第三电容器C3中。
在第三阶段S3，求差子电路130中的第二电压跟随器132与第三电压跟随器133分别从第二电容器C2和第三电容器C3中读取第一电压V1和第二电压V2，并通过减法器131求差得到第三电压V3，其中，第三电压V3＝Id*T/Cf，即第三电压V3为驱动电流Id的函数。
显示装置通常包括相耦接的模数转换器和处理器。其中，模数转换器与采样电路耦接，被配置为接收采样电路输出的第三电压V3。第三电压V3通过模数转换器可以转换为数字信号，转化后的数字信号进一步传输至处理器处理，便可求出像素驱动电路中驱动电流Id’的大小。
本公开的实施例通过像素采样电路，可以输出第三电压V3，而第三电压V3为像素驱动电路中的驱动电流的线性函数，因此，通过像素采样电路采集到的第三电压V3可以进一步作为计算像素驱动电路的补偿电压的依据。示例性地，处理器根据第三电压V3计算驱动电流Id’，再通过驱动电流Id’计算补偿电压。
在一些实施例中，参见图7，像素驱动电路200还包括电压端ELVDD，其中，像素驱动电路200还被配置为将电压端ELVDD的电压传输到采样电路100的第三输入端Iput3。
示例性地，采样电路100将电压端ELVDD的电压(即第四电压V4)通过第四电压跟随器141读取出来，并将读取到的第四电压V4存储在第四电容器C4中。此外，第六开关器件SW6响应于第六控制信号在显示阶段闭合，以在显示阶段将第四电压V4输出。
采样电路100输出的第四电压V4为像素驱动电路200中的驱动晶体管的第一极T1a在显示阶段的真实电压，第四电压V4也可以进一步通过模数转换器转换为数字信号，并且传输至显示装置的处理器作为计算补偿电压的依据，从而提高补偿电压计算的准确性。
在显示装置中，可以将显示区AA划分成多个块(也可以称为子区)B，一个块B中可以包括多个子像素。一个块B中的子像素可以共用一个或几个采样电路100(或采样电路中的子电路)，例如，参见图11，一个块B中的至少一个(例如，一个)像素驱动电路200与一个第一电压采集子电路110耦接，该第一电压采集子电路110被配置为对相耦接的至少一个子像素的像素驱动电路200采集第一电压V1，并且，该采集到的第一电压V1将用做该块B内子像素所耦接的所有电流积分子电路120的参考电压，也就是，该块B内子像素所耦接的所有电流积分子电路120均以上述采集到的第一电压V1为根据，输出第二电压V2；又如，一个块B内的一列子像素与一个电流积分子电路120耦接，该电流积分子电路120被配置为采集该列子像素的像素驱动电路200中的驱动电流Id，并根据所采集到的驱动电流Id输出第二电压V2。
示例性地，在一个块B中，仅有一个子像素的像素驱动电路200与第一电压采集子电路110耦接，并且块B中的一列子像素共用一个电流积分子电路120。通过对显示面板中级联的移位寄存器进行控制，可以使一个电流积分子电路120依次输出多个第二电压V2，其中，每个第二电压V2均对应一个从像素驱动电路200中采集的电信号。并且，对于同一排子像素来说，多个电流积分子电路120同时输出多个第二电压V2，例如，所述多个第二电压V2可以通过多路选择开关MUX的控制依次传输至模数转换单元中进行处理。
在一些实施例中，一个块B中还可以仅包括一个第二电压采集子电路140，所述一个第二电压采集子电路140仅对本块B中的一个像素驱动电路200采集第四电压V4。对于整个显示装置来说，将采集到多个第四电压V4，那么，处理器可以进一步将所接收到的多个第四电压V4求取平均值，作为后续补偿电压的计算依据。
通过对显示面板中的子像素分块，并且使一个块中的子像素共用一个或几个采样电路100(或采样电路中的子电路)，可以将显示装置中采样电路的数量大大减少，进而有利于显示装置的小尺寸化设计。
本公开的实施例还提供一种采样电路的驱动方法，参见图12，该驱动方法包括：
步骤S1：第一电压采集子电采集第一输入端的第一电压，并将第一电压传输至电流积分子电路。示例性地，第一电压采集子电在显示阶段采集并存储第一电压，在采集阶段的第一阶段，将第一电压传输至电流积分子电路。
步骤S2：电流积分子电路根据第一电压和第二输入端传输至电流积分子 电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。示例性地，电流积分子电路在采集阶段的第一阶段将接收的第一电压输出，在采集的第二阶段根据第一电压和驱动电流对时间的积分，生成并输出第二电压。
在一些实施例中，所述驱动方法还包括：
步骤S3：求差子电路求取第一电压和第二电压之差，得到第三电压。示例性地，求差子电路在采集的第三阶段求取第一电压和第二电压之差，得到第三电压，并将第三电压输出。
在一些实施例中，所述驱动方法还可以包括：
使用模数转换器将采样电路输出的第一电压、第二电压转换为数字信号；
使用处理器根据转换后的第一电压、第二电压计算驱动电流。
在一些实施例中，所述驱动方法还可以包括：
使用模数转换器将采样电路输出的第三电压转换为数字信号；
使用处理器根据转换后的第三电压计算驱动电流。
在一些实施例中，所述驱动方法还包括：第二电压采集子电路采集并输出第三输入端提供的第四电压。示例性地，第二电压采集子电路在显示阶段采集并输出第四电压。
上述采样电路的驱动方法中的各个步骤可以参考采样电路中各子电路的描述来实现，在此不再赘述。上述采样电路的驱动方法所能实现的效果与采样电路能够实现的效果相同，不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种采样电路，包括：第一输入端、第二输入端、第一电压采集子电路和电流积分子电路；
    其中，所述第一电压采集子电路与所述第一输入端以及所述电流积分子电路耦接，被配置为采集所述第一输入端的第一电压，并将所述第一电压传输至所述电流积分子电路；
    所述电流积分子电路还与所述第二输入端耦接，被配置为根据所述第一电压和所述第二输入端传输至所述电流积分子电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。
  2. 根据权利要求1所述的采样电路，其中，
    所述第二输入端被配置为与所述第一输入端耦接。
  3. 根据权利要求1所述的采样电路，其中，
    所述第一电压采集子电路包括：
    第一电压跟随器，所述第一电压跟随器的输入端与所述第一输入端耦接；
    和/或，
    所述电流积分子电路包括：
    积分器，所述积分器包括：正相输入端、反相输入端，所述积分器的正相输入端与所述第一电压采集子电路耦接，所述积分器的反相输入端与所述第二输入端耦接；
    第一开关器件，并联在所述积分器的正相输入端与所述积分器的反相输入端之间，被配置为响应于所述积分控制信号闭合。
  4. 根据权利要求3所述的采样电路，其中，
    所述第一电压采集子电路还包括：
    第一电容器，所述第一电容器的第一极板与所述第一电压跟随器的输出端耦接，所述第一电容器的第二极板接地；
    第二开关器件，所述第二开关器件耦接在所述第一电容器的第一极板与所述电流积分子电路之间。
  5. 根据权利要求1至4中的任一项所述采样电路，还包括：
    求差子电路，与所述电流积分子电路耦接，被配置为求取所述第一电压和所述第二电压之差，得到第三电压。
  6. 根据权利要求5所述的采样电路，其中，
    所述求差子电路包括：
    减法器，所述减法器包括正相输入端、反相输入端和输出端；
    第二电压跟随器，所述第二电压跟随器的输入端与所述电流积分子电路 耦接，所述第二电压跟随器的输出端与所述减法器的正相输入端耦接；
    第三电压跟随器，所述第三电压跟随器的输入端与所述电流积分子电路耦接，所述第三电压跟随器的输出端与所述减法器的反相输入端耦接。
  7. 根据权利要求1至6中的任一项所述的采样电路，其中，
    所述电流积分子电路包括一个电压输出端，所述电流积分子电路被配置为通过所述电压输出端输出所述第一电压和所述第二电压；
    所述求差子电路还包括：存储子电路，所述存储子路与所述电流积分子电路的电压输出端耦接，被配置为响应于第三控制信号，存储接收到的所述第一电压，响应于第四控制信号，存储所述第二电压。
  8. 根据权利要求7所述的采样电路，其中，
    所述存储子电路包括：
    第二电容器，所述第二电容器的第一极板与所述电压输出端耦接，所述第二电容器的第二极板接地；
    第三电容器，所述第三电容器的第一极板与所述电压输出端耦接，所述第三电容器的第二极板接地；
    第三开关器件，所述第三开关器件耦接在所述电压输出端与所述第二电容器的第一极板之间；
    第四开关器件，所述第四开关器件耦接在所述电压输出端与所述第三电容器的第一极板之间。
  9. 根据权利要求5至8中的任一项所述的采样电路，还包括：
    采样输出端；
    第五开关器件，所述第五开关器件耦接在所述求差子电路与所述采样输出端之间。
  10. 根据权利要求1至9中的任一项所述的采样电路，还包括：
    第二电压采集子电路，与第三输入端耦接，被配置为采集并输出所述第三输入端提供的第四电压。
  11. 根据权利要求10所述的采样电路，其中，
    所述第二电压采集子电路包括：
    第四电压跟随器，所述第四电压跟随器的输入端与所述第三输入端耦接；
    第四电容器，所述第四电容器的第一极板与所述第四电压跟随器的输出端耦接，所述第四电容器的第二极板接地。
  12. 根据权利要求11所述的采样电路，还包括：
    采样输出端；
    所述第三电压采集子电路还包括第六开关器件，所述第六开关器件耦接在所述第四电容器的第一极板与所述采样输出端之间。
  13. 一种像素采样电路，包括：
    权利要求1至12中的任一项所述的采样电路；
    像素驱动电路，所述像素驱动电路包括驱动晶体管，所述驱动晶体管包括第一级、第二极和控制极；
    其中，所述像素驱动电路被配置为将流经所述驱动晶体管的第一级和第二极的驱动电流传输到所述采样电路的第二输入端，以及将所述驱动晶体管的第二极的电压传输到所述采样电路的第一输入端。
  14. 根据权利要求13所述的像素采样电路，其中，
    所述像素驱动电路还包括感测晶体管，所述感测晶体管的控制极与扫描信号端耦接，所述感测晶体管的第一极与所述第一输入端耦接，所述感测晶体管的第二极与所述第二输入端耦接。
  15. 根据权利要求13或15所述的像素采样电路，其中，
    所述像素驱动电路还包括电压端，其中，所述像素驱动电路还被配置为将所述电压端的电压传输到所述采样电路的所述第三输入端。
  16. 一种显示装置，包括：
    权利要求1至12中的任一项所述的采样电路；
    或者，
    权利要求13至15中的任一项所述的像素采样电路。
  17. 根据权利要求16所述的显示装置，还包括：
    处理器，与所述采样电路或者所述像素采样电路耦接，被配置为根据所述第一电压和第二电压的差值计算驱动电流。
  18. 一种采样电路的驱动方法，包括：
    第一电压采集子电路采集第一输入端的第一电压，并将所述第一电压传输至电流积分子电路；
    所述电流积分子电路根据所述第一电压和第二输入端传输至所述电流积分子电路的驱动电流对时间的积分，生成并输出第二电压；以及，响应于积分控制信号，输出所述第一电压。
  19. 根据权利要求18所述的驱动方法，还包括：
    求差子电路求取第一电压和第二电压之差，得到并输出第三电压。
PCT/CN2021/131519 2021-05-10 2021-11-18 采样电路及驱动方法、像素采样电路、显示装置 WO2022237111A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/015,394 US12027085B2 (en) 2021-05-10 2021-11-18 Sampling circuit and driving method thereof, pixel sampling circuit, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110506648.6A CN113257184B (zh) 2021-05-10 2021-05-10 采样电路及驱动方法、像素采样电路、显示装置
CN202110506648.6 2021-05-10

Publications (1)

Publication Number Publication Date
WO2022237111A1 true WO2022237111A1 (zh) 2022-11-17

Family

ID=77222441

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/131519 WO2022237111A1 (zh) 2021-05-10 2021-11-18 采样电路及驱动方法、像素采样电路、显示装置

Country Status (3)

Country Link
US (1) US12027085B2 (zh)
CN (1) CN113257184B (zh)
WO (1) WO2022237111A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257184B (zh) 2021-05-10 2022-10-25 京东方科技集团股份有限公司 采样电路及驱动方法、像素采样电路、显示装置

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100289734A1 (en) * 2009-05-15 2010-11-18 Himax Display, Inc. Pixel circuitry of display device and display method thereof
CN106557724A (zh) * 2015-09-25 2017-04-05 上海思立微电子科技有限公司 指纹传感电路及控制方法
US20170256199A1 (en) * 2016-03-02 2017-09-07 Apple Inc. System and method for data sensing for compensation in an electronic display
CN108074524A (zh) * 2016-11-11 2018-05-25 乐金显示有限公司 驱动器集成电路和包括该驱动器集成电路的显示装置
CN111243507A (zh) * 2018-11-29 2020-06-05 乐金显示有限公司 像素感测装置及包括该像素感测装置的有机发光显示装置
CN111290654A (zh) * 2018-12-10 2020-06-16 乐金显示有限公司 触摸屏驱动器电路以及触摸传感器显示装置
CN111583872A (zh) * 2020-06-11 2020-08-25 京东方科技集团股份有限公司 像素补偿装置及像素补偿方法、显示装置
CN112331113A (zh) * 2019-08-05 2021-02-05 三星电子株式会社 Oled驱动特性检测电路及包括其的oled显示装置
CN113257184A (zh) * 2021-05-10 2021-08-13 京东方科技集团股份有限公司 采样电路及驱动方法、像素采样电路、显示装置
CN113362763A (zh) * 2021-06-01 2021-09-07 京东方科技集团股份有限公司 显示面板、显示装置及其像素驱动电路的电流检测方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2832537B1 (fr) * 2001-11-16 2003-12-19 Commissariat Energie Atomique Procede et dispositif de commande en tension d'une source d'electrons a structure matricielle, avec regulation de la charge emise
DE10316901A1 (de) * 2003-04-12 2004-10-28 Roche Diagnostics Gmbh Kontrollsystem und Kontrollverfahren zum Überprüfen der Funktion von LCD-Anzeigen
US7285964B1 (en) * 2005-06-03 2007-10-23 Sensor Platforms, Inc. Method for signal extraction in a universal sensor IC
TWI287214B (en) 2005-06-17 2007-09-21 Innolux Display Corp Backlight broken protecting circuit
JP5127278B2 (ja) 2007-04-05 2013-01-23 三菱電機株式会社 熱型赤外線固体撮像素子及び赤外線カメラ
JP2010039436A (ja) * 2008-08-08 2010-02-18 Sony Corp 表示パネルモジュール及び電子機器
CN101621292B (zh) * 2009-04-10 2012-05-09 浙江大学 开关电容积分器
CN102298407A (zh) * 2010-06-28 2011-12-28 中国人民解放军国防科学技术大学 基于电流控制环路的低输出电压快速响应ldo电路
CN103384313B (zh) * 2012-05-01 2017-02-08 香港科技大学 Cmos有源像素图像传感器及其校准方法
CN203616605U (zh) * 2013-12-20 2014-05-28 优科新能源科技有限公司 工业控制用dsp开发板底板
KR101529005B1 (ko) * 2014-06-27 2015-06-16 엘지디스플레이 주식회사 구동소자의 전기적 특성을 센싱할 수 있는 유기발광 표시장치
KR102390374B1 (ko) * 2015-06-24 2022-04-25 삼성전자주식회사 화소 회로, 화소 회로의 구동 방법, 및 유기 발광 표시 장치
CA2900170A1 (en) * 2015-08-07 2017-02-07 Gholamreza Chaji Calibration of pixel based on improved reference values
KR102427553B1 (ko) * 2015-12-01 2022-08-02 엘지디스플레이 주식회사 전류 적분기와 이를 포함하는 유기발광 표시장치
CN105548666B (zh) * 2016-01-05 2018-04-24 深圳市金霆正通科技有限公司 无采样电阻的电动汽车充电电流计算方法
KR102423861B1 (ko) * 2016-04-08 2022-07-22 엘지디스플레이 주식회사 전류 센싱형 센싱 유닛과 그를 포함한 유기발광 표시장치
CN107526993A (zh) * 2016-06-20 2017-12-29 康达生命科学有限公司 电容式指纹传感器
KR102603596B1 (ko) * 2016-08-31 2023-11-21 엘지디스플레이 주식회사 유기발광 표시장치와 그의 열화 센싱 방법
CN206440802U (zh) * 2016-09-28 2017-08-25 西门子瑞士有限公司 监测现场干接点状态的监测电路
CN106531041B (zh) * 2016-12-29 2019-01-22 深圳市华星光电技术有限公司 Oled驱动薄膜晶体管的k值侦测方法
CN106782312B (zh) * 2017-03-08 2019-01-29 合肥鑫晟光电科技有限公司 一种像素电路及其驱动方法、显示装置
CN207020243U (zh) * 2017-07-17 2018-02-16 郑州众智科技股份有限公司 一种发电机组控制器三相电流采样电路
CN107945722A (zh) * 2018-01-16 2018-04-20 京东方科技集团股份有限公司 像素电流检测范围调整方法、检测电路及显示装置
CN110164362B (zh) 2018-06-26 2021-08-17 京东方科技集团股份有限公司 发光器件的补偿装置及方法、显示基板及其制作方法
CN109342797A (zh) * 2018-08-24 2019-02-15 维沃移动通信有限公司 一种背光源检测电路、终端及背光源检测方法
EP3663779B1 (en) * 2018-12-05 2021-10-06 Nxp B.V. Apparatus and method for measuring a capacitance, and a fingerprint sensor utilizing the same
CN109951925B (zh) * 2019-04-11 2024-07-12 上海晶丰明源半导体股份有限公司 可调电阻及其应用的电流纹波消除电路和线电压补偿电路
CN110503920B (zh) * 2019-08-29 2021-02-23 云谷（固安）科技有限公司 一种显示装置及其驱动方法
KR102610829B1 (ko) * 2019-09-30 2023-12-07 주식회사 엘엑스세미콘 화소센싱회로

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100289734A1 (en) * 2009-05-15 2010-11-18 Himax Display, Inc. Pixel circuitry of display device and display method thereof
CN106557724A (zh) * 2015-09-25 2017-04-05 上海思立微电子科技有限公司 指纹传感电路及控制方法
US20170256199A1 (en) * 2016-03-02 2017-09-07 Apple Inc. System and method for data sensing for compensation in an electronic display
CN108074524A (zh) * 2016-11-11 2018-05-25 乐金显示有限公司 驱动器集成电路和包括该驱动器集成电路的显示装置
CN111243507A (zh) * 2018-11-29 2020-06-05 乐金显示有限公司 像素感测装置及包括该像素感测装置的有机发光显示装置
CN111290654A (zh) * 2018-12-10 2020-06-16 乐金显示有限公司 触摸屏驱动器电路以及触摸传感器显示装置
CN112331113A (zh) * 2019-08-05 2021-02-05 三星电子株式会社 Oled驱动特性检测电路及包括其的oled显示装置
CN111583872A (zh) * 2020-06-11 2020-08-25 京东方科技集团股份有限公司 像素补偿装置及像素补偿方法、显示装置
CN113257184A (zh) * 2021-05-10 2021-08-13 京东方科技集团股份有限公司 采样电路及驱动方法、像素采样电路、显示装置
CN113362763A (zh) * 2021-06-01 2021-09-07 京东方科技集团股份有限公司 显示面板、显示装置及其像素驱动电路的电流检测方法

Also Published As

Publication number Publication date
US12027085B2 (en) 2024-07-02
US20230343256A1 (en) 2023-10-26
CN113257184A (zh) 2021-08-13
CN113257184B (zh) 2022-10-25

Similar Documents

Publication Publication Date Title
CN109215569B (zh) 一种像素电路、驱动方法及显示装置
WO2018209917A1 (zh) 像素电路及其驱动方法、显示装置
KR102071296B1 (ko) 디스플레이 패널의 소스 드라이버
US11138932B2 (en) Pixel current detection circuit and method, and display device
CN108962146B (zh) 外部补偿电路及补偿方法、显示装置
KR20100019378A (ko) 표시 장치 및 전자 기기
KR20200057373A (ko) 포토 센서가 내장된 표시패널과 이를 이용한 표시장치
JP4127243B2 (ja) 光センサ、光センサの読取方法、マトリクス型光センサ回路および電子機器
WO2022237111A1 (zh) 采样电路及驱动方法、像素采样电路、显示装置
US10777146B2 (en) Source driver
WO2022252723A1 (zh) 显示面板、显示装置及其像素驱动电路的电流检测方法
US11631351B2 (en) Current detection device and display device
CN108922940A (zh) 光学检测像素单元、电路、光学检测方法和显示装置
WO2022267055A1 (zh) 一种电流检测装置
JP2005148285A (ja) 表示装置およびその駆動方法
US11079272B2 (en) Detection circuit and driving method therefor, detection substrate and detection device comprising a second storage sub-circuit group with a second voltage terminal group and a second control signal terminal group
WO2024087098A1 (zh) 坏点修复方法、显示模组及显示装置
JP4946486B2 (ja) 検出装置の駆動方法、検出装置、電気光学装置および電子機器
WO2021088120A1 (zh) 显示面板的电压调节方法及计算机可读存储介质
JP4701603B2 (ja) 表示装置およびその駆動方法
CN113593458B (zh) 显示面板及其检测电路的驱动方法、显示装置
WO2024020940A1 (zh) 光线检测结构及其方法、显示基板和显示装置
WO2023092503A1 (zh) 光检测模组、光检测方法和显示装置
JP2009065209A (ja) 光センサ、光センサの読取方法、マトリクス型光センサ回路および電子機器
CN114170990B (zh) 显示面板及其环境光检测驱动方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21941675

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 12/03/2024)

122 Ep: pct application non-entry in european phase

Ref document number: 21941675

Country of ref document: EP

Kind code of ref document: A1