WO2022267055A1 - 一种电流检测装置 - Google Patents

一种电流检测装置 Download PDF

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Publication number
WO2022267055A1
WO2022267055A1 PCT/CN2021/102538 CN2021102538W WO2022267055A1 WO 2022267055 A1 WO2022267055 A1 WO 2022267055A1 CN 2021102538 W CN2021102538 W CN 2021102538W WO 2022267055 A1 WO2022267055 A1 WO 2022267055A1
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Prior art keywords
voltage
circuit
coupled
detection line
detection
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PCT/CN2021/102538
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English (en)
French (fr)
Inventor
殷新社
商广良
杨华玲
韩新斌
朱健超
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/102538 priority Critical patent/WO2022267055A1/zh
Priority to CN202180001707.2A priority patent/CN116018634A/zh
Publication of WO2022267055A1 publication Critical patent/WO2022267055A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror

Definitions

  • the present application relates to the field of organic electro-laser display technology, in particular to a current detection device.
  • the difference in the electrical characteristics of the drive tube (DTFT) in the organic laser display (Organic Light-Emitting Diode, OLED) causes a deviation in the current of the DTFT at the same gray scale, so the brightness of the screen will vary, and the displayed picture There will be brightness unevenness.
  • the purpose of the present application is to provide a current detection device, which is used to detect the current of the pixel, and compensate the gray scale of the pixel according to the difference of the detected current, so that the brightness uniformity of the pixel points is uniform.
  • an embodiment of the present application provides a current detection device, the device comprising: a plurality of detection circuits, wherein the detection circuits are coupled to detection lines in a display panel;
  • the detection circuit includes a current detection circuit
  • the current detection circuit is used to detect the current on the detection line coupled with the current detection circuit.
  • the current detection circuit includes:
  • the integral sub-circuit the integral sub-circuit is configured to integrate the current on the detection line to obtain an integrated voltage signal, and after sampling the integrated voltage signal multiple times, obtain the output between different sampling points Voltage difference.
  • the integral sub-circuit includes an integrator, at least two voltage acquisition circuits, a voltage difference determination circuit and a digital-to-analog conversion circuit, wherein:
  • the integrator is configured to perform an integration operation on the current on the detection line to obtain an integrated voltage signal varying with time;
  • Each of the voltage acquisition circuits is configured to sample the integrated voltage signal, and output the sampled voltage to the voltage difference determination circuit; The voltage signal is sampled;
  • the voltage difference determining circuit is configured to determine the output voltage difference based on the voltages collected by each of the voltage collecting circuits, and send the output voltage difference to the digital-to-analog conversion circuit;
  • the digital-to-analog conversion circuit is configured to obtain the output voltage difference, convert the output voltage difference from an analog signal into a digital signal, and then output it to the controller, so that the controller can determine according to the output voltage difference current in the sense line.
  • the voltage acquisition circuit includes: an acquisition switch and a holding capacitor, wherein:
  • One end of the acquisition switch is coupled to the output end of the integrator, and the other end is coupled to the first end of the holding capacitor and the input end of the voltage difference determination circuit;
  • the first terminal of the storage capacitor is coupled to the acquisition switch, and the second terminal of the storage capacitor is coupled to a ground terminal.
  • the voltage difference determination circuit includes: a plurality of subtractors; each of the subtractors is coupled to two voltage acquisition circuits, wherein:
  • the two input terminals of the subtractor are respectively coupled to one of the voltage acquisition circuits, and the output terminals of the subtractor are coupled to the digital-to-analog conversion circuit.
  • one end of the detection line is coupled to the current detection circuit, and the other end is coupled to the sensing control switch in the pixel circuit.
  • the current detection circuit further includes a reference voltage writing circuit and a reset circuit, wherein:
  • the reference voltage writing circuit has one end coupled to at least one detection line, and the other end is coupled to a reference voltage terminal, and the reference voltage writing circuit is configured to write a reference voltage to the at least one detection line;
  • One end of the reset circuit is coupled to the at least one detection line, and the other end is coupled to the initial voltage end and the integral sub-circuit, and the reset circuit is configured to write an initial voltage into the at least one detection line.
  • the reference voltage writing circuit includes: a reference level control switch
  • One end of the reference level control switch is coupled to the at least one detection line, and the other end is coupled to the reference voltage end.
  • the reset circuit includes: a follower amplifier and a reset control switch; wherein:
  • the follower amplifier has one terminal coupled to the reset control switch and the other terminal coupled to the initial voltage terminal, and is configured to reset the voltage on the detection line when the reset control switch is in a conducting state to said initial voltage;
  • One end of the reset control switch is coupled to at least one detection line, and the other end is coupled to the follower amplifier.
  • the voltage difference determination circuit further includes a plurality of high input impedance followers, and the input terminal of each subtractor is coupled to two of the high input impedance followers;
  • each high input impedance follower is coupled to the subtractor, and the other end is coupled to the voltage acquisition circuit.
  • the voltage difference determination circuit further includes a first resistance module and a second resistance module,
  • One end of the first resistance module is coupled to the positive input end of the subtractor, and the other end is coupled to the output end of a high input impedance follower;
  • One end of the second resistance module is coupled to the negative input end of the subtractor, and the other end is coupled to the output end of another high input impedance follower.
  • the first resistor module includes a first resistor and a second resistor, wherein one end of the first resistor is coupled to the output end of a high input impedance follower, and the other end is coupled to the second resistor and the positive input terminal of the subtractor, the other end of the second resistor is coupled to the ground terminal;
  • the second resistor module includes a third resistor and a fourth resistor, one end of the third resistor is coupled to the output end of the high input impedance follower, and the other end is coupled to the fourth resistor and the negative input of the subtractor terminal, and the other terminal of the fourth resistor is coupled to the output terminal of the subtractor.
  • the current detection circuit includes:
  • An integral sub-circuit includes an integrator, a digital-to-analog conversion circuit, a multi-channel channel selection switch, and a plurality of voltage acquisition circuits, wherein the plurality of voltage acquisition circuits include at least two groups of voltage acquisition circuits, wherein:
  • the integrator is configured to perform an integration operation on the current on the detection line to obtain an integrated voltage signal varying with time;
  • the at least two groups of voltage acquisition circuits are configured to use one of the groups of voltage acquisition circuits to sample the integrated voltage signal of the detection line multiple times to obtain and store multiple sampling points;
  • the detection line performs current detection
  • the integrated voltage signal of the other detection line is sampled multiple times to obtain a plurality of sampling points and save them;
  • the digital-to-analog conversion circuit is configured to perform analog-to-digital conversion on the sampling points of the detection line to obtain a digital signal and output it to the controller, so that the controller determines the current of the detection line according to the digital signal.
  • the multiple sets of voltage acquisition circuits include a first set of voltage acquisition circuits and a second set of voltage acquisition circuits, wherein:
  • the first set of voltage acquisition circuits and the second set of voltage acquisition circuits are configured to use one of the set of voltage acquisition circuits to perform multiple samplings on the integrated voltage signal of the detection line to obtain and store multiple sampling points; When a group of voltage acquisition circuits performs current detection on the next detection line of the detection line, multiple sampling points are obtained from the integrated voltage signal of the next detection line of the detection line and stored.
  • the integral sub-circuit further includes a multi-channel selection switch, one end of the multi-channel selection switch is coupled to the plurality of voltage acquisition circuits, and the other end is coupled to the digital-to-analog conversion circuit. It is configured to turn on a group of voltage acquisition circuits for saving the sampling points of the detection line when the current detection circuit detects the current of the next detection line of the detection line at a specified timing.
  • the current detection circuit further includes a voltage difference determination circuit, one end of which is coupled to the multi-channel selection switch, and the other end is coupled to the digital-to-analog conversion circuit, configured to determine the number of detection lines The output voltage difference between sampling points;
  • the digital-to-analog conversion circuit is specifically configured to perform analog-to-digital conversion on the output voltage difference to obtain the digital signal.
  • the specified timing is before the integration sub-circuit samples the integrated voltage signal of the detection line next to the detection line, and after the current detection is performed on the detection line next to the detection line.
  • the voltage acquisition circuit includes: an acquisition switch and a holding capacitor, wherein:
  • the acquisition switch has one end coupled to the output end of the integrator, and the other end coupled to the first end of the holding capacitor and the multichannel channel selection switch;
  • the first terminal of the storage capacitor is coupled to the acquisition switch, and the second terminal of the storage capacitor is coupled to a ground terminal.
  • the voltage difference determination circuit includes: a plurality of subtractors; each of the subtractors is coupled to two voltage acquisition circuits, wherein:
  • the two input terminals of the subtractor are respectively coupled to one of the voltage acquisition circuits through the multiple channel selection switch, and the output terminals of the subtractor are coupled to the digital-to-analog conversion circuit. catch.
  • the integral sub-circuit further includes a protection circuit
  • the protection circuit includes a resistance module and a control switch arranged in parallel, one end of the protection circuit is coupled to the output end of the integrator, and the other end is coupled to Each of the voltage acquisition circuits.
  • the detection circuit further includes a plurality of multiplex control switches, wherein,
  • One end of the multiplex control switch is coupled to the current detection circuit, and the other end is coupled to the detection line; and different multiplex control switches are in conduction states at different times.
  • the present application also provides a display device, including: a display panel and the current detection device according to any one of the above;
  • the display panel includes a display area and a non-display area
  • the display area includes a plurality of sub-pixels and a plurality of detection lines; wherein each of the sub-pixels includes a pixel circuit; a column of the pixel circuits is coupled to one detection line;
  • the non-display area includes a predetermined power line, a reference voltage writing unit of the detection circuit and a reset circuit;
  • the first end of the current detection circuit in each of the detection circuits is coupled to the corresponding one of the detection lines.
  • FIG. 1A is a schematic diagram of a pixel circuit device of a current detection device provided by an embodiment of the present disclosure
  • FIG. 1B is a schematic diagram of a 6T1C internal compensation pixel circuit device of a current detection device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a display panel of a current detection device provided by an embodiment of the present disclosure
  • FIG. 3 is a device schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of the overall framework of the current detection device provided by the embodiment of the present disclosure.
  • FIG. 4B is an overall schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 4C is a schematic diagram of the overall frame of the current detection device provided by the embodiment of the present disclosure.
  • FIG. 4D is an overall schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 4E is an overall schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 4F is an overall schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • 5A is a circuit diagram of the data writing stage of the current detection device provided by the embodiment of the present disclosure.
  • 5B is a timing diagram of the data writing phase of the current detection device provided by the embodiment of the present disclosure.
  • FIG. 6A is a circuit diagram of a reset phase of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 6B is a timing diagram of a reset phase of the current detection device provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an integration module of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a control method of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of turning on the sensing control switch at time t1 before the integration operation of the current detection device provided by an embodiment of the present disclosure
  • FIG. 10A is a flow chart of correcting the current of the current detection device provided by an embodiment of the present disclosure.
  • FIG. 10B is a flow chart of correcting currents in different gray scales of the current detection device provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of a current detection device provided by an embodiment of the present disclosure.
  • FIG. 13 is a timing diagram of a current detection device provided by an embodiment of the present disclosure.
  • the transistors of the pixel circuit may be N-type or P-type, which is not limited in the present disclosure.
  • the transistor is N-type as an example for illustration.
  • the driving transistor T 1 , the first switching transistor T 2 , the sensing control switch (T 3 ) and the storage capacitor C st form a 3T1C pixel circuit as shown in FIG. 1A , connected to a sense line (sense line, SL) through a sensing control switch (T 3 ).
  • the pixel circuit controls the first switching transistor T2 to turn on , so as to write the grayscale voltage V data of the pixel circuit into the gate of the driving transistor T1, and controls the driving transistor T1 to generate an operating current to drive the electroluminescent diode OLED to emit light .
  • the driving current I DS of the driving transistor T1 is shown in the following formula ( 1 ):
  • ⁇ represents the mobility
  • Cox represents the gate oxide layer capacitance of the driving transistor
  • W represents the channel width of the driving transistor T1
  • L represents the channel length of the driving transistor T1.
  • V GS represents the voltage difference between the gate voltage and source voltage of the drive transistor T1
  • V th represents the threshold voltage of the drive transistor T1
  • V data represents the data voltage at the data signal terminal
  • V OLED represents the voltage at the anode voltage power supply terminal of the OLED device .
  • threshold voltage V th and mobility ⁇ between different pixels, resulting in different brightness of pixels in the same gray scale.
  • the driving transistor T1 will age, which will cause the threshold voltage and mobility of the driving transistor T1 to drift, and will also aggravate the difference in display brightness.
  • one detection circuit is coupled to a plurality of detection lines SL.
  • Electroluminescent diodes such as OLEDs and quantum dot light emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs) have the advantages of self-luminescence and low energy consumption, and are one of the hotspots in the field of electroluminescent display panel application research today. Electroluminescent diodes are generally current-driven and require a stable current to drive them to emit light. After the electroluminescent diode is applied to the display panel 200 , pixel circuits are usually used to drive the electroluminescent diode to emit light.
  • the display panel 200 may include: a display area AA (Active area) and a non-display area NB around the frame portion of AA.
  • the display area AA includes a plurality of pixels arranged in an array.
  • Each pixel includes a plurality of sub-pixels spx.
  • a pixel may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue can be mixed to achieve color display.
  • the pixels may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that color mixing of red, green, blue and white can be performed to realize color display.
  • the luminous color of the sub-pixel spx in the pixel can be designed and determined according to the practical application environment, which is not limited here.
  • the sub-pixel spx may include an electroluminescent diode and a pixel circuit for driving the electroluminescent diode to emit light.
  • the electroluminescent diode includes an anode, a light-emitting functional layer and a cathode layer which are stacked.
  • the light-emitting functional layer may include: a hole injection layer positioned between the anode and the cathode layer, a hole transport layer positioned between the hole injection layer and the cathode layer, an organic light-emitting layer positioned between the hole transport layer and the cathode layer, A hole blocking layer located between the organic light emitting layer and the cathode layer, and an electron transport layer located between the hole blocking layer and the cathode layer.
  • the display area AA of the display panel 200 also has a plurality of scan lines G, and the first switching transistor T 2 in a row of sub-pixels spx is coupled to one scan line, so that the scan line and the data
  • the line V data (not shown in FIGS. 1A and 2 ) and the detection line SL cross each other, so that there is load capacitance and line resistance between the detection line SL and these scanning lines G. Due to the effect of load capacitance and line resistance, when the signal on the scanning line G fluctuates, the current signal transmitted on the detection line SL will change, resulting in inaccurate detected current on the detection line SL, which will cause external Inaccurate compensation will affect the display effect of the screen.
  • the 6T1C internal compensation pixel circuit requires 6 thin film transistors (Thin Film Transistor, TFT) and 1 capacitor and 6EA (Elementa advance)
  • TFT Thin Film Transistor
  • 6EA Organic Advance
  • the resolution of the corresponding display device is also getting higher and higher.
  • each pixel takes up less and less space. More and more electronic devices and control signal lines (including detection lines SL and scan lines G) and limited pixel space form an irreconcilable contradiction.
  • the external compensation method is to use an external circuit to check the electrical characteristics of the driving transistor T1 of each pixel circuit, such as threshold voltage, mobility, etc., and store the detected electrical parameters of each pixel circuit in the external memory.
  • the display screen is driven , converting the electrical parameter of the driving transistor T1 into a grayscale voltage and superimposing it on the display data, so that the difference in the electrical parameter of the driving transistor can be compensated.
  • the principle of voltage detection is to drive and charge the detection line SL through the driving transistor T1 in the pixel circuit. When the voltage on the detection line SL is full, read the voltage on the detection line SL, and calculate the driving transistor T1 according to the voltage. threshold voltage.
  • the driving transistor T1 of the pixel circuit is to increase the area of the driving transistor T1 as much as possible in the limited pixel space to improve the driving capability of the driving transistor T1.
  • the storage capacitance (Cs) is relatively small, The drive transistor quickly fills up the storage capacitor.
  • the detection line SL is relatively long and crosses with the pixel scan line G and other signal lines, so the detection parameters of the driving transistor T1 are inaccurate due to the load capacitance and line resistance.
  • the voltage detection method because the driving current of the driving transistor T1 decreases as the voltage of the detection line SL rises, the voltage detection method generally takes a long time, so the voltage detection is generally performed before leaving the factory or before powering on the display screen. parameters to check.
  • the present disclosure proposes a current detection device and method.
  • the inventive concept of the present disclosure can be summarized as: write a driving voltage to the storage capacitor C st of the pixel circuit, drive the transistor T 1 to output a constant current to the detection line SL,
  • the current of the detection line SL is integrated by an integral sub-circuit to obtain an output voltage, and the current of the detection line SL is obtained according to the output voltage.
  • the pixel circuit corresponding to the current detection device of the present disclosure includes, but is not limited to, the 6T1C internal compensation pixel circuit as shown in Figure 1B, such as 3T1C, 4T1C, 5T1C, 5T2C, etc. All the pixel circuits are also applicable to the present disclosure, which is not limited in the present disclosure.
  • the transistor connected to the detection line in the pixel circuit can be referred to as a sensing control switch T 3 .
  • the current detection device includes a plurality of detection circuits, and one detection circuit in the current detection device is taken as an example in FIG. 3 for illustration.
  • Fig. 3 includes: a detection circuit 101, a detection line 102 (equal to the detection line SL described above, which will not be described later); wherein, one detection circuit 101 corresponds to at least one detection line 102 in the display panel; the detection circuit 101 includes a current detection circuit 201; the detection line 102 is a metal line extending along the second direction, and is arranged on a different layer through a metal material between the scanning line G extending along the first direction as shown in FIG.
  • the horizontal direction may be the first direction
  • the longitudinal direction may be the second direction
  • the first direction X intersects the second direction Y.
  • the present disclosure does not limit the extension directions of the first direction X and the second direction Y, and the angle between these two directions.
  • the included angle between the first direction X and the second direction Y is between 70° and 90°, including 70° and 90°.
  • the angle between the first direction X and the second direction Y is 70°, 75°, 85°, 90°, or 80°, etc., and the specific value of the angle can be set according to the actual situation. No limit.
  • multiplex control switches 202 are also provided in the detection circuit 101, wherein each The multiplex control switch 202 corresponds to one detection line 102 .
  • Each multiplex control switch 202 corresponds to at least one detection line 102 , and by controlling conduction of the multiplex control switch 202 , detection of the corresponding detection line 102 is realized.
  • the multi-way selection control switch 202 can be: a four-to-one data selector, a six-to-one data selector, an eight-to-one data selector (multiplexer, MUX), etc., and other switches with control functions are applicable.
  • a current detection device proposed in an embodiment of the present disclosure.
  • the current detection circuit 201 is configured to detect the current on the detection line 102 connected to the multi-way selection control switch 202 that is currently in an on state.
  • the current detection device may include a plurality of current detection circuits 201 , and each current detection circuit corresponds to a plurality of detection lines 102 .
  • each current detection circuit corresponds to a plurality of detection lines 102 .
  • the specific structure and functions of the current detection circuit 201 will be described in detail below in conjunction with the accompanying drawings. Take one detection line 102, one pixel circuit and its corresponding current detection circuit 201 as an example for illustration, as shown in FIG. 4A and FIG. 4B:
  • the current detection circuit 201 includes an integral sub-circuit 301, a reference voltage writing circuit 304, and a reset circuit 305;
  • the integral sub-circuit 301 is configured to perform an integral operation on the current on the detection line 102 to obtain an integral voltage signal;
  • the current on the detection line 102 needs to balance charge the parasitic load capacitance 103 on the detection line 102 in addition to flowing to the integration sub-circuit 301 .
  • the current on the detection line 102 can all flow to the integral sub-circuit 301 to generate a voltage drop, so the detection line 102 is under the condition of small current, and in the stage of establishing balance at the beginning of integration (that is, the charging time to the parasitic load capacitance 103 segment), the detected current error is relatively large.
  • the integral sub-circuit 301 includes an integrator 401, a plurality of voltage acquisition circuits 402 and voltage difference determination circuit 403, digital-to-analog conversion circuit 302, wherein:
  • the integrator 401 is coupled to the voltage acquisition circuit 402, and the other end is respectively coupled to the initial voltage terminal V INT and the multiplex control switch 202, wherein the second end of the integrator 401 is coupled to the multiplex control switch 202, the second One terminal is coupled to the initial voltage terminal V INT .
  • the initial voltage terminal V INT is configured to provide an initial voltage V int
  • the integrator 401 is configured to integrate the current on the detection line 102 to obtain an integrated voltage signal varying with time.
  • the integrator 401 includes an integrating control switch K 1 , an integrating capacitor C INT and a low-noise operational amplifier OP 1 arranged in parallel.
  • the low-noise operational amplifier OP 1 is provided with a first terminal, a second terminal and a third terminal.
  • One end of the integral capacitor C INT and the integral control switch K 1 is coupled to the second end of the low-noise operational amplifier OP 1 , the other end is coupled to the third end of the low-noise operational amplifier OP 1 , and the first end of the low-noise operational amplifier OP 1 coupled to the initial voltage terminal V INT .
  • the first terminal may be a positive input terminal
  • the second terminal may be a negative input terminal
  • the third terminal may be an output terminal.
  • the first terminal may be a negative input terminal
  • the second terminal may be a positive input terminal
  • the third terminal may be an output terminal. This application does not limit this.
  • the integrator when the integral control switch K 1 is turned on, the integrator has a reset function, which mainly clears the charge on the integral capacitor C INT .
  • the integrator 401 starts to work (that is, starts to perform integral operation).
  • one of the voltage acquisition circuits 402 includes an acquisition switch KA and a holding capacitor C A
  • the other voltage acquisition circuit 402 includes an acquisition switch KB and a holding capacitor C B .
  • the voltage acquisition circuit 402 is configured to acquire the voltage of the integrator 401 at a specified integration time point to realize the sampling of the integrated voltage signal, and save the sampled voltage to the holding capacitors C A and C B ; wherein, different voltage acquisition circuits 402 correspond to Different specified integration time points, that is, storage capacitors C A and C B store voltages at different integration time points.
  • the present disclosure provides a plurality of voltage collection circuits 402 in the integration sub-circuit 301 .
  • two voltage acquisition circuits 402 are taken as an example for illustration in FIG. 4A and FIG. 4B , where:
  • one end of the acquisition switch K A is coupled to the high input impedance follower OP 3 in the voltage difference determination circuit 403 and the first end of the holding capacitor CA , and the other end is coupled to the third end of the integrator 401.
  • one end of the acquisition switch KB is coupled to the high input impedance follower OP 4 in the voltage difference determination circuit 403 and the first end of the holding capacitor C B , and the other end is coupled to the third end of the integrator 401 .
  • the holding capacitors C A and C B of the voltage acquisition circuit 402 have their first ends coupled to the corresponding acquisition switches KA and KB respectively, and their second ends coupled to the ground.
  • the high input impedance followers OP 3 and OP 4 sample the integrated voltage signal through the acquisition switches K A and KB respectively, and store the voltages V A and V B at different specified integration time points in the hold Capacitors C A and C B.
  • the voltage difference determination circuit 403 is configured to calculate the output voltage difference at different sampling points obtained by the multiple voltage acquisition circuits 402, and send the output voltage difference to the digital-to-analog conversion circuit 302 for digital-to-analog conversion.
  • the voltage difference determination circuit 403 is provided with: a plurality of subtractors OP 5 (only one is shown in FIG. 4B ) and a follower with high input impedance; wherein:
  • the two input terminals of the subtractor are respectively coupled to two followers with high input impedance, and the third terminal of the subtractor is coupled to the digital-to-analog conversion circuit 302 .
  • each high input impedance follower is coupled to the subtractor, and the other end is coupled to the voltage acquisition circuit.
  • two input terminals of the subtractor OP 5 are respectively coupled to high input impedance followers OP 3 and OP 4 .
  • a first resistor module and a second resistor module are also set in the voltage difference determination circuit 403, as shown in FIG. 11 , wherein: the first resistor One end of the module is coupled to the first end of the subtractor, and the other end is coupled to the third end of a high input impedance follower; one end of the second resistance module is coupled to the second end of the subtractor, and the other end is coupled to another high input impedance The third terminal of the follower.
  • two resistors can be set in the first resistor module and the second resistor module.
  • the first resistor module includes a first resistor and a second resistor, wherein the first resistor is coupled to Connect the third terminal of the follower with high input impedance, the other terminal is coupled to the second resistor and the first terminal of the subtractor, and the other terminal of the second resistor is coupled to the ground terminal;
  • the second resistor module includes a third resistor and a fourth resistor , one end of the third resistor is coupled to the third end of the high input impedance follower, the other end is coupled to the fourth resistor and the second end of the subtractor, and the other end of the fourth resistor is coupled to the third end of the subtractor.
  • the present disclosure does not limit the quantity of resistors in the first resistor module and the second resistor module.
  • the integrated voltage V A of the detection line obtained at the first integration time point t is the first integrated voltage
  • the integrated voltage V B of the detection line obtained at the second integration time point t+T is the second integrated voltage
  • the first integrated voltage V A and the second integrated voltage V B are respectively stored in the holding capacitors C A and C B
  • the first ends of the holding capacitors C A and C B are respectively coupled to a follower OP 3 and OP 4 with high input impedance, and then subtracted
  • Equation 2 The voltage difference obtained by the device OP 5 is shown in Equation 2:
  • V out V A -V B ;
  • the output voltage difference V out should be converted from an electrical signal to a digital signal, so the present disclosure is provided with a digital-to-analog conversion circuit 302 in the integral sub-circuit 301 so as to be output to the controller, so that the controller according to The output voltage at different integration time points determines the current of the detection line 102 .
  • each voltage acquisition circuit sequentially samples the integrated voltage signal in time sequence to obtain multiple sampling points.
  • a sampling point pair is formed by two adjacent sampling points, and the voltage difference between the two sampling points in each sampling point pair is determined to obtain multiple voltage differences, and then the input voltage difference can be obtained by averaging the multiple voltage differences .
  • the first voltage acquisition circuit 402 saves the voltage at time point t to the holding capacitor C A
  • the second voltage acquisition circuit 402 saves the voltage at time point (t+T)
  • the voltage of the voltage is saved to the holding capacitor C B
  • the third voltage acquisition circuit 402 saves the voltage at the (t+2T) time point to the holding capacitor C C
  • the fourth voltage acquisition circuit 402 saves the voltage at the (t+3T) time point Save it to the holding capacitor CD, so you can calculate the voltage difference between the t time point and the (t+ T ) time point, the voltage difference between the (t+2T) time point and the (t+3T) time point, and then take the average to get Voltage difference.
  • T represents the time interval between sampling points
  • T between sampling points arranged in sequence in time sequence can be the same
  • the integrated voltage signal can be sampled at equal intervals, or it can be sampled at non-equal intervals, both of which are applicable to the embodiments of the present application.
  • the detection line 102 is coupled to the sensing control switch 303 in the corresponding pixel circuit. As shown in FIG. The situation is shown in FIG. 1A (only the sensing control switch 303 is shown in FIG. 4B ), and its function has been described in FIG. 1A and will not be repeated here.
  • one end of the reference voltage writing circuit 304 is coupled to the multiplex control switch 202, and the other end is coupled to the reference voltage terminal V REF .
  • the reference voltage terminal V REF is configured to provide a reference voltage V ref
  • the writing circuit 304 includes a reference level control switch 404 , the gate of the reference level control switch 404 is coupled to the control level WR.
  • the reference voltage writing circuit 304 is configured to write to the storage capacitor C st of the pixel circuit (C as shown in FIG. st ) writes the reference voltage V ref into one end.
  • the data writing phase is described by taking the reference level control switch 404 as a TWR transistor as an example.
  • TWR transistors and other transistors in this disclosure such as drive transistor T 1 , first switch transistor T 2 and sensing control switch T 3 in Figure 1A
  • control switches such as multiplex control switch 202
  • the reference voltage V ref is at a high level
  • the sensing control switch 303 and the reference level control switch 404 are turned on, and the reference voltage V ref is at a high level.
  • the voltage terminal V REF writes the reference voltage V ref into the source of the driving transistor T 1 through the reference level control switch 404 (TWR transistor), the detection line 102 and the sensing control switch 303 .
  • V ref is controlled to be at a high level
  • the first switching transistor T 2 is controlled to be turned on at the same time, and the gray scale voltage V data on the pixel circuit is written into the gate of the driving transistor T 1 . Therefore, the gate - source voltage of the driving transistor T1 in the data writing phase is shown in Equation 3:
  • V GS V data -V ref ;
  • the drive transistor T1 outputs a constant current:
  • the reset circuit 305 one end is coupled to the multi-way selection control switch 202, and the other end is coupled to the initial voltage terminal V INT and the low-noise operational amplifier OP 1 , and is configured to reset the voltage of the detection line 102 . That is, the voltage on the detection line 102 is reset to reset the voltage on the detection line 102 to the initial voltage V int .
  • the reset circuit 305 is provided with: a follower amplifier 405, a reset control switch 406; wherein:
  • a follower amplifier (such as OP 2 in FIG. 4B ) 405, one end is coupled to the reset control switch 406, and the other end is coupled to the initial voltage terminal V INT , is configured to switch the detection line
  • the voltage on 102 is reset to the initial voltage V int ;
  • the manufacturing process of the TRST transistor is the same as that of other transistors and control switches in the present disclosure, which is simple and easy to implement.
  • One end of the reset control switch 406 (TRST transistor) is coupled to the corresponding multiplex control switch 202 on the plurality of detection lines 102 , and the other end is coupled to the follower amplifier 405 .
  • the reset circuit 305 is configured to reset the voltage on the detection line 102 to an initial voltage V int before the integrator 401 starts the integration operation, thereby shortening the time for the detection line 102 to establish a balance phase during integration.
  • the integral sub-circuit 301 shown in FIG. 4C in order to improve the detection efficiency, the integral sub-circuit 301 shown in FIG. In the scheme provided by FIG. 4C, the operations in the data writing phase and the reset phase are the same, the difference lies in the structure and working principle of the integral sub-circuit 301 shown in FIG. 4B and the integral sub-circuit 301 shown in FIG. 4C , wherein the working efficiency of the integral sub-circuit 301 shown in FIG. 4C can be understood to be higher than that of the integral sub-circuit 301 shown in FIG. 4B .
  • An integrator 401, a plurality of voltage acquisition circuits 407, a multi-channel channel selection switch 408, and a digital-to-analog conversion circuit 302 are arranged in the integral sub-circuit as shown in Figure 4C, wherein a plurality of voltage acquisition circuits 407 include at least two groups of voltage acquisition circuits 407.
  • the integrator 401 is configured to perform an integral operation on the current on the detection line 102 to obtain an integrated voltage signal varying with time;
  • At least two groups of voltage acquisition circuits 407 are configured to use one of the group of voltage acquisition circuits 407 to sample the integrated voltage signal of the detection line 102 multiple times to obtain and save multiple sampling points; When the detection line 102 performs current detection, multiple sampling points are obtained from the integrated voltage signals of other detection lines 102 and stored.
  • the multiple sets of voltage acquisition circuits include a first set of voltage acquisition circuits and a second set of voltage acquisition circuits.
  • two sets of voltage acquisition circuits are illustrated in FIG. 4C and FIG. 4D as examples.
  • the first group of voltage acquisition circuits and the second group of voltage acquisition circuits are configured to use one of the group of voltage acquisition circuits to sample the integral voltage signal of the detection line multiple times to obtain and save multiple sampling points; the other group
  • the voltage acquisition circuit performs current detection on the next detection line of the detection line, multiple sampling points are obtained from the integrated voltage signal of the next detection line of the detection line and stored. For example: since the operations in the data writing phase and the reset phase are the same, no further details are given here.
  • the multiplex control switch 202 and the reset switch K1 are in a conducting state, after the capacitor balancing stage ends, in the sampling stage, adopt the first set of voltage
  • the acquisition circuit samples the integral voltage signal of the detection line 1 multiple times to obtain multiple sampling points and saves them, then cuts off the multiplex control switch 202 of the detection line 1, and turns on the multiplex control switch 202 of the detection line 2, This enables the current detection circuit 201 to detect the current of the detection line 2 .
  • the capacitance balance stage is firstly carried out.
  • the second group of voltage acquisition circuits is used to obtain multiple sampling points after sampling the integral voltage signal of the detection line 2 for many times and save them.
  • the digital-to-analog conversion circuit 302 can be controlled to perform analog-to-digital conversion on the sampling points of the detection line 1 stored in the first group of voltage acquisition circuits.
  • the voltage acquisition circuit 407 includes: an acquisition switch and a holding capacitor, wherein: the acquisition switch has one end coupled to the output end of the integrator, and the other end coupled to the first end of the holding capacitor and Multi-channel channel selector switch 408; As shown in Figure 4C, CDS (Compact Digital Switch, compact digital switch) can be adopted as the acquisition switch; the first end of the retention capacitor is coupled with the acquisition switch, and the second end of the retention capacitor is grounded terminal coupling.
  • CDS Compact Digital Switch, compact digital switch
  • the multichannel channel selection switch 408 is coupled to a plurality of voltage acquisition circuits 407 at one end and a digital-to-analog conversion circuit 302 at the other end, and is configured to perform a detection on the next detection line of the detection line in the current detection circuit 201.
  • a group of voltage acquisition circuits that save the sampling points of the detection line are turned on; in some embodiments, the specified timing is that the integral sub-circuit 301 samples the integrated voltage signal of the next detection line 102 of the detection line 102 Before and after the multiplex control switch 202 corresponding to the next detection line 102 of the detection line 102 is in the ON state.
  • the multi-channel selection switch 408 may be a MUX switch, which is manufactured in the same process as the multi-channel selection control switch 202 and is easy to implement.
  • the operations in the data writing phase and the reset phase are the same, we will not repeat them here.
  • the nth detection line is turned on.
  • the multi-channel selection control switch MUX n+1 202 corresponding to the line and the corresponding sensing control switch 303 in the pixel circuit can enable multi-channel channel selection at any stage before the sampling stage for the n+1th detection line
  • the switch 408MUX gates the acquisition switches CDS 1A and CDS 1B
  • a protection circuit 409 is set between the integrator 401 and the voltage acquisition circuit 407, wherein the protection circuit 409 It includes a resistance module and a control switch arranged in parallel, wherein the control switch can be an isolating switch (factroy auto, FA); the resistance module can be a low pass filter (Low Pass Filter, LPF).
  • the control switch can be an isolating switch (factroy auto, FA); the resistance module can be a low pass filter (Low Pass Filter, LPF).
  • the parameters of the electronic devices in the integral sub-circuit 301 need to be adjusted, the parameters of the electronic devices in the integral sub-circuit 301 can be adjusted by adjusting the resistance value of the resistance module LPF.
  • the control switch FA should be turned on before the sampling phase.
  • the voltage difference determination circuit may not be provided in the current detection device.
  • the sampling control switches CDS 1A and CDS 1B are turned on at different integration time points, and the obtained voltages are stored in the storage capacitors C 1A and C 1B respectively;
  • the multi-channel selection control switch 202MUX gates the sampling control switches CDS 1A and CDS 1B , at this time, the voltage in the storage capacitors C 1A and C 1B will pass through the multiple selection control switch 202MUX to the digital-to-analog conversion circuit 302 for digital-to-analog conversion, and at the same time turn on the sampling control switches CDS 2A and CDS 2B at different integration time points, and store the obtained voltages in the storage capacitors C 2A and C 2B respectively.
  • the current detection method provided by the present disclosure may include the following parts: write the grayscale voltage V data on the pixel circuit shown in FIG. A reset phase from the reference voltage V ref to an initial voltage V int , an integration phase for performing an integration operation on the detection line 102 , and a calculation phase for determining the current on the detection line 102 according to the output voltage. These main parts are explained separately below.
  • the gate level Gn of the first switching transistor T2 that is, Gn in FIG. 1A
  • the sensing control switch 303 T 3
  • gate control level Sn that is, Sn in FIG. 1A
  • the gate control signal MUX of the multiplex control switch 202 MUX 1 ⁇ n
  • the gate control signal MUX of the reference level control switch 404 TWR
  • Both pole control levels WR are high level (as shown in FIG. 5B )
  • the sensing control switch 303 (T 3 ) and the multiplex control switch 202 MUX 1 ⁇ n
  • the gray scale voltage V data on the pixel circuit is written into the gate G of the drive transistor T1 in the pixel circuit through the first switch transistor T2, and the reference voltage V ref is controlled by the reference level switch 404 ( TWR), the detection line 102 and the sensing control switch 303 (T 3 ) are written into the source S of the driving transistor T 1 , at this time, the voltage at the gate-source port of the T 1 transistor is shown in formula (4):
  • V GS V data - V ref ;
  • V GS is the voltage of the gate - source port of the T1 tube
  • V data is the gray scale voltage on the pixel circuit
  • V ref is the reference voltage
  • the reference voltage V ref is stored in the storage capacitor C st of the pixel circuit.
  • IT1 is the output current of the driving transistor T1
  • ⁇ represents the mobility
  • Cox represents the capacitance of the gate oxide layer
  • W represents the channel width of the driving transistor T1
  • L represents the channel length of the driving transistor T1.
  • V TH represents the threshold voltage of the driving transistor T1
  • V data represents the grayscale voltage on the pixel circuit
  • V ref represents the reference voltage.
  • the voltages on the reference level control switch 404 (TWR in FIG. 6A ) and the detection line 102 are both the reference voltage V ref in the data writing phase. Since the low-noise operational amplifier OP 1 (not shown in FIG. 6A ) in the integrator 401 needs to detect the voltage on the line 102 to be the initial voltage V int when performing the integration operation, therefore, it needs to be reset by the reset circuit 305 (TRST) in advance. The voltage on the detection line 102 is reset from the reference voltage V ref to the initial voltage V int .
  • the gate level Gn of the first switching transistor T2, the gate control level Sn of the sensing control switch 303, and the gate control level WR signal of the reference level control switch 404 are at low level (As shown in Figure 6B)
  • the multi-way selection control switch 202 and the reset signal (Reset) are high level
  • the multi-way selection control switch 202 and the reset control switch 406 (TRST) are in a conducting state
  • the initial voltage V int is followed by
  • the amplifier OP 2 , the reset control switch 406 (TRST), and the multiplex control switch 202 charge the detection line 102 to reset the level of the detection line 102 from the reference voltage V ref in the data writing phase to the initial voltage V int .
  • the integration control switch K 1 is in the conduction state, and the gate-source port of the sensing control switch 303 exists
  • the junction capacitance, the detection line 102 , the junction capacitance existing at the gate-source port of the multiplex control switch 202 , etc. are reset, and reset to the initial voltage V int .
  • the reset time period is set as the time period from the conduction of the sensing control switch 303 to the conduction of the integral control switch K 1 , which is marked as t 1 .
  • t 1 is determined empirically by those skilled in the art, and t 1 It is related to parameters such as the junction capacitance existing at the gate-source port of the sensing control switch 303 and the junction capacitance existing at the gate-source port of the multiplex control switch 202 .
  • the sampling phase will be described below based on the circuit diagram shown in FIG. 4B and the timing diagram shown in FIG. 12 : when the integration control switch K1 is turned from on to off at the time point B from the start of integration, the low-noise operation in the integrator 401
  • the amplifier OP 1 is in the open-loop integration state, the multiplex control switch 202 (as shown in Figure 12MUX is at a high level) and the sensing control switch 303 (as shown in Figure 12Sn is at a high level) are turned on, and the drive transistor T1 is in the storage capacitor C
  • the driving current output under the action of the voltage stored on st is transmitted to the integrating capacitor C INT through the sensing control switch 303 , the detection line 102 , and the multiplex control switch 202 (MUX).
  • the output voltage V OP1 of the integrator decreases with time. After t s , the output voltage V OP1 of the integrator drops from V int to V A , the K A of the voltage acquisition circuit 402 is turned on, and sampling starts to obtain the acquisition voltage V A , which is stored in the capacitor CA. After a period of time T, the integrated voltage drops from VA to V B , the KB of the voltage acquisition circuit 402 is turned on, and the voltage V B is collected and stored in the capacitor C B.
  • V out (that is, the voltage difference between V A and V B ) as shown in formula (6a):
  • V out V A -V B ; formula (6a)
  • the digital-to-analog conversion circuit 302 receives the output voltage, that is, the voltage difference V out , it converts V out from an electrical signal into a digital signal and outputs it to the controller (not shown in the figure), and the controller uses the capacitance C A and C B , and the output voltage V out (the voltage difference from V A to V B when the integrator is from the time point t s to the time point t s +T when the time difference is T), the average current during this T time period is as the formula As shown in (7a):
  • I T1 is the average current of the T time period
  • C INT represents the integration capacitance
  • V A represents the voltage collected by the voltage acquisition circuit 402 at the time point t s , and is stored in the capacitor C A
  • V B represents the voltage acquisition at the time point t s +T
  • the voltage collected by the circuit 402 is stored in the capacitor C B
  • T represents the time interval between two voltage collections by the voltage collection circuit.
  • the circuit diagram shown in Figure 4D and the timing diagram shown in Figure 13 can also be used.
  • the data writing phase, reset phase, and capacitor balancing phase are all It is the same as that in FIG. 12, and will not be repeated here.
  • the timing diagram of the sampling stage in FIG. 13 will be described below in conjunction with the circuit diagram of FIG. 4D:
  • the integration control switch K 1 is turned on to off, the low-noise operational amplifier OP 1 in the integrator 401 is in the open-loop integration state, and the multiplex control switch 202 (as shown in Figure 13 MUX is at a high level) and the sensing control switch 303 (Sn is at a high level as shown in Figure 13) is turned on, and the driving current output by the driving transistor T1 under the effect of the voltage stored on the storage capacitor Cst passes through the sensing control switch 303, the detection line 102, the multiple The channel selection control switch 202 (MUX) is transmitted to the integrating capacitor C INT . As shown in FIG.
  • the output voltage V OP1 of the integrator decreases with time. After t s , the output voltage V OP1 of the integrator drops from V int to V 1A , the CDS 1A of the voltage acquisition circuit 407 is turned on, and sampling starts to obtain the acquisition voltage V 1A , which is stored in the holding capacitor C 1A . After T time, the integrated voltage drops from V 1A to V 1B , the CDS 1B of the voltage acquisition circuit 407 is turned on, and the voltage V 1B is collected and stored in the holding capacitor C 1B .
  • V out (that is, the voltage of V A and V B difference) as shown in formula (6b):
  • V out V 1A -V 1B ; formula (6b)
  • the digital-to-analog conversion circuit 302 receives the output voltage, that is, the voltage difference V out , converts V out from an electrical signal into a digital signal and outputs it to the controller (not shown in the figure) shown), the controller is based on the capacitors C 1A and C 1B , and the output voltage V out (the voltage difference from V 1A to V 1B when the time difference of the integrator is from t s time point to t s +T time point when the time difference is T) , the average current during this T period is shown in formula (6c):
  • I T1 is the average current of the T time period
  • C INT represents the integration capacitance
  • V 1A represents the voltage collected by the voltage acquisition circuit 402 at the time point t s , and is stored in the capacitor C 1A
  • V 1B represents the voltage acquisition at the time point t s +T
  • the voltage collected by the circuit 402 is stored in the capacitor C 1B
  • T represents the time interval between two voltage collections by the voltage collection circuit.
  • the capacitor balance stage is performed before the integration start time point B. After the capacitor balance stage ends, when K1 is switched from the on state to the off state, the output voltage V OP1 of the integrator decreases with time. After t s , the output voltage V OP1 of the integrator drops from V int to V 2A , the CDS 2A of the voltage acquisition circuit 407 is turned on, and sampling starts to obtain the acquisition voltage V 2A , which is stored in the holding capacitor C 2A . After T time, the integrated voltage drops from V 2A to V 2B , the CDS 2B of the voltage acquisition circuit 407 is turned on, and the voltage V 2B is collected and stored in the holding capacitor C 2B . After V 2A and V 2B are stored in holding capacitors C 2A and C 2B respectively , the voltage difference V out (that is, the voltage of V A and V B difference) as shown in formula (6d):
  • V out V 2A -V 2B ; formula (6d)
  • the voltage acquisition circuit 402 acquires the voltage at time point t, (t+T) time point, (t+2T) time point, (t+3T) time point, and the controller (not shown in the figure)
  • the controller (not shown in the figure)
  • t time point, (t+T) time point, (t+2T) time point, (t+3T) time point respectively corresponding holding capacitors C A , C B , and C C , CD (not shown in the figure out); calculate the voltage difference at the t time point, (t+T) time point and the voltage difference at the (t+2T) time point, (t+3T) time point; according to the t time point, (t+T) time point
  • the voltage difference and the voltage difference at (t+2T) time point and (t+3T) time point determine the average current I T1 , as shown in formula (7b):
  • the 4T1C pixel circuit includes a driving transistor T 1 , a first switching transistor T 2 , a sensing control switch T 3 and a second Two switching transistors T 4 , C st and OLED.
  • the OLED shown in FIG. 1A does not emit light, and the current driving the transistor T1 does not pass through the OLED.
  • the gate level Gn of the first switching transistor T2 is at a high level, the gray scale voltage V data and the reference voltage V ref .
  • the gate level G n of the first switching transistor T 2 is at low level, the voltage of V data -V ref is stored on the storage capacitor C st .
  • the sensing control switch 303 (T 3 ) When the gate control level Sn of the sensing control switch 303 (T 3 ) is high level, the sensing control switch 303 (T 3 ) is in the conduction state, and the gate-source voltage V GS of the driving transistor T 1 is in the storage capacitor
  • the driving current I D is generated under the voltage of V data -V ref stored at both ends of C st as shown in formula (8):
  • the drive current ID flows to the detection line 102 and the integral sub-circuit 301, the drive current ID generates a voltage drop on the load capacitor CL , and the output voltage V output of the integral sub-circuit is shown in formula (9):
  • ⁇ represents the mobility
  • Cox represents the capacitance of the gate oxide layer per unit area
  • W represents the width of the channel of the driving transistor T1
  • L represents the length of the channel of the driving transistor T1.
  • V TH represents the threshold voltage of the driving transistor T1
  • V data represents the grayscale voltage of the pixel circuit
  • V ref represents the reference voltage.
  • the embodiment of the present disclosure is based on the current detection device proposed in the present disclosure, and also proposes a method for improving the accuracy of current detection.
  • the method for improving the accuracy of current detection provided by the embodiment of the present disclosure will be described in detail below based on the integral sub-circuit 301 .
  • step 801 at the first time point before the current detection circuit 201 integrates the detection line 102 (such as the time point where the first integration time point A in Figure 9 and Figure 12 is), control the sensing control switch 303 is in the conduction state; the duration between the first time point and the integration start time point when the current detection circuit 201 starts the integration operation (such as the time point where the second integration time point B is located in Figure 9 and Figure 12 ) is The first time period; in some embodiments, as shown in FIG. 9 , the first time period is t 1 , and the sensing control switch 303 is turned on during the time t 1 before the integration operation.
  • step 802 control the current detection circuit 201 to start integrating the current of the detection line 102 at the integration start time point to obtain the integrated voltage signal corresponding to the detection line 102;
  • step 803 sampling the integrated voltage signal multiple times, and determining the output voltage difference between different sampling points
  • step 804 Based on the output voltage difference, determine the current of the detection line 102.
  • the first duration is related to the following factors including but not limited to: the gate-to-source transition voltage of the multiplex control switch 202, the gate-source parasitic capacitance of the multiplex control switch 202, the detection The parasitic capacitance of the line 102, the load capacitance 103 corresponding to the integral sub-circuit 301 and the detection line 102, the threshold voltage drift caused by device aging, and the like.
  • the first duration is 2-4 microseconds, for example, it may be 2, 2.5, 3.5, or 4 microseconds.
  • the above method is used to turn on the sensing control switch 303 (T 3 ) before the integration operation, effectively avoiding the error of the detected current caused by the junction capacitance.
  • the output voltage of the integral sub-circuit 301 has a linear relationship with the integration time, but since the parasitic load capacitance 103 on the detection line 102 and the open-loop magnification of the integrator 401 cannot be infinite, there is an The capacitive balancing process on the line 102 is detected. During this process, the curve of output voltage and integration time deviates from the linear relationship. In order to improve the accuracy of detection, the capacitance balancing process should be avoided during detection.
  • the time length between the time point when the integrated voltage signal is first sampled and the integration start time point is the second time length, and the second time length is greater than or equal to the time length for establishing equilibrium, wherein the establishment
  • the balance time is the time required for the sensing control switch, the detection circuit, and the detection line to establish a stable balance.
  • the second duration can be used to charge the load capacitance until the load capacitance is in a balanced state before the integral sub-circuit 301 performs an integration operation on the detection line 102; the second duration is shown as t2 in FIG.
  • the second duration can be about 10 microseconds, for example, it can be 8, 9, 10, 11 microseconds.
  • the integration operation can be started at the t3 stage as shown in FIG. 9, the acquisition switch K A is turned on, and at the time point A', the voltage V A at the time point A ' is stored in the holding capacitor CA , the acquisition switch KB is turned on, and at the time point B ', the voltage V B at the time point B' is stored in the holding capacitor C B.
  • the voltage difference at the time point A' and the time point B' can be obtained.
  • the second duration is negatively correlated with the current of the detection line 102 , that is, the smaller the current of the detection line 102 is, the longer the second duration is.
  • Table 1 shows the results of the leakage current obtained from the simulation experiment:
  • V GS is listed as the voltage difference between the gate voltage and the source voltage of the drive transistor T1
  • V is the voltage unit volt (volt, V)
  • C INT is the integral capacitance
  • pF is the capacitance unit picofarad
  • nA is the current unit Naan.
  • the preset value is the current of the detection line 102 calculated by the experimental parameters, that is, the measured current is smaller than the calculated current, and there is a leakage current.
  • the method shown in FIG. 10A is used to correct the current. What needs to be known is that if there is no leakage current in the circuit (that is, the measured current is equal to the calculated current), there is no need to correct the current:
  • step 1001 obtain the current of the detection line 102 and the compensation current of the current flowing through the OLED device;
  • the method of determining the compensation current may be implemented as:
  • the driving voltage value can be determined according to the parameter value of the detection line 102, and the parameter of the detection line 102 when obtaining the driving voltage corresponding to the detection line 102 is the same as the parameter value of the detection line 102 when the integral sub-circuit 301 detects the current of the detection line 102
  • the parameters are consistent. During specific implementation, it can be specifically set by those skilled in the art according to actual application scenarios.
  • the driving voltage corresponding to the detection line 102 can also be determined according to the parameters of the detection line 102 when the current compensation is performed on the detection line 102 for the first time, and stored in a database (not shown in the figure) Afterwards, when the current compensation of the detection line 102 needs to be performed, the driving voltage corresponding to the detection line 102 is directly obtained from the database, and the current compensation is performed according to the driving voltage.
  • step 1002 based on the compensation current, a correction operation is performed on the current of the detection line 102 detected by the integrating sub-circuit 301 . That is, the actual current on the detection line 102 is the sum of the detected current and the compensation current.
  • step 1001B determine the input gray scale voltage
  • step 1002B obtaining the compensation current corresponding to the gray scale voltage
  • step 1003B based on the compensation current, a correction operation is performed on the current of the detection line 102 detected by the integrating sub-circuit 301 .
  • V GS is listed as the voltage difference between the gate voltage and the source voltage of the drive transistor T1
  • V is the voltage unit volt (volt, V)
  • C INT is the integral capacitance
  • pF is the capacitance unit picofarad
  • nA is the current unit Naan.
  • Figure 11 includes: detection lines 102 sense1-sense3, a first multiplex control switch 202 (MUX1), a second multiplex control switch 202 (MUX2), third multiplex control switch 202 (MUX3), load capacitor 103C SL , low-noise operational amplifier OP 1 , reset switch K 1 , integrating capacitor C INT , acquisition switches K A , KB , and holding capacitor C A , C B , followers OP 3 and OP 4 with high input impedance, subtractor OP 5 , resistors R1, R2, R3, R4, digital-to-analog conversion circuit 302, reference level control switch 404 (TWR), reset control switch 406 (TRST), follower amplifier OP 2 , pixel circuit; the pixel circuit is provided with: first switch transistor T 2 , drive transistor T 1 , sensing control switch 303 (T 3 ), capacitor C st , OLED (Fig. 11 Only the sens
  • the timing diagram shown in Figure 12 In the data writing phase, the gate G n of the sensing control switch 303 (T 3 ) corresponding to the detection line 102, the writing voltage and the Sn signal are at a high level, and at this time A switching transistor T 2 and a reference level control switch 404 (TWR) are in a conducting state.
  • the detection voltage of the detection line 102 is V ref , so the multiplex control switch 202 (MUX 1 ) corresponding to the detection line 102 is in a conducting state.
  • the reset signal Reset is at a high level, and at this time, the reset control switch 406 (TRST transistor) is in a conducting state. Reset the detection line 102 voltage to the initial voltage V int .
  • the sensing control switch 303, the multiplex control switch 202 and the reset switch K1 are in a conducting state.
  • the sampling switch K A is turned on to start sampling.
  • the voltage V A is collected and stored in the holding capacitor CA.
  • the voltage acquisition circuit turns on the acquisition switch KB for sampling, and at the time point B ', the voltage V B is acquired and stored in the holding capacitor C B ;
  • FIG. 1A, FIG. 11, and FIG. 12 illustrate the working process of a current detection circuit detecting multiple detection lines. It is assumed that the plurality of detection lines are respectively detection lines 1-n.
  • the pixel circuits to which the detection lines 1-n are respectively coupled perform a data writing phase and a reset phase simultaneously. After the reset phase is over, if the detection line 1 needs to be detected, only the first multiplex control switch 202 (MUX 1 ) coupled to the detection line 1 is kept in a conducting state, and the multiplex selection of the detection line 2-n is cut off. control switch. Then, the subsequent capacitive balancing phase and sampling phase are only performed on the detection line 1 in order to complete the current detection on the detection line 1 .
  • MUX 1 first multiplex control switch
  • the first multiplex control switch 202 (MUX 1 ) coupled to the detection line 1 is turned off; Two multiplex control switch 202 (MUX 2 ), and then complete the capacitance balancing phase and sampling phase for the detection line 2, thereby completing the current detection for the detection line 2.
  • MUX 1 the first multiplex control switch 202 coupled to the detection line 1
  • MUX 2 Two multiplex control switch 202
  • MUX m the capacitance balancing phase and sampling phase for the detection line 2
  • the detection line m is any one of the aforementioned n detection lines
  • only the mth multiplex control switch 202 (MUX m ) coupled to the detection line m is kept in the conducting state. The on state, and then complete the capacitance balancing phase and the sampling phase of the detection line m, thereby completing the current detection of the detection line m.
  • each detection line is individually detected in sequence until the detection of n detection lines is completed.
  • the various stages of each detection line are described: in the data writing stage, the sensing control switch 303 (T 3 ) in the pixel circuit 1 coupled to the detection line 1, the pixel circuit 1
  • the first switching transistor T2 in the current detection circuit is turned on, and at the same time the reference level control switch 404 (TWR) in the current detection circuit is in the conductive state, and the first multiplex control switch 202 (MUX 1 ) coupled with the detection line 1 ) is in the conduction state, the potential of the source of the driving transistor T 1 in the pixel circuit 1 is the reference voltage V ref ; in the reset phase, the first switching transistor T 2 in the pixel circuit 1 and the pixel coupled to the detection line 1
  • the sensing control switch 303 (T 3 ) in the circuit 1 is cut off, while the reset control switch 406 (TRST tube) is in the conduction state, and the potential on the detection line 1 is the initial voltage V int ; in the capacitance balancing stage, the reset control switch 406 (TRST
  • the voltage acquisition circuit turns on the acquisition switch KB for sampling.
  • the voltage V B is collected and stored in the holding capacitor C B ; and according to the voltage at the time point A' and the time point B' difference determines the current in the sense line.
  • the reset control switch 406 (TRST transistor) is turned off ;
  • the second multiplex control switch 202 (MUX 2 ) and the reset switch K 1 are in a conduction state; in the sampling phase, the conduction acquisition switch K A begins to sample , at the time point A', the voltage V A is collected and stored in the holding capacitor C A.
  • the voltage acquisition circuit turns on the acquisition switch KB for sampling.
  • the time point B ' the voltage V B is collected and stored in the holding capacitor C B ; and according to the voltage at the time point A' and the time point B' difference determines the current in the sense line.
  • the sensing control switch 303 (T 3 ) coupled to the detection line 102, the pixel circuit 1.
  • the pixel circuit 2 , pixel circuit 3, ... pixel circuit n respectively corresponding to the first switch transistor T2 conduction, and at the same time the reference level control switch 404 (TWR) in the current detection circuit is in the conduction state,
  • the nth multiple channel selection control switch 202 (MUX n ) coupled to the detection line n are all in a conducting state.
  • the driving transistor T1 in the pixel circuit n The potentials of the sources of both are the reference voltage V ref ; in the reset phase, the first switching transistor T 2 and the sensing control switch 303 (T 3 ) in the pixel circuit 1, the first switching transistor T 2 , the sensing control switch 303 (T 3 ) in the pixel circuit 2
  • the sensing control switch 303 (T 3 ), the first switching transistor T 2 in the pixel circuit 3, the sensing control switch 303 (T 3 ), ... the first switching transistor T 2 in the pixel circuit n, the sensing control switch 303 (T 3 ) are all cut off; at the same time, the reset control switch 406 (TRST tube) is in the conduction state, and the potentials on the detection line 1, detection line 2, detection line 3...
  • detection line n are all reset to the initial voltage V int ; when current detection is performed on the detection line 1 coupled to the first multiplex control switch 202 (MUX 1 ), then in the capacitance balancing stage, the reset control switch 406 (TRST tube) is cut off; the first multiplex control switch 202 (MUX 1 ) is in the conduction state, and the multiplex control switch 202 (MUX) corresponding to other detection lines is in the cut-off state; at the first time point A before the first integration starts, the multiplex control switch 202 (MUX 1 ) and the reset switch K 1 are in the conduction state; after the capacitor balancing stage, the conduction acquisition switch K A starts to sample, and at the time point A', the voltage V A is collected and stored in the holding capacitor CA.
  • the voltage acquisition circuit turns on the acquisition switch KB for sampling.
  • the voltage V B is collected and stored in the holding capacitor C B ; and according to the voltage at the time point A' and the time point B' difference determines the current in the sense line.
  • the second multi-way selection control switch 202 When detection line 2 is detected, the second multi-way selection control switch 202 (MUX 2 ) is in a conducting state, and the multi-way selection control switch 202 (MUX) corresponding to other detection lines is in a cut-off state; At the first time point A before, the second multiplex control switch 202 (MUX 2 ) and the reset switch K 1 are in the conduction state; after the capacitance balance stage, the conduction acquisition switch K A starts to sample, and at the time A' point, the voltage V A is collected and stored in the holding capacitor C A. After T time, the voltage acquisition circuit turns on the acquisition switch KB for sampling.
  • the voltage V B is collected and stored in the holding capacitor C B ; and according to the voltage at the time point A' and the time point B' difference determines the current in the sense line.
  • the detection process for the n detection lines coupled to the detection circuit is the same, and will not be repeated hereafter.
  • the multiplexing of the same current detection device can realize the current detection of multiple detection lines.
  • This application does not limit the number of multiplex control switches 202 (MUX) and detection lines 102, and the subsequent multiplex control switch 202MUX
  • the detection method for the detection lines corresponding to 3 ⁇ n is the same as the detection method for the detection lines corresponding to MUX 1 and MUX 2 , so the subsequent description will not be repeated, but what those skilled in the art need to know is that for the subsequent multiple
  • the detection of the detection lines corresponding to the channel selection control switches 202MUX 2-n still belongs to the protection scope of the present application.
  • the integral sub-circuit 301 includes a multi-channel channel selection switch 408, a plurality of voltage acquisition circuits 407 and a digital-to-analog conversion circuit 302, and a plurality of voltage acquisition circuits 407 includes at least two groups of voltage acquisition circuits 407 (in Figure 4D Only two groups are shown), sampling the integrated voltage signal multiple times, and determining the output voltage difference between different sampling points includes:
  • One of the voltage acquisition circuits 407 is used to sample the integral voltage signal of the detection line multiple times to obtain a plurality of sampling points and save them; when the remaining group of voltage acquisition circuits 407 detects the current of other detection lines, the current detection of other detection lines is performed.
  • the integrated voltage signal is sampled multiple times to obtain multiple sampling points and save them; at the specified timing for current detection on the next detection line of the detection line, control the multi-channel channel selection switch 408 to turn on and save a group of voltages of the sampling points of the detection line Acquisition circuit: acquire multiple sampling points of the detection line through the multi-channel selection switch 408, and determine the output voltage difference based on the multiple sampling points.
  • the specified timing is before the integration sub-circuit 301 samples the integrated voltage signal of the next detection line of the detection line, and the multiplex control switch 202 corresponding to the next detection line of the detection line is in the ON state after.
  • the integration control switch K 1 is turned on to off from the integration start time point B, and the low-noise operational amplifier OP 1 in the integrator 401 is at
  • the multi-way selection control switch 202 (as shown in Figure 13MUX is at a high level) and the sensing control switch 303 (as shown in Figure 13Sn is at a high level) are turned on, and the drive transistor T1 is stored on the storage capacitor Cst
  • the driving current output under the action of the voltage is transmitted to the integrating capacitor C INT through the sensing control switch 303 , the detection line 102 , and the multiplex control switch 202 (MUX).
  • the output voltage V OP1 of the integrator decreases with time.
  • the output voltage V OP1 of the integrator drops from V int to V 1A
  • the CDS 1A of the voltage acquisition circuit 407 is turned on, and sampling starts to obtain the acquisition voltage V 1A , which is stored in the holding capacitor C 1A .
  • the integrated voltage drops from V 1A to V 1B
  • the CDS 1B of the voltage acquisition circuit 407 is turned on, and the voltage V 1B is collected and stored in the holding capacitor C 1B .
  • the multiplexer switch 202 between the detection line 1 and the current detection circuit After saving a plurality of sampling points of the integrated voltage signal of the detection line 1, set the multiplexer switch 202 between the detection line 1 and the current detection circuit to cut-off state, and set the multi-way selector switch 202 between the detection line 2 and the current detection circuit
  • the multi-way selection control switch 202 is set to a conducting state.
  • the detection line 2 is detected, and after the capacitive balance phase is over, when K 1 is switched from the on state to the off state, the output voltage V OP1 of the integrator decreases with time.
  • the output voltage V OP1 of the integrator drops from V int to V 2A , the CDS 2A of the voltage acquisition circuit 407 is turned on, and sampling starts to obtain the acquisition voltage V 2A , which is stored in the holding capacitor C 2A .
  • the integrated voltage drops from V 2A to V 2B , the CDS 2B of the voltage acquisition circuit 407 is turned on, and the voltage V 2B is collected and stored in the holding capacitor C 2B .
  • the method of detecting n detection lines is the same as the above process, and will not be repeated here. That is, when detecting the next detection line, digital-to-analog conversion is performed on the sampled voltage of the current detection line, thereby improving the detection efficiency.
  • an embodiment of the present disclosure also provides a display device, as shown in FIG. 2 , including a display panel 200 and the above-mentioned current detection device; wherein, the display panel 200 includes a display area AA and a non-display area NB; the display area AA includes a plurality of sub-pixels spx and a plurality of detection lines 102 (SL); the non-display area NB includes a predetermined power supply line; wherein, each sub-pixel spx includes a pixel circuit; a column of pixel circuits is coupled to a detection line 102 (SL); explanation is required It is noted that the coupling manner between the display panel 200 and the current detection device can refer to the above description, and will not be repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • circuits or sub-circuits of the apparatus have been mentioned in the above detailed description, such division is only exemplary and not mandatory.
  • the features and functions of two or more circuits described above may be embodied in one circuit.
  • the features and functions of one circuit described above may be further divided to be embodied by a plurality of circuits.
  • the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

Abstract

一种电流检测装置，用于检测检测线（102）的电流，根据检测到电流的差异对像素的灰阶进行补偿，使得像素点的亮度均匀性一致。上述电流检测装置采用积分子电路（301）对检测线（102）进行积分操作，得到输出电压，并根据该输出电压得到该检测线（102）的电流（804）。

Description

一种电流检测装置 技术领域
本申请涉及有机电激光显示技术领域，尤其涉及一种电流检测装置。
背景技术
有机电激光显示(Organic Light-Emitting Diode，OLED)中的驱动管(DTFT)的电学特性的差异，在同一灰阶下引起DTFT的电流出现偏差，因此屏幕的亮度会产生差异，进而显示的画面就会出现亮度不均匀。
相关技术中，大多数采用像素内部自补偿的方法，例如采用6T1C像素电路，需要6个薄膜晶体管(TFT)和1个电容以及6EA信号线，随着客户对显示器件画质要求的提高，相应显示器件的分辨率也越来越高。随着分辨率越高，每个像素点所占的空间越来越小。越来越多的电子器件和控制信号线和有限的像素空间形成了不可调和矛盾。
发明内容
本申请的目的是提供一种电流检测装置，用于检测像素的电流，根据检测到电流的差异对像素的灰阶进行补偿，使得像素点的亮度均匀性一致。
第一方面，本申请实施例提供了一种电流检测装置，所述装置包括：多个检测电路，其中，所述检测电路耦接显示面板中的检测线；
所述检测电路包括电流检测电路；
所述电流检测电路，用于对与所述电流检测电路耦接的检测线上的电流进行检测。
在一些实施例中，所述电流检测电路包括：
积分子电路，所述积分子电路，被配置为对所述检测线上的电流进行积分操作得到积分电压信号，并对所述积分电压信号进行多次采样后，得到不同采样点之间的输出电压差。
在一些实施例中，所述积分子电路包括积分器、至少两个电压采集电路、电压差确定电路和数模转换电路，其中：
所述积分器，被配置为对所述检测线上的电流进行积分操作，得到随时间变化的积分电压信号；
各所述电压采集电路，被配置为对所述积分电压信号进行采样，将采样得到的电压输出给所述电压差确定电路；其中，各所述电压采集电路在时序上依序对所述积分电压信号进行采样；
所述电压差确定电路，被配置为基于各所述电压采集电路采集的电压确定所述输出电压差，并将所述输出电压差发送给所述数模转换电路；
所述数模转换电路，被配置为获取所述输出电压差，并将所述输出电压差由模拟信号转换为数字信号后输出给控制器，以使所述控制器根据所述输出电压差确定所述检测线的电流。
在一些实施例中，所述电压采集电路包括：采集开关，保持电容，其中：
所述采集开关，一端与所述积分器的输出端耦接，另一端耦接所述保持电容的第一端和所述电压差确定电路的输入端；
所述保持电容的所述第一端与所述采集开关耦接，所述保持电容的第二端与接地端耦接。
在一些实施例中，所述电压差确定电路包括：多个减法器；每个所述减法器与两个电压采集电路耦接，其中：
针对任一所述减法器，所述减法器的两个输入端分别耦接一个所述电压采集电路，所述减法器的输出端与所述数模转换电路耦接。
在一些实施例中，所述检测线一端耦接所述电流检测电路，另一端耦接像素电路中的感测控制开关。
在一些实施例中，所述电流检测电路还包括参考电压写入电路和复位电路，其中：
所述参考电压写入电路，一端与至少一条检测线耦接，另一端与参考电压端耦接，所述参考电压写入电路被配置为向所述至少一条检测线写入参考 电压；
所述复位电路，一端与所述至少一条检测线耦接，另一端与初始电压端和积分子电路耦接，所述复位电路被配置为向所述至少一条检测线写入初始电压。
在一些实施例中，所述参考电压写入电路包括：参考电平控制开关；
所述参考电平控制开关，一端与所述至少一条检测线耦接，另一端与所述参考电压端耦接。
在一些实施例中，所述复位电路包括：跟随放大器，复位控制开关；其中：
所述跟随放大器，一端与所述复位控制开关耦接，另一端与所述初始电压端耦接，被配置为在所述复位控制开关处于导通状态时，将所述检测线上的电压复位至所述初始电压；
所述复位控制开关,一端与至少一条检测线耦接，另一端与所述跟随放大器耦接。
在一些实施例中，所述电压差确定电路还包括多个高输入阻抗的跟随器，每个所述减法器的输入端耦接两个所述高输入阻抗的跟随器；
各所述高输入阻抗的跟随器，一端耦接所述减法器，另一端耦接电压采集电路。
在一些实施例中，所述电压差确定电路中还包括第一电阻模块和第二电阻模块，
所述第一电阻模块一端耦接所述减法器的正输入端，另一端耦接一个高输入阻抗的跟随器的输出端；
所述第二电阻模块一端耦接所述减法器的负输入端，另一端耦接另一个高输入阻抗的跟随器的输出端。
在一些实施例中，所述第一电阻模块包括第一电阻和第二电阻，其中，所述第一电阻一端耦接高输入阻抗的跟随器的输出端，另一端耦接所述第二电阻和所述减法器的正输入端，所述第二电阻的另一端耦接接地端；
所述第二电阻模块包括第三电阻和第四电阻，所述第三电阻一端耦接高输入阻抗的跟随器的输出端，另一端耦接所述第四电阻和所述减法器的负输入端，所述第四电阻的另一端耦接所述减法器的输出端。
在一些实施例中，所述电流检测电路包括：
积分子电路，所述积分子电路包括积分器、数模转换电路、多路通道选择开关、多个电压采集电路，其中所述多个电压采集电路包括至少两组电压采集电路，其中：
所述积分器，被配置为对所述检测线上的电流进行积分操作，得到随时间变化的积分电压信号；
所述至少两组电压采集电路，被配置为采用其中一组电压采集电路对所述检测线的积分电压信号进行多次采样后得到多个采样点并保存；由剩余组电压采集电路在对其他检测线进行电流检测时，对所述其他检测线的积分电压信号进行多次采样后得到多个采样点并保存；
所述数模转换电路，被配置为对所述检测线的采样点进行模数转换得到数字信号后输出给控制器，以使所述控制器根据所述数字信号确定所述检测线的电流。
在一些实施例中，所述多组电压采集电路包括第一组电压采集电路和第二组电压采集电路，其中：
所述第一组电压采集电路和第二组电压采集电路，被配置为采用其中一组电压采集电路对所述检测线的积分电压信号进行多次采样后得到多个采样点并保存；由另一组电压采集电路在对所述检测线的下一条检测线进行电流检测时，对所述检测线的下一条检测线的积分电压信号进行多次采样后得到多个采样点并保存。
在一些实施例中，所述积分子电路还包括多路通道选择开关，所述多路通道选择开关，一端耦接所述多个电压采集电路、另一端耦接所述数模转换电路，被配置为在所述电流检测电路对所述检测线的下一条检测线进行电流检测的指定时机，导通保存所述检测线的采样点的一组电压采集电路。
在一些实施例中，所述电流检测电路还包括电压差确定电路，一端耦接所述多路通道选择开关，另一端耦接所述数模转换电路，被配置为确定所述检测线的多个采样点之间的输出电压差；
所述数模转换电路，具体被配置为对所述输出电压差进行模数转换得到所述数字信号。
在一些实施例中，所述指定时机为所述积分子电路对所述检测线的下一条检测线的积分电压信号进行采样之前，且在所述检测线的下一条检测线进行电流检测之后。
在一些实施例中，所述电压采集电路包括：采集开关，保持电容，其中：
所述采集开关，一端与所述积分器的输出端耦接，另一端耦接所述保持电容的第一端和所述多路通道选择开关；
所述保持电容的所述第一端与所述采集开关耦接，所述保持电容的第二端与接地端耦接。
在一些实施例中，所述电压差确定电路包括：多个减法器；每个所述减法器与两个电压采集电路耦接，其中：
针对任一所述减法器，所述减法器的两个输入端通过所述多路通道选择开关分别耦接一个所述电压采集电路，所述减法器的输出端与所述数模转换电路耦接。
在一些实施例中，所述积分子电路还包括保护电路，所述保护电路包括并联设置的电阻模块和控制开关，所述保护电路的一端耦接所述积分器的输出端，另一端耦接各所述电压采集电路。
在一些实施例中，所述检测电路还包括多个多路选择控制开关，其中，
所述多路选择控制开关，一端耦接所述电流检测电路，另一端耦接所述检测线；且不同所述多路选择控制开关在不同时间处于导通状态。
第二方面本申请还提供了一种显示装置，包括：显示面板和如上述任一项所述的电流检测装置；
所述显示面板包括显示区和非显示区；
所述显示区包括多个子像素和多条检测线；其中，各所述子像素包括像素电路；一列所述像素电路耦接一条所述检测线；
所述非显示区包括预定电源线，检测电路的参考电压写入单元和复位电路；
各所述检测电路中的所述电流检测电路的第一端与对应的一条所述检测线耦接。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所介绍的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为本公开实施例提供的电流检测装置的像素电路装置示意图；
图1B为本公开实施例提供的电流检测装置的6T1C内部补偿像素电路装置示意图；
图2为本公开实施例提供的电流检测装置的显示面板示意图；
图3为本公开实施例提供的电流检测装置的装置示意图；
图4A为本公开实施例提供的电流检测装置的装置整体框架示意图；
图4B为本公开实施例提供的电流检测装置的装置整体示意图；
图4C为本公开实施例提供的电流检测装置的装置整体框架示意图；
图4D为本公开实施例提供的电流检测装置的装置整体示意图；
图4E为本公开实施例提供的电流检测装置的装置整体示意图；
图4F为本公开实施例提供的电流检测装置的装置整体示意图；
图5A为本公开实施例提供的电流检测装置的数据写入阶段的电路图；
图5B为本公开实施例提供的电流检测装置的数据写入阶段的时序图；
图6A为本公开实施例提供的电流检测装置的复位阶段的电路图；
图6B为本公开实施例提供的电流检测装置的复位阶段的时序图；
图7为本公开实施例提供的电流检测装置的积分模块示意图；
图8为本公开实施例提供的电流检测装置的控制方法流程图；
图9为本公开实施例提供的电流检测装置的在积分操作前的t1时间将感测控制开关导通的时序图；
图10A为本公开实施例提供的电流检测装置的对电流进行修正的流程图；
图10B为本公开实施例提供的电流检测装置的对不同灰阶下的电流进行修正的流程图；
图11为本公开实施例提供的电流检测装置的装置示意图；
图12为本公开实施例提供的电流检测装置的时序图；
图13为本公开实施例提供的电流检测装置的时序图。
具体实施方式
为了使本领域普通人员更好地理解本公开的技术方案，下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述。
需要说明的是，本公开的说明书和权利要求书的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例能够以除了在这里图示或描述的那些以外的顺序实施。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。 “连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
示例性地，像素电路的晶体管可以为N型也可以为P型，本公开对此不作限定。在本公开实施例中以晶体管是N型为例进行说明，驱动晶体管T 1、第一开关晶体管T 2、感测控制开关(T 3)以及存储电容C st构成如图1A所示3T1C像素电路，通过感测控制开关(T 3)与检测线(sense line，SL)连接。该像素电路通过控制第一开关晶体管T 2导通，以将像素电路的灰阶电压V data写入驱动晶体管T 1的栅极，控制驱动晶体管T 1产生工作电流以驱动电致发光二极管OLED发光。驱动晶体管T 1的驱动电流I DS如下述公式(1)所示：
I DS＝k(V GS-V th) 2＝k(V data-V OLED-V th) 2；其中，
Figure PCTCN2021102538-appb-000001
其中，μ代表迁移率，Cox代表驱动晶体管栅氧化层电容，W代表驱动晶体管T 1的沟道的宽，L代表驱动晶体管T 1的沟道的长。V GS代表驱动晶体管T 1的栅极电压和源极电压的电压差，V th代表驱动晶体管T 1的阈值电压，V data代表数据信号端的数据电压，V OLED代表OLED器件的阳极电压电源端的电压。然而，不同像素间的阈值电压V th和迁移率μ会存在差异，造成同一灰阶下像素亮度不一样。同时随着使用时间的增加，驱动晶体管T 1会出现老化等情况，导致驱动晶体管T 1的阈值电压与迁移率发生漂移，也会加重显示亮度的差异。例如，还需要在如图2所示的显示面板200的显示区AA中设置检测线SL以及在像素电路中设置耦接驱动晶体管T 1的漏极的感测控制开关T 3。并且，如图2所示，一个检测电路耦接多条检测线SL。
OLED、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示面板应用研究领域的热点之一。电致发光二极管一般属于电流驱动型，需要稳定的 电流来驱动其发光。在将电致发光二极管应用于显示面板200中后，通常采用像素电路来驱动电致发光二极管发光。
在具体实施时，在本公开实施例中，如图2所示，显示面板200可以包括：显示区AA(Active area)和AA周围边框部分的非显示区NB。其中显示区AA包括阵列排布的多个像素。每个像素包括多个子像素spx。示例性地，像素可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素中的子像素spx的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，子像素spx可以包括电致发光二极管以及用于驱动电致发光二极管发光的像素电路。其中，电致发光二极管包括层叠设置的阳极、发光功能层以及阴极层。发光功能层可以包括：位于阳极与阴极层之间的空穴注入层、位于空穴注入层与阴极层之间的空穴传输层、位于空穴传输层与阴极层之间的有机发光层、位于有机发光层与阴极层之间的空穴阻挡层、以及位于空穴阻挡层与阴极层之间的电子传输层。
然而，结合图1A与图2所示，显示面板200的显示区AA还具有多条扫描线G，一行子像素spx中的第一开关晶体管T 2耦接一条扫描线，这样使得扫描线和数据线V data(图1A和2中均未示出)以及检测线SL产生交叉，从而使得检测线SL与这些扫描线G之间具有负载电容和线电阻。由于负载电容和线电阻的作用，导致扫描线G上的信号出现波动时，会使检测线SL上传输的电流信号发生变化，从而造成检测到的检测线SL上的电流不准确，进而导致外部补偿不准确，影响画面显示效果。
相关技术中，大多数采用像素内部自补偿的方法，如图1B所示，例如采用6T1C内部补偿像素电路，需要6个薄膜晶体管(Thin Film Transistor，TFT)和1个电容以及6EA(Elementa advance)信号线，随着对显示器件画质要求的提高，相应显示器件的分辨率也越来越高。随着分辨率越高，每个像素所 占的空间越来越小。越来越多的电子器件和控制信号线(包括检测线SL和扫描线G)和有限的像素空间形成了不可调和的矛盾。
除了通过像素内部自补偿的方法补偿外，还有一种外部补偿方法。外部补偿方法即通过外部电路对每个像素电路的驱动晶体管T 1的电学特性如阈值电压、迁移率等，将检测到的每个像素电路的电学参数保存到外部存储器中，显示屏显示驱动时，将这个驱动晶体管T 1的电学参数转换成灰阶电压叠加到显示数据中，使得这个驱动晶体管的电学参数的差异得到补偿。
发明人研究发现，外部补偿方法最重要的一个技术是对像素电路中驱动晶体管T 1的电学参数检测，一般现在有两种检测方法，一种是电压检测，一种是电流检测。其中电压检测的原理是通过像素电路中的驱动晶体管T 1对检测线SL驱动充电，当检测线SL上电压充满时读取检测线SL上的电压，根据该电压就可以推算出驱动晶体管T 1的阈值电压。
一般情况下，像素电路的驱动晶体管T 1是在有限的像素空间尽量增加驱动晶体管T 1的面积，提升驱动晶体管T 1的驱动能力，像素内部自补偿的方法中存储电容(Cs)比较小，驱动晶体管很快可以将存储电容充满。而外部补偿方法中，检测线SL比较长而且和像素的扫描线G以及其他信号线存在交叉，因此存在负载电容和线电阻导致驱动晶体管T 1的检测参数不准确。此外，由于驱动晶体管T 1的驱动电流，随着检测线SL的电压上升，驱动电流减小，因此电压检测方法一般需要很长时间，所以电压检测一般在出厂前或者开机前对显示屏的电学参数进行检测。
有鉴于此，本公开提出了一种电流检测装置及方法，本公开的发明构思可概括为：向像素电路的存储电容C st写入驱动电压，驱动晶体管T 1向检测线SL输出恒定电流，采用积分子电路对该检测线SL的电流进行积分操作，得到输出电压，并根据该输出电压得到该检测线SL的电流。本领域的技术人员需要知道的是，本公开的电流检测装置对应的像素电路包括但不限于为如图1B所示的6T1C内部补偿像素电路，如3T1C、4T1C、5T1C、5T2C等其他具有检测线的像素电路也均适用于本公开，本公开对此不作限定。此外，无论 何种像素电路，该像素电路中与检测线连接的晶体管可称之为感测控制开关T 3。
本公开实施例中提供的电流检测装置包括多个检测电路，在图3中以电流检测装置中的一个检测电路为例进行说明。图3中包括：检测电路101，检测线102(等同于前文所述的检测线SL，后文不再说明)；其中，一个检测电路101对应显示面板中的至少一条检测线102；检测电路101中包括电流检测电路201；检测线102为沿第二方向延伸的金属线，与如图2中所示的沿第一方向延伸的扫描线G之间通过金属材料设置在不同层上，所以这种沿不同方向延伸的线会存在交叉点，检测线102与扫描线G之间的交叉面积以及金属材料会构成一个寄生电容，即如图3所示的寄生负载电容103；
在一些实施例中，可以以横向为第一方向，纵向为第二方向，第一方向X与第二方向Y相交。本公开对第一方向X和第二方向Y的延伸方向，以及这两个方向之间的夹角不作限定。例如，第一方向X与第二方向Y的夹角在70°到90°之间，并包括70°和90°。例如，第一方向X与第二方向Y的夹角为70°、75°、85°、90°或80°等，夹角的具体数值可根据实际情况设定，本公开的实施例对此不作限制。
在本申请实施例中，为了便于选择检测哪条检测线102的电流，所以在检测电路101中还设置了多路选择控制开关202(即图2中的MUX 1～n)，其中，每个多路选择控制开关202对应一条检测线102。
多路选择控制开关202，一端耦接电流检测电路201，另一端耦接对应的检测线102。也即，每个多路选择控制开关202对应至少一条检测线102，通过控制多路选择控制开关202的导通，实现对相应检测线102的检测。
在一些实施例中，多路选择控制开关202可以为：四选一数据选择器、六选一数据选择器、八选一数据选择器(multiplexer，MUX)等，其他具有控制功能的开关均适用于本公开实施例提出的电流检测装置。
电流检测电路201，被配置为对当前处于导通状态的多路选择控制开关202连接的检测线102上的电流进行检测。
实施时，电流检测装置中可包括多个电流检测电路201，每个电流检测电路对应多条检测线102。为了便于理解，下面结合附图对电流检测电路201的具体结构及功能进行详细说明。以一条检测线102一个像素电路及其对应的电流检测电路201为例进行说明，如图4A和图4B所示：
电流检测电路201中包括积分子电路301、参考电压写入电路304、复位电路305；
积分子电路301，被配置为对检测线102上的电流进行积分操作得到积分电压信号；
由于在积分初始阶段，检测线102上的电流除了流向积分子电路301外，还需要对检测线102上的寄生负载电容103进行平衡充电。当达到稳定状态后，检测线102上的电流才能全部流向积分子电路301产生压降，所以检测线102在小电流情况下、在积分开始的建立平衡阶段内(即向寄生负载电容103充电时间段内)，检测到的电流误差比较大。
在一些实施例中，为了消除在积分开始的建立平衡阶段内造成的误差，如图4A和图4B所示，本申请实施例中，积分子电路301中包括积分器401、多个电压采集电路402和电压差确定电路403、数模转换电路302，其中：
积分器401一端与电压采集电路402耦接，另一端分别与初始电压端V INT和多路选择控制开关202耦接，其中，积分器401的第二端耦接多路选择控制开关202，第一端耦接初始电压端V INT。初始电压端V INT配置为提供初始电压V int，积分器401配置为对检测线102上的电流进行积分操作得到随时间变化的积分电压信号。如图4B所示，积分器401包括并联设置的积分控制开关K 1、积分电容C INT和低噪声运放OP 1。低噪声运放OP 1设置有第一端和第二端以及第三端。积分电容C INT和积分控制开关K 1一端耦接低噪声运放OP 1的第二端，另一端耦接低噪声运放OP 1的第三端，且低噪声运放OP 1的第一端耦接初始电压端V INT。第一端可以是正输入端，第二端可以是负输入端，第三端可以是输出端。可选地，第一端可以是负输入端，第二端可以是正输入端，第三端可以是输出端。本申请对此不做限定。
其中，积分控制开关K 1导通时积分器具有复位功能，主要对积分电容C INT上的电荷清零。积分控制开关K 1截止时，积分器401开始工作(即开始进行积分操作)。
如图4A和图4B所示，示出了两个电压采集电路402。如图4B所示，其中一个电压采集电路402包括采集开关K A、保持电容C A，另一个电压采集电路402包括采集开关K B、保持电容C B。电压采集电路402配置为采集积分器401在指定积分时间点的电压以实现对积分电压信号的采样，并将采样得到的电压保存到保持电容C A和C B；其中，不同电压采集电路402对应不同的指定积分时间点，也即保持电容C A和C B存储的是不同积分时间点的电压。为了采集不同积分时间点的电压，本公开在积分子电路301中设置了多个电压采集电路402。为了便于理解，图4A和图4B中以有两个电压采集电路402为例进行说明，其中：
如图4B所示，采集开关K A一端与电压差确定电路403中的高输入阻抗的跟随器OP 3和保持电容C A的第一端耦接，另一端与积分器401的第三端耦接；采集开关K B一端与电压差确定电路403中的高输入阻抗的跟随器OP 4和保持电容C B的第一端耦接，另一端与积分器401的第三端耦接。
电压采集电路402的保持电容C A、C B，第一端分别与对应的采集开关K A、K B耦接，第二端与接地端耦接。如图4B所示，高输入阻抗的跟随器OP 3和OP 4分别通过采集开关K A和K B对积分电压信号进行采样，将不同指定积分时间点的电压V A和V B分别保存在保持电容C A和C B中。
电压差确定电路403，被配置为计算多个电压采集电路402得到的不同采样点的输出电压差，并将该输出电压差发送给数模转换电路302进行数模转换。其中，如图4B所示，电压差确定电路403中设置有：多个减法器OP 5(图4B中仅示出一个)和高输入阻抗的跟随器；其中：
针对任一减法器，该减法器的两个输入端分别耦接两个高输入阻抗的跟随器，该减法器的第三端与数模转换电路302耦接。
各所述高输入阻抗的跟随器，一端耦接所述减法器，另一端耦接电压采 集电路。如图4B所示，减法器OP 5的两个输入端分别耦接高输入阻抗的跟随器OP 3和OP 4。
在本申请实施例中，为了灵活设置减法器OP 5的放大系数，所以在电压差确定电路403中还设置了第一电阻模块和第二电阻模块，如图11所示，其中：第一电阻模块一端耦接减法器的第一端，另一端耦接一个高输入阻抗的跟随器的第三端；第二电阻模块一端耦接减法器的第二端，另一端耦接另一个高输入阻抗的跟随器的第三端。
在一些实施例中，可在上述第一电阻模块和第二电阻模块中设置两个电阻，如图11所示，第一电阻模块包括第一电阻和第二电阻，其中，第一电阻一端耦接高输入阻抗的跟随器的第三端，另一端耦接第二电阻和减法器的第一端，第二电阻的另一端耦接接地端；第二电阻模块包括第三电阻和第四电阻，第三电阻一端耦接高输入阻抗的跟随器的第三端，另一端耦接第四电阻和减法器的第二端，第四电阻的另一端耦接减法器的第三端。但需要知道的是，本公开对第一电阻模块和第二电阻模块中的电阻的数量不作限定。
假设第一积分时间点t获取的检测线的积分电压V A为第一积分电压，第二积分时间点t+T获取的检测线的积分电压V B为第二积分电压，第一积分电压V A和第二积分电压V B分别保存在保持电容C A和C B里，保持电容C A和C B的第一端分别耦接一个高输入阻抗的跟随器OP 3和OP 4，再经过减法器OP 5得到电压差如公式2所示：
V out＝V A-V B；公式(2)
V out表示t时间点和t+T时间点的输出电压差，也就说明在积分时间段T内积分电压的变化是V out＝V A-V B。
在得到输出电压差后要将该输出电压差V out由电信号转换为数字信号，所以本公开在积分子电路301中设置有数模转换电路302以便于输出给控制器，以使控制器根据不同积分时间点的输出电压确定检测线102的电流。
当然需要说明的是，不局限图4A和图4B所示的设置两个电压采集电路402。如在另一实施例中，本公开中还可以设置多个电压采集电路402。每个 电压采集电路在时序上依序对积分电压信号进行采样，得到多个采样点。由相邻两次采样构成一个采样点对，并确定各采样点对中两采样点之间的电压差，由此得到多个电压差，然后对多个电压差求均值即可得到输入电压差。如以4个电压采集电路402为例，第一个电压采集电路402将t时间点的电压保存到保持电容C A，第二个电压采集电路402在开始积分后将(t+T)时间点的电压保存到保持电容C B，第三个电压采集电路402将(t+2T)时间点的电压保存到保持电容C C，第四个电压采集电路402将(t+3T)时间点的电压保存到保持电容C D，由此可以计算t时间点和(t+T)时间点的电压差，(t+2T)时间点和(t+3T)时间点的电压差，然后取平均值得到电压差。以此类推可扩展到更多个电压采集电路402，但需要说明的是，前述例子中T表示采样点之间的时间间隔，时序上依序排列的采样点之间的时间间隔T可以相同，也可以不同，即可以对积分电压信号等间隔采样，也可以非等间隔采样均适用于本申请实施例。
本公开中检测线102与对应的像素电路中的感测控制开关303耦接如图4B所示，感测控制开关303，一端与对应的检测线102耦接，另一端与像素电路的耦接情况如图1A所示(图4B中仅示出感测控制开关303)，其作用已在图1A中说明这里不再赘述。
如图4B所示，参考电压写入电路304的一端与多路选择控制开关202耦接，另一端与参考电压端V REF耦接，参考电压端V REF配置为提供参考电压V ref，参考电压写入电路304包括参考电平控制开关404，参考电平控制开关404的栅极与控制电平WR耦接。如图4B所示，参考电压写入电路304，被配置为通过多路选择控制开关202、检测线102以及感测控制开关303，向像素电路的存储电容C st(如图1A所示的C st)的一端写入参考电压V ref。
在一些实施例中，以参考电平控制开关404为TWR晶体管为例对数据写入阶段进行说明。TWR晶体管与本公开中其他晶体管(如图1A中的驱动晶体管T 1、第一开关晶体管T 2和感测控制开关T 3)及控制开关(如多路选择控制开关202)制作工艺相同，简单易实现；当向像素电路中的驱动晶体管T 1 栅源级写入数据时，参考电压V ref为高电平，感测控制开关303和参考电平控制开关404(TWR管)导通，参考电压端V REF通过参考电平控制开关404(TWR管)、检测线102以及感测控制开关303将参考电压V ref写入到驱动晶体管T 1的源极。控制V ref为高电平时，同时控制第一开关晶体管T 2导通，像素电路上的灰阶电压V data写入到驱动晶体管T 1的栅极。所以在数据写入阶段驱动晶体管T 1的栅源电压如公式3所示：
V GS＝V data-V ref；公式(3)
驱动晶体管T 1输出恒定电流：
Figure PCTCN2021102538-appb-000002
如图4B所示，复位电路305，一端与多路选择控制开关202耦接，另一端与初始电压端V INT和低噪声运放OP 1耦接，被配置为对检测线102的电压进行复位。即对检测线102上的电压进行复位，以将检测线102上的电压复位至初始电压V int。复位电路305中设置有：跟随放大器405，复位控制开关406；其中：
跟随放大器(如图4B中的OP 2)405，一端与复位控制开关406耦接，另一端与初始电压端V INT耦接，被配置为在复位控制开关406处于导通状态时，将检测线102上的电压复位至初始电压V int；
在一些实施例中，以复位控制开关406为TRST管为例，TRST晶体管与本公开中其他晶体管及控制开关制作工艺相同，简单易实现。复位控制开关406(TRST管)一端与多个检测线102上对应的多路选择控制开关202耦接，一端与跟随放大器405耦接。复位电路305被配置为在积分器401开始进行积分操作之前，将检测线102上的电压复位到初始电压V int，从而缩短了检测线102在积分时建立平衡阶段的时间。
在一些实施例中，为了提高检测效率，上述本申请实施例提供的如图4B所示的积分子电路301可替换为如图4C所示的积分子电路301，需要知道的是，图4A与图4C提供的方案中在数据写入阶段和复位阶段的操作是相同的，不同之处在于如图4B所示的积分子电路301和如图4C所示的积分子电路301 的结构和工作原理，其中如图4C所示的积分子电路301的工作效率可理解为高于如图4B所示的积分子电路301。如图4C所示的积分子电路中设置有积分器401,多个电压采集电路407，多路通道选择开关408，数模转换电路302，其中多个电压采集电路407包括至少两组电压采集电路407。
如图4C和图4D所示，积分器401，被配置为对检测线102上的电流进行积分操作，得到随时间变化的积分电压信号；
至少两组电压采集电路407，被配置为采用其中一组电压采集电路407对检测线102的积分电压信号进行多次采样后得到多个采样点并保存；由剩余组电压采集电路407在对其他检测线102进行电流检测时，对其他检测线102的积分电压信号进行多次采样后得到多个采样点并保存。
如在一些实施例中，多组电压采集电路包括第一组电压采集电路和第二组电压采集电路，为了便于说明，在图4C和图4D中有两组电压采集电路为例进行说明。其中：第一组电压采集电路和第二组电压采集电路，被配置为采用其中一组电压采集电路对检测线的积分电压信号进行多次采样后得到多个采样点并保存；由另一组电压采集电路在对检测线的下一条检测线进行电流检测时，对检测线的下一条检测线的积分电压信号进行多次采样后得到多个采样点并保存。例如：由于在数据写入阶段和复位阶段的操作是相同的，在此不再赘述，当采用如图4C所示的积分子电路301对检测线1进行检测时，在数据写入阶段和复位阶段结束后，进行电容平衡阶段，在电容平衡阶段感测控制开关303、多路选择控制开关202和复位开关K 1处于导通状态，电容平衡阶段结束后，在采样阶段，采用第一组电压采集电路对检测线1的积分电压信号进行多次采样后得到多个采样点并保存，然后截止检测线1的多路选择控制开关202，并导通检测线2的多路选择控制开关202，使得电流检测电路201能够对检测线2进行电流检测。在对检测线2进行检测时，首先进行电容平衡阶段，在电容平衡阶段结束后，采用第二组电压采集电路在对检测线2的积分电压信号进行多次采样后得到多个采样点并保存。同时，可控制数模转换电路302对第一组电压采集电路中保存的检测线1的采样点进行 模数转换。
在一些实施例中，如图4D所示，电压采集电路407包括：采集开关，保持电容，其中：采集开关，一端与积分器的输出端耦接，另一端耦接保持电容的第一端和多路通道选择开关408；如图4C所示，可采用CDS(Compact Digital Switch，紧凑型数码开关)作为采集开关；保持电容的第一端与采集开关耦接，保持电容的第二端与接地端耦接。
如图4D所示，多路通道选择开关408，一端耦接多个电压采集电路407、另一端耦接数模转换电路302，被配置为在电流检测电路201对检测线的下一条检测线进行电流检测的指定时机，导通保存检测线的采样点的一组电压采集电路；在一些实施例中，指定时机为积分子电路301对检测线102的下一条检测线102的积分电压信号进行采样之前，且在检测线102的下一条检测线102对应的多路选择控制开关202处于导通状态之后。实施时，对上一条检测线的采样点的模数转换操作，与对下一条检测线进行采样的时间不重叠即可。在一些实施例中，多路通道选择开关408可以为MUX开关，该开关与多路选择控制开关202制作工艺相同，容易实现。
例如：由于在数据写入阶段和复位阶段的操作是相同的，在此不再赘述，如图13中的时序图所示，在对第n条检测线进行检测时，导通第n条检测线对应的多路选择控制开关MUX n202和对应的像素电路中的感测控制开关303,在采样阶段，在不同的积分时间点导通采集开关CDS 1A和CDS 1B，并将得到的电压分别保存在到保持电容C 1A和C 1B中；在对第n+1条检测线进行检测时，截止第n条检测线的多路选择控制开关MUX n202，并导通第n+1条检测线对应的多路选择控制开关MUX n+1202和对应的像素电路中的感测控制开关303,在对第n+1条检测线的采样阶段之前的任一阶段均可使多路通道选择开关408MUX选通采集开关CDS 1A和CDS 1B，保持电容C 1A和C 1B中的电压将通过多路通道选择开关408MUX到电压差确定电路中。
在本申请实施例中，如图4F所示，为了便于控制积分子电路301中的电子器件的参数，所以在积分器401和电压采集电路407之间设置了保护电路 409，其中保护电路409中包括并联设置的电阻模块和控制开关，其中，控制开关可以为隔离开关(factroy auto，FA)；电阻模块可以为低通滤波器(Low Pass Filter，LPF)。在需要调节积分子电路301中的电子器件的参数时可以通过调节电阻模块LPF的电阻值进而实现对积分子电路301中的电子器件的参数的调节。在对检测线102进行电流检测时，在采样阶段之前，要导通该控制开关FA。
在一些实施例中，由于可以先由数模转换电路302对电压直接进行计算从而得到电压差，所以如图4E所示，在电流检测装置中可以不设置电压差确定电路，在对第n条检测线进行检测时，在采样阶段，在不同的积分时间点导通采样控制开关CDS 1A和CDS 1B，并将得到的电压分别保存在到存储电容C 1A和C 1B中；在对第n+1条检测线进行检测时，在采样阶段之前，多路选择控制开关202MUX选通采样控制开关CDS 1A和CDS 1B，此时，存储电容C 1A和C 1B中的电压将通过多路选择控制开关202MUX到数模转换电路302中进行数模转换，同时在不同的积分时间点导通采样控制开关CDS 2A和CDS 2B，并将得到的电压分别保存在到存储电容C 2A和C 2B中。
在介绍了本公开实施例提出的电流检测装置之后，下面结合附图对本公开实施例提供的应用于该电流检测装置的电流检测方法进行详细说明。
本公开提供的电流检测方法可包括以下几部分内容：将如图1A所示的像素电路上的灰阶电压V data写入到驱动晶体管T 1的数据写入阶段、将检测线102上的电压从参考电压V ref复位至初始电压V int的复位阶段、对检测线102进行积分操作的积分阶段、根据输出电压确定检测线102上的电流的计算阶段。下面对这几个主要部分分别进行说明。
如图5A所示的电路图与图5B所示的时序图，在数据写入阶段，第一开关晶体管T 2的栅极电平G n(即图1A中的G n)以及感测控制开关303(T 3)的栅极控制电平Sn(即图1A中的Sn)、多路选择控制开关202(MUX 1～n)的栅极控制信号MUX以及参考电平控制开关404(TWR)的栅极控制电平WR都为高电平(如图5B所示)，此时像素电路(如图5A中的虚线框中所示) 的第一开关晶体管T 2、参考电平控制开关404(TWR)、感测控制开关303(T 3)以及多路选择控制开关202(MUX 1～n)处于导通状态。
如图5A所示像素电路上的灰阶电压V data通过第一开关晶体管T 2写入到像素电路中的驱动晶体管T 1的栅极G，同时参考电压V ref通过参考电平控制开关404(TWR)、检测线102以及感测控制开关303(T 3)写入到驱动晶体管T 1的源级S，此时，T 1管的栅源端口的电压如公式(4)所示：
V GS＝V data-V ref；公式(4)
其中，V GS为T 1管的栅源端口的电压，V data为像素电路上的灰阶电压，V ref为参考电压，同时将参考电压V ref保存到像素电路的存储电容C st中。
在第一开关晶体管T 2管处于截止状态后，在存储电容C st上的电压的驱动下驱动晶体管T 1的输出电流如公式(5)所示：
Figure PCTCN2021102538-appb-000003
其中，I T1为驱动晶体管T 1的输出电流，μ代表迁移率，Cox代表栅氧化层电容，W代表驱动晶体管T 1的沟道的宽，L代表驱动晶体管T 1的沟道的长。V TH代表驱动晶体管T 1的阈值电压，V data代表像素电路上的灰阶电压，V ref代表参考电压。
如图6A所示的电路图和图6B所示的时序图，在数据写入阶段参考电平控制开关404(图6A中的TWR)和检测线102上的电压均为参考电压V ref。由于积分器401中的低噪声运放OP 1(图6A中未示出)在进行积分操作时需要检测线102上的电压为初始电压V int，因此，需要预先通过复位电路305(TRST)将检测线102上的电压从参考电压V ref复位至初始电压V int。
在复位过程中，第一开关晶体管T 2的栅极电平G n、感测控制开关303的栅极控制电平Sn以及参考电平控制开关404的栅极控制电平WR信号为低电平(如图6B所示)，多路选择控制开关202和复位信号(Reset)为高电平，多路选择控制开关202和复位控制开关406(TRST)处于导通状态，初始电压V int通过跟随放大器OP 2、复位控制开关406(TRST)、多路选择控制开关202 向检测线102充电，将检测线102的电平由数据写入阶段的参考电压V ref复位到初始电压V int。
如图4B和图4D所示，当积分器401的积分控制开关K1为导通状态时，低噪声运放OP 1的第三端和第二端短接，积分电容C INT短接，积分电容C INT上电荷复位到0，同时低噪声运放OP 1工作状态为跟随器的状态，低噪声运放OP 1第三端电压为第二端的初始电压V int。
由于像素电路的感测控制开关303(T 3)的栅源端口存在结电容，当感测控制开关303的栅极控制电平Sn由低电平提升到高电平时，结电容上的电荷会释放到检测线102上，从而引起积分子电路301输出发生跳变。
因此，如图4B、图4D和图9所示，需要确保在积分子电路301开始进行积分操作之前，使得积分控制开关K 1处于导通状态，对感测控制开关303的栅源端口存在的结电容、检测线102、多路选择控制开关202的栅源端口存在的结电容等进行复位，并复位至初始电压V int。设定该复位时间段为感测控制开关303导通到积分控制开关K 1导通的时间段，标记为t 1，需要知道的是，t 1由本领域的技术人员根据经验确定，且t 1与感测控制开关303的栅源端口存在的结电容、多路选择控制开关202的栅源端口存在的结电容等参数相关。
下面首先基于图4B所示的电路图和图12所示的时序图，对采样阶段进行说明：在从积分开始时间点B积分控制开关K 1由导通到截止，积分器401中的低噪声运放OP 1处于开环积分状态，多路选择控制开关202(如图12MUX处于高电平)和感测控制开关303(如图12Sn处于高电平)导通，驱动晶体管T 1在存储电容C st上存储的电压的作用下输出的驱动电流经过感测控制开关303、检测线102、多路选择控制开关202(MUX)传输至积分电容C INT。如图12所示，当K 1由导通状态切换到截止状态时，积分器的输出电压V OP1随着时间下降。经过t s时长积分器的输出电压V OP1从V int下降到V A，电压采集电路402的K A导通，开始进行采样得到采集电压V A，并保存在电容C A中。再经过T时长，积分电压从V A下降到V B，电压采集电路402的K B导通，采集到电压V B并保存在电容C B中。
V A和V B分别保存在电容C A和C B里后，经过高输入阻抗的跟随器OP 3和OP 4，以及减法器OP 5得到电压差V out(即V A和V B的电压差)如公式(6a)所示：
V out＝V A-V B；公式(6a)
如图4B所示，数模转换电路302接收到输出电压即电压差V out后，将V out由电信号转换为数字信号输出给控制器(图中未示出)，控制器根据电容C A和C B，以及输出电压V out(积分器从t s时间点到t s+T时间点，时间差为T时，从V A到V B的电压差)，这T时间段的平均电流如公式(7a)所示：
Figure PCTCN2021102538-appb-000004
其中，I T1为T时间段平均电流，C INT表示积分电容，V A表示t s时间点电压采集电路402采集的电压，保存在电容C A中，V B表示t s+T时间点电压采集电路402采集的电压，保存在电容C B中，T表示电压采集电路两次采集电压的时间间隔。
除了采用如图4B所示的电路图，还可采用如图4D所示的电路图和图13所示的时序图，在图13所示的时序图中数据写入阶段、复位阶段、电容平衡阶段均与图12中相同，在此不再赘述，下面结合图4D的电路图对图13中的采样阶段的时序图进行说明：
在从积分开始时间点B积分控制开关K 1由导通到截止，积分器401中的低噪声运放OP 1处于开环积分状态，多路选择控制开关202(如图13MUX处于高电平)和感测控制开关303(如图13Sn处于高电平)导通，驱动晶体管T 1在存储电容C st上存储的电压的作用下输出的驱动电流经过感测控制开关303、检测线102、多路选择控制开关202(MUX)传输至积分电容C INT。如图13所示，当K 1由导通状态切换到截止状态时，积分器的输出电压V OP1随着时间下降。经过t s时长积分器的输出电压V OP1从V int下降到V 1A，电压采集电路407的CDS 1A导通，开始进行采样得到采集电压V 1A，并保存在保持电容C 1A中。再经过T时长，积分电压从V 1A下降到V 1B，电压采集电路407的CDS 1B 导通，采集到电压V 1B并保存在保持电容C 1B中。
V 1A和V 1B分别保存在保持电容C 1A和C 1B里后，经过高输入阻抗的跟随器OP 3和OP 4，以及减法器OP 5得到电压差V out(即V A和V B的电压差)如公式(6b)所示：
V out＝V 1A-V 1B；公式(6b)
在对下一条检测线进行检测时，如图4D所示，数模转换电路302接收到输出电压即电压差V out后，将V out由电信号转换为数字信号输出给控制器(图中未示出)，控制器根据电容C 1A和C 1B，以及输出电压V out(积分器从t s时间点到t s+T时间点，时间差为T时，从V 1A到V 1B的电压差)，这T时间段的平均电流如公式(6c)所示：
Figure PCTCN2021102538-appb-000005
其中，I T1为T时间段平均电流，C INT表示积分电容，V 1A表示t s时间点电压采集电路402采集的电压，保存在电容C 1A中，V 1B表示t s+T时间点电压采集电路402采集的电压，保存在电容C 1B中，T表示电压采集电路两次采集电压的时间间隔。在保存检测线1的积分电压信号的多个采样点之后，将检测线1和电流检测电路之间的多路选择开关202设置为截止状态，并将检测线2和电流检测电路之间的多路选择控制开关202设置为导通状态。在积分开始时间点B之前进行电容平衡阶段，电容平衡阶段结束后，当K 1由导通状态切换到截止状态时，积分器的输出电压V OP1随着时间下降。经过t s时长积分器的输出电压V OP1从V int下降到V 2A，电压采集电路407的CDS 2A导通，开始进行采样得到采集电压V 2A，并保存在保持电容C 2A中。再经过T时长，积分电压从V 2A下降到V 2B，电压采集电路407的CDS 2B导通，采集到电压V 2B并保存在保持电容C 2B中。V 2A和V 2B分别保存在保持电容C 2A和C 2B里后，经过高输入阻抗的跟随器OP 3和OP 4，以及减法器OP 5得到电压差V out(即V A和V B的电压差)如公式(6d)所示：
V out＝V 2A-V 2B；公式(6d)
在一些实施例中，电压采集电路402采集t时间点、(t+T)时间点、(t+2T)时间点、(t+3T)时间点的电压，控制器(图中未示出)根据t时间点、(t+T)时间点、(t+2T)时间点、(t+3T)时间点分别对应的保持电容C A、C B、和C C、C D(图中未示出)；计算t时间点、(t+T)时间点的电压差和(t+2T)时间点、(t+3T)时间点的电压差；根据t时间点、(t+T)时间点的电压差和(t+2T)时间点、(t+3T)时间点的电压差确定平均电流I T1，如公式(7b)所示：
Figure PCTCN2021102538-appb-000006
在相关技术中，一般情况下，电流检测采用积分模块来实现，如图7所示，其中4T1C像素电路中包括，驱动晶体管T 1、第一开关晶体管T 2、感测控制开关T 3和第二开关晶体管T 4、C st和OLED。
在电流检测阶段，图1A中所示的OLED不发光，驱动晶体管T 1的电流不会通过OLED。第一开关晶体管T 2的栅极电平G n为高电平时，向驱动晶体管T 1的栅极、源极以及存储电容C st两端写入像素电路的灰阶电压V data和参考电压V ref。当第一开关晶体管T 2的栅极电平G n为低电平时，存储电容C st上就保存了V data-V ref的电压。当感测控制开关303(T 3)的栅极控制电平Sn为高电平时，感测控制开关303(T 3)处于导通状态，驱动晶体管T 1的栅源极电压V GS在存储电容C st两端保存的V data-V ref的电压作用下产生驱动电流I D如公式(8)所示：
Figure PCTCN2021102538-appb-000007
驱动电流I D流向检测线102和积分子电路301，该驱动电流I D在负载电容C L上产生压降，积分子电路的输出电压V output如公式(9)所示：
Figure PCTCN2021102538-appb-000008
当驱动电流I D为恒流时，上式可简写为公式(10)：
Figure PCTCN2021102538-appb-000009
其中，μ代表迁移率，Cox代表单位面积栅氧化层电容，W代表驱动晶体 管T 1的沟道的宽，L代表驱动晶体管T 1的沟道的长。V TH代表驱动晶体管T 1的阈值电压，V data代表像素电路的灰阶电压，V ref代表参考电压。
但是采用上述公式可以发现检测线102的电流和仿真电流存在较大差异，且在检测线102的电流越小，差异越大。
因此，本公开实施例基于本公开提出的电流检测装置，还提出了一种提升电流检测精度的方法，下面基于积分子电路301对本公开实施例提供的提升电流检测精度的方法进行详细说明。
由于感测控制开关303(T 3)存在结电容，控制信号MUX电压跳变会引起结电容中电荷向检测线102充放电，有鉴于此，本公开实施例中，采用如图8所示的步骤：
在步骤801中：在电流检测电路201对检测线102进行积分操作前的第一时间点(如图9和图12中的第一积分时间点A点所在的时间点)，控制感测控制开关303处于导通状态；第一时间点与电流检测电路201开始进行积分操作的积分开始时间点(如图9和图12中的第二积分时间点B点所在的时间点)之间的时长为第一时长；在一些实施例中，如图9所示，该第一时长即为t 1，在积分操作前的t 1时间将感测控制开关303导通。
在步骤802中：控制电流检测电路201在积分开始时间点开始对检测线102的电流进行积分操作，得到检测线102对应的积分电压信号；
在步骤803中：对积分电压信号进行多次采样，并确定不同采样点之间的输出电压差；
在步骤804中:基于输出电压差，确定检测线102的电流。
在一些实施例中，该第一时长与包括但不限于的以下因素有关：多路选择控制开关202的栅极与源级的跳变电压、多路选择控制开关202的栅源寄生电容、检测线102的寄生电容、积分子电路301以及检测线102对应的负载电容103、由于器件老化造成的阈值电压漂移等。根据本领域技术人员的经验，一般情况下第一时长为2～4微秒，例如，可以是2、2.5、3.5、4微秒。
在本公开实施例中采用上述方法，在积分操作前导通感测控制开关303 (T 3)，有效的避免了结电容导致的检测的电流的误差。
理想情况下，积分子电路301的输出电压和积分时间呈线性关系，但是由于检测线102上存在的寄生负载电容103以及积分器401的开环放大倍数不可能为无穷大，所以在积分初始阶段存在检测线102上的电容平衡过程。该过程中，输出电压和积分时间的曲线偏移了线性关系，为了提升检测的准确度，检测时应避开电容平衡过程。
有鉴于此，在本公开实施例中，首次对积分电压信号进行采样的时间点与积分开始时间点之间的时长为第二时长，且第二时长大于或等于建立平衡的时长，其中，建立平衡的时长为感测控制开关、检测电路以及与检测线建立稳定平衡所需的时长。可通过该第二时长，在积分子电路301对检测线102进行积分操作前，向负载电容充电，直至负载电容处于平衡状态；该第二时长如图9中的t 2所示，根据本领域技术人员的经验，一般情况下第二时长可以为10微秒左右，例如，可以是8、9、10、11微秒。
在一些实施例中，可在如图9所示的t 3阶段开始积分操作，采集开关K A导通，在A’时间点，将A’时间点的电压V A保存到保持电容C A中，采集开关K B导通，在B’时间点，将B’时间点的电压V B保存到保持电容C B中。从而可以得到A’时间点和B’时间点的电压差。
在一些实施例中，上述第二时长与检测线102的电流呈负相关，即检测线102的电流越小，则该第二时长越长。
影响电流检测精度的还有一个重要的因素是电路存在漏电流，如表1所示为仿真实验得到的漏电流情况的结果：
V GS C INT 积分时长 T 1电流 输出电压 C INT电流 误差
1.0V 0.25pF 5微秒 0.031nA 4.0959V 0.005nA 83.87％
1.2V 0.25pF 5微秒 0.228nA 4.0929V 0.155nA 32.02％
1.4V 0.25pF 5微秒 1.08nA 4.0795V 0.825nA 23.64％
1.6V 0.25pF 5微秒 3.665nA 4.0401V 2.795nA 22.86％
1.8V 0.25pF 5微秒 9.743nA 3.9457V 7.515nA 22.68％
2.0V 0.25pF 5微秒 21.37nA 3.7656V 16.52nA 22.57％
2.2V 0.25pF 5微秒 40.26nA 3.4725V 31.18nA 22.73％
2.4V 0.25pF 5微秒 67.4nA 3.0545V 52.08nA 22.46％
2.5V 0.25pF 5微秒 102.8nA 2.502V 79.7nA 22.58％
表1
其中：V GS列为驱动晶体管T1的栅极电压和源级电压的电压差，V为电压单位伏特(volt，V)；C INT为积分电容，pF为电容的单位皮法；nA为电流单位纳安。
由上表的实验数据以及像素电路中驱动晶体管T 1的栅源电压公式V GS＝V data-V ref可以看出，在不同的灰阶电压V data下，实际检测到的检测线的电流和实际仿真电流存在相近22％的误差，在小电流下误差更大。因此，在本公开实施例中，若电路中存在漏电流则根据指定积分时长分别对应的输出电压，确定检测线102的电流之后，若检测线102的电流小于预设值，则获取检测线102的补偿电流；基于补偿电流对检测线102的电流进行校正操作。其中，预设值为通过实验参数计算得到的检测线102的电流，即测得的电流小于计算得到的电流，则存在漏电流，此时采用如图10A所示的方法来对电流进行修正，需要知道的是，若电路中不存在漏电流(即测得的电流等于计算得到的电流)则无需对电流进行修正：
如图10A所示，在步骤1001中：获取检测线102的电流与流经OLED器件的电流的补偿电流；
在一些实施例中，确定补偿电流的方法可实施为：
向检测线102对应的像素电路中的驱动晶体管T 1写入驱动电压，在驱动晶体管T 1的栅源端形成的栅源电压小于该驱动晶体管T 1的阈值电压V th；向检测线102传输0电流；这时将电流检测装置检测到的检测线102的电流作为补偿电流。
在一些实施例中，该驱动电压值可以根据检测线102的参数值确定，且获取检测线102对应的驱动电压时的检测线102的参数与积分子电路301检测该检测线102的电流时的参数一致。在具体实施时，可由本领域的技术人 员根据实际应用场景具体设定。
在另一实施例中，还可以在第一次对检测线102进行电流补偿时根据该检测线102的参数确定该检测线102对应的驱动电压，并存储在数据库(图中未示出)中，后续在需对该检测线102进行电流补偿时，直接在数据库中获取该检测线102对应的驱动电压，并根据该驱动电压进行电流补偿。
在步骤1002中：基于补偿电流对积分子电路301检测到的检测线102的电流进行校正操作。即检测线102上的实际电流为检测到的电流与补偿电流的和。
本领域的技术人员需要知道的是，在需要提升电流精度时，可采用上述本公开实施例提供的任一一种方法，也可以根据实际应用情况采用多种。
在不同的灰阶电压下，针对每种灰阶电压均可以分别得到对应的补偿电流。实施时，对检测电流进行补偿时的流程图可如图10B所示，包括以下步骤：
在步骤1001B中：确定输入的灰阶电压；
在步骤1002B中：获取该灰阶电压对应的补偿电流；
在步骤1003B中：基于补偿电流对积分子电路301检测到的检测线102的电流进行校正操作。
如表2所示，为本公开实施例采用上述本公开提供的电流检测装置以及补偿电流的方法得到的仿真数据：
Figure PCTCN2021102538-appb-000010
Figure PCTCN2021102538-appb-000011
表2
其中：V GS列为驱动晶体管T1的栅极电压和源级电压的电压差，V为电压单位伏特(volt，V)；C INT为积分电容，pF为电容的单位皮法；nA为电流单位纳安。
由表2可以看出，经过电流补偿后的小电流情况下其检测电流的精度得到了明显的提升。
为了便于理解，下面对本公开实施例提出的电流检测装置的整体结构进行详细说明：
如图11所示，以一个检测电路检测3条检测线为例进行说明，图11中包括：检测线102sense1-sense3、第一多路选择控制开关202(MUX1)、第二多路选择控制开关202(MUX2)、第三多路选择控制开关202(MUX3)、负载电容103C SL、低噪声运放OP 1、复位开关K 1、积分电容C INT、采集开关K A、K B、保持电容C A、C B、高输入阻抗的跟随器OP 3和OP 4、减法器OP 5、电阻R1、R2、R3、R4、数模转换电路302、参考电平控制开关404(TWR)、复位控制开关406(TRST)、跟随放大器OP 2、像素电路；其中像素电路中设置有：第一开关晶体管T 2、驱动晶体管T 1、感测控制开关303(T 3)、电容C st、OLED(图11中仅示出像素电路中的感测控制开关303)。
如图12所示的时序图：在数据写入阶段，与检测线102对应的感测控制开关303(T 3)的栅极G n和写入电压以及Sn信号为高电平，此时第一开关晶体管T 2、参考电平控制开关404(TWR)处于导通状态。
在复位阶段，检测线102的检测电压为V ref，因此与检测线102对应的多路选择控制开关202(MUX 1)处于导通状态。复位信号Reset处于高电平，此时，复位控制开关406(TRST管)处于导通状态。将检测线102电压复位到初始电压V int。
在电容平衡阶段(t1)，感测控制开关303、多路选择控制开关202和复位开关K 1处于导通状态。
在采样阶段(ts+T)，导通采集开关K A开始进行采样，在A’时间点，采集电压V A，并保存在保持电容C A中。再经过T时间，电压采集电路导通采集开关K B进行采样，在B’时间点，采集电压V B，并保存在保持电容C B中；
结合图1A、图11、图12说明一个电流检测电路检测多条检测线的工作过程。假设多条检测线分别为检测线1-n。检测线1-n各自耦接的像素电路同时执行数据写入阶段和复位阶段。复位阶段结束之后，若需要对检测线1进行检测，则仅保留检测线1耦接的第一多路选择控制开关202(MUX 1)处于导通状态，截止检测线2-n的多路选择控制开关。然后，仅对检测线1执行后续的电容平衡阶段和采样阶段，以便于完成对检测线1的电流检测。当完成对检测线1的电流检测之后，截止检测线1耦接的第一多路选择控制开关202(MUX 1)，若需要对检测线2进行检测，则导通检测线2耦接的第二多路选择控制开关202(MUX 2)，然后完成对检测线2的电容平衡阶段和采样阶段，由此完成对检测线2的电流检测。以此类推，若需对检测线m(m是前述n条检测线中任一条检测线)进行检测，则仅保留检测线m耦接的第m多路选择控制开关202(MUX m)处于导通状态，然后完成对检测线m的电容平衡阶段和采样阶段，由此完成对检测线m的电流检测。由此，依序对每条检测线单独进行电流检测，直至完成对n条检测线的检测为止。
以检测线1为例，对每条检测线的各个阶段进行说明：在数据写入阶段，将与检测线1耦接的像素电路1中的感测控制开关303(T 3)、像素电路1中的第一开关晶体管T 2导通，同时将电流检测电路中的参考电平控制开关404(TWR)处于导通状态，与检测线1耦接的第一多路选择控制开关202(MUX 1)处于导通状态，像素电路1中的驱动晶体管T 1的源极的电位为参考电压V ref；在复位阶段，像素电路1中的第一开关晶体管T 2、与检测线1耦接的像素电路1中的感测控制开关303(T 3)截止，同时复位控制开关406(TRST管)处于导通状态，检测线1上的电位为初始电压V int；在电容平衡阶段，将复位 控制开关406(TRST管)截止，在积分开始前的第一时间点A，第一多路选择控制开关202(MUX 1)和复位开关K 1处于导通状态；在采样阶段后，导通采集开关K A开始进行采样，在A’时间点，采集电压V A，并保存在保持电容C A中。再经过T时间，电压采集电路导通采集开关K B进行采样，在B’时间点，采集电压V B，并保存在保持电容C B中；并根据A’时间点和B’时间点的电压差确定该检测线的电流。
因此，当对第二选择控制开关202(MUX 2)对应的检测线2进行检测时，无需再次进行数据写入和复位两个阶段，在电容平衡阶段，将复位控制开关406(TRST管)截止；在第二次积分开始前的第一时间点A，第二多路选择控制开关202(MUX 2)和复位开关K 1处于导通状态；在采样阶段，导通采集开关K A开始进行采样，在A’时间点，采集电压V A，并保存在保持电容C A中。再经过T时间，电压采集电路导通采集开关K B进行采样，在B’时间点，采集电压V B，并保存在保持电容C B中；并根据A’时间点和B’时间点的电压差确定该检测线的电流。
以此类推，扩展到一个检测电路耦接n条检测线、n个像素电路的情况，工作过程为：
当对第一多路选择控制开关202(MUX 1)耦接的检测线1进行检测时，在数据写入阶段，将与检测线102耦接的感测控制开关303(T 3)、像素电路1、像素电路2、像素电路3、……像素电路n中的分别对应的第一开关晶体管T 2导通，同时将电流检测电路中的参考电平控制开关404(TWR)处于导通状态，与检测线1耦接的第一多路选择控制开关202(MUX 1)、与检测线2耦接的第二多路选择控制开关202(MUX 2)、与检测线3耦接的第三多路选择控制开关202(MUX 3)、……与检测线n耦接的第n多路选择控制开关202(MUX n)均处于导通状态。像素电路1中的驱动晶体管T 1的源极、像素电路2中的驱动晶体管T 1的源极、像素电路3中的驱动晶体管T 1的源极、……像素电路n中的驱动晶体管T 1的源极的电位均为参考电压V ref；在复位阶段，像素电路1中的第一开关晶体管T 2、感测控制开关303(T 3)，像素电路2中 的第一开关晶体管T 2、感测控制开关303(T 3)，像素电路3中的第一开关晶体管T 2、感测控制开关303(T 3)，……像素电路n中的第一开关晶体管T 2、感测控制开关303(T 3)均截止；同时复位控制开关406(TRST管)处于导通状态，检测线1、检测线2、检测线3……检测线n上的电位均复位到初始电压V int；当对第一多路选择控制开关202(MUX 1)耦接的检测线1进行电流检测时，则在电容平衡阶段，将复位控制开关406(TRST管)截止；将第一多路选择控制开关202(MUX 1)处于导通状态，其他检测线对应的多路选择控制开关202(MUX)处于截止状态；在第一次积分开始前的第一时间点A，多路选择控制开关202(MUX 1)和复位开关K 1处于导通状态；在电容平衡阶段后，导通采集开关K A开始进行采样，在A’时间点，采集电压V A，并保存在保持电容C A中。再经过T时间，电压采集电路导通采集开关K B进行采样，在B’时间点，采集电压V B，并保存在保持电容C B中；并根据A’时间点和B’时间点的电压差确定该检测线的电流。
对检测线2进行检测时，将第二多路选择控制开关202(MUX 2)处于导通状态，其他检测线对应的多路选择控制开关202(MUX)处于截止状态；在第二次积分开始前的第一时间点A，第二多路选择控制开关202(MUX 2)和复位开关K 1处于导通状态；在电容平衡阶段后，导通采集开关K A开始进行采样，在A’时间点，采集电压V A，并保存在保持电容C A中。再经过T时间，电压采集电路导通采集开关K B进行采样，在B’时间点，采集电压V B，并保存在保持电容C B中；并根据A’时间点和B’时间点的电压差确定该检测线的电流。对检测电路耦接的n个检测线的检测过程相同，后续不在赘述。
能够实现复用同一电流检测装置可以实现对多条检测线的电流检测，本申请对多路选择控制开关202(MUX)以及检测线102的数量不作限定，且对后续的多路选择控制开关202MUX 3～n对应的检测线进行检测时的方法与对MUX 1和MUX 2对应的检测线进行检测的方法相同，因此后续不在进行赘述，但是本领域的技术人员需要知道的是，对后续的多路选择控制开关202MUX 2～n对应的检测线进行检测仍属于本申请的保护范围。
在介绍了采用如图4B所示的积分子电路301对检测线进行检测的方法之后，基于相同的发明构思，下面对采用如图4C、4D所示的积分子电路301对检测线进行检测的方法，由于在数据写入阶段、复位阶段、电容平衡阶段两个积分子电路的处理方法相同，所以在此不再赘述，下面仅对采样阶段进行详细说明：
如图4D所示，积分子电路301中包括多路通道选择开关408、多个电压采集电路407和数模转换电路302，多个电压采集电路407包括至少两组电压采集电路407(图4D中仅示出两组)，对积分电压信号进行多次采样，并确定不同采样点之间的输出电压差包括：
采用其中一组电压采集电路407对检测线的积分电压信号进行多次采样后得到多个采样点并保存；由剩余组电压采集电路407在对其他检测线进行电流检测时，对其他检测线的积分电压信号进行多次采样后得到多个采样点并保存；对检测线的下一条检测线进行电流检测的指定时机，控制多路通道选择开关408导通保存检测线的采样点的一组电压采集电路；通过多路通道选择开关408获取检测线的多个采样点，并基于多个采样点确定输出电压差。
在一些实施例中，指定时机为积分子电路301对检测线的下一条检测线的积分电压信号进行采样之前，且在检测线的下一条检测线对应的多路选择控制开关202处于导通状态之后。
例如：如图4D和图13所示，在对检测线1进行采样时，在从积分开始时间点B积分控制开关K 1由导通到截止，积分器401中的低噪声运放OP 1处于开环积分状态，多路选择控制开关202(如图13MUX处于高电平)和感测控制开关303(如图13Sn处于高电平)导通，驱动晶体管T 1在存储电容C st上存储的电压的作用下输出的驱动电流经过感测控制开关303、检测线102、多路选择控制开关202(MUX)传输至积分电容C INT。如图13所示，当K 1由导通状态切换到截止状态时，积分器的输出电压V OP1随着时间下降。经过t s时长积分器的输出电压V OP1从V int下降到V 1A，电压采集电路407的CDS 1A导通，开始进行采样得到采集电压V 1A，并保存在保持电容C 1A中。再经过T 时长，积分电压从V 1A下降到V 1B，电压采集电路407的CDS 1B导通，采集到电压V 1B并保存在保持电容C 1B中。在保存检测线1的积分电压信号的多个采样点之后，将检测线1和电流检测电路之间的多路选择开关202设置为截止状态，并将检测线2和所述电流检测电路之间的多路选择控制开关202设置为导通状态。对检测线2进行检测，电容平衡阶段结束后，当K 1由导通状态切换到截止状态时，积分器的输出电压V OP1随着时间下降。经过t s时长积分器的输出电压V OP1从V int下降到V 2A，电压采集电路407的CDS 2A导通，开始进行采样得到采集电压V 2A，并保存在保持电容C 2A中。再经过T时长，积分电压从V 2A下降到V 2B，电压采集电路407的CDS 2B导通，采集到电压V 2B并保存在保持电容C 2B中。
对n条检测线进行检测的方式与上述过程相同，在此不在赘述，即对下一条检测线进行检测时，对当前检测线的采样的电压进行数模转换，进而提高了检测的效率。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图2所示，包括显示面板200和上述电流检测装置；其中，显示面板200包括显示区AA和非显示区NB；显示区AA包括多个子像素spx和多条检测线102(SL)；非显示区NB包括预定电源线；其中，各子像素spx包括像素电路；一列像素电路耦接一条检测线102(SL)；需要说明的是，显示面板200和电流检测装置的耦接方式可以参照上述描述，在此不作赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
应当注意，尽管在上文详细描述中提及了装置的若干电路或子电路，但是这种划分仅仅是示例性的并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多电路的特征和功能可以在一个电路中具体化。反之，上文描述的一个电路的特征和功能可以进一步划分为由多个电路来具体化。
此外，尽管在附图中以特定顺序描述了本公开方法的操作，但是，这并非要求或者暗示必须按照该特定顺序来执行这些操作，或是必须执行全部所示的操作才能实现期望的结果。附加地或备选地，可以省略某些步骤，将多个步骤合并为一个步骤执行，和/或将一个步骤分解为多个步骤执行。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (22)

  1. 一种电流检测装置，其中，所述装置包括：多个检测电路，其中，所述检测电路耦接显示面板中的检测线；
    所述检测电路包括电流检测电路；
    所述电流检测电路，用于对与所述电流检测电路耦接的检测线上的电流进行检测。
  2. 根据权利要求1所述的装置，其中，所述电流检测电路包括：
    积分子电路，所述积分子电路，被配置为对所述检测线上的电流进行积分操作得到积分电压信号，并对所述积分电压信号进行多次采样后，得到不同采样点之间的输出电压差。
  3. 根据权利要求2所述的装置，其中，所述积分子电路包括积分器、至少两个电压采集电路、电压差确定电路和数模转换电路，其中：
    所述积分器，被配置为对所述检测线上的电流进行积分操作，得到随时间变化的积分电压信号；
    各所述电压采集电路，被配置为对所述积分电压信号进行采样，将采样得到的电压输出给所述电压差确定电路；其中，各所述电压采集电路在时序上依序对所述积分电压信号进行采样；
    所述电压差确定电路，被配置为基于各所述电压采集电路采集的电压确定所述输出电压差，并将所述输出电压差发送给所述数模转换电路；
    所述数模转换电路，被配置为获取所述输出电压差，并将所述输出电压差由模拟信号转换为数字信号后输出给控制器，以使所述控制器根据所述输出电压差确定所述检测线的电流。
  4. 根据权利要求3所述的装置，其中，所述电压采集电路包括：采集开关，保持电容，其中：
    所述采集开关，一端与所述积分器的输出端耦接，另一端耦接所述保持电容的第一端和所述电压差确定电路的输入端；
    所述保持电容的所述第一端与所述采集开关耦接，所述保持电容的第二端与接地端耦接。
  5. 根据权利要求3所述的装置，其中，所述电压差确定电路包括：多个减法器；每个所述减法器与两个电压采集电路耦接，其中：
    针对任一所述减法器，所述减法器的两个输入端分别耦接一个所述电压采集电路，所述减法器的输出端与所述数模转换电路耦接。
  6. 根据权利要求1所述的装置，其中，所述检测线一端耦接所述电流检测电路，另一端耦接像素电路中的感测控制开关。
  7. 根据权利要求2-6中任一所述的装置，其中，所述电流检测电路还包括参考电压写入电路和复位电路，其中：
    所述参考电压写入电路，一端与至少一条检测线耦接，另一端与参考电压端耦接，所述参考电压写入电路被配置为向所述至少一条检测线写入参考电压；
    所述复位电路，一端与所述至少一条检测线耦接，另一端与初始电压端和积分子电路耦接，所述复位电路被配置为向所述至少一条检测线写入初始电压。
  8. 根据权利要求7所述的装置，其中，所述参考电压写入电路包括：参考电平控制开关；
    所述参考电平控制开关，一端与所述至少一条检测线耦接，另一端与所述参考电压端耦接。
  9. 根据权利要求7所述的装置，其中，所述复位电路包括：跟随放大器，复位控制开关；其中：
    所述跟随放大器，一端与所述复位控制开关耦接，另一端与所述初始电压端耦接，被配置为在所述复位控制开关处于导通状态时，将所述检测线上的电压复位至所述初始电压；
    所述复位控制开关,一端与至少一条检测线，另一端与所述跟随放大器耦接。
  10. 根据权利要求5所述的装置，其中，所述电压差确定电路还包括多个高输入阻抗的跟随器，每个所述减法器的输入端耦接两个所述高输入阻抗的跟随器；
    各所述高输入阻抗的跟随器，一端耦接所述减法器，另一端耦接电压采集电路。
  11. 根据权利要求10所述的装置，其中，所述电压差确定电路中还包括第一电阻模块和第二电阻模块，
    所述第一电阻模块一端耦接所述减法器的正输入端，另一端耦接一个高输入阻抗的跟随器的输出端；
    所述第二电阻模块一端耦接所述减法器的负输入端，另一端耦接另一个高输入阻抗的跟随器的输出端。
  12. 根据权利要求11所述的装置，其中，所述第一电阻模块包括第一电阻和第二电阻，其中，所述第一电阻一端耦接高输入阻抗的跟随器的输出端，另一端耦接所述第二电阻和所述减法器的正输入端，所述第二电阻的另一端耦接接地端；
    所述第二电阻模块包括第三电阻和第四电阻，所述第三电阻一端耦接高输入阻抗的跟随器的输出端，另一端耦接所述第四电阻和所述减法器的负输入端，所述第四电阻的另一端耦接所述减法器的输出端。
  13. 根据权利要求1所述的装置，其中，所述电流检测电路包括：
    积分子电路，所述积分子电路包括积分器、数模转换电路、多个电压采集电路，其中所述多个电压采集电路包括至少两组电压采集电路，其中：
    所述积分器，被配置为对所述检测线上的电流进行积分操作，得到随时间变化的积分电压信号；
    所述至少两组电压采集电路，被配置为采用其中一组电压采集电路对所述检测线的积分电压信号进行多次采样后得到多个采样点并保存；由剩余组电压采集电路在对其他检测线进行电流检测时，对所述其他检测线的积分电压信号进行多次采样后得到多个采样点并保存；所述数模转换电路，被配置 为对所述检测线的采样点进行模数转换得到数字信号后输出给控制器，以使所述控制器根据所述数字信号确定所述检测线的电流。
  14. 根据权利要求13所述的装置，其中，所述多组电压采集电路包括第一组电压采集电路和第二组电压采集电路，其中：
    所述第一组电压采集电路和第二组电压采集电路，被配置为采用其中一组电压采集电路对所述检测线的积分电压信号进行多次采样后得到多个采样点并保存；由另一组电压采集电路在对所述检测线的下一条检测线进行电流检测时，对所述检测线的下一条检测线的积分电压信号进行多次采样后得到多个采样点并保存。
  15. 根据权利要求13所述的装置，其中，所述积分子电路还包括多路通道选择开关，所述多路通道选择开关，一端耦接所述多个电压采集电路、另一端耦接所述数模转换电路，被配置为在所述电流检测电路对所述检测线的下一条检测线进行电流检测的指定时机，导通保存所述检测线的采样点的一组电压采集电路。
  16. 根据权利要求15所述的装置，其中，所述电流检测电路还包括电压差确定电路，一端耦接所述多路通道选择开关，另一端耦接所述数模转换电路，被配置为确定所述检测线的多个采样点之间的输出电压差；
    所述数模转换电路，具体被配置为对所述输出电压差进行模数转换得到所述数字信号。
  17. 根据权利要求15所述的装置，其中，所述指定时机为所述积分子电路对所述检测线的下一条检测线的积分电压信号进行采样之前，且在对所述检测线的下一条检测线进行电流检测之后。
  18. 根据权利要求15所述的装置，其中，所述电压采集电路包括：采集开关，保持电容，其中：
    所述采集开关，一端与所述积分器的输出端耦接，另一端耦接所述保持电容的第一端和所述多路通道选择开关；
    所述保持电容的所述第一端与所述采集开关耦接，所述保持电容的第二 端与接地端耦接。
  19. 根据权利要求15所述的装置，其中，所述电压差确定电路包括：多个减法器；每个所述减法器与两个电压采集电路耦接，其中：
    针对任一所述减法器，所述减法器的两个输入端通过所述多路通道选择开关分别耦接一个所述电压采集电路，所述减法器的输出端与所述数模转换电路耦接。
  20. 根据权利要求13-19任一所述的装置，其中，所述积分子电路还包括保护电路，所述保护电路包括并联设置的电阻模块和控制开关，所述保护电路的一端耦接所述积分器的输出端，另一端耦接各所述电压采集电路。
  21. 根据权利要求1-6、8-19任一所述的装置，其中，所述检测电路还包括多个多路选择控制开关，其中，
    所述多路选择控制开关，一端耦接所述电流检测电路，另一端耦接所述检测线；且不同所述多路选择控制开关在不同时间处于导通状态。
  22. 一种显示装置，其中，包括：显示面板和如权利要求1-21中任一项所述的电流检测装置；
    所述显示面板包括显示区和非显示区；
    所述显示区包括多个子像素和多条检测线；其中，各所述子像素包括像素电路；一列所述像素电路耦接至少一条所述检测线；
    所述非显示区包括电源线，检测电路的参考电压写入电路和复位电路；
    各所述检测电路中的所述电流检测电路的第一端与至少一条所述检测线耦接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108957334A (zh) * 2018-05-18 2018-12-07 华润矽威科技（上海）有限公司 电池采样系统

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107293239A (zh) * 2016-04-08 2017-10-24 乐金显示有限公司 电流感测型感测单元和包括该感测单元的有机发光显示器
US20190147781A1 (en) * 2017-11-16 2019-05-16 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN110969990A (zh) * 2018-09-28 2020-04-07 乐金显示有限公司 电流感测装置以及包括电流感测装置的有机发光显示装置
CN111276100A (zh) * 2018-12-04 2020-06-12 乐金显示有限公司 像素感测装置、包括其的有机发光显示装置及其方法
CN111554220A (zh) * 2020-06-04 2020-08-18 京东方科技集团股份有限公司 感测电路及其校正方法、像素驱动模组及其感测方法
CN111951734A (zh) * 2020-09-02 2020-11-17 京东方科技集团股份有限公司 获取像素单元的电学数据的方法和装置、阵列基板
CN112331113A (zh) * 2019-08-05 2021-02-05 三星电子株式会社 Oled驱动特性检测电路及包括其的oled显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107293239A (zh) * 2016-04-08 2017-10-24 乐金显示有限公司 电流感测型感测单元和包括该感测单元的有机发光显示器
US20190147781A1 (en) * 2017-11-16 2019-05-16 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN110969990A (zh) * 2018-09-28 2020-04-07 乐金显示有限公司 电流感测装置以及包括电流感测装置的有机发光显示装置
CN111276100A (zh) * 2018-12-04 2020-06-12 乐金显示有限公司 像素感测装置、包括其的有机发光显示装置及其方法
CN112331113A (zh) * 2019-08-05 2021-02-05 三星电子株式会社 Oled驱动特性检测电路及包括其的oled显示装置
CN111554220A (zh) * 2020-06-04 2020-08-18 京东方科技集团股份有限公司 感测电路及其校正方法、像素驱动模组及其感测方法
CN111951734A (zh) * 2020-09-02 2020-11-17 京东方科技集团股份有限公司 获取像素单元的电学数据的方法和装置、阵列基板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YIN XINSHE, DONG TIAN, HUANGFU LUJIANG, LIU LIBIN, SHI SHIMING: "P‐22: The Pixel Circuit of Out‐Pixel Compensation for LTPS PMOS OLED Displays", SID SYMPOSIUM DIGEST OF TECHNICAL PAPERS, vol. 50, no. 1, 1 June 2019 (2019-06-01), US , pages 1294 - 1297, XP093016361, ISSN: 0097-966X, DOI: 10.1002/sdtp.13171 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108957334A (zh) * 2018-05-18 2018-12-07 华润矽威科技（上海）有限公司 电池采样系统
CN108957334B (zh) * 2018-05-18 2024-03-08 华润微集成电路(无锡)有限公司 电池采样系统

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