WO2024087098A1 - 坏点修复方法、显示模组及显示装置 - Google Patents

坏点修复方法、显示模组及显示装置 Download PDF

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Publication number
WO2024087098A1
WO2024087098A1 PCT/CN2022/127956 CN2022127956W WO2024087098A1 WO 2024087098 A1 WO2024087098 A1 WO 2024087098A1 CN 2022127956 W CN2022127956 W CN 2022127956W WO 2024087098 A1 WO2024087098 A1 WO 2024087098A1
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Prior art keywords
pixel
sub
circuit
sensing voltage
voltage signal
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PCT/CN2022/127956
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English (en)
French (fr)
Inventor
孟松
毛健
许程
刘苗
姚星
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to PCT/CN2022/127956 priority Critical patent/WO2024087098A1/zh
Publication of WO2024087098A1 publication Critical patent/WO2024087098A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a bad pixel repairing method, a display module and a display device.
  • OLED organic light emitting diodes
  • a display module includes a plurality of sub-pixels, a data line, a source driving circuit and a processor.
  • Each sub-pixel includes a plurality of sub-light-emitting units, each sub-light-emitting unit includes a pixel circuit and at least one light-emitting device, and the data signals received by the plurality of pixel circuits in each sub-pixel are the same.
  • the data line is electrically connected to the sub-pixel.
  • the source driving circuit is electrically connected to the data line.
  • the source driving circuit is configured to output a first data signal or a second data signal to the sub-pixel through the data line, and the voltage of the second data signal is different from the voltage of the first data signal.
  • the processor is electrically connected to the source driving circuit.
  • the processor is configured to determine the position information of the target sub-pixel; and, based on the position information, control the source driving circuit to output the second data signal to the target sub-pixel, so that the brightness of the target sub-pixel is substantially the same as the brightness of the non-target sub-pixel;
  • the target sub-pixel is a sub-pixel in which at least one sub-light-emitting unit does not emit light
  • the non-target sub-pixel is a sub-pixel in which all sub-light-emitting units emit light.
  • the display module further includes a sensing voltage signal line and a sampling sensing circuit.
  • the sensing voltage signal line is electrically connected to the sub-pixel.
  • the sampling sensing circuit is electrically connected to the sensing voltage signal line; the sampling sensing circuit is configured to collect the sensing voltage signal of the pixel circuit through the sensing voltage signal line.
  • the processor is also electrically connected to the sampling sensing circuit; the processor is also configured to determine the sensing voltage signals of all pixel circuits.
  • the display module further includes a scanning signal line and a gate driving circuit.
  • the scanning signal line is electrically connected to the sub-pixel.
  • the gate driving circuit is electrically connected to the scanning signal line.
  • the gate driving circuit is configured to output a scanning signal to the sub-pixel through the scanning signal line.
  • the processor is also electrically connected to the gate driving circuit; the processor is also configured to control the gate driving circuit, the source driving circuit, and the sampling sensing circuit to obtain a sensing voltage signal of at least one pixel circuit in each sub-pixel.
  • the processor is configured to control the gate drive circuit, the source drive circuit, and the sampling sensing circuit to obtain the sensing voltage signals of all the pixel circuits. And the sensing voltage signal of any pixel circuit in the non-target sub-pixel is determined as the sensing voltage signal of all the pixel circuits in the non-target sub-pixel. And, it is determined whether the target sub-pixel is luminous. If so, the sensing voltage signal of any pixel circuit electrically connected to the luminous light-emitting device in the target sub-pixel is determined as the sensing voltage signal of all the pixel circuits in the target sub-pixel. If not, the sensing voltage signal of any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all the pixel circuits in the target sub-pixel.
  • the processor is configured to control the gate drive circuit, the source drive circuit, and the sampling sensing circuit to obtain a sensing voltage signal of a pixel circuit in each sub-pixel.
  • the sensing voltage signal obtained in the non-target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the non-target sub-pixel. And, it is determined whether the difference between the sensing voltage signal obtained in the target sub-pixel and the sensing voltage signal obtained in any adjacent non-target sub-pixel is within a first preset range. If so, the sensing voltage signal obtained in the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel. If not, the sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the processor is configured to control the gate drive circuit, the source drive circuit, and the sampling sensing circuit to obtain an average sensing voltage signal of multiple pixel circuits in each sub-pixel.
  • the average sensing voltage signal obtained in the non-target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the non-target sub-pixel.
  • the average sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the processor is configured to control the source driving circuit to output the second data signal to the pixel circuit connected to the light-emitting device that emits light in the target sub-pixel, and to control the pixel circuit connected to the non-light-emitting device not to output the data signal.
  • the display module includes a scan signal line, and all sub-light-emitting units in the multiple sub-pixels are arranged in multiple rows and columns, each row includes multiple sub-light-emitting units arranged in a first direction, and each column includes multiple sub-light-emitting units arranged in a second direction; the first direction is substantially the same as the extension direction of the scan signal line, and the second direction is substantially the same as the extension direction of the data line.
  • Multiple sub-light-emitting units in the same row are electrically connected to the same scan signal line; multiple sub-light-emitting units in the same column are electrically connected to the same data line.
  • the display module includes a sensing voltage signal line
  • the sub-light-emitting units in the same column are also electrically connected to the same sensing voltage signal line.
  • sub-light emitting units in the same column are divided into a plurality of sub-pixels, and each sub-pixel includes two sub-light emitting units.
  • the pixel circuit includes a driving subcircuit, which is coupled to a first scan signal terminal, a second scan signal terminal, a data signal terminal and a sensing voltage signal terminal; and the driving subcircuit is configured to output a grayscale current signal to the light-emitting device under the control of a first scan signal from the first scan signal terminal and a second scan signal from the second scan signal terminal.
  • the anode of the light-emitting device is coupled to the driving sub-circuit, and the cathode of the light-emitting device is coupled to the second voltage signal terminal.
  • the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device.
  • the anode of the first light-emitting device is coupled to the first voltage signal terminal, and the cathode of the first light-emitting device is coupled to the driving sub-circuit.
  • the anode of the second light-emitting device is coupled to the driving sub-circuit, and the cathode of the second light-emitting device is coupled to the second voltage signal terminal.
  • the driving subcircuit includes a first transistor, a second transistor, a third transistor and a storage capacitor.
  • the control electrode of the first transistor is coupled to the first scan signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is coupled to the first node.
  • the control electrode of the second transistor is coupled to the second scan signal terminal, the first electrode of the second transistor is coupled to the sensing voltage signal terminal, and the second electrode of the second transistor is coupled to the second node.
  • the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the third node, and the second electrode of the third transistor is coupled to the second node.
  • the first plate of the storage capacitor is coupled to the first node, and the second plate of the storage capacitor is coupled to the second node.
  • the pixel circuit when the sub-light-emitting unit includes a pixel circuit and a plurality of light-emitting devices, the pixel circuit also includes a switch sub-circuit, which is coupled to the third scan signal terminal; and the switch sub-circuit is configured to, under the control of a third scan signal from the third scan signal terminal, output a grayscale current signal to the first light-emitting device and the second light-emitting device; or, output the grayscale current signal to the second light-emitting device and not to the first light-emitting device.
  • the display module includes a gate drive circuit and a scan signal line.
  • the third scan signal terminal and the first scan signal terminal are electrically connected to different scan signal lines, and the third scan signal terminal and the second scan signal terminal are electrically connected to different scan signal lines.
  • the switch subcircuit is connected in parallel with the first light-emitting device, and the processor is further configured to determine whether the second light-emitting device is short-circuited. If so, the gate drive circuit is controlled to output a non-working voltage to the third scan signal terminal of the pixel circuit, and the switch subcircuit is turned off, so that the grayscale current signal is output to the first light-emitting device and the second light-emitting device.
  • the gate drive circuit is controlled to output an operating voltage to the third scan signal terminal of the pixel circuit, and the switch subcircuit is turned on, so that the grayscale current signal is output to the second light-emitting device, and not to the first light-emitting device.
  • At least two of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal are coupled to the same scan signal line.
  • an area of a light emitting region of the first light emitting device is greater than an area of a light emitting region of the second light emitting device.
  • a voltage of the second data signal is greater than a voltage of the first data signal.
  • a display device comprising the display panel as described in any one of the above embodiments.
  • a bad pixel repair method is provided.
  • the bad pixel repair method is applied to the display module described in any of the above embodiments, comprising: determining the position of a target sub-pixel. According to the position of the target sub-pixel, controlling the source driving circuit to output the second data signal to the target sub-pixel so that the brightness of the target sub-pixel is substantially the same as the brightness of the non-target sub-pixel.
  • the display module includes a sampling sensing circuit and a gate drive circuit.
  • the bad pixel repair method also includes: controlling the gate drive circuit, the source drive circuit and the sampling sensing circuit to obtain sensing voltage signals of all pixel circuits. And the sensing voltage signal of any pixel circuit in the non-target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the non-target sub-pixel. Determine whether the target sub-pixel is luminous.
  • the sensing voltage signal of any pixel circuit electrically connected to the luminous light-emitting device in the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel; if not, the sensing voltage signal of any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the display module includes a sampling sensing circuit and a gate driving circuit
  • the bad pixel repair method further includes: controlling the gate driving circuit, the source driving circuit and the sampling sensing circuit to obtain a sensing voltage signal of a pixel circuit in each sub-pixel.
  • the sensing voltage signal obtained in the non-target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the non-target sub-pixel. And, it is determined whether the difference between the sensing voltage signal obtained in the target sub-pixel and the sensing voltage signal obtained in any adjacent non-target sub-pixel is within a first preset range.
  • the sensing voltage signal of the pixel circuit in the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel; if not, the sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the display module includes a sampling sensing circuit and a gate driving circuit
  • the bad pixel repair method further includes: controlling the gate driving circuit, the source driving circuit and the sampling sensing circuit to obtain an average sensing voltage signal of multiple pixel circuits in each sub-pixel.
  • the average sensing voltage signal obtained in the non-target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the non-target sub-pixel.
  • the average sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • determining the position of the target sub-pixel includes: receiving image data from an optical device, determining a sub-pixel with lower brightness as a target sub-pixel based on the image data, and acquiring the position of the target sub-pixel.
  • the display module includes a sampling sensing circuit
  • the determining the position of the target sub-pixel includes: receiving a sensing voltage signal group from the sampling sensing circuit; the sensing voltage signal group includes the sensing voltage signals of all pixel circuits. Determining an abnormal sensing voltage signal; the abnormal sensing voltage signal is the difference between the sensing voltage signal in the sensing voltage signal group and other adjacent sensing voltage signals, and is a sensing voltage signal outside a first preset range.
  • the sub-pixel corresponding to the abnormal sensing voltage signal is determined as the target sub-pixel, and the position of the target sub-pixel is obtained.
  • the display module includes a gate drive circuit
  • the sub-light emitting unit includes a pixel circuit, a first light emitting device and a second light emitting device
  • the pixel circuit includes a third scanning signal terminal.
  • the bad pixel repair method also includes: determining whether the second light emitting device is short-circuited. If so, controlling the gate drive circuit to output a non-working voltage to the third scanning signal terminal of the pixel circuit to turn off the switch sub-circuit; if not, controlling the gate drive circuit to output a working voltage to the third scanning signal terminal of the pixel circuit to turn on the switch sub-circuit.
  • a computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed on a computer (eg, a display device), the computer executes the bad pixel repair method as described in any of the above embodiments.
  • a computer program product comprising computer program instructions, and when the computer program instructions are executed on a computer (eg, a display device), the computer program instructions cause the computer to execute the bad pixel repair method as described in any of the above embodiments.
  • a computer program is provided.
  • the computer program When the computer program is executed on a computer (eg, a display device), the computer program enables the computer to execute the bad pixel repair method as described in any one of the above embodiments.
  • FIG1 is a structural diagram of a display device according to some embodiments.
  • FIG2 is a cross-sectional view of a display device according to some embodiments.
  • FIG3 is a circuit block diagram of a display module according to some embodiments.
  • FIG4 is a cross-sectional view of a display panel according to some embodiments.
  • FIG5 is a structural diagram of a display panel according to some embodiments.
  • FIG6A is a circuit diagram of a sub-pixel according to some embodiments.
  • FIG6B is a circuit diagram of another sub-pixel according to some embodiments.
  • FIG6C is a circuit diagram of yet another sub-pixel according to some embodiments.
  • FIG7A is a circuit diagram of a sub-light emitting unit according to some embodiments.
  • FIG7B is a circuit diagram of another sub-light emitting unit according to some embodiments.
  • FIG7C is a circuit diagram of another seed light emitting unit according to some embodiments.
  • FIG8 is a structural diagram of the connection between a sampling sensing circuit and a pixel circuit according to some embodiments.
  • FIG9 is a timing diagram of a pixel circuit in a display period according to some embodiments.
  • FIG. 10 is a timing diagram of a pixel circuit during a compensation sensing period according to some embodiments.
  • FIG11 is a timing diagram of the pixel circuit of the sub-pixel shown in FIG6A in the charging phase and the sampling phase;
  • FIG12 is another timing diagram of the pixel circuit of the sub-pixel shown in FIG6A in the charging phase and the sampling phase;
  • FIG13 is another timing diagram of the pixel circuit of the sub-pixel shown in FIG6A in the charging phase and the sampling phase;
  • FIG14 is a timing diagram of a sub-pixel when all sub-light-emitting units emit light according to some embodiments
  • FIG15 is a timing diagram of a sub-pixel when at least one sub-light-emitting unit does not emit light according to some embodiments
  • 16 to 22 are flow charts of bad pixel repair methods according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled indicates, for example, that two or more components are in direct physical or electrical contact.
  • coupled or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the pixel circuit provided in the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, abbreviated as: TFT), field effect transistors (Metal Oxide Semiconductor, abbreviated as: MOS) or other switching devices with the same characteristics.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the embodiments of the present disclosure are described by taking thin film transistors as an example.
  • the control electrode of each thin film transistor used in the pixel circuit is the gate of the transistor
  • the first electrode is one of the source and drain of the thin film transistor
  • the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiment of the present disclosure can be structurally indistinguishable.
  • the first electrode of the thin film transistor is the source, and the second electrode is the drain;
  • the first electrode of the transistor is the drain, and the second electrode is the source.
  • the storage capacitor may be a storage capacitor device separately manufactured by a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each capacitor electrode of the storage capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc.
  • the storage capacitor may also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or realized by utilizing the parasitic capacitor between the circuits of the circuit itself.
  • the "working level” refers to a level that enables the operated transistor included therein to be turned on
  • the “non-working level” refers to a level that cannot enable the operated transistor included therein to be turned on (i.e., the transistor is turned off).
  • the working level may be higher or lower than the non-working level.
  • the working level corresponds to the level of the square wave pulse portion of the square wave pulse signal
  • the non-working level corresponds to the level of the non-square wave pulse portion.
  • a display device 1000 which may be any device that displays an image, whether in motion (eg, video) or fixed (eg, still image), and whether text or text.
  • the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.
  • a display function such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.
  • PDA personal digital assistant
  • VR virtual reality
  • a display device 1000 includes a display module 100 .
  • the display device 1000 further includes a frame 200 and a cover glass 300 .
  • the longitudinal section of the frame 200 is U-shaped, the cover glass 300 is disposed on the opening side of the frame 200 , and the display module 100 is disposed in the frame 200 .
  • the display module 100 includes a display panel 110 .
  • the display module 100 further includes other electronic components such as a circuit board 120 and a processor 130 .
  • the circuit board 120 is disposed on a side of the display panel 110 away from the cover glass 300 , and the processor 130 can be disposed on the circuit board 120 .
  • the display panel 110 includes a display substrate 10 and an encapsulation layer 20 for encapsulating the display substrate 10 .
  • the display substrate 10 has a light-emitting side and a non-light-emitting side that are arranged opposite to each other, and the encapsulation layer 20 is arranged on the light-emitting side of the display substrate 10, that is, the upper side in FIG4.
  • the encapsulation layer 20 can be an encapsulation film or an encapsulation substrate.
  • the display panel 110 has a display area A and a peripheral area B disposed on at least one side of the display area A.
  • the peripheral area B is disposed around the display area A as an example.
  • the display area A is a region for displaying images and is configured to set a plurality of sub-pixels P.
  • the peripheral area B is a region for not displaying images and is configured to set a display driving circuit, for example, a gate driving circuit 140 and a source driving circuit 150 .
  • the display panel 110 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A. As shown in FIG. 4 and FIG. 5 , the display panel 110 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A. As shown in FIG. 4 and FIG. 5 , the display panel 110 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A. As shown in FIG.
  • the substrate 11 There are many types of the substrate 11, which can be selected according to actual needs.
  • the substrate 11 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a polymethyl methacrylate (PMMA) substrate.
  • PMMA polymethyl methacrylate
  • the substrate 11 may be a flexible substrate.
  • the flexible substrate may be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PI polyimide
  • the plurality of sub-pixels P may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color.
  • the first color, the second color and the third color are three primary colors.
  • the first color is red
  • the second color is blue
  • the third color is green.
  • each sub-pixel P includes a light emitting device 30 and a pixel circuit 40 disposed on a substrate 11 .
  • the structure of the light emitting device 30 includes various types, which can be selected and set according to actual needs.
  • the light emitting device 30 can be an OLED, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) or a micro light emitting diode (Micro Light Emitting Diodes, referred to as Micro LED), etc., which is not specifically limited in the embodiments of the present disclosure.
  • the pixel circuit 40 includes a thin film transistor 400.
  • the thin film transistor includes a semiconductor channel 410, a source electrode 420, a drain electrode 430, and a gate electrode 440.
  • the source electrode 420 and the drain electrode 430 are in contact with the semiconductor channel 410, respectively.
  • source 420 and the drain 430 are interchangeable, that is, 420 in FIG. 4 represents the drain, and 430 in FIG. 4 represents the source.
  • the light-emitting device 30 includes an anode 31, a light-emitting functional layer 32 and a cathode 33.
  • the anode 31 is electrically connected to a source 420 or a drain 430 of a thin film transistor 400 among multiple thin film transistors 400.
  • FIG4 illustrates the electrical connection between the anode 31 and the drain 430 of the thin film transistor 400.
  • the structure of the pixel circuit 40 includes multiple structures, which can be selected and set according to actual needs.
  • the structure of the pixel circuit may include “2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structures.
  • T represents a transistor
  • the number in front of “T” represents the number of transistors
  • C represents a storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the stability of the transistors and the light-emitting device 30 in the pixel circuit 40 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 110, so that the sub-pixel P needs to be compensated.
  • a pixel compensation circuit can be set in the sub-pixel P, so as to use the pixel compensation circuit to perform internal compensation on the sub-pixel P.
  • the driving transistor or the light-emitting device can be sensed by the transistor inside the sub-pixel P, and the sensed data can be transmitted to the external sensing circuit, so as to use the external sensing circuit to calculate the driving voltage value to be compensated and provide feedback, thereby realizing external compensation for the sub-pixel P.
  • the present disclosure takes the external compensation method and the pixel circuit 40 adopting the "3T1C" structure as an example to schematically illustrate the embodiments of the present disclosure, and the details can be found below.
  • the pixel circuit 40 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , and a storage capacitor C. As shown in FIG. 7A , the pixel circuit 40 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , and a storage capacitor C. As shown in FIG. 7A , the pixel circuit 40 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , and a storage capacitor C. As shown in FIG.
  • a control electrode of the first transistor T1 is coupled to the first scan signal terminal G1
  • a first electrode of the first transistor T1 is coupled to the data signal terminal D
  • a second electrode of the first transistor T1 is coupled to the first node N1.
  • the first node N1 does not represent an actual component, but represents a junction point of related electrical connections in the circuit diagram. That is, the first node N1 is a node equivalent to the junction point of related electrical connections in the circuit diagram.
  • a control electrode of the second transistor T2 is coupled to the second scan signal terminal G2 , a first electrode of the second transistor T2 is coupled to the sensing voltage signal terminal S, and a second electrode of the second transistor T2 is coupled to the second node N2 .
  • the second node N2 does not represent an actual component, but represents a junction point of related electrical connections in the circuit diagram. That is, the second node N2 is a node formed by the junction point of related electrical connections in the circuit diagram.
  • the control electrode of the third transistor T3 is coupled to the first node N1
  • the first electrode of the third transistor T3 is coupled to the first voltage signal terminal VDD
  • the second electrode of the third transistor T3 is coupled to the second node N2 .
  • the third transistor T3 is the driving transistor of the 3T1C pixel circuit 40 .
  • a first plate of the storage capacitor C is coupled to the first node N1
  • a second plate of the storage capacitor C is coupled to the second node N2 .
  • the display panel 110 further includes scan signal lines GL, data lines DL, a gate driving circuit 140 and a source driving circuit 150 disposed on the substrate 11 .
  • the gate driving circuit 140 is electrically connected to the pixel circuit 40 in the sub-pixel P through the scanning signal line GL to transmit the scanning signal to the pixel circuit 40;
  • the source driving circuit 150 is electrically connected to the pixel circuit 40 in the sub-pixel P through the data line DL to transmit the data signal to the pixel circuit 40, thereby driving each light-emitting device 30 to emit light.
  • a plurality of sub-pixels P may be arranged in a plurality of rows and columns, each row may include a plurality of sub-pixels P arranged along a first direction X, and each column may include a plurality of sub-pixels P arranged along a second direction Y.
  • the first direction X is the row direction of the plurality of sub-pixels P arranged in an array
  • the second direction Y is the column direction of the plurality of sub-pixels P arranged in an array.
  • sub-pixels P in the same row a plurality of sub-pixels P arranged in a row along the first direction X are referred to as sub-pixels P in the same row, and a plurality of sub-pixels P arranged in a column along the second direction Y are referred to as sub-pixels P in the same column.
  • the scan signal line GL may extend along the first direction X and be electrically connected to the pixel circuit 40 of a row of sub-pixels P; the data line DL may extend along the second direction Y and be electrically connected to the pixel circuit 40 of a column of sub-pixels P.
  • the light-emitting devices in some sub-pixels in the display panel do not emit light, forming bad pixels, resulting in a decrease in display effect; and when the bad pixels exceed the set number, the display panel cannot be shipped as a product, resulting in a decrease in product yield.
  • each sub-pixel P includes a plurality of sub-light-emitting units P′.
  • Each sub-light emitting unit P′ includes a pixel circuit 40 and at least one light emitting device 30 , and the pixel circuit 40 in each sub-light emitting unit P′ is electrically connected to the light emitting device 30 .
  • each sub-light emitting unit P′ includes a pixel circuit 40 and a light emitting device 30 .
  • the pixel circuit 40 includes a driving subcircuit 41, and the driving subcircuit 41 is coupled to the first scanning signal terminal G1, the second scanning signal terminal G2, the data signal terminal D, and the sensing voltage signal terminal S.
  • the driving subcircuit 41 is configured to output a grayscale current signal to the light emitting device 30 under the control of a first scanning signal from the first scanning signal terminal G1 and a second scanning signal from the second scanning signal terminal G2.
  • the anode 31 of the light emitting device 30 is electrically connected to the pixel circuit 40 , and the cathode 33 of the light emitting device 30 is coupled to the second voltage signal terminal VSS.
  • the second voltage signal terminal VSS is configured to receive a DC low-level signal, which is referred to as a second voltage signal herein.
  • the driving sub-circuit 41 may be the above-mentioned 3T1C pixel circuit 40 , that is, the driving sub-circuit 41 may include a first transistor T1 , a second transistor T2 , a third transistor T3 and a storage capacitor C.
  • the anode 31 of the light emitting device 30 is electrically connected to the second node N2, and the cathode 33 of the light emitting device 30 is electrically connected to the second voltage signal terminal VSS.
  • each sub-light emitting unit P′ includes a pixel circuit 40 and a plurality of light emitting devices 30.
  • the plurality of light emitting devices 30 include a first light emitting device 310 and a second light emitting device 320.
  • FIG7B takes the example of a sub-light emitting unit including two light emitting devices.
  • the area of the light-emitting region of the first light-emitting device 310 may be larger than the area of the light-emitting region of the second light-emitting device 320.
  • the failure probability of the first light-emitting device 310 is higher than that of the second light-emitting device 320.
  • the second light-emitting device 320 can still continue to emit light, thereby reducing the risk of each sub-light-emitting unit P' failing to emit light and reducing the risk of the sub-pixel P failing to emit light.
  • the pixel circuit 40 includes a driving subcircuit 41, which is coupled to the first scanning signal terminal G1, the second scanning signal terminal G2, the data signal terminal D, and the sensing voltage signal terminal S.
  • the driving subcircuit is configured to output a grayscale current signal to the light emitting device 30 under the control of a first scanning signal from the first scanning signal terminal G1 and a second scanning signal from the second scanning signal terminal G2.
  • the anode 31 of the first light emitting device 310 is coupled to the first voltage signal terminal VDD, and the cathode 33 of the first light emitting device 310 is coupled to the driving subcircuit 41.
  • the anode 31 of the second light emitting device 320 is coupled to the driving subcircuit 41, and the cathode 33 of the second light emitting device 320 is coupled to the second voltage signal terminal VSS.
  • the first voltage signal terminal VDD is configured to receive a DC high level signal, which is referred to as a first voltage signal.
  • a first voltage signal a DC high level signal
  • the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal.
  • the driving subcircuit 41 may be the above-mentioned 3T1C pixel circuit 40, that is, the driving subcircuit 41 may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C. The first electrode of the third transistor T3 is coupled to the third node N3.
  • the anode 31 of the first light emitting device 310 is coupled to the first voltage signal terminal VDD, and the cathode 33 of the first light emitting device 310 is coupled to the third node N3.
  • the anode 31 of the second light emitting device 320 is coupled to the second node N2, and the cathode 33 of the second light emitting device 320 is coupled to the second voltage signal terminal VSS.
  • each sub-light-emitting unit P' includes at least two light-emitting devices 30, and at least two light-emitting devices 30 are connected in series with the driving sub-circuit 41.
  • the remaining other light-emitting devices 30 can still emit light, reducing the risk of each sub-light-emitting unit P' failing to emit light, thereby reducing the risk of the sub-pixel P failing to emit light, reducing the number of bad pixels, and improving the display effect and product yield.
  • the pixel circuit 40 further includes a switch subcircuit 42, which is coupled to the third scan signal terminal G3.
  • the switch subcircuit 42 is configured to, under the control of the third scan signal from the third scan signal terminal G3, output the grayscale current signal to the first light-emitting device 310 and the second light-emitting device 320; or output the grayscale current signal to the second light-emitting device 320, and not to the first light-emitting device 310.
  • the switch subcircuit 42 is connected in parallel with the first light emitting device 310 .
  • the switching subcircuit 42 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is coupled to the third scan signal terminal G3, the first electrode of the fourth transistor T4 is coupled to the anode 31 of the first light-emitting device 310, and the second electrode of the fourth transistor T4 is coupled to the cathode 33 of the first light-emitting device 310.
  • the grayscale current signal is output to the second light emitting device 320, and is not output to the first light emitting device 310.
  • the fourth transistor T4 is turned off, the grayscale current signal is output to the first light emitting device 310 and the second light emitting device 320.
  • the third scan signal terminal G3 and the first scan signal terminal G1 are electrically connected to different scan signal lines GL
  • the third scan signal terminal G3 and the second scan signal terminal G2 are electrically connected to different scan signal lines GL.
  • the processor 130 is further configured to determine whether the second light emitting device 320 is short-circuited.
  • the gate driving circuit 140 is controlled to output a non-operating voltage to the third scanning signal terminal G3 of the pixel circuit 40, so that the switch sub-circuit 42 is turned off, that is, the grayscale current signal is output to the first light-emitting device 310 and the second light-emitting device 320.
  • the second light-emitting device 320 cannot emit light due to the short circuit, and the first light-emitting device 310 can emit light normally, reducing the risk of the sub-light-emitting unit P' failing to emit light due to the short circuit of the second light-emitting device 320, thereby improving the product yield.
  • the gate driving circuit 140 is controlled to output the working voltage to the third scanning signal terminal of the pixel circuit 40, so that the switch sub-circuit 42 is turned on, that is, the grayscale current signal is output to the second light-emitting device 320, and is not output to the first light-emitting device 310.
  • the first light-emitting device 310 is connected in parallel with the switch sub-circuit 42, the first light-emitting device 310 cannot emit light, and the second light-emitting device 320 can emit light normally, so that the brightness of the sub-pixel P where the first light-emitting device 310 and the second light-emitting device 320 emit light at the same time can be avoided, and the brightness of the sub-pixel P where only the first light-emitting device 310 emits light is significantly different.
  • any one of the first light-emitting device 310 and the second light-emitting device 320 in each sub-pixel P can emit light to achieve the set brightness.
  • At least two of the first scan signal terminal G1 , the second scan signal terminal G2 and the third scan signal terminal G3 are coupled to the same scan signal line GL.
  • the first scan signal terminal G1 and the second scan signal terminal G2 are coupled to the same scan signal line GL, and the second scan signal terminal G2 and the third scan signal terminal G3 are coupled to different scan signal lines GL.
  • the first scanning signal terminal G1 and the second scanning signal terminal G2 are electrically connected to the first scanning signal line GL1.1; and the third scanning signal terminal G3 is electrically connected to the third scanning signal line GL1.3.
  • the processor 130 may still be configured to determine whether the second light emitting device 320 is short-circuited.
  • the gate driving circuit 140 is controlled to output a non-operating voltage to the third scanning signal terminal G3 of the pixel circuit 40, so that the fourth transistor T4 is turned off, and the grayscale current signal is output to the first light-emitting device 310 and the second light-emitting device 320.
  • the second light-emitting device 320 cannot emit light due to the short circuit, and the first light-emitting device 310 can emit light normally, reducing the risk of the sub-light-emitting unit P' failing to emit light due to the short circuit of the second light-emitting device 320, thereby improving the product yield.
  • the gate driving circuit 140 is controlled to output an operating voltage to the third scanning signal terminal G3 of the pixel circuit 40, so that the fourth transistor T4 is turned on, and the grayscale current signal is output to the second light-emitting device 320.
  • the first light-emitting device 310 is connected in parallel with the fourth transistor T4, the first light-emitting device 310 cannot emit light, and the second light-emitting device 320 can emit light normally, so that the brightness of the sub-pixel P where the first light-emitting device 310 and the second light-emitting device 320 emit light at the same time can be avoided, and the brightness of the sub-pixel P where only the first light-emitting device 310 emits light is significantly different.
  • the first light-emitting device 310 or the second light-emitting device 320 can emit light to achieve the set brightness.
  • the first scan signal terminal G1 and the second scan signal terminal G2 are coupled to different scan signal lines GL, and the second scan signal terminal G2 and the third scan signal terminal G3 are coupled to the same scan signal line.
  • the first light emitting device 310 and the second light emitting device 320 emit light simultaneously to reach a set brightness.
  • the first scanning signal terminal G1 is electrically connected to the first scanning signal line GL1.1; the second scanning signal terminal G2 and the third scanning signal terminal G3 are electrically connected to the second scanning signal line GL1.2.
  • all sub-light emitting units P' are arranged in multiple rows and columns, each row includes multiple sub-light emitting units P' arranged in a first direction X, and each column includes multiple sub-light emitting units P' arranged in a second direction Y.
  • first direction X is substantially the same as the extending direction of the scanning signal lines GL
  • second direction Y is substantially the same as the extending direction of the data lines DL.
  • the plurality of sub-light emitting units P' in the same row can be electrically connected to the same scan signal line GL
  • the plurality of sub-light emitting units P' in the same column can be electrically connected to the same data line DL
  • the sub-light emitting units P' in the same column can also be electrically connected to the same sensing voltage signal line SL.
  • multiple sub-light-emitting units P' in the same row can be electrically connected to the same scanning signal line GL, which means that the same scanning signal terminal in the pixel circuit 40 of the multiple sub-light-emitting units P' in the same row is electrically connected to the same scanning signal line GL, and different scanning signal terminals can be electrically connected to different scanning signal terminals.
  • each sub-pixel P may include, for example, two sub-light emitting units P'.
  • two sub-light emitting units P′ in a sub-pixel P are arranged along the second direction Y.
  • Two pixel circuits 40 in a sub-pixel P are electrically connected to the same data line DL.
  • the circuit arrangement in the display module 100 is simple, and the data signals received by the multiple pixel circuits 40 in the sub-pixel P can be the same.
  • any sub-light-emitting unit P' does not emit light
  • the remaining sub-light-emitting units P' can still emit light, which can reduce the risk of each sub-pixel P failing to emit light, reduce the number of bad pixels, and improve display effects and product yields.
  • FIG. 14 is a timing diagram of a sub-pixel when all sub-light-emitting units emit light according to some embodiments;
  • FIG. 15 is a timing diagram of a sub-pixel when at least one sub-light-emitting unit does not emit light according to some embodiments.
  • the first data signal DATA1 is a data signal received by the sub-pixel P to achieve a set brightness when each sub-light-emitting unit P' in the sub-pixel P emits light
  • the second data signal DATA2 is a data signal received by the sub-pixel P to achieve a set brightness when at least one sub-light-emitting unit P' in the sub-pixel P does not emit light.
  • the voltage of the second data signal DATA2 is different from the voltage of the first data signal DATA1, so that the brightness when all the sub-light-emitting units P' in the sub-pixel P emit light is substantially the same as the brightness when all the sub-light-emitting units P' in at least one sub-light-emitting unit in the sub-pixel P do not emit light.
  • the voltage of the second data signal DATA2 is greater than the voltage of the first data signal DATA1 .
  • the source driving circuit 150 is configured to output the first data signal DATA1 or the second data signal DATA2 to the pixel circuit 40 in the sub-pixel P through the data line DL, and the voltage of the second data signal DATA2 is greater than the voltage of the first data signal DATA1.
  • the processor 130 is electrically connected to the source driving circuit 150. Moreover, the processor 130 is configured to determine the position information of the target sub-pixel; and, according to the position information, control the source driving circuit 150 to output the second data signal DATA2 to the target sub-pixel, so that the brightness of the target sub-pixel is substantially the same as the brightness of the non-target sub-pixel.
  • the target sub-pixel is a sub-pixel P in which at least one sub-light emitting unit P' does not emit light
  • the non-target sub-pixel is a sub-pixel P in which all sub-light emitting units P' emit light.
  • the processor 130 can also control the size of the current flowing through the light-emitting device 30 by controlling the size of the data signal output by the source driver circuit 150 to the sub-pixel P, thereby avoiding a significant difference in brightness between the target sub-pixel and the non-target sub-pixel.
  • the processor 130 is further configured to control the source driving circuit 150 to output a second data signal DATA2 to the pixel circuit 40 connected to the light-emitting device 30 that emits light in the target sub-pixel, and to prevent the pixel circuit 40 connected to the light-emitting device 30 that does not emit light from outputting a data signal.
  • the data signal terminal D of the pixel circuit 40 connected to the non-luminous light-emitting device 30 will not be written with a data signal, thereby preventing the pixel circuit 40 from generating a dark current.
  • the display module 100 further includes a sensing voltage signal line SL and a sampling sensing circuit 160 .
  • the sampling sensing circuit 160 is electrically connected to the sensing voltage signal line SL
  • the sensing voltage signal line SL is electrically connected to the sub-pixel P.
  • the sampling sensing circuit 160 is configured to collect the sensing voltage signal of the pixel circuit 40 through the sensing voltage signal line SL.
  • the sampling sensing circuit 160 includes a first switch K1, a second switch K2, a sample hold circuit (Sample Hold Devices, referred to as: S/H), and an analog-to-digital converter (Analog-to-Digital Converter, referred to as: ADC).
  • S/H Sample Hold Devices
  • ADC Analog-to-Digital Converter
  • the sensing voltage signal line SL can be connected to the sampling and holding circuit S/H through the first switch K1, and the sampling and holding circuit S/H is connected to the analog-to-digital converter ADC; and the sensing voltage signal line SL is also connected to the reference voltage terminal VREF through the second switch K2.
  • the first switch K1 is controlled to be turned on and the second switch K2 is turned off, so as to sample the voltage of the second node N2 through the sample-and-hold circuit (S/H) and the analog-to-digital converter (ADC).
  • the first switch K1 is controlled to be turned off and the second switch K2 is controlled to be turned on, so as to input the voltage of the reference voltage terminal VREF to the second node N2.
  • the sampling sensing circuit 160 may be integrated into one chip, and the chip may be disposed in a peripheral area B of the display panel 110 along the extending direction of the sensing voltage signal line SL, for example.
  • the following takes the 3T1C pixel circuit 40 provided in the embodiment of the present invention, in which the first scanning signal terminal G1 and the second scanning signal terminal G2 are connected to different scanning signal lines GL as an example, and the driving process of the pixel circuit 40 is exemplarily described.
  • FIG. 9 is a timing diagram of a pixel circuit in a display period according to some embodiments.
  • FIG. 10 is a timing diagram of a pixel circuit in a compensation sensing period according to some embodiments.
  • a frame period displayed by the display module 100 includes a display period and a compensation sensing period.
  • the display period includes a pixel data writing phase P1 and a light emitting phase P2 .
  • a first scan signal is input to the first scan signal terminal G1, and the first transistor T1 is turned on.
  • a data signal is input to the data signal terminal D through the data line DL, and the data signal is stored in the storage capacitor C through the turned-on first transistor T1.
  • the second scan signal is input to the second scan signal terminal G2, and the second transistor T2 is turned on.
  • the reference voltage of the reference voltage terminal VREF is input to the second node N2 through the sensing voltage signal line SL via the turned-on second transistor T2.
  • the voltage of the first node N1 gradually rises, the third transistor T3 is turned on, the voltage of the second node N2 gradually rises accordingly, and through the bootstrap effect of the storage capacitor C, the voltage of the first node N1 is further raised, the pixel circuit 40 enters the light-emitting stage P2, and the light-emitting device 30 starts to emit light.
  • the aforementioned step of inputting the reference voltage of the reference voltage terminal VREF to the second node N2 via the turned-on second transistor T2 through the sensing voltage signal line SL connected to the second transistor T2 may include:
  • the second switch K2 is controlled to be turned on, and the first switch K1 is turned off, so that the reference voltage of the reference voltage terminal VREF is input to the second node N2 in each pixel circuit 40 of the turned-on row through the turned-on second transistor T2.
  • the compensation sensing period includes a data writing phase S1 , a charging phase S2 , a sampling phase S3 , and a data writing back phase S4 .
  • a scan signal is input to the second scan terminal G2, and the second transistor T2 remains turned on. Also, during the entire compensation sensing period, a data signal is input to the data signal terminal D.
  • a scan signal is input to the first scan terminal G1, the first transistor T1 is turned on, the data signal on the data line DL is input to the first node N1, and stored in the storage capacitor C.
  • the sensing voltage signal line SL inputs a reference voltage to the second node N2 via the turned-on second transistor T2.
  • the step of inputting a reference voltage to the second node N2 through the sensing voltage signal line SL via the turned-on second transistor T2 may include:
  • the second switch K2 connected to the sensing voltage signal line SL connected to each pixel circuit 40 of the currently turned-on row is controlled to be turned on, and all the first switches K1 are controlled to be turned off, so that the reference voltage of the reference voltage terminal VREF is input to the second node N2 in each pixel circuit 40 of the turned-on row through the turned-on second transistor T2.
  • the sensing voltage signal line SL stops inputting the reference voltage to the second node N2, and the second node N2 is in a floating state. At this time, under the action of the voltage of the first node N1, the third transistor T3 is turned on, and the second node N2 starts to charge (that is, the sensing voltage signal line SL is charged).
  • the voltage on the sensing voltage signal line SL remains substantially stable. At this time, the voltage on the sensing voltage signal line SL is collected (that is, the voltage of the second node N2 connected to the sensing voltage signal line SL is collected).
  • the collecting of data by sensing the voltage on the voltage signal line SL may include:
  • the first switch K1 is controlled to be turned on and the second switch K2 is controlled to be turned off, so that the voltage of the second node N2 in each pixel circuit 40 of the turned-on row passes through a sampling and holding circuit (S/H) and is converted by an analog-to-digital converter ADC to obtain a corresponding digital signal.
  • S/H sampling and holding circuit
  • the threshold voltage of the driving transistor can be obtained through subsequent data processing, calculation, etc., and the data signal can be compensated according to the threshold voltage in the subsequent display period for display.
  • a scan signal is input to the first scan signal terminal G1, the first transistor T1 is turned on, and the data signal on the data line DL is input to the first node N1.
  • a reference voltage is input to the second node N2 through the sensing voltage signal line SL via the turned-on second transistor T2.
  • the step of inputting a reference voltage to the second node N2 through the sensing voltage signal line SL via the turned-on second transistor T2 may include:
  • the second switch K2 is controlled to be turned on, and the first switch K1 is turned off, so that the reference voltage of the reference voltage terminal VREF is input to the second node N2 in each pixel circuit 40 of the turned-on row through the turned-on second transistor T2.
  • the sampling sensing circuit 160 may respectively collect sensing voltage signals of a plurality of pixel circuits 40 of a column of sub-pixels P through the same sensing voltage signal line SL.
  • the plurality of sub-light emitting units P' in the sub-pixel P are arranged along the first direction X.
  • the plurality of pixel circuits 40 in the sub-pixel P are electrically connected to the same sensing voltage signal line SL. In this way, the circuit arrangement in the display module 100 is simple.
  • the processor 130 is also electrically connected to the sampling sensing circuit 160 , and the processor 130 is further configured to determine the sensing voltage signals of all the pixel circuits 40 .
  • the processor 130 is electrically connected to the gate driving circuit 140, the source driving circuit 150 and the sampling sensing circuit 160.
  • the processor 130 is also configured to control the gate driving circuit 140, the source driving circuit 150 and the sampling sensing circuit 160 to obtain a sensing voltage signal of at least one pixel circuit 40 in each sub-pixel P.
  • the processor 130 is configured to control the gate driving circuit 140 , the source driving circuit 150 , and the sampling sensing circuit 160 to obtain sensing voltage signals of all pixel circuits 40 .
  • first scanning signal terminal G1 and the second scanning signal terminal G2 may share the same scanning signal line GL as shown in FIG. 6B .
  • the display module 100 may include, for example, a gate drive circuit 140, each gate drive circuit 140 includes a plurality of cascaded shift registers RS.
  • Each sub-light emitting unit P' corresponds to a shift register RS, and a scanning signal line GL electrically connected to a sub-light emitting unit P' is electrically connected to a shift register RS.
  • the first scanning signal terminal G1 and the second scanning signal terminal G2 of the plurality of pixel circuits 40 in each sub-pixel P are turned on, and the sensing voltage signals of all the pixel circuits 40 can be obtained.
  • the processor 130 is further configured to determine the sensing voltage signal of any pixel circuit 40 in the non-target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the non-target sub-pixel. And, determine whether the target sub-pixel is emitting light. If so, the sensing voltage signal of any pixel circuit 40 in the target sub-pixel that is electrically connected to the emitting light-emitting device 30 is determined as the sensing voltage signal of all pixel circuits 40 in the target sub-pixel; if not, the sensing voltage signal of any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all pixel circuits 40 in the target sub-pixel.
  • the processor 130 is configured to control the gate driving circuit 140 , the source driving circuit 150 , and the sampling sensing circuit 160 to obtain a sensing voltage signal of a pixel circuit 40 in each sub-pixel P.
  • first scanning signal terminal G1 and the second scanning signal terminal G2 may share the same scanning signal line GL as shown in FIG. 6B .
  • the processor 130 is also configured to determine the sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all the pixel circuits 40 in the non-target sub-pixel. And, determine whether the difference between the sensing voltage signal obtained in the target sub-pixel and the sensing voltage signal obtained in any adjacent non-target sub-pixel is within a first preset range. If so, the sensing voltage signal obtained in the target sub-pixel is determined as the sensing voltage signal of all the pixel circuits 40 in the target sub-pixel. If not, the sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel is determined as the sensing voltage signal of all the pixel circuits 40 in the target sub-pixel. In this way, the sensing voltage signal can be shared and the amount of data of the sensing voltage signal can be reduced.
  • the processor 130 may also be configured to determine the sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the non-target sub-pixel. And, determine whether the sensing voltage signal obtained in the target sub-pixel is within the second preset range. If so, determine the sensing voltage signal obtained in the target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the target sub-pixel. If not, determine the sensing voltage signal obtained in any non-target sub-pixel adjacent to the target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the target sub-pixel. In this way, the sensing voltage signal can be shared and the amount of data of the sensing voltage signal can be reduced.
  • the first preset range can be set according to actual conditions, for example, the first preset range is -0.15V to 0.15V.
  • the second preset range can be set according to actual conditions, for example, the second preset range is 0.5V to 2.5V.
  • each sub-pixel P may include, for example, two sub-light-emitting units P'
  • the display module 100 may include, for example, two gate drive circuits 140, each gate drive circuit 140 including a plurality of cascaded shift registers RS.
  • Each sub-light-emitting unit P' corresponds to a shift register RS.
  • the scanning signal line GL electrically connected to the sub-light-emitting units P of odd-numbered rows is electrically connected to the shift register RS in one gate drive circuit 140; the scanning signal line GL electrically connected to the sub-light-emitting units P of even-numbered rows is electrically connected to the shift register RS in another gate drive circuit 140.
  • one gate drive circuit 140 is working and the other gate drive circuit 140 is not working. Only the first scanning signal terminal G1 and the second scanning signal terminal G2 of one pixel circuit 40 in each sub-pixel P are turned on, and the sensing voltage signal of one pixel circuit 40 in each sub-pixel P can be obtained.
  • the processor 130 is configured to control the gate driving circuit 140 , the source driving circuit 150 , and the sampling sensing circuit 160 to obtain an average sensing voltage signal of multiple pixel circuits 40 in each sub-pixel P.
  • first scanning signal terminal G1 and the second scanning signal terminal G2 may share the same scanning signal line GL as shown in FIG. 6B .
  • the processor 130 is further configured to determine the average sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the non-target sub-pixel. And, determine the average sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the target sub-pixel. In this way, the sensing voltage signal can be shared and the amount of data of the sensing voltage signal can be reduced.
  • the average sensing voltage signal refers to the sensing voltage signal obtained by the multiple pixel circuits 40 in each sub-pixel P simultaneously collecting the voltage on the sensing voltage signal line SL through the same sensing voltage signal line SL.
  • the display module 100 may include, for example, a gate driving circuit 140, and the gate driving circuit 140 includes a plurality of cascaded shift registers RS, wherein all pixel circuits 40 in each sub-pixel P are electrically connected to a shift register RS through a plurality of scanning signal lines GL.
  • each sub-pixel P corresponds to a shift register RS
  • multiple scanning signal lines GL electrically connected to a sub-pixel P are electrically connected to a shift register RS, so that in the charging stage S2 and the sampling stage S3, the first scanning signal terminal G1 and the second scanning signal terminal G2 of the multiple pixel circuits 40 in each sub-pixel P are opened at the same time, so that the average sensing voltage signal of the multiple pixel circuits 40 in each sub-pixel P can be obtained.
  • Some embodiments of the present disclosure also provide a bad pixel repair method, which can be applied to the display module of any of the above embodiments.
  • the bad pixel repair method includes S100 to S200.
  • S100 includes S111 - S112 .
  • S111 receiving image data from an optical device.
  • the optical device is coupled to the processor 130 .
  • the optical device can take a picture of the illuminated display panel 110 (see FIG5 ) and send the image data to the processor 130 .
  • S112 According to the image data, a sub-pixel with lower brightness is determined as a target sub-pixel, and a position of the target sub-pixel is obtained.
  • the processor 130 may locate the position of the target sub-pixel according to the image data, and store the position of the target sub-pixel to be applied to the subsequent control process.
  • the display module 100 includes a sampling sensing circuit 160.
  • S100 may include S121 to S123.
  • S121 receiving a sensing voltage signal group from a sampling sensing circuit.
  • the processor 130 is electrically connected to the sampling sensing circuit 160 to receive a sensing voltage signal group from the sampling sensing circuit 160 .
  • the sensing voltage signal group includes sensing voltage signals of all pixel circuits 40 .
  • S122 Determine an abnormal sensing voltage signal.
  • the processor 130 may calculate the difference between the sensing voltage signal in the sensing voltage signal group and other adjacent sensing voltage signals, and compare it with the first preset range. A sensing voltage signal whose difference between the sensing voltage signal in the sensing voltage signal group and other adjacent sensing voltage signals is outside the first preset range is determined as an abnormal sensing voltage signal.
  • the abnormal sensing voltage signal is the difference between the sensing voltage signal in the sensing voltage signal group and other adjacent sensing voltage signals, and is a sensing voltage signal outside the first preset range.
  • the sensing voltage signal corresponding to the second sub-light-emitting unit P' is the abnormal sensing voltage signal.
  • the first preset range can be set according to actual conditions.
  • the first preset range is -0.15V to 0.15V.
  • the processor 130 may compare the sensing voltage signal with a second preset range, and determine a sensing voltage signal that is outside the second preset range as an abnormal sensing voltage signal.
  • the abnormal sensing voltage signal is a sensing voltage signal outside the second preset range.
  • the sensing voltage signal corresponding to the second sub-light emitting unit P' is the abnormal sensing voltage signal.
  • the second preset range can be set according to actual conditions.
  • the second preset range is 0.5V to 2.5V.
  • S123 Determine the sub-pixel corresponding to the abnormal sensing voltage signal as a target sub-pixel, and obtain the position of the target sub-pixel.
  • the processor 130 can locate the sub-pixel P corresponding to the abnormal sensing voltage signal based on the abnormal sensing voltage signal, and determine the sub-pixel P corresponding to the abnormal sensing voltage signal as the target sub-pixel; and obtain the position of the target sub-pixel, and store the position of the target sub-pixel for application in subsequent control processes.
  • S200 controlling the source driving circuit to output a second data signal to the target sub-pixel according to the position of the target sub-pixel.
  • the processor 130 can control the source driving circuit 150 to output the second data signal DATA2 to the target sub-pixel according to the position of the target sub-pixel.
  • the data signal received by the target sub-pixel can be increased, thereby increasing the current flowing through the light-emitting device 30 in the target sub-pixel, and then increasing the light-emitting brightness of each light-emitting device 30, so that the brightness of the target sub-pixel is substantially the same as the brightness of the non-target sub-pixel.
  • the bad pixel repairing method further includes S300 to S340 .
  • S300 Control the gate driving circuit, the source driving circuit and the sampling sensing circuit to obtain sensing voltage signals of all pixel circuits.
  • the processor 130 can control the gate drive circuit 140, the source drive circuit 150 and the sampling sensing circuit 160, so that the waveforms of the signals transmitted by the scanning signal line GL, the data line DL and the sensing voltage signal line SL are as shown in Figure 11, thereby obtaining the sensing voltage signals of all the pixel circuits 40.
  • S310 Determine a sensing voltage signal of any pixel circuit in a non-target sub-pixel as the sensing voltage signals of all pixel circuits in the non-target sub-pixel.
  • the processor 130 can determine the sensing voltage signal of any pixel circuit 40 in the non-target sub-pixel as the sensing voltage signal of all pixel circuits 40 in the non-target sub-pixel, thereby realizing the sharing of the sensing voltage signal and reducing the data amount of the sensing voltage signal.
  • S320 Determine whether the target sub-pixel emits light.
  • the processor 130 executes S330 .
  • S330 Determine the sensing voltage signal of any pixel circuit electrically connected to the light-emitting device in the target sub-pixel as the sensing voltage signals of all pixel circuits in the target sub-pixel.
  • S340 Determine the sensing voltage signal of any non-target sub-pixel adjacent to the target sub-pixel as the sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the processor 130 can obtain the threshold voltage of the third transistor T3 (driving transistor) in each sub-pixel according to the sensing voltage signal through data processing, calculation, etc., and compensate the data signal according to the threshold voltage in the subsequent display period for display.
  • the bad pixel repairing method further includes S400 to S440 .
  • S400 Control the gate driving circuit, the source driving circuit and the sampling sensing circuit to obtain a sensing voltage signal of a pixel circuit in each sub-pixel.
  • the processor 130 can control the gate driving circuit 140, the source driving circuit 150 and the sampling sensing circuit 160, so that the waveforms of the signals transmitted by the scanning signal line GL, the data line DL and the sensing voltage signal line SL are as shown in Figure 12, thereby obtaining the sensing voltage signal of a pixel circuit 40 in each sub-pixel P.
  • S410 Determine the sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all pixel circuits in the non-target sub-pixel.
  • the processor 130 may determine the sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all pixel circuits in the non-target sub-pixel, thereby realizing the sharing of the sensing voltage signal and reducing the data volume of the sensing voltage signal.
  • S420 Determine whether a difference between a sensing voltage signal obtained in a target sub-pixel and a sensing voltage signal obtained in any adjacent non-target sub-pixel is within a first preset range.
  • S430 Determine the sensing voltage signal of the pixel circuit in the target sub-pixel as the sensing voltage signals of all the pixel circuits in the target sub-pixel.
  • S440 Determine a sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel as a sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the processor 130 can obtain the threshold voltage of the third transistor T3 (driving transistor) in each sub-pixel according to the sensing voltage signal through data processing, calculation, etc., and compensate the data signal according to the threshold voltage in the subsequent display period for display.
  • the bad pixel repairing method further includes S500 to S520 .
  • S500 Control the gate driving circuit, the source driving circuit and the sampling sensing circuit to obtain an average sensing voltage signal of a plurality of pixel circuits in each sub-pixel.
  • the processor 130 can control the gate drive circuit 140, the source drive circuit 150 and the sampling sensing circuit 160, so that the waveforms of the signals transmitted by the scanning signal line GL, the data line DL and the sensing voltage signal line SL are as shown in Figure 13, thereby obtaining the average sensing voltage signal of multiple pixel circuits 40 in each sub-pixel P.
  • S510 Determine the average sensing voltage signal obtained in the non-target sub-pixel as the sensing voltage signal of all pixel circuits in the non-target sub-pixel.
  • S520 Determine an average sensing voltage signal obtained from any non-target sub-pixel adjacent to the target sub-pixel as a sensing voltage signal of all pixel circuits in the target sub-pixel.
  • the processor 130 can obtain the threshold voltage of the third transistor T3 (driving transistor) in each sub-pixel according to the sensing voltage signal through data processing, calculation, etc., and compensate the data signal according to the threshold voltage in the subsequent display period for display.
  • the sub-light-emitting unit P′ includes a pixel circuit 40, a first light-emitting device 310 and a second light-emitting device 320, and the pixel circuit 40 includes a switch sub-circuit 42.
  • the above-mentioned bad pixel repairing method also includes S600 to S620.
  • the processor 130 can determine whether the second light emitting device 320 is short-circuited according to the brightness of the sub-light emitting unit P' based on the image data. If the sub-light emitting unit P' is not lit or has a low brightness, it means that the second light emitting device 320 is short-circuited, and if the brightness of the sub-light emitting unit P' is approximately the same as the set brightness, it means that the second light emitting device 320 is normal.
  • the image data can be captured by an optical device on the illuminated display panel 110 (see FIG. 5 ) and then sent to the processor 130 .
  • the processor 130 may also determine whether the second light emitting device 320 is short-circuited according to the sensed voltage signal.
  • the second light-emitting device 320 is short-circuited, and if the difference between the sensing voltage signal and the sensing voltage signal of other adjacent sub-light-emitting units P' is within the first preset range, it means that the second light-emitting device 320 is normal.
  • the sensing voltage signal is outside the second preset range, it means that the second light emitting device 320 is short-circuited, and if the sensing voltage signal is within the second preset range, it means that the second light emitting device 320 is normal.
  • the switch subcircuit 42 is turned off, that is, the fourth transistor T4 is turned off, and the grayscale current signal is output to the first light-emitting device 310 and the second light-emitting device 320.
  • the second light-emitting device 320 cannot emit light due to the short circuit, and the first light-emitting device 310 can emit light normally, reducing the risk of the sub-light-emitting unit P' failing to emit light due to the short circuit of the second light-emitting device 320, thereby improving the product yield.
  • S620 Control the gate driving circuit to output an operating voltage to the third scanning signal terminal of the pixel circuit.
  • the switch subcircuit 42 is turned on, that is, the fourth transistor T4 is turned on, and the grayscale current signal is output to the second light-emitting device 320.
  • the first light-emitting device 310 is connected in parallel with the fourth transistor T4, the first light-emitting device 310 cannot emit light, and the second light-emitting device 320 can emit light normally, so that the brightness of the sub-pixel P where the first light-emitting device 310 and the second light-emitting device 320 emit light at the same time can be avoided, and the brightness of the sub-pixel P where only the first light-emitting device 310 emits light is significantly different.
  • Some embodiments of the present disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium), which stores computer program instructions.
  • a computer e.g., a display device
  • the computer executes the bad pixel repair method described in any of the above embodiments.
  • the above-mentioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or magnetic tapes, etc.), optical disks (e.g., CD (Compact Disk), DVD (Digital Versatile Disk), etc.), smart cards and flash memory devices (e.g., EPROM (Erasable Programmable Read-Only Memory), cards, sticks or key drives, etc.).
  • the various computer-readable storage media described in the present disclosure may represent one or more devices and/or other machine-readable storage media for storing information.
  • the term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and/or carrying instructions and/or data.
  • Some embodiments of the present disclosure further provide a computer program product, for example, the computer program product is stored on a non-transitory computer-readable storage medium.
  • the computer program product includes computer program instructions, and when the computer program instructions are executed on a computer (for example, a display device), the computer program instructions cause the computer to execute the bad pixel repair method described in the above embodiment.
  • Some embodiments of the present disclosure further provide a computer program.
  • the computer program When the computer program is executed on a computer (eg, a display device), the computer program enables the computer to execute the bad pixel repair method described in the above embodiments.

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Abstract

一种显示模组，包括多个子像素、数据线、源极驱动电路和处理器。每个子像素包括多个子发光单元，每个子发光单元包括一个像素电路和至少一个发光器件。数据线与子像素电连接。源极驱动电路与数据线电连接。源极驱动电路被配置为，通过数据线向子像素输出第一数据信号或第二数据信号，第二数据信号的电压与第一数据信号的电压不同。处理器与源极驱动电路电连接。处理器被配置为，确定目标子像素的位置信息；以及，根据位置信息，控制源极驱动电路向目标子像素输出第二数据信号，以使得目标子像素的亮度与非目标子像素的亮度大致相同；目标子像素为至少一个子发光单元不发光的子像素，非目标子像素为所有的子发光单元均发光的子像素。

Description

坏点修复方法、显示模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种坏点修复方法、显示模组及显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light Emitting Diode，简称：OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
发明内容
一方面，提供一种显示模组。所述显示模组包括多个子像素、数据线、源极驱动电路和处理器。每个子像素包括多个子发光单元，每个子发光单元包括一个像素电路和至少一个发光器件，每个子像素中的多个像素电路所接收的数据信号相同。所述数据线与所述子像素电连接。所述源极驱动电路与所述数据线电连接。所述源极驱动电路被配置为，通过所述数据线向所述子像素输出第一数据信号或第二数据信号，所述第二数据信号的电压与所述第一数据信号的电压不同。
所述处理器与所述源极驱动电路电连接。所述处理器被配置为，确定目标子像素的位置信息；以及，根据所述位置信息，控制所述源极驱动电路向所述目标子像素输出所述第二数据信号，以使得所述目标子像素的亮度与非目标子像素的亮度大致相同；所述目标子像素为至少一个子发光单元不发光的子像素，所述非目标子像素为所有的子发光单元均发光的子像素。
在一些实施例中，所述显示模组还包括感测电压信号线和采样感测电路。所述感测电压信号线与所述子像素电连接。所述采样感测电路与所述感测电压信号线电连接；所述采样感测电路被配置为，通过所述感测电压信号线采集所述像素电路的感测电压信号。所述处理器还与所述采样感测电路电连接；所述处理器还被配置为，确定所有的像素电路的感测电压信号。
在一些实施例中，所述显示模组还包括扫描信号线和栅极驱动电路。所述扫描信号线与所述子像素电连接。所述栅极驱动电路与所述扫描信号线电连接。所述栅极驱动电路被配置为，通过所述扫描信号线向所述子像素输出扫描信号。所述处理器还与所述栅极驱动电路电连接；所述处理器还被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获 取每个子像素中的至少一个像素电路的感测电压信号。
在一些实施例中，所述处理器被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取所有的所述像素电路的感测电压信号。并将所述非目标子像素中的任一像素电路的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。以及，判断所述目标子像素是否发光。若是，将所述目标子像素中，任一与发光的发光器件电连接的像素电路的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。若否，将与所述目标子像素相邻的任一个非目标子像素的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述处理器被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中一个像素电路的感测电压信号。将所述非目标子像素中获取的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。以及，判断所述目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范围内。若是，将所述目标子像素中获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。若否，将与所述目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述处理器被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中多个像素电路的平均感测电压信号。将非目标子像素中获取的平均感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。以及，将与所述目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述处理器被配置为，控制所述源极驱动电路向所述目标子像素中，与发光的发光器件连接的像素电路输出所述第二数据信号，以及，与不发光的发光器件连接的像素电路不输出数据信号。
在一些实施例中，所述显示模组包括扫描信号线，所述多个子像素中，所有的子发光单元排列为多行多列，每行包括在第一方向排列的多个子发光单元，每列包括在第二方向排列的多个子发光单元；所述第一方向与所述扫描信号线的延伸方向大致相同，所述第二方向与所述数据线的延伸方向大致相同。同一行的多个子发光单元与相同的扫描信号线电连接；同一列的多个子发光单元与相同的数据线电连接。在所述显示模组包括感测电压信号线的 情况下，同一列的子发光单元还与相同的感测电压信号线电连接。
在一些实施例中，同一列的子发光单元被划分为多个子像素，每个子像素包括两个子发光单元。
在一些实施例中，所述像素电路包括驱动子电路，所述驱动子电路与第一扫描信号端、第二扫描信号端、数据信号端和感测电压信号端耦接；且所述驱动子电路被配置为，在来自所述第一扫描信号端的第一扫描信号，以及第二扫描信号端的第二扫描信号的控制下，向所述发光器件输出灰阶电流信号。
在所述子发光单元包括一个像素电路和一个发光器件的情况下，所述发光器件的阳极与所述驱动子电路耦接，所述发光器件的阴极与第二电压信号端耦接。在所述子发光单元包括一个像素电路和多个发光器件的情况下，所述多个发光器件包括第一发光器件和第二发光器件。所述第一发光器件的阳极与第一电压信号端耦接，所述第一发光器件的阴极与所述驱动子电路耦接。所述第二发光器件的阳极与所述驱动子电路耦接，所述第二发光器件的阴极与所述第二电压信号端耦接。
在一些实施例中，所述驱动子电路包括第一晶体管、第二晶体管、第三晶体管和存储电容器。所述第一晶体管的控制极与所述第一扫描信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与第一节点耦接。所述第二晶体管的控制极与所述第二扫描信号端耦接，所述第二晶体管的第一极与所述感测电压信号端耦接，所述第二晶体管的第二极与第二节点耦接。所述第三晶体管的控制极与所述第一节点耦接，所述第三晶体管的第一极与第三节点耦接，所述第三晶体管的第二极与所述第二节点耦接。所述存储电容器的第一极板与第一节点耦接，所述存储电容器的第二极板与所述第二节点耦接。
在一些实施例中，在所述子发光单元包括一个像素电路和多个发光器件的情况下，所述像素电路还包括开关子电路，所述开关子电路与第三扫描信号端耦接；且所述开关子电路被配置为，在来自所述第三扫描信号端的第三扫描信号的控制下，使灰阶电流信号输出至所述第一发光器件和所述第二发光器件；或，使所述灰阶电流信号输出至所述第二发光器件，且不输出至所述第一发光器件。
在一些实施例中，所述显示模组包括栅极驱动电路和扫描信号线。所述第三扫描信号端与所述第一扫描信号端与不同的扫描信号线电连接，且所述第三扫描信号端与所述第二扫描信号端与不同的扫描信号线电连接。所述开 关子电路与所述第一发光器件并联，所述处理器还被配置为，判断所述第二发光器件是否短路。若是，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出非工作电压，所述开关子电路关断，使所述灰阶电流信号输出至所述第一发光器件和所述第二发光器件。若否，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出工作电压，所述开关子电路导通，使所述灰阶电流信号输出至所述第二发光器件，且不输出至第一发光器件。
在一些实施例中，所述第一扫描信号端、所述第二扫描信号端和所述第三扫描信号端中的至少两者与同一条扫描信号线耦接。
在一些实施例中，所述第一发光器件的发光区的面积大于所述第二发光器件的发光区的面积。
在一些实施例中，所述第二数据信号的电压大于所述第一数据信号的电压。
另一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示面板。
又一方面，提供一种坏点修复方法。所述坏点修复方法应用于上述任一实施例所述的显示模组，包括：确定目标子像素的位置。根据所述目标子像素的位置，控制源极驱动电路向所述目标子像素输出所述第二数据信号，以使得所述目标子像素的亮度与非目标子像素的亮度大致相同。
在一些实施例中，所述显示模组包括采样感测电路和栅极驱动电路。所述坏点修复方法还包括：控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取所有的像素电路的感测电压信号。并将所述非目标子像素中的任一像素电路的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。判断所述目标子像素是否发光。若是，将所述目标子像素中，任一与发光的发光器件电连接的像素电路的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；若否，将与所述目标子像素相邻的任一个非目标子像素的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述显示模组包括采样感测电路和栅极驱动电路，所述坏点修复方法还包括：控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中一个像素电路的感测电压信号。将所述非目标子像素中获取的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。以及，判断所述目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范 围内。若是，将所述目标子像素中的像素电路的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；若否，将与所述目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述显示模组包括采样感测电路和栅极驱动电路，所述坏点修复方法还包括：控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中多个像素电路的平均感测电压信号。将非目标子像素中获取的平均感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号。以及，将与所述目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
在一些实施例中，所述确定目标子像素的位置包括：接收来自光学设备的图像数据。根据所述图像数据，将亮度较低的子像素确定为目标子像素，并获取所述目标子像素的位置。
在一些实施例中，所述显示模组包括采样感测电路，所述确定目标子像素的位置包括：接收来自采样感测电路的感测电压信号组；所述感测电压信号组包括所有的像素电路的感测电压信号。确定异常感测电压信号；所述异常感测电压信号为所述感测电压信号组中的感测电压信号与相邻的其他感测电压信号的差值，位于第一预设范围之外的感测电压信号。将所述异常感测电压信号所对应的子像素，确定为目标子像素，并获取所述目标子像素的位置。
在一些实施例中，所述显示模组包括栅极驱动电路，子发光单元包括像素电路、第一发光器件和第二发光器件，所述像素电路包括第三扫描信号端。所述坏点修复方法还包括：判断所述第二发光器件是否短路。若是，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出非工作电压，以使所述开关子电路关断；若否，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出工作电压，以使所述开关子电路导通。
再一方面，提供一种计算机可读存储介质。所述计算机可读存储介质存储有计算机程序指令，所述计算机程序指令在计算机(例如，显示装置)上运行时，使得所述计算机执行如上述任一实施例所述的坏点修复方法。
又一方面，提供一种计算机程序产品。所述计算机程序产品包括计算机程序指令，在计算机(例如，显示装置)上执行所述计算机程序指令时，所述计算机程序指令使计算机执行如上述任一实施例所述的坏点修复方法。
又一方面，提供一种计算机程序。当所述计算机程序在计算机(例如，显示装置)上执行时，所述计算机程序使计算机执行如上述任一实施例所述的坏点修复方法。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示装置的剖视图；
图3为根据一些实施例的显示模组的电路框图；
图4为根据一些实施例的显示面板的剖视图；
图5为根据一些实施例的显示面板的结构图；
图6A为根据一些实施例的一种子像素的电路图；
图6B为根据一些实施例的另一种子像素的电路图；
图6C为根据一些实施例的又一种子像素的电路图；
图7A为根据一些实施例的一种子发光单元的电路图；
图7B为根据一些实施例的另一种子发光单元的电路图；
图7C为根据一些实施例的又一种子发光单元的电路图；
图8为根据一些实施例的采样感测电路与像素电路连接的结构图；
图9为根据一些实施例的像素电路在显示时段的时序图；
图10为根据一些实施例的像素电路在补偿感测时段的时序图；
图11为图6A所示的子像素的像素电路在充电阶段和采样阶段的一种时序图；
图12为图6A所示的子像素的像素电路在充电阶段和采样阶段的另一种时序图；
图13为图6A所示的子像素的像素电路在充电阶段和采样阶段的又一种时序图；
图14为根据一些实施例的子像素在所有的子发光单元均发光时的时序图；
图15为根据一些实施例的子像素在至少一个子发光单元不发光时的时序 图；
图16～图22为根据一些实施例的坏点修复方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是 “当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的像素电路所采用的晶体管可以为薄膜晶体管(Thin  Film Transistor，简称：TFT)、场效应晶体管(Metal Oxide Semiconductor，简称：MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
本文中，像素电路所采用的各薄膜晶体管的控制极为晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极为源极，第二极为漏极；示例性的，在薄膜晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例中，存储电容器可以是通过工艺制程单独制作的存储电容器件，例如通过制作专门的电容电极来实现电容器件，该存储电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。存储电容器也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
本公开的实施例中，“工作电平”指的是能够使得其包括的被操作晶体管被导通的电平，相应地，“非工作电平”(或“非开启电平”)指的是不能使得其包括的被操作晶体管被导通(即，该晶体管被截止)的电平。根据晶体管的类型(N型或P型)等因素，工作电平可以比非工作电平高或者低。通常，在像素电路工作期间使用的方波脉冲信号，工作电平对应于该方波脉冲信号的方波脉冲部分的电平，而非工作电平则对应于非方波脉冲部分的电平。
如图1所示，本公开的一些实施例提供一种显示装置1000，该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、虚拟现实(Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，参阅图2，显示装置1000包括显示模组100。
示例性地，如图1和图2所示，显示装置1000还包括框架200和盖板玻璃300。
其中，框架200的纵截面呈U型，盖板玻璃300设置于框架200的开口侧，显示模组100设置于框架200内。
在一些实施例中，参阅图2，显示模组100包括显示面板110。
示例性地，如图2和图3所示，显示模组100还包括电路板120和处理器130等其它电子配件，电路板120设置于显示面板110的远离盖板玻璃300的一侧，处理器130可以设置于电路板120上。
在一些实施例中，参阅图4，显示面板110包括显示基板10和用于封装显示基板10的封装层20。
其中，如图4所示，显示基板10具有相对设置的出光侧和非出光侧，封装层20设置于显示基板10的出光侧，即图4中的上侧。此处，封装层20可以为封装薄膜，也可以为封装基板。
参阅图1和图5，显示面板110具有显示区A，以及设置在显示区A的至少一侧的周边区B。图1和图5中以周边区B围绕显示区A设置为例进行示意。
其中，显示区A为显示图像的区域，被配置为设置多个子像素P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路，例如，栅极驱动电路140和源极驱动电路150。
示例性地，参阅图4和图5，显示面板110包括衬底11和设置在衬底11的一侧，且位于显示区A的多个子像素P。
上述衬底11的类型包括多种，可以根据实际需要选择设置。
示例性地，衬底11可以为刚性衬底。例如，该刚性衬底可以为玻璃衬底或聚甲基丙烯酸甲酯(Polymethyl Methacrylate，简称：PMMA)衬底等。
示例性地，衬底11可以为柔性衬底。例如，该柔性衬底可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，简称：PET)衬底、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称：PEN)衬底或聚酰亚胺(Polyimide，简称：PI)衬底等。
参阅图1和图5，上述多个子像素P可以包括发光颜色为第一颜色的第一子像素、发光颜色为第二颜色的第二子像素、以及发光颜色为第三颜色的第三子像素。
需要说明的是，第一颜色、第二颜色和第三颜色为三基色，例如，第一颜色为红色，第二颜色为蓝色，第三颜色为绿色。
其中，参阅图4和图6A，每个子像素P均包括设置于衬底11上的发光器件30和像素电路40。
上述发光器件30的结构包括多种，可以根据实际需要选择设置。例如，上述发光器件30可以为OLED、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)或微发光二极管(Micro Light Emitting Diodes，简称Micro LED)等，本公开实施例在此不作具体限定。
下面以上述发光器件30为OLED为例，对本公开的一些实施例进行示意性说明。
如图4和图6A所示，像素电路40包括薄膜晶体管400。薄膜晶体管包括半导体沟道410、源极420、漏极430和栅极440，源极420和漏极430分别与半导体沟道410接触。
需要说明的是，上述源极420和漏极430可以互换，即图4中的420表示漏极，图4中的430表示源极。
如图4所示，发光器件30包括阳极31、发光功能层32以及阴极33，阳极31和多个薄膜晶体管400中的一个薄膜晶体管400的源极420或漏极430电连接，图4中以阳极31和薄膜晶体管400的漏极430电连接进行示意。
可以理解的是，上述像素电路40的结构包括多种，可以根据实际需要选择设置。例如，像素电路的结构可以包括“2T1C”、“3T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
此外，在显示面板110使用的过程中，像素电路40中的晶体管及发光器件30的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板110的显示效果，这样便需要对子像素P进行补偿。
对子像素P进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素P中设置像素补偿电路，以利用该像素补偿电路对子像素P进行内部补偿。又如，可以通过子像素P内部的晶体管对驱动晶体管或发光器件进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对子像素P的外部补偿。
本公开以采用外部补偿的方式，且像素电路40采用“3T1C”的结构为例，对本公开实施例进行示意性说明，具体可以参阅下文。
示例性地，如图7A所示，像素电路40包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容器C。
参阅图7A，第一晶体管T1的控制极与第一扫描信号端G1耦接，第一晶 体管T1的第一极与数据信号端D耦接，第一晶体管T1的第二极与第一节点N1耦接。
需要说明的是，第一节点N1并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，第一节点N1是由电路图中相关电连接的汇合点等效而成的节点。
参阅图7A，第二晶体管T2的控制极与第二扫描信号端G2耦接，第二晶体管T2的第一极与感测电压信号端S耦接，第二晶体管T2的第二极与第二节点N2耦接。
需要说明的是，第二节点N2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，第二节点N2是由电路图中相关电连接的汇合点等效而成的节点。
参阅图7A，第三晶体管T3的控制极与第一节点N1耦接，第三晶体管T3的第一极与第一电压信号端VDD耦接，第三晶体管T3的第二极与第二节点N2耦接。这里，第三晶体管T3即为该3T1C像素电路40的驱动晶体管。
参阅图7A，存储电容器C的第一极板与第一节点N1耦接，存储电容器C的第二极板与第二节点N2耦接。
参阅图5和图6A，显示面板110还包括设置于衬底11上的扫描信号线GL、数据线DL、栅极驱动电路140和源极驱动电路150。
其中，栅极驱动电路140通过扫描信号线GL与子像素P中的像素电路40电连接，以向像素电路40传输扫描信号；源极驱动电路150通过数据线DL与子像素P中的像素电路40电连接，以向像素电路40传输数据信号，从而驱动各个发光器件30发光。
示例性地，参阅图1和图5，多个子像素P例如可以排列成多行多列，每行可以包括沿第一方向X排列的多个子像素P，每列可以包括沿第二方向Y排列的多个子像素P。
这里，第一方向X为阵列排布的多个子像素P的行方向，第二方向Y为阵列排布的多个子像素P的列方向。
需要说明的是，在本文中，行和列的定义是相对的概念，分别表示阵列排布的两个不同的延伸方向。
为了便于描述，将沿第一方向X排列成一行的多个子像素P称为同一行子像素P，将沿第二方向Y排列成一列的多个子像素P称为同一列子像素P。
此时，扫描信号线GL可以沿第一方向X延伸，并与一行子像素P的像素电路40电连接；数据线DL可以沿第二方向Y延伸，并与一列子像素P的 像素电路40电连接。
相关技术中，显示面板中的部分子像素中的发光器件不发光，形成坏点，导致显示效果下降；并且，当坏点超过设定的数量时，则该显示面板不能作为产品出货，导致产品良率下降。
基于此，在本公开的一些实施例提供的显示模组100中，参阅图6A、图6B和图6C，每个子像素P包括多个子发光单元P＇。
其中，每个子发光单元P＇包括一个像素电路40和至少一个发光器件30，且每个子发光单元P＇中的像素电路40与发光器件30电连接。
在一些示例中，参阅图7A，每个子发光单元P＇包括一个像素电路40和一个发光器件30。
例如，如图7A所示，像素电路40包括驱动子电路41，驱动子电路41与第一扫描信号端G1、第二扫描信号端G2、数据信号端D和感测电压信号端S耦接。其中，驱动子电路41被配置为，在来自第一扫描信号端G1的第一扫描信号，以及第二扫描信号端G2的第二扫描信号的控制下，向发光器件30输出灰阶电流信号。
其中，该发光器件30的阳极31与像素电路40电连接，发光器件30的阴极33与第二电压信号端VSS耦接。
需要说明的是，上述第二电压信号端VSS被配置为接收直流低电平信号，这里将该直流低电平信号称为第二电压信号。
这里，该驱动子电路41可以为上述3T1C的像素电路40，也即该驱动子电路41可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容器C。
此时，发光器件30的阳极31与第二节点N2电连接，发光器件30的阴极33与第二电压信号端VSS电连接。
在另一些示例中，参阅图7B，每个子发光单元P＇包括一个像素电路40和多个发光器件30。其中，多个发光器件30包括第一发光器件310和第二发光器件320。图7B中以子发光单元包括两个发光器件为例进行示意。
需要说明的是，第一发光器件310的发光区的面积可以大于第二发光器件320的发光区的面积。这样的话，第一发光器件310相较于第二发光器件320的失效概率较高，当第一发光器件310失效后，第二发光器件320仍可以继续发光，从而降低每个子发光单元P＇无法发光的风险，降低子像素P无法发光的风险。
例如，如图7B所示，像素电路40包括驱动子电路41，驱动子电路41 与第一扫描信号端G1、第二扫描信号端G2、数据信号端D和感测电压信号端S耦接。其中，驱动子电路被配置为，在来自第一扫描信号端G1的第一扫描信号，以及第二扫描信号端G2的第二扫描信号的控制下，向发光器件30输出灰阶电流信号。
其中，第一发光器件310的阳极31与第一电压信号端VDD耦接，第一发光器件310的阴极33与驱动子电路41耦接。第二发光器件320的阳极31与驱动子电路41耦接，第二发光器件320的阴极33与第二电压信号端VSS耦接。
需要说明的是，第一电压信号端VDD被配置为接收直流高电平信号。这里将该直流高电平信号称为第一电压信号，示例性地，该第一电压信号的电压值大于第二电压信号的电压值。
这里，该驱动子电路41可以为上述3T1C的像素电路40，也即该驱动子电路41可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容器C。其中，第三晶体管T3的第一极与第三节点N3耦接。
此时，第一发光器件310的阳极31与第一电压信号端VDD耦接，第一发光器件310的阴极33与第三节点N3耦接。第二发光器件320的阳极31与第二节点N2耦接，第二发光器件320的阴极33与第二电压信号端VSS耦接。
在这种情况下，每个子发光单元P＇中包括至少两个发光器件30，且至少两个发光器件30与驱动子电路41串联。这样的话，在任一个发光器件30短路失效的情况下，剩余的其他发光器件30仍可以发光，降低每个子发光单元P＇无法发光的风险，进而降低子像素P无法发光的风险，减少坏点数量，提升显示效果及产品良率。
在此基础上，参阅图7C，上述像素电路40还包括开关子电路42，开关子电路42与第三扫描信号端G3耦接。其中，开关子电路42被配置为，在来自第三扫描信号端G3的第三扫描信号的控制下，使灰阶电流信号输出至第一发光器件310和第二发光器件320；或，使灰阶电流信号输出至第二发光器件320，且不输出至第一发光器件310。
在一些实施例中，如图7C所示，开关子电路42与第一发光器件310并联。
示例性地，如图7C所示，开关子电路42包括第四晶体管T4，第四晶体管T4的控制极与第三扫描信号端G3耦接，第四晶体管T4的第一极与第一发光器件310的阳极31耦接，第四晶体管T4的第二极与第一发光器件310的阴极33耦接。
此时，在第四晶体管T4导通的情况下，灰阶电流信号输出至第二发光器件320，且不输出至第一发光器件310。在第四晶体管T4断开的情况下，灰阶电流信号输出至第一发光器件310和第二发光器件320。
在一些实施例中，参阅图6B和图7C，第三扫描信号端G3与第一扫描信号端G1与不同的扫描信号线GL电连接，且第三扫描信号端G3与第二扫描信号端G2与不同的扫描信号线GL电连接。
此时，处理器130还被配置为，判断第二发光器件320是否短路。
若是，控制栅极驱动电路140，向像素电路40的第三扫描信号端G3输出非工作电压，以使开关子电路42关断，即灰阶电流信号输出至第一发光器件310和第二发光器件320。此时，第二发光器件320由于短路无法发光，第一发光器件310可以正常发光，降低由于第二发光器件320短路导致子发光单元P＇无法发光的风险，提升产品良率。
若否，控制栅极驱动电路140，向像素电路40的第三扫描信号端输出工作电压，以使开关子电路42导通，即灰阶电流信号输出至第二发光器件320，且不输出至第一发光器件310。此时，第一发光器件310与开关子电路42并联，第一发光器件310无法发光，第二发光器件320可以正常发光，这样可以避免第一发光器件310和第二发光器件320同时发光的子像素P的亮度，与仅第一发光器件310发光的子像素P的亮度产生明显的差异。
需要说明的是，在上述控制过程中，每个子像素P中的第一发光器件310和第二发光器件320中的任一者发光即可达到设定的亮度。
在一些实施例中，参阅图6B、图6C和图7C，第一扫描信号端G1、第二扫描信号端G2和第三扫描信号端G3中的至少两者与同一条扫描信号线GL耦接。
在一些示例中，如图6B和图7C所示，第一扫描信号端G1和第二扫描信号端G2与同一条扫描信号线GL耦接，第二扫描信号端G2与第三扫描信号端G3与不同的扫描信号线GL耦接。
例如，如图6B和图7C所示，第一扫描信号端G1和第二扫描信号端G2与第一扫描信号线GL1.1电连接；第三扫描信号端G3与第三扫描信号线GL1.3电连接。
此时，处理器130仍可以被配置为，判断第二发光器件320是否短路。
若是，控制栅极驱动电路140，向像素电路40的第三扫描信号端G3输出非工作电压，以使第四晶体管T4关断，灰阶电流信号输出至第一发光器件310和第二发光器件320。此时，第二发光器件320由于短路无法发光，第一 发光器件310可以正常发光，降低由于第二发光器件320短路导致子发光单元P＇无法发光的风险，提升产品良率。
若否，控制栅极驱动电路140，向像素电路40的第三扫描信号端G3输出工作电压，以使第四晶体管T4导通，灰阶电流信号输出至第二发光器件320。此时，第一发光器件310与第四晶体管T4并联，第一发光器件310无法发光，第二发光器件320可以正常发光，这样可以避免第一发光器件310和第二发光器件320同时发光的子像素P的亮度，与仅第一发光器件310发光的子像素P的亮度产生明显的差异。
这里，每个子像素P中，第一发光器件310或第二发光器件320发光即可达到设定的亮度。
在另一些示例中，如图6C和图7C所示，第一扫描信号端G1和第二扫描信号端G2与不同的扫描信号线GL耦接，第二扫描信号端G2和第三扫描信号端G3与同一条扫描信号线耦接。这里，第一发光器件310和第二发光器件320同时发光达到设定的亮度。
例如，如图6C和图7C所示，第一扫描信号端G1与第一扫描信号线GL1.1电连接；第二扫描信号端G2和第三扫描信号端G3与第二扫描信号线GL1.2电连接。
在一些实施例中，如图5、图6A、图6B和图6C所示，所有的子发光单元P＇排列为多行多列，每行包括在第一方向X排列的多个子发光单元P＇，每列包括在第二方向Y排列的多个子发光单元P＇。
需要说明的是，第一方向X与扫描信号线GL的延伸方向大致相同，第二方向Y与数据线DL的延伸方向大致相同。
其中，同一行的多个子发光单元P＇可以与相同的扫描信号线GL电连接；同一列的多个子发光单元P＇可以与相同的数据线DL电连接。以及，同一列的子发光单元P＇还可以与相同的感测电压信号线SL电连接。
需要说明的是，同一行的多个子发光单元P＇可以与相同的扫描信号线GL电连接，指的是同一行的多个子发光单元P＇的像素电路40中相同的扫描信号端与相同的扫描信号线GL电连接，不同的扫描信号端可以与不同的扫描信号端电连接。
在此基础上，同一列的子发光单元P＇被划分为多个子像素P，每个子像素P例如可以包括两个子发光单元P＇。
如图6A、图6B和图6C所示，子像素P中的两个子发光单元P＇沿第二方向Y排列。子像素P中的两个像素电路40与同一数据线DL电连接。以这 种方式设置，显示模组100(参见图2)中的电路排布简单，且可以使得子像素P中的多个像素电路40所接收的数据信号相同。
在这种情况下，在任一个子发光单元P＇不发光的情况下，剩余的其他子发光单元P＇仍可以发光，这样可以降低每个子像素P无法发光的风险，减少坏点数量，提升显示效果及产品良率。
图14为根据一些实施例的子像素在所有的子发光单元均发光时的时序图；图15为根据一些实施例的子像素在至少一个子发光单元不发光时的时序图。
参阅图6A、图14和图15，第一数据信号DATA1为子像素P中的每个子发光单元P＇均发光时，子像素P所接收的可以达到设定亮度的数据信号；第二数据信号DATA2为该子像素P中的至少一个子发光单元P＇不发光时，子像素P所接收的可以达到设定亮度的数据信号。其中，第二数据信号DATA2的电压与第一数据信号DATA1的电压不同，以使得子像素P中所有的子发光单元P＇均发光时的亮度，与该子像素P中至少一个子发光单元所有的子发光单元P＇不发光时的亮度大致相同。
示例性地，第二数据信号DATA2的电压大于第一数据信号DATA1的电压。
在此基础上，参阅图5、图6A、图14和图15，源极驱动电路150被配置为，通过数据线DL向子像素P中的像素电路40输出第一数据信号DATA1或第二数据信号DATA2，第二数据信号DATA2的电压大于第一数据信号DATA1的电压。
此外，处理器130与源极驱动电路150电连接。且，处理器130被配置为，确定目标子像素的位置信息；以及，根据位置信息，控制源极驱动电路150向目标子像素输出第二数据信号DATA2，以使得目标子像素的亮度与非目标子像素的亮度大致相同。
需要说明的是，目标子像素为至少一个子发光单元P＇不发光的子像素P，非目标子像素为所有的子发光单元P＇均发光的子像素P。
此时，处理器130还可以通过控制源极驱动电路150向子像素P输出的数据信号的大小，来控制流经发光器件30的电流的大小，从而避免目标子像素的亮度与非目标子像素的亮度产生明显的差异。
在一些实施例中，处理器130还被配置为，控制源极驱动电路150向目标子像素中，与发光的发光器件30连接的像素电路40输出第二数据信号DATA2，以及，与不发光的发光器件30连接的像素电路40不输出数据信号。
此时，与不发光的发光器件30连接的像素电路40的数据信号端D不会写入数据信号，避免该像素电路40产生暗态电流。
在像素电路40采用外部补偿的方式的情况下，参阅图3和图8，上述显示模组100还包括感测电压信号线SL和采样感测电路160，采样感测电路160与感测电压信号线SL电连接，感测电压信号线SL与子像素P电连接。
其中，采样感测电路160被配置为，通过感测电压信号线SL采集像素电路40的感测电压信号。
在一些实施例中，如图8所示，采样感测电路160包括第一开关K1、第二开关K2、采样保持电路(Sample Hold Devices，简称：S/H)、模数转换器(Analog-to-Digital Converter，简称：ADC)。
其中，感测电压信号线SL可以通过第一开关K1与采样保持电路S/H连接，采样保持电路S/H与模数转换器ADC连接；并且，该感测电压信号线SL还通过第二开关K2与参考电压端VREF连接。
基于此，在实际控制过程中，通过控制第一开关K1导通，第二开关K2断开，以通过采样保持电路(S/H)与模数转换器(ADC)来实现对第二节点N2的电压的采样。通过控制第一开关K1断开，第二开关K2导通，以将参考电压端VREF的电压输入至第二节点N2。
需要说明的是，参阅图5，采样感测电路160可以集成在一个芯片中，且该芯片例如可以设置于显示面板110中沿感测电压信号线SL延伸方向上的周边区B。
以下以本发明实施例中提供的3T1C的像素电路40，且第一扫描信号端G1和第二扫描信号端G2与不同的扫描信号线GL连接为例，对该像素电路40驱动过程进行示例性的说明。
图9为根据一些实施例的像素电路在显示时段的时序图；图10为根据一些实施例的像素电路在补偿感测时段的时序图。
如图9和图10所示，显示模组100显示的一个帧周期包括显示时段以及补偿感测时段。
如图9所示，显示时段包括像素数据写入阶段P1和发光阶段P2。
在像素数据写入阶段P1：
参阅图6A、图7A和图9，向第一扫描信号端G1输入第一扫描信号，第一晶体管T1导通。此时，通过数据线DL向数据信号端D输入数据信号，该数据信号经导通的第一晶体管T1存储至存储电容器C中。
参阅图6A、图7A和图9，向第二扫描信号端G2输入第二扫描信号，第 二晶体管T2导通。此时，结合图8，通过感测电压信号线SL将参考电压端VREF的参考电压经导通的第二晶体管T2输入至第二节点N2。
在此基础上，第一节点N1电压逐渐上升，第三晶体管T3导通，第二节点N2电压相应的逐渐上升，并通过存储电容器C的自举作用，对第一节点N1的电压进一步抬升，像素电路40进入发光阶段P2，发光器件30开始发光。
上述像素数据写入阶段P1中，前述通过与第二晶体管T2连接的感测电压信号线SL，将参考电压端VREF的参考电压经导通的第二晶体管T2输入至第二节点N2可以包括：
控制第二开关K2导通，以及第一开关K1断开，以将参考电压端VREF的参考电压经导通的第二晶体管T2输入至开启行的各像素电路40中的第二节点N2。
如图10所示，补偿感测时段包括数据写入阶段S1、充电阶段S2、采样阶段S3和数据写回阶段S4。
参阅图6A、图7A和图10，在整个补偿感测时段，向第二扫描端G2输入扫描信号，第二晶体管T2保持导通。以及，在整个补偿感测时段，向数据信号端D输入数据信号。
在数据写入阶段S1：
参阅图6A、图7A和图10，向第一扫描端G1输入扫描信号，第一晶体管T1导通，将数据线DL上的数据信号输入至第一节点N1，并存储至存储电容器C。感测电压信号线SL经导通的第二晶体管T2向第二节点N2输入参考电压。
其中，通过感测电压信号线SL经导通的第二晶体管T2向第二节点N2输入参考电压可以包括：
控制与当前开启行的各像素电路40连接的感测电压信号线SL连接的第二开关K2导通，同时控制所有的第一开关K1断开，以将参考电压端VREF的参考电压经导通的第二晶体管T2输入至该开启行的各像素电路40中的第二节点N2。
在充电阶段S2：
参阅图6A、图7A和图10，感测电压信号线SL停止向第二节点N2输入参考电压，第二节点N2处于浮空状态。此时，在第一节点N1的电压的作用下，第三晶体管T3导通，第二节点N2开始充电(也即向感测电压信号线SL充电)。
在采样阶段S3：
参阅图6A、图7A和图10，在经过充电阶段S2的一段时间的充电后，感测电压信号线SL上的电压基本保持稳定。此时，对感测电压信号线SL上的电压进行采集(也即对与该感测电压信号线SL连接的第二节点N2的电压进行采集)。
其中，通过感测电压信号线SL上的电压进行采集可以包括：
控制第一开关K1导通，以及第二开关K2断开，以将开启行的各像素电路40中第二节点N2的电压，通过采样保持电路(S/H)后，经模数转换器ADC转换得到对应的数字信号。
对于上述采集得到与第二节点N2的电压对应的数字信号而言，可以通过后续的数据处理、运算等，得到驱动晶体管的阈值电压，并在后续的显示时段中根据该阈值电压对数据信号进行补偿，以进行显示。
在数据写回阶段S4：
参阅图6A、图7A和图10，向第一扫描信号端G1输入扫描信号，第一晶体管T1导通，将数据线DL上的数据信号输入至第一节点N1。通过感测电压信号线SL经导通的第二晶体管T2向第二节点N2输入参考电压。
其中，通过感测电压信号线SL经导通的第二晶体管T2向第二节点N2输入参考电压可以包括：
控制第二开关K2导通，以及第一开关K1断开，以将参考电压端VREF的参考电压经导通的第二晶体管T2输入至开启行的各像素电路40中的第二节点N2。
在一些实施例中，参阅图5和图8，采样感测电路160可以通过同一条感测电压信号线SL分别采集一列子像素P的多个像素电路40的感测电压信号。
示例性地，子像素P中的多个子发光单元P＇沿第一方向X排列。子像素P中的多个像素电路40与同一感测电压信号线SL电连接。以这种方式设置，显示模组100中的电路排布简单。
此外，处理器130还与采样感测电路160电连接，处理器130还被配置为，确定所有的像素电路40的感测电压信号。
这里，处理器130与栅极驱动电路140、源极驱动电路150和采样感测电路160电连接。处理器130还被配置为，控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，获取每个子像素P中的至少一个像素电路40的感测电压信号。
在一些示例中，参阅图6A和图11，处理器130被配置为，控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，获取所有的像素电路 40的感测电压信号。
此时，像素电路40在充电阶段S2和采样阶段S3的时序如图11所示。
需要说明的是，由于同一个像素电路40中，第一扫描信号端G1和第二扫描信号端G2接收的信号相同，因此，第一扫描信号端G1和第二扫描信号端G2可以如图6B所示共用同一条扫描信号线GL。
这里，显示模组100例如可以包括一个栅极驱动电路140，每个栅极驱动电路140包括级联的多个移位寄存器RS。其中，每个子发光单元P＇与一个移位寄存器RS对应，且与一个子发光单元P＇电连接的扫描信号线GL与一个移位寄存器RS电连接。这样的话，在充电阶段S2和采样阶段S3，每个子像素P中的多个像素电路40的第一扫描信号端G1和第二扫描信号端G2打开，即可获取所有的像素电路40的感测电压信号。
此外，处理器130还被配置为，将非目标子像素中的任一像素电路40的感测电压信号，确定为非目标子像素中所有的像素电路40的感测电压信号。以及，判断目标子像素是否发光。若是，将目标子像素中，任一与发光的发光器件30电连接的像素电路40的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号；若否，将与目标子像素相邻的任一个非目标子像素的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。
在另一些示例中，参阅图6A和图12，处理器130被配置为，控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，获取每个子像素P中一个像素电路40的感测电压信号。
此时，像素电路40在充电阶段S2和采样阶段S3的时序如图12所示。
需要说明的是，由于同一个像素电路40中，第一扫描信号端G1和第二扫描信号端G2接收的信号相同，因此，第一扫描信号端G1和第二扫描信号端G2可以如图6B所示共用同一条扫描信号线GL。
此外，处理器130还被配置为，将非目标子像素中获取的感测电压信号，确定为非目标子像素中所有的像素电路40的感测电压信号。以及，判断目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范围内。若是，将目标子像素中获取的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。若否，将与目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。这样可以实现感测电压信号的共用，减少感测电压信号的数据量。
或，处理器130还可以被配置为，将非目标子像素中获取的感测电压信号，确定为非目标子像素中所有的像素电路40的感测电压信号。以及，判断目标子像素中获取的感测电压信号是否在第二预设范围内。若是，将目标子像素中获取的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。若否，将与目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。这样可以实现感测电压信号的共用，减少感测电压信号的数据量。
需要说明的是，上述第一预设范围可以根据实际情况进行设定，例如，第一预设范围为-0.15V～0.15V。上述第二预设范围可以根据实际情况进行设定，例如，第二预设范围为0.5V～2.5V。
这里，每个子像素P例如可以包括两个子发光单元P＇，显示模组100例如可以包括两个栅极驱动电路140，每个栅极驱动电路140包括级联的多个移位寄存器RS。其中，每个子发光单元P＇与一个移位寄存器RS对应。且与奇数行的子发光单元P电连接的扫描信号线GL，与一个栅极驱动电路140中的移位寄存器RS电连接；与偶数行的子发光单元P电连接的扫描信号线GL，与另一个栅极驱动电路140中的移位寄存器RS电连接。
这样的话，在充电阶段S2和采样阶段S3，一个栅极驱动电路140工作，另一个栅极驱动电路140不工作，每个子像素P中仅一个像素电路40的第一扫描信号端G1和第二扫描信号端G2打开，即可获取每个子像素P中一个像素电路40的感测电压信号。
在又一些示例中，参阅图6A和图13，处理器130被配置为，控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，获取每个子像素P中多个像素电路40的平均感测电压信号。
此时，像素电路40在充电阶段S2和采样阶段S3的时序如图13所示。
需要说明的是，由于同一个像素电路40中，第一扫描信号端G1和第二扫描信号端G2接收的信号相同，因此，第一扫描信号端G1和第二扫描信号端G2可以如图6B所示共用同一条扫描信号线GL。
此外，处理器130还被配置为，将非目标子像素中获取的平均感测电压信号，确定为非目标子像素中所有的像素电路40的感测电压信号。以及，将与目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为目标子像素中所有的像素电路40的感测电压信号。这样可以实现感测电压信号的共用，减少感测电压信号的数据量。
需要说明的是，平均感测电压信号指的是每个子像素P中的多个像素电 路40通过同一条感测电压信号线SL同时对感测电压信号线SL上的电压进行采集所得到的感测电压信号。
这里，显示模组100例如可以包括一个栅极驱动电路140，该栅极驱动电路140包括级联的多个移位寄存器RS。其中，每个子像素P中所有的像素电路40通过多条扫描信号线GL与一个移位寄存器RS电连接。
其中，每个子像素P与一个移位寄存器RS对应，且与一个子像素P电连接的多条扫描信号线GL与一个移位寄存器RS电连接，这样在充电阶段S2和采样阶段S3，每个子像素P中的多个像素电路40的第一扫描信号端G1和第二扫描信号端G2同时打开，从而可以获取每个子像素P中多个像素电路40的平均感测电压信号。
本公开的一些实施例还提供了一种坏点修复方法，可以应用于上述任一实施例的显示模组。参阅图16，该坏点修复方法包括S100～S200。
S100：确定目标子像素的位置。
上述步骤中，确定目标子像素的位置的方法并不唯一。
在一些实施例中，参阅图17，S100包括S111～S112。
S111：接收来自光学设备的图像数据。
上述步骤中，参阅图3，光学设备与处理器130耦接。光学设备可以对点亮后的显示面板110(参见图5)进行拍摄，并将图像数据发送给处理器130。
S112：根据图像数据，将亮度较低的子像素确定为目标子像素，并获取目标子像素的位置。
上述步骤中，参阅图3，处理器130可以根据图像数据，定位出对目标子像素的位置，并将目标子像素的位置进行存储，以应用于后续的控制过程。
在另一些实施例中，显示模组100包括采样感测电路160。此时，参阅图18，S100可以包括S121～S123。
S121：接收来自采样感测电路的感测电压信号组。
上述步骤中，参阅图3，处理器130与采样感测电路160电连接，以接收来自采样感测电路160的感测电压信号组。其中，感测电压信号组包括所有的像素电路40的感测电压信号。
S122：确定异常感测电压信号。
在一些实施例中，处理器130可以计算感测电压信号组中的感测电压信号与相邻的其他感测电压信号的差值，并与第一预设范围进行比较。将感测电压信号组中的感测电压信号与相邻的其他感测电压信号的差值位于第一预设范围之外的感测电压信号，确定为异常感测电压信号。
也就是说，异常感测电压信号为感测电压信号组中的感测电压信号与相邻的其他感测电压信号的差值，位于第一预设范围之外的感测电压信号。如图6A和图11所示，感测电压信号线SL采集的感测电压信号中，第二个子发光单元P＇对应的感测电压信号即为异常感测电压信号。
需要说明的是，上述第一预设范围可以根据实际情况进行设定，例如，第一预设范围为-0.15V～0.15V。
在另一些实施例中，处理器130可以将感测电压信号与第二预设范围进行比较。将感测电压信号位于第二预设范围之外的感测电压信号，确定为异常感测电压信号。
也就是说，异常感测电压信号为感测电压信号，位于第二预设范围之外的感测电压信号。如图6A和图11所示，感测电压信号线SL采集的感测电压信号中，第二个子发光单元P＇对应的感测电压信号即为异常感测电压信号。
需要说明的是，上述第二预设范围可以根据实际情况进行设定，例如，第二预设范围为0.5V～2.5V。
S123：将异常感测电压信号所对应的子像素，确定为目标子像素，并获取目标子像素的位置。
上述步骤中，参阅图3和图5，处理器130可以根据异常感测电压信号，定位出对该异常感测电压信号所对应的子像素P，将异常感测电压信号所对应的子像素P确定为目标子像素；并获取目标子像素的位置，将目标子像素的位置进行存储，以应用于后续的控制过程。
S200：根据目标子像素的位置，控制源极驱动电路向目标子像素输出第二数据信号。
上述步骤中，参阅图3、图4和图15，处理器130可以根据目标子像素的位置，控制源极驱动电路150向目标子像素输出第二数据信号DATA2。这样，可以增大目标子像素接收的数据信号，从而增大目标子像素中流经发光器件30的电流，进而增大每个发光器件30的发光亮度，以使得目标子像素的亮度与非目标子像素的亮度大致相同。
在一些实施例中，参阅图19，上述坏点修复方法还包括S300～S340。
S300：控制栅极驱动电路、源极驱动电路以及采样感测电路，获取所有的像素电路的感测电压信号。
上述步骤中，参阅图3、图6A和图11，处理器130可以控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，使得扫描信号线GL、数据线DL和感测电压信号线SL传输的信号的波形如图11所示，从而获取所 有的像素电路40的感测电压信号。
S310：将非目标子像素中的任一像素电路的感测电压信号，确定为非目标子像素中所有的像素电路的感测电压信号。
上述步骤中，参阅图3和图6A，处理器130可以将非目标子像素中的任一像素电路40的感测电压信号，确定为非目标子像素中所有的像素电路40的感测电压信号，从而实现感测电压信号的共用，减少感测电压信号的数据量。
S320：判断目标子像素是否发光。
若是，处理器130执行S330。
S330：将目标子像素中，任一与发光的发光器件电连接的像素电路的感测电压信号，确定为目标子像素中所有的像素电路的感测电压信号。
若否，处理器130执行S340。
S340：将与目标子像素相邻的任一个非目标子像素的感测电压信号，确定为目标子像素中所有的像素电路的感测电压信号。
在获得感测电压信号之后，参阅图3和图7A，处理器130可以根据感测电压信号，通过数据处理、运算等，得到各个子像素中的第三晶体管T3(驱动晶体管)的阈值电压，并在后续的显示时段中根据该阈值电压对数据信号进行补偿，以进行显示。
在另一些实施例中，参阅图20，坏点修复方法还包括S400～S440。
S400：控制栅极驱动电路、源极驱动电路以及采样感测电路，获取每个子像素中一个像素电路的感测电压信号。
上述步骤中，参阅图3、图6A和图12，处理器130可以控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，使得扫描信号线GL、数据线DL和感测电压信号线SL传输的信号的波形如图12所示，从而获取每个子像素P中一个像素电路40的感测电压信号。
S410：将非目标子像素中获取的感测电压信号，确定为非目标子像素中所有的像素电路的感测电压信号。
上述步骤中，参阅图3和图6A，处理器130可以将非目标子像素中获取的感测电压信号，确定为非目标子像素中所有的像素电路的感测电压信号，从而实现感测电压信号的共用，减少感测电压信号的数据量。
S420：判断目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范围内。
需要说明的是，该第一预设范围的描述可以参考上文，本公开实施例在 此不做赘述。
若是，处理器130执行S430。
S430：将目标子像素中的像素电路的感测电压信号，确定为目标子像素中所有的像素电路的感测电压信号。
若是，处理器130执行S440。
S440：将与目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为目标子像素中所有的像素电路的感测电压信号。
在获得感测电压信号之后，参阅图3和图7A，处理器130可以根据感测电压信号，通过数据处理、运算等，得到各个子像素中的第三晶体管T3(驱动晶体管)的阈值电压，并在后续的显示时段中根据该阈值电压对数据信号进行补偿，以进行显示。
在又一些实施例中，参阅图21，上述坏点修复方法还包括S500～S520。
S500：控制栅极驱动电路、源极驱动电路以及采样感测电路，获取每个子像素中多个像素电路的平均感测电压信号。
上述步骤中，参阅图3、图6A和图12，处理器130可以控制栅极驱动电路140、源极驱动电路150以及采样感测电路160，使得扫描信号线GL、数据线DL和感测电压信号线SL传输的信号的波形如图13所示，从而获取每个子像素P中多个像素电路40的平均感测电压信号。
S510：将非目标子像素中获取的平均感测电压信号，确定为非目标子像素中所有的像素电路的感测电压信号。
S520：将与目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为目标子像素中所有的像素电路的感测电压信号。
在获得感测电压信号之后，参阅图3和图7A，处理器130可以根据感测电压信号，通过数据处理、运算等，得到各个子像素中的第三晶体管T3(驱动晶体管)的阈值电压，并在后续的显示时段中根据该阈值电压对数据信号进行补偿，以进行显示。
在一些实施例中，参阅图6C和图7C，子发光单元P＇包括像素电路40、第一发光器件310和第二发光器件320，像素电路40包括开关子电路42，参阅图22，上述坏点修复方法还包括S600～S620。
S600：判断第二发光器件是否短路。
上述步骤中，处理器130可以根据图像数据，将根据子发光单元P＇的亮度来判断第二发光器件320是否短路。其中，子发光单元P＇不亮或亮度较低代表第二发光器件320短路，子发光单元P＇的亮度与设定的亮度大致相同代 表第二发光器件320正常。
需要说明的是，图像数据可以由光学设备可以对点亮后的显示面板110(参见图5)进行拍摄，然后发送给处理器130。
此外，处理器130还可以根据感测电压信号来判断第二发光器件320是否短路。
例如，感测电压信号与相邻的其他子发光单元P＇的感测电压信号差值位于第一预设范围之外代表第二发光器件320短路，感测电压信号与相邻的其他子发光单元P＇的感测电压信号差值位于第一预设范围之内代表第二发光器件320正常。
需要说明的是，第一预设范围可以参考上文，本公开实施例在此不做赘述。
又例如，感测电压信号位于第二预设范围之外代表第二发光器件320短路，感测电压信号位于第二预设范围之内代表第二发光器件320正常。
需要说明的是，第二预设范围可以参考上文，本公开实施例在此不做赘述。
若是，处理器130执行S610。
S610：若是，控制栅极驱动电路，向像素电路的第三扫描信号端输出非工作电压。
此时，参阅图7C，开关子电路42关断，即第四晶体管T4关断，灰阶电流信号输出至第一发光器件310和第二发光器件320。此时，第二发光器件320由于短路无法发光，第一发光器件310可以正常发光，降低由于第二发光器件320短路导致子发光单元P＇无法发光的风险，提升产品良率。
若否，处理器130执行S620。
S620：控制栅极驱动电路，向像素电路的第三扫描信号端输出工作电压。
此时，参阅图7C，开关子电路42导通，即第四晶体管T4导通，灰阶电流信号输出至第二发光器件320。此时，第一发光器件310与第四晶体管T4并联，第一发光器件310无法发光，第二发光器件320可以正常发光，这样可以避免第一发光器件310和第二发光器件320同时发光的子像素P的亮度，与仅第一发光器件310发光的子像素P的亮度产生明显的差异。
本公开的一些实施例提供了一种计算机可读存储介质(例如，非暂态计算机可读存储介质)，该计算机可读存储介质中存储有计算机程序指令，计算机程序指令在计算机(例如，显示装置)上运行时，使得计算机执行如上述实施例中任一实施例所述的坏点修复方法。
示例性的，上述计算机可读存储介质可以包括，但不限于：磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，CD(Compact Disk，压缩盘)、DVD(Digital Versatile Disk，数字通用盘)等)，智能卡和闪存器件(例如，EPROM(Erasable Programmable Read-Only Memory，可擦写可编程只读存储器)、卡、棒或钥匙驱动器等)。本公开描述的各种计算机可读存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读存储介质。术语“机器可读存储介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
本公开的一些实施例还提供了一种计算机程序产品，例如，该计算机程序产品存储在非瞬时性的计算机可读存储介质上。该计算机程序产品包括计算机程序指令，在计算机(例如，显示装置)上执行该计算机程序指令时，该计算机程序指令使计算机执行如上述实施例所述的坏点修复方法。
本公开的一些实施例还提供了一种计算机程序。当该计算机程序在计算机(例如，显示装置)上执行时，该计算机程序使计算机执行如上述实施例所述的坏点修复方法。
上述计算机可读存储介质、计算机程序产品及计算机程序的有益效果和上述一些实施例所述的坏点修复方法的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种显示模组，包括：
    多个子像素，每个子像素包括多个子发光单元，每个子发光单元包括一个像素电路和至少一个发光器件，每个子像素中的多个像素电路所接收的数据信号相同；
    数据线，与所述子像素电连接；
    源极驱动电路，与所述数据线电连接；所述源极驱动电路被配置为，通过所述数据线向所述子像素输出第一数据信号或第二数据信号，所述第二数据信号的电压与所述第一数据信号的电压不同；
    处理器，与所述源极驱动电路电连接；所述处理器被配置为，确定目标子像素的位置信息；以及，根据所述位置信息，控制所述源极驱动电路向所述目标子像素输出所述第二数据信号，以使得所述目标子像素的亮度与非目标子像素的亮度大致相同；所述目标子像素为至少一个子发光单元不发光的子像素，所述非目标子像素为所有的子发光单元均发光的子像素。
  2. 根据权利要求1所述的显示模组，还包括：
    感测电压信号线，与所述子像素电连接；
    采样感测电路，与所述感测电压信号线电连接；所述采样感测电路被配置为，通过所述感测电压信号线采集所述像素电路的感测电压信号；
    所述处理器还与所述采样感测电路电连接；所述处理器还被配置为，确定所有的像素电路的感测电压信号。
  3. 根据权利要求2所述的显示模组，还包括：
    扫描信号线，与所述子像素电连接；
    栅极驱动电路，与所述扫描信号线电连接；所述栅极驱动电路被配置为，通过所述扫描信号线向所述子像素输出扫描信号；
    所述处理器还与所述栅极驱动电路电连接；所述处理器还被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中的至少一个像素电路的感测电压信号。
  4. 根据权利要求3所述的显示模组，其中，所述处理器被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取所有的所述像素电路的感测电压信号；
    并将所述非目标子像素中的任一像素电路的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    以及，判断所述目标子像素是否发光；
    若是，将所述目标子像素中，任一与发光的发光器件电连接的像素电路 的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；
    若否，将与所述目标子像素相邻的任一个非目标子像素的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  5. 根据权利要求3所述的显示模组，其中，所述处理器还配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中一个像素电路的感测电压信号；
    将所述非目标子像素中获取的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    以及，判断所述目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范围内；
    若是，将所述目标子像素中获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；
    若否，将与所述目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  6. 根据权利要求3所述的显示模组，其中，所述处理器被配置为，控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中多个像素电路的平均感测电压信号；
    将非目标子像素中获取的平均感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    以及，将与所述目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  7. 根据权利要求1～6中任一项所述的显示模组，其中，所述处理器被配置为，控制所述源极驱动电路向所述目标子像素中，与发光的发光器件连接的像素电路输出所述第二数据信号，以及，与不发光的发光器件连接的像素电路不输出数据信号。
  8. 根据权利要求1～7中任一项所述的显示模组，其中，所述显示模组包括扫描信号线，所述多个子像素中，所有的子发光单元排列为多行多列，每行包括在第一方向排列的多个子发光单元，每列包括在第二方向排列的多个子发光单元；所述第一方向与所述扫描信号线的延伸方向大致相同，所述第二方向与所述数据线的延伸方向大致相同；
    同一行的多个子发光单元与相同的扫描信号线电连接；同一列的多个子发光单元与相同的数据线电连接；
    在所述显示模组包括感测电压信号线的情况下，同一列的子发光单元还 与相同的感测电压信号线电连接。
  9. 根据权利要求8所述的显示模组，其中，同一列的子发光单元被划分为多个子像素，每个子像素包括两个子发光单元。
  10. 根据权利要求1～9中任一项所述的显示模组，其中，所述像素电路包括：
    驱动子电路，与第一扫描信号端、第二扫描信号端、数据信号端和感测电压信号端耦接；且所述驱动子电路被配置为，在来自所述第一扫描信号端的第一扫描信号，以及第二扫描信号端的第二扫描信号的控制下，向所述发光器件输出灰阶电流信号；
    在所述子发光单元包括一个像素电路和一个发光器件的情况下，所述发光器件的阳极与所述驱动子电路耦接，所述发光器件的阴极与第二电压信号端耦接；
    在所述子发光单元包括一个像素电路和多个发光器件的情况下，所述多个发光器件包括：
    第一发光器件，所述第一发光器件的阳极与第一电压信号端耦接，所述第一发光器件的阴极与所述驱动子电路耦接；
    第二发光器件，所述第二发光器件的阳极与所述驱动子电路耦接，所述第二发光器件的阴极与所述第二电压信号端耦接。
  11. 根据权利要求10所述的显示模组，其中，所述驱动子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第一扫描信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与第一节点耦接；
    第二晶体管，所述第二晶体管的控制极与所述第二扫描信号端耦接，所述第二晶体管的第一极与所述感测电压信号端耦接，所述第二晶体管的第二极与第二节点耦接；
    第三晶体管，所述第三晶体管的控制极与所述第一节点耦接，所述第三晶体管的第一极与第三节点耦接，所述第三晶体管的第二极与所述第二节点耦接；
    存储电容器，所述存储电容器的第一极板与第一节点耦接，所述存储电容器的第二极板与所述第二节点耦接。
  12. 根据权利要求10或11所述的显示模组，其中，在所述子发光单元包括一个像素电路和多个发光器件的情况下，所述像素电路还包括：
    开关子电路，与第三扫描信号端耦接；且所述开关子电路被配置为，在 来自所述第三扫描信号端的第三扫描信号的控制下，使灰阶电流信号输出至所述第一发光器件和所述第二发光器件；或，使所述灰阶电流信号输出至所述第二发光器件，且不输出至所述第一发光器件。
  13. 根据权利要求12所述的显示模组，包括栅极驱动电路和扫描信号线；所述第三扫描信号端与所述第一扫描信号端与不同的扫描信号线电连接，且所述第三扫描信号端与所述第二扫描信号端与不同的扫描信号线电连接；
    所述开关子电路与所述第一发光器件并联，所述处理器还被配置为，判断所述第二发光器件是否短路；
    若是，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出非工作电压，以使所述开关子电路关断；
    若否，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出工作电压，以使所述开关子电路导通。
  14. 根据权利要求12或13所述的显示模组，其中，所述第一扫描信号端、所述第二扫描信号端和所述第三扫描信号端中的至少两者与同一条扫描信号线耦接。
  15. 根据权利要求10～14中任一项所述的显示模组，其中，所述第一发光器件的发光区的面积大于所述第二发光器件的发光区的面积。
  16. 根据权利要求1～15中任一项所述的显示模组，其中，所述第二数据信号的电压大于所述第一数据信号的电压。
  17. 一种显示装置，包括如权利要求1～16中任一项所述的显示模组。
  18. 一种坏点修复方法，应用于权利1～16中任一项所述的显示模组，包括：
    确定目标子像素的位置；
    根据所述目标子像素的位置，控制源极驱动电路向所述目标子像素输出所述第二数据信号，以使得所述目标子像素的亮度与非目标子像素的亮度大致相同。
  19. 根据权利要求18所述的坏点修复方法，其中，所述显示模组包括采样感测电路和栅极驱动电路，所述坏点修复方法还包括：
    控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取所有的像素电路的感测电压信号；
    并将所述非目标子像素中的任一像素电路的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    判断所述目标子像素是否发光；
    若是，将所述目标子像素中，任一与发光的发光器件电连接的像素电路的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；
    若否，将与所述目标子像素相邻的任一个非目标子像素的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  20. 根据权利要求18所述的坏点修复方法，其中，所述显示模组包括采样感测电路和栅极驱动电路，所述坏点修复方法还包括：
    控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中一个像素电路的感测电压信号；
    将所述非目标子像素中获取的感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    以及，判断所述目标子像素中获取的感测电压信号，与相邻的任一非目标子像素中获取的感测电压信号的差值是否在第一预设范围内；
    若是，将所述目标子像素中的像素电路的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号；
    若否，将与所述目标子像素相邻的任一非目标子像素获取的感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  21. 根据权利要求18所述的坏点修复方法，其中，所述显示模组包括采样感测电路和栅极驱动电路，所述坏点修复方法还包括：
    控制所述栅极驱动电路、所述源极驱动电路以及所述采样感测电路，获取每个子像素中多个像素电路的平均感测电压信号；
    将非目标子像素中获取的平均感测电压信号，确定为所述非目标子像素中所有的像素电路的感测电压信号；
    以及，将与所述目标子像素相邻的任一非目标子像素获取的平均感测电压信号，确定为所述目标子像素中所有的像素电路的感测电压信号。
  22. 根据权利要求18～21中任一项所述的坏点修复方法，其中，所述确定目标子像素的位置包括：
    接收来自光学设备的图像数据；
    根据所述图像数据，将亮度较低的子像素确定为目标子像素，并获取所述目标子像素的位置。
  23. 根据权利要求18～21中任一项所述的坏点修复方法，其中，所述显示模组包括采样感测电路，所述确定目标子像素的位置包括：
    接收来自采样感测电路的感测电压信号组；所述感测电压信号组包括所有的像素电路的感测电压信号；
    确定异常感测电压信号；所述异常感测电压信号为所述感测电压信号组中的感测电压信号与相邻的其他感测电压信号的差值，位于第一预设范围之外的感测电压信号；
    将所述异常感测电压信号所对应的子像素，确定为目标子像素，并获取所述目标子像素的位置。
  24. 根据权利要求18～23中任一项所述的坏点修复方法，所述显示模组包括栅极驱动电路，子发光单元包括像素电路、第一发光器件和第二发光器件，所述像素电路包括开关子电路；
    所述坏点修复方法还包括：
    判断所述第二发光器件是否短路；
    若是，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出非工作电压，以使所述开关子电路关断；
    若否，控制所述栅极驱动电路，向所述像素电路的第三扫描信号端输出工作电压，以使所述开关子电路导通。
  25. 一种计算机可读存储介质，存储有计算机程序指令，所述计算机程序指令在计算机上运行时，使得所述计算机执行如权利要求18～24中任一项所述的坏点修复方法。
  26. 一种计算机程序产品，包括计算机程序指令，在计算机上执行所述计算机程序指令时，所述计算机程序指令使计算机执行如权利要求18～24中任一项所述的坏点修复方法。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882093A (zh) * 2014-02-28 2015-09-02 三星显示有限公司 有机发光显示装置
CN106652961A (zh) * 2017-02-06 2017-05-10 北京京东方专用显示科技有限公司 一种极化后的液晶显示面板的修复方法及修复装置
CN109887461A (zh) * 2019-03-29 2019-06-14 京东方科技集团股份有限公司 一种显示装置及显示方法
CN114005855A (zh) * 2021-09-28 2022-02-01 惠科股份有限公司 阵列基板、显示面板及面板坏点修复方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882093A (zh) * 2014-02-28 2015-09-02 三星显示有限公司 有机发光显示装置
CN106652961A (zh) * 2017-02-06 2017-05-10 北京京东方专用显示科技有限公司 一种极化后的液晶显示面板的修复方法及修复装置
CN109887461A (zh) * 2019-03-29 2019-06-14 京东方科技集团股份有限公司 一种显示装置及显示方法
CN114005855A (zh) * 2021-09-28 2022-02-01 惠科股份有限公司 阵列基板、显示面板及面板坏点修复方法

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