WO2023092503A1 - 光检测模组、光检测方法和显示装置 - Google Patents

光检测模组、光检测方法和显示装置 Download PDF

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Publication number
WO2023092503A1
WO2023092503A1 PCT/CN2021/133718 CN2021133718W WO2023092503A1 WO 2023092503 A1 WO2023092503 A1 WO 2023092503A1 CN 2021133718 W CN2021133718 W CN 2021133718W WO 2023092503 A1 WO2023092503 A1 WO 2023092503A1
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Prior art keywords
circuit
control
voltage
capacitance
conversion
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PCT/CN2021/133718
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English (en)
French (fr)
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殷新社
赵辉
韩新斌
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003617.7A priority Critical patent/CN116507890A/zh
Priority to PCT/CN2021/133718 priority patent/WO2023092503A1/zh
Priority to US17/927,109 priority patent/US20240125648A1/en
Publication of WO2023092503A1 publication Critical patent/WO2023092503A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J1/46—Electric circuits using a capacitor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/446—Photodiode

Definitions

  • the present disclosure relates to the technical field of light detection, and in particular, to a light detection module, a light detection method and a display device.
  • the relative photodetection module can detect a large range of photocurrent values, and the photosensitive circuit needs to use multiple photodiodes connected in parallel to generate a photocurrent with a large current value, resulting in high cost and large space occupation.
  • an embodiment of the present disclosure provides a light detection module, including N light sensing circuits, a control circuit, a capacitance integration conversion circuit, and a processing circuit; N is a positive integer; the N light sensing circuits sense Light signals of different colors generate corresponding photocurrents;
  • the control circuit is used to control the time-sharing to provide the photocurrent generated by each of the photosensitive circuits to the capacitance integral amplifier circuit, and to control the conversion parameters of the capacitance integral amplifier circuit;
  • the capacitance integral conversion circuit is used to perform integral conversion on the photocurrent according to the conversion parameter and the integration time, so as to obtain an analog output voltage
  • the processing circuit is used to obtain the characteristics of the optical signal according to the analog output voltage.
  • the capacitance integral conversion circuit includes a conversion subcircuit, a sampling subcircuit and a sampling control subcircuit;
  • the control circuit includes a photosensitive control subcircuit and a capacitance control subcircuit;
  • the sampling subcircuit includes M integral capacitors ; M is a positive integer;
  • the photosensitive control sub-circuit is used to provide the photocurrent generated by each photosensitive circuit to the input end of the conversion sub-circuit under the control of the photosensitive control signal;
  • the capacitance control sub-circuit is used to control the first end of each integration capacitor to communicate with the input end of the conversion sub-circuit under the control of the capacitance control signal; the second end of each integration capacitor is connected to the input end of the conversion sub-circuit The output end of the conversion sub-circuit is electrically connected;
  • the sampling control subcircuit is used to control the connection or disconnection between the output terminal of the conversion subcircuit and the processing circuit under the control of the sampling control signal;
  • the conversion sub-circuit is used to convert the photocurrent to obtain and output the analog output voltage through the output terminal of the conversion sub-circuit;
  • the conversion parameter is the capacitance value of the integration capacitor currently connected to the input terminal of the conversion sub-circuit.
  • the light detection module further includes a reset circuit;
  • the reset circuit includes M reset sub-circuits;
  • the mth reset subcircuit is electrically connected to the first terminal of the mth integrating capacitor, the second terminal of the mth integrating capacitor and the reset control terminal respectively, and is used to control the reset control signal provided by the reset control terminal, controlling the communication between the first terminal of the mth integrating capacitor and the second terminal of the mth integrating capacitor, so as to release the charge stored in the mth integrating capacitor;
  • n is a positive integer less than or equal to M.
  • the photosensitive control subcircuit includes N photosensitive control transistors;
  • the capacitance control subcircuit includes M capacitance control transistors;
  • n is a positive integer less than or equal to N,
  • m is a positive integer less than or equal to M Integer;
  • the sampling control subcircuit includes a sampling switch and a storage capacitor;
  • the control pole of the nth photosensitive control transistor is electrically connected to the nth photosensitive control terminal, the first pole of the nth photosensitive control transistor is electrically connected to the nth photocurrent output terminal, and the second pole of the nth photosensitive control transistor is connected to the nth photosensitive control transistor.
  • the input terminal of the conversion sub-circuit is electrically connected; the nth photosensitive control terminal is used to provide the nth photosensitive control signal;
  • the control pole of the mth capacitance control transistor is electrically connected to the mth capacitance control terminal, the first pole of the mth capacitance control transistor is electrically connected to the input end of the conversion subcircuit, and the second pole of the mth capacitance control transistor is connected to the mth capacitance control terminal.
  • the first terminal of the integrating capacitor is electrically connected, and the second terminal of the mth integrating capacitor is electrically connected to the output terminal of the conversion sub-circuit; the mth capacitor control terminal is used to provide the mth capacitor control signal;
  • the control end of the sampling switch is electrically connected to the sampling control end, the first end of the sampling switch is electrically connected to the output end of the conversion sub-circuit, and the second end of the sampling switch is electrically connected to the processing circuit;
  • the first end of the storage capacitor is electrically connected to the second end of the sampling switch, and the second end of the storage capacitor is electrically connected to the DC voltage end.
  • the light detection module according to at least one embodiment of the present disclosure further includes a filter circuit
  • the filter circuit is connected between the output end of the conversion sub-circuit and the first end of the sampling switch, and is used to filter out high-frequency noise in the analog output voltage, and filter out the high-frequency noise
  • the analog output voltage is provided to the first end of the sampling switch.
  • the mth reset subcircuit includes an mth reset transistor
  • the control pole of the mth reset transistor is electrically connected to the reset control terminal, the first pole of the mth reset transistor is electrically connected to the first end of the mth integration capacitor, and the first pole of the mth reset transistor is electrically connected to the first terminal of the mth integration capacitor.
  • the diode is electrically connected to the second end of the mth integrating capacitor.
  • the N photosensitive circuits, the photosensitive control subcircuit, the capacitance control subcircuit and the reset circuit are all arranged on a display substrate.
  • the capacitance value of at least part of the integration capacitor is less than 10pF
  • the at least part of the integration capacitor is arranged on the display substrate
  • the sampling subcircuit includes an integration capacitor other than the at least part of the integration capacitor.
  • the capacitor is arranged on the circuit board or the driving integrated circuit.
  • the conversion subcircuit includes an operational amplifier; the inverting input terminal of the operational amplifier is the input terminal of the conversion subcircuit, and the output terminal of the operational amplifier is the output terminal of the conversion subcircuit;
  • the non-inverting input terminal of the operational amplifier is electrically connected to a reference voltage terminal, and the reference voltage terminal is used to provide a reference voltage.
  • the light detection module further includes a control signal generation unit;
  • the control signal generating unit is used for providing sampling control signal, photosensitive control signal, capacitance control signal and reset control signal.
  • the processing circuit includes an analog-to-digital converter and an output processing unit;
  • the analog-to-digital converter is used to convert the analog output voltage into an output digital signal
  • the output processing unit is electrically connected to the analog-to-digital converter, and is used for receiving the output digital signal, and obtaining the feature of the optical signal according to the output digital signal.
  • the characteristics of the light signal include at least one of light intensity, brightness, color coordinates, and color temperature.
  • the light detection module further includes a micro control unit;
  • the control signal generation unit includes a control signal generation circuit and a level converter;
  • the control signal generation circuit is used to provide a sampling control signal, an input photosensitive control signal, an input capacitance control signal and an input reset control signal;
  • the level shifter is electrically connected to the control signal generating circuit, and is used for performing level conversion on the input photosensitive control signal to generate the photosensitive control signal, and performing level conversion on the input capacitance control signal. converting to generate the capacitance control signal, and performing level conversion on the input reset control signal to generate the reset control signal;
  • the output processing unit and the control signal generating circuit are arranged in the micro control unit.
  • the light detection module further includes a filter circuit
  • the micro control unit, the level converter, the analog-to-digital converter, the filter circuit, and the conversion sub-circuit and sampling control sub-circuit included in the capacitance integral conversion circuit are all arranged on the circuit board or the drive integrated circuit.
  • the nth photosensitive circuit includes an nth photodiode; n is a positive integer less than or equal to N;
  • the cathode of the nth photodiode is electrically connected to the power supply voltage terminal, and the anode of the nth photodiode is used to provide the nth photocurrent;
  • the power supply voltage terminal is used to provide a power supply voltage signal.
  • the embodiment of the present disclosure also provides a light detection method, which is applied to the above light detection module, and the light detection method includes:
  • N light-sensing circuits respectively sense light signals of different colors and generate corresponding photocurrents
  • the control circuit controls to provide the photocurrent generated by each of the photosensitive circuits to the capacitance integral amplifier circuit in time-sharing, and controls the conversion parameters of the capacitance integral amplifier circuit;
  • the capacitance integral conversion circuit converts the photocurrent according to the conversion parameter and the integration time to obtain an analog output voltage
  • the processing circuit obtains the characteristics of the optical signal according to the analog output voltage.
  • control circuit includes a photosensitive control subcircuit, a sampling subcircuit, and a capacitance control subcircuit;
  • sampling subcircuit includes M integrating capacitors; M is a positive integer;
  • the step of controlling the control circuit to provide the photocurrent generated by each photo-sensing circuit to the conversion circuit in time-sharing includes: the photo-sensing control sub-circuit controls the photo-current generated by each photo-sensing circuit under the control of the photo-sensing control signal in time-sharing The photocurrent is provided to the input end of the capacitance integration conversion circuit; the capacitance control subcircuit controls the first end of each integration capacitor to time-share with the input end of the capacitance integration conversion circuit under the control of the capacitance control signal connection between
  • the conversion parameter is the capacitance value of the integration capacitor currently connected to the input terminal of the capacitance integration conversion circuit.
  • the processing circuit includes an analog-to-digital converter and an output processing unit;
  • the analog-to-digital converter converts the analog output voltage into an output digital signal
  • the output processing unit obtains the feature of the optical signal according to the output digital signal.
  • the high-precision voltage conversion range of the analog-to-digital converter is greater than or equal to the first voltage VS1 and less than or equal to the second voltage VS2;
  • the output processing unit judges whether the voltage value of the input voltage corresponding to the output digital signal is within the high-precision voltage conversion range; the input voltage is the voltage input to the analog-to-digital converter;
  • the output processing unit determines that the voltage value of the input voltage corresponding to the output digital signal is less than the first voltage VS1 or greater than the second voltage VS2, the output processing unit determines that the input voltage corresponding to the output digital signal is If the voltage value is not within the high-precision voltage conversion range, the digital output signal is discarded;
  • the output processing unit determines that the voltage value of the input voltage corresponding to the output digital signal is greater than or equal to the first voltage VS1 and less than or equal to the second voltage VS2, the output processing unit determines that the input voltage corresponding to the output digital signal The voltage value of the voltage is within the high-precision voltage conversion range, and the output processing unit obtains the characteristics of the optical signal according to the digital output signal.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned light detection module.
  • FIG. 1 is a structural diagram of a photodetection module described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a light detection module according to at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a light detection module according to at least one embodiment of the present disclosure.
  • Fig. 4 is a structural diagram of a light detection module according to at least one embodiment of the present disclosure.
  • Fig. 5 is a structural diagram of a light detection module according to at least one embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a light detection module according to at least one embodiment of the present disclosure.
  • FIG. 7 is a working timing diagram of at least one embodiment of the light detection module shown in FIG. 6 of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the light detection module described in the embodiment of the present disclosure includes N light sensing circuits, a control circuit, a capacitance integration conversion circuit and a processing circuit; N is a positive integer; the N light sensing circuits respectively sense light signals of different colors to generate The corresponding photocurrent;
  • the control circuit is used to control the time-sharing to provide the photocurrent generated by each of the photosensitive circuits to the capacitance integral amplifier circuit, and to control the conversion parameters of the capacitance integral amplifier circuit;
  • the capacitance integral conversion circuit is used to perform integral conversion on the photocurrent according to the conversion parameter and the integration time, so as to obtain an analog output voltage
  • the processing circuit is used to obtain the characteristics of the optical signal according to the analog output voltage.
  • the photodetection module described in the embodiment of the present disclosure provides the photocurrent generated by each photosensitive circuit to the capacitance integral amplifier circuit in time-sharing through the control circuit, and controls the conversion parameters of the capacitance integral amplifier circuit.
  • the capacitance integral conversion circuit adopts the current In the method of integration, the photocurrent is converted according to the conversion parameter and the integration time to obtain an analog output voltage, and the processing circuit obtains the characteristics of the optical signal according to the analog output voltage.
  • the light detection module described in the embodiments of the present disclosure uses the current capacitance integration principle through the capacitance integration conversion circuit to convert the photocurrent into a sampling voltage (the sampling voltage is the analog output voltage), and the voltage value of the analog output voltage is
  • the ratio between the absolute value of the variation of the photocurrent and the absolute value of the variation of the photocurrent is the transfer coefficient of the capacitance-integrating conversion circuit, and the transfer coefficient is related to the capacitance value and the integration time of the integration capacitor.
  • the transfer coefficient is related to the capacitance value and the integration time of the integration capacitor.
  • the embodiment of the present disclosure adopts the method of small capacitance integration to convert the photocurrent of the photodiode into a sampling voltage capable of analog-to-digital conversion, and can collect a smaller photocurrent, that is, a leakage current of tens of pA, which reduces the parallel connection of photodiodes. number, reducing the area occupied by the photodiode.
  • the integration time of the capacitance integral amplifier circuit is also the time for integrating and converting the photocurrent.
  • N is equal to 4, but in actual operation, N may be any positive integer, and the value of N may be selected according to actual conditions.
  • the light detection module described in the embodiment of the present disclosure includes a first light sensing circuit 11, a second light sensing circuit 12, a third light sensing circuit 13, a fourth light sensing circuit 14, a control circuit 21, Capacitance integral conversion circuit 22 and processing circuit 23;
  • the first light-sensing circuit 11 is used to sense a red light signal to generate a first photocurrent
  • the second photosensitive circuit 12 is used to sense the green light signal to generate a second photocurrent
  • the third light-sensing circuit 13 is used to sense a blue light signal to generate a third photocurrent
  • the fourth light-sensing circuit 14 is used to sense a white light signal to generate a fourth photocurrent
  • the control circuit 21 is connected with the first photosensitive circuit 11, the second photosensitive circuit 12, the third photosensitive circuit 13, the fourth photosensitive circuit 14 and the capacitance integral conversion circuit 22 respectively. Electrically connected, used to control time-sharing to provide the first photocurrent, the second photocurrent, the third photocurrent, and the fourth photocurrent to the capacitance integration amplifier circuit 22, and used to control the The conversion parameters of the capacitance integral amplifier circuit 22;
  • the capacitance integration conversion circuit 22 is used to convert the first photocurrent according to the conversion parameter and integration time to obtain a corresponding first analog output voltage, and convert the second photocurrent to obtain a corresponding converting the third photocurrent to obtain a corresponding third analog output voltage, and converting the fourth photocurrent to obtain a corresponding fourth analog output voltage;
  • the processing circuit 23 is electrically connected to the capacitance integration conversion circuit 22, and is used to obtain the characteristics of the red light signal according to the first analog output voltage, and obtain the characteristics of the green light signal according to the second analog output voltage.
  • the characteristic is that the characteristic of the blue light signal is obtained according to the third analog output voltage, and the characteristic of the white light signal is obtained according to the fourth analog output voltage.
  • the capacitance integral conversion circuit includes a conversion subcircuit, a sampling subcircuit, and a sampling control subcircuit;
  • the control circuit includes a photosensitive control subcircuit and a capacitance control subcircuit;
  • the sampling subcircuit Including M integral capacitors; M is a positive integer;
  • the photosensitive control sub-circuit is used to provide the photocurrent generated by each photosensitive circuit to the input end of the conversion sub-circuit under the control of the photosensitive control signal;
  • the capacitance control sub-circuit is used to control the first end of each integration capacitor to communicate with the input end of the conversion sub-circuit under the control of the capacitance control signal; the second end of each integration capacitor is connected to the input end of the conversion sub-circuit The output end of the conversion sub-circuit is electrically connected;
  • the sampling control subcircuit is used to control the connection or disconnection between the output terminal of the conversion subcircuit and the processing circuit under the control of the sampling control signal;
  • the conversion sub-circuit is used to convert the photocurrent to obtain and output the analog output voltage through the output terminal of the conversion sub-circuit;
  • the conversion parameter is the capacitance value of the integration capacitor currently connected to the input terminal of the conversion sub-circuit.
  • the capacitance integral conversion circuit may include a conversion subcircuit, a sampling subcircuit and a sampling control subcircuit
  • the control circuit may include a photosensitive control subcircuit and a capacitance control subcircuit
  • the sampling subcircuit may include M Integral capacitor
  • the photosensitive control sub-circuit controls the time-sharing to provide the photocurrent generated by each photo-sensitive circuit to the input end of the conversion sub-circuit
  • the capacitance control sub-circuit controls the connection between each integral capacitor time-sharing and the input end of the conversion sub-circuit
  • the sampling control subcircuit controls the connection or disconnection between the output end of the conversion subcircuit and the processing circuit
  • the conversion subcircuit converts the photocurrent into a corresponding analog output voltage.
  • M is equal to 5 for illustration, but in actual operation, N may be a positive integer, and the value of M may be selected according to actual conditions.
  • the photocurrent generated by the photosensitive circuit is as small as tens of pA
  • a smaller integrating capacitor (pF level) is required to integrate.
  • the pF Ultra-small capacitors are fabricated on the display substrate using semiconductor technology.
  • the embodiment of the present disclosure adopts a standard capacitor with a large capacitance and integrates the standard capacitor with a large capacitance into the circuit board or driver IC.
  • the integral capacitor with small capacitance value can be arranged on the display substrate. Since the plate size of the integral capacitor with larger capacitance value is larger, the integral capacitor with larger capacitance value can be arranged on the circuit board or the driver. integrated circuit.
  • the capacitance integration conversion circuit includes a conversion sub-circuit 31, a sampling sub-circuit and a sampling control sub-circuit 33;
  • the control The circuit includes a photosensitive control subcircuit 41 and a capacitance control subcircuit 42;
  • the sampling subcircuit includes a first integrating capacitor CG1, a second integrating capacitor CG2, a third integrating capacitor CG3, a fourth integrating capacitor CG4 and a fifth integrating capacitor CG5 ;
  • the photosensitive control subcircuit 41 is electrically connected to the first photosensitive circuit 11, the second photosensitive circuit 12, the third photosensitive circuit 13, the fourth photosensitive circuit 14 and the input end of the conversion subcircuit 31, respectively, Under the control of the photosensitive control signal, it is used to control the time-sharing of the first photocurrent generated by the first photosensitive circuit 11, the second photocurrent generated by the second photosensitive sub-circuit 12, and the photocurrent generated by the third photosensitive circuit 13.
  • the third photocurrent and the fourth photocurrent generated by the fourth photosensitive circuit 14 are provided to the input end of the conversion sub-circuit 31;
  • the capacitance control sub-circuit 42 is connected to the first terminal of the first integrating capacitor CG1, the first terminal of the second integrating capacitor CG2, the first terminal of the third integrating capacitor CG3, the first terminal of the fourth integrating capacitor CG4, the first terminal of the
  • the first end of the five integral capacitor CG5 is electrically connected to the input end of the conversion sub-circuit 31, and is used to control the first end of the first integral capacitor CG1 and the first end of the second integral capacitor CG2 under the control of the capacitance control signal.
  • the first end of the third integrating capacitor CG3, and the first end of the fourth integrating capacitor CG4 are time-divided and communicated with the input end of the conversion sub-circuit 31; the second end of the first integrating capacitor CG1, the The second terminal of the second integrating capacitor CG2, the second terminal of the third integrating capacitor CG3, the second terminal of the fourth integrating capacitor CG4 and the second terminal of the fifth integrating capacitor CG5 are respectively connected to the The output terminal of the conversion sub-circuit 31 is electrically connected;
  • the sampling control sub-circuit 33 is electrically connected to the output end of the conversion sub-circuit 31 and the processing circuit 23 respectively, and is used to control the output end of the conversion sub-circuit 31 and the processing circuit 23 under the control of the sampling control signal. 23 are connected or disconnected;
  • the conversion sub-circuit 31 is used to convert each of the photocurrents to obtain and output the analog output voltage through the output terminal of the conversion sub-circuit 31;
  • the conversion parameter is the capacitance value of the integral capacitor currently connected to the input terminal of the conversion sub-circuit 31 .
  • the photosensitive control subcircuit 41 controls the photosensitive subcircuit that provides photocurrent to the input end of the conversion subcircuit 31.
  • the capacitance control The subcircuit 42 controls the integral capacitance connected between the input terminals of the conversion subcircuit 31, the sampling control subcircuit 33 controls whether the output terminal of the conversion subcircuit 31 is connected with the processing circuit 23, and the conversion subcircuit Each photocurrent is converted to obtain an analog output voltage.
  • the light detection module may further include a reset circuit; the reset circuit includes M reset sub-circuits;
  • the mth reset subcircuit is electrically connected to the first terminal of the mth integrating capacitor, the second terminal of the mth integrating capacitor and the reset control terminal respectively, and is used to control the reset control signal provided by the reset control terminal, controlling the communication between the first terminal of the mth integrating capacitor and the second terminal of the mth integrating capacitor, so as to release the charge stored in the mth integrating capacitor;
  • n is a positive integer less than or equal to M.
  • the photodetection module may further include a reset circuit, the reset circuit includes M reset subcircuits, and the mth reset subcircuit controls the first terminal of the mth integrating capacitor to connect to the The second ends of the m integral capacitors are connected to release the charge stored in the m th integral capacitor so as not to affect the sampling result.
  • the reset circuit includes M reset subcircuits
  • the mth reset subcircuit controls the first terminal of the mth integrating capacitor to connect to the The second ends of the m integral capacitors are connected to release the charge stored in the m th integral capacitor so as not to affect the sampling result.
  • the light detection module described in at least one embodiment of the present disclosure may further include a reset circuit;
  • the reset circuit includes a first A reset subcircuit 51, a second reset subcircuit 52, a third reset subcircuit 53, a fourth reset subcircuit 54 and a fifth reset subcircuit 55;
  • the first reset subcircuit 51 is electrically connected to the first end of the first integrating capacitor CG1, the second end of the first integrating capacitor CG1, and the reset control terminal SR, respectively, and is used to provide the reset control terminal SR Under the control of a reset control signal, controlling the connection between the first terminal of the first integrating capacitor CG1 and the second terminal of the first integrating capacitor CG1, so as to release the charge stored in the first integrating capacitor CG1;
  • the first reset subcircuit 52 is electrically connected to the first end of the second integrating capacitor CG2, the second end of the second integrating capacitor CG2, and the reset control terminal SR, respectively, and is used for providing the reset control terminal SR Under the control of the reset control signal, control the connection between the first terminal of the second integrating capacitor CG2 and the second terminal of the second integrating capacitor CG2, so as to release the charge stored in the second integrating capacitor CG2;
  • the third reset subcircuit 53 is electrically connected to the first end of the third integrating capacitor CG3, the second end of the third integrating capacitor CG3, and the reset control terminal SR respectively, and is used for providing the reset control terminal SR at the reset control terminal SR Under the control of the reset control signal, control the connection between the first terminal of the third integrating capacitor CG3 and the second terminal of the third integrating capacitor CG3, so as to release the charge stored in the third integrating capacitor CG3;
  • the fourth reset subcircuit 54 is electrically connected to the first end of the fourth integrating capacitor CG4, the second end of the fourth integrating capacitor CG4, and the reset control terminal SR, respectively, for Under the control of the reset control signal, control the connection between the first terminal of the fourth integrating capacitor CG4 and the second terminal of the fourth integrating capacitor CG4, so as to release the charge stored in the fourth integrating capacitor CG4;
  • the fifth reset subcircuit 55 is electrically connected to the first end of the fifth integrating capacitor CG5, the second end of the fifth integrating capacitor CG5, and the reset control terminal SR, respectively, for providing the reset control terminal SR at the reset control terminal SR. Under the control of the reset control signal, the connection between the first terminal of the fifth integrating capacitor CG5 and the second terminal of the fifth integrating capacitor CG5 is controlled, so as to release the charge stored in the fifth integrating capacitor CG5.
  • the first reset sub-circuit 51 controls the connection between the first end of the first integral capacitor CG1 and the input end of the conversion sub-circuit 31 from disconnection to connection.
  • the second terminals of the first integrating capacitor CG1 are connected to release the charge stored in the first integrating capacitor CG1 so as not to affect the sampling result;
  • the second reset sub-circuit 52 controls the connection between the first end of the second integral capacitor CG2 and the input end of the conversion sub-circuit 31 before the connection between the first end of the second integral capacitor CG2 and the input end of the conversion sub-circuit 31
  • the second ends of the second integrating capacitor CG2 are connected to release the charge stored in the second integrating capacitor CG2 so as not to affect the sampling result;
  • the third reset sub-circuit 53 controls the connection between the first end of the third integral capacitor CG3 and the input end of the conversion sub-circuit 31 before the connection between the first end of the third integral capacitor CG3 and the input end of the conversion sub-circuit 31 is connected.
  • the second terminals of the third integrating capacitor CG3 are connected to release the charge stored in the third integrating capacitor CG3 so as not to affect the sampling result;
  • the fourth reset sub-circuit 54 controls the connection between the first end of the fourth integral capacitor CG4 and the input end of the conversion sub-circuit 31 before the connection between the first end of the fourth integral capacitor CG4 and the input end of the conversion sub-circuit 31 is disconnected.
  • the second terminals of the fourth integrating capacitor CG4 are connected to release the charge stored in the fourth integrating capacitor CG4 so as not to affect the sampling result;
  • the fifth reset sub-circuit 55 controls the connection between the first end of the fifth integral capacitor CG5 and the input end of the conversion sub-circuit 31 before the connection between the first end of the fifth integral capacitor CG5 and the input end of the conversion sub-circuit 31 is connected.
  • the second terminals of the fifth integrating capacitor CG5 are connected to release the charge stored in the fifth integrating capacitor CG5 so as not to affect the sampling result.
  • the photosensitive control subcircuit includes N photosensitive control transistors;
  • the capacitance control subcircuit includes M capacitance control transistors;
  • n is a positive integer less than or equal to N,
  • m is a positive integer less than or equal to M Integer;
  • the sampling control subcircuit includes a sampling switch and a storage capacitor;
  • the control pole of the nth photosensitive control transistor is electrically connected to the nth photosensitive control terminal, the first pole of the nth photosensitive control transistor is electrically connected to the nth photocurrent output terminal, and the second pole of the nth photosensitive control transistor is connected to the nth photosensitive control transistor.
  • the input terminal of the conversion sub-circuit is electrically connected; the nth photosensitive control terminal is used to provide the nth photosensitive control signal;
  • the control pole of the mth capacitance control transistor is electrically connected to the mth capacitance control terminal, the first pole of the mth capacitance control transistor is electrically connected to the input end of the conversion subcircuit, and the second pole of the mth capacitance control transistor is connected to the mth capacitance control terminal.
  • the first terminal of the integrating capacitor is electrically connected, and the second terminal of the mth integrating capacitor is electrically connected to the output terminal of the conversion sub-circuit; the mth capacitor control terminal is used to provide the mth capacitor control signal;
  • the control end of the sampling switch is electrically connected to the sampling control end, the first end of the sampling switch is electrically connected to the output end of the conversion sub-circuit, and the second end of the sampling switch is electrically connected to the processing circuit;
  • the first end of the storage capacitor is electrically connected to the second end of the sampling switch, and the second end of the storage capacitor is electrically connected to the DC voltage end.
  • the DC voltage terminal may be a ground terminal, but not limited thereto.
  • the light detection module described in at least one embodiment of the present disclosure may further include a filter circuit
  • the filter circuit is connected between the output end of the conversion sub-circuit and the first end of the sampling switch, and is used to filter out high-frequency noise in the analog output voltage, and filter out the high-frequency noise
  • the analog output voltage is provided to the first end of the sampling switch.
  • the filter circuit may be a low-pass filter circuit, which can effectively filter high-frequency noise in the analog output voltage, so that the output signal is stable and noise fluctuations are reduced.
  • the sampling control subcircuit 33 includes a sampling switch S0 and a storage capacitor C0; the photodetection module described in the present disclosure At least one embodiment of also includes a filter circuit 60;
  • the control end of the sampling switch S0 is electrically connected to the sampling control end KD, the first end of the sampling switch S0 is electrically connected to the output end of the conversion sub-circuit 31 through the filter circuit 60, and the sampling switch S0 The second end is electrically connected to the processing circuit 23;
  • the first end of the storage capacitor C0 is electrically connected to the second end of the sampling switch S0, and the second end of the storage capacitor C0 is electrically connected to the ground;
  • the filter circuit 60 is connected between the output end of the conversion sub-circuit 31 and the first end of the sampling switch S0, and is used to filter out high-frequency noise in the analog output voltage, and filter out high-frequency noise The analog output voltage after the noise is provided to the first terminal of the sampling switch S0.
  • the mth reset subcircuit includes an mth reset transistor
  • the control pole of the mth reset transistor is electrically connected to the reset control terminal, the first pole of the mth reset transistor is electrically connected to the first end of the mth integration capacitor, and the first pole of the mth reset transistor is electrically connected to the first terminal of the mth integration capacitor.
  • the diode is electrically connected to the second end of the mth integrating capacitor.
  • the N photosensitive circuits, the photosensitive control subcircuit, the capacitance control subcircuit and the reset circuit may all be disposed on a display substrate.
  • the conversion subcircuit includes an operational amplifier; the inverting input terminal of the operational amplifier is the input terminal of the conversion subcircuit, and the output terminal of the operational amplifier is the output terminal of the conversion subcircuit;
  • the non-inverting input terminal of the operational amplifier is electrically connected to the reference voltage terminal, and the reference voltage terminal is used to provide a reference voltage.
  • the voltage value of the reference voltage may be 1.5V or 2V, but not limited thereto, and the voltage value of the reference voltage may be determined according to the input voltage of the digital-to-analog converter.
  • the light detection module may further include a control signal generating unit;
  • the control signal generating unit is used for providing sampling control signal, photosensitive control signal, capacitance control signal and reset control signal.
  • control signal generation unit may include a control signal generation circuit and a level shifter
  • the control signal generation circuit is used to provide a sampling control signal, an input photosensitive control signal, an input capacitance control signal and an input reset control signal;
  • the level shifter is electrically connected to the control signal generating circuit, and is used for performing level conversion on the input photosensitive control signal to generate the photosensitive control signal, and performing level conversion on the input capacitance control signal. converting to generate the capacitance control signal, and performing level conversion on the input reset control signal to generate the reset control signal.
  • the processing circuit includes an analog-to-digital converter and an output processing unit;
  • the analog-to-digital converter is used to convert the analog output voltage into an output digital signal
  • the output processing unit is electrically connected to the analog-to-digital converter, and is used to receive the output digital signal, obtain the characteristics of the optical signal according to the output digital signal, and transmit the characteristic information of the optical signal to An application unit, so that the application unit can obtain current ambient light data according to the light signal.
  • the feature of the optical signal may include at least one of light intensity, brightness, color coordinates, and color temperature, but is not limited thereto.
  • the output processing unit may be an algorithm unit, which processes the output digital signal, judges the validity of the output digital signal, and converts the output digital signal into a digital value corresponding to light intensity and brightness. signal, and calculate the optical characteristic parameters such as color coordinates or color temperature according to the output digital signals corresponding to different colors, so as to meet the needs of the application unit.
  • the light detection module described in at least one embodiment of the present disclosure may further include a control signal generating unit; the processing circuit Including an analog-to-digital converter A0 and an output processing unit 72; the control signal generating unit includes a control signal generating circuit 701 and a level shifter 702;
  • the control signal generating circuit 701 is electrically connected to the sampling control terminal KD and the level shifter 702 respectively, and is used to provide a sampling control signal for the sampling control terminal KD, and is used to provide a sampling control signal to the level shifter 702 Provide input photosensitive control signal, input capacitance control signal and input reset control signal;
  • the level shifter 702 is electrically connected to the reset control terminal SR, the photosensitive control subcircuit 41, the capacitance control subcircuit 42 and the reset control terminal SR, and is used to electrically control the input photosensitive control signal.
  • level conversion to generate the photosensitive control signal perform level conversion on the input capacitance control signal to generate the capacitance control signal, and perform level conversion on the input reset control signal to generate the reset control signal signal, and provide the photosensitive control signal to the photosensitive control subcircuit 41, provide the capacitance control signal to the capacitance control subcircuit 42, and provide the reset control signal to the reset control terminal SR;
  • the analog-to-digital converter A0 is electrically connected to the second end of the sampling switch S0, and is used to convert the analog output voltage into an output digital signal;
  • the output processing unit 72 is electrically connected to the analog-to-digital converter A0, and is configured to receive the output digital signal, and obtain the characteristics of the optical signal according to the output digital signal.
  • each photosensitive control transistor, each capacitance control transistor, and each reset transistor when each photosensitive control transistor, each capacitance control transistor, and each reset transistor is an n-type transistor, the potential of each photosensitive control signal, the potential of each capacitance control signal, and each reset control signal
  • the potential of each photosensitive control transistor, each capacitance control transistor, and each reset transistor were turned on when the electric potential was 7V, when each photosensitive control transistor, each capacitance control transistor, and each reset transistor were p-type transistors, when each photosensitive control signal , the potential of each capacitance control signal, and the potential of each reset control signal are -7V, each photosensitive control transistor, each capacitance control transistor, and each reset transistor are turned on; and each control signal provided by the control signal generating circuit 701
  • the low voltage value and the high voltage value are 0V and 3V respectively.
  • the level shifter 70 is required to convert the 0V voltage to -7V voltage, and convert the 3.3V voltage to 7V voltage, so as to meet the requirements of each photosensitive control transistor control circuit. level, each capacitor control transistor control level, each reset transistor control level requirements.
  • the light detection module may further include a micro control unit; both the control signal generation circuit and the output processing unit are disposed in the micro control unit.
  • the light detection module may also include a filter circuit
  • the micro control unit, the level converter, the analog-to-digital converter, the filter circuit, and the conversion sub-circuit and sampling control sub-circuit included in the capacitance integral conversion circuit may all be arranged on a circuit board or on the driver IC.
  • the nth photosensitive circuit includes an nth photodiode; n is a positive integer less than or equal to N;
  • the cathode of the nth photodiode is electrically connected to the power supply voltage terminal, and the anode of the nth photodiode is used to provide the nth photocurrent;
  • the power supply voltage terminal is used to provide a power supply voltage signal.
  • the processing circuit includes an analog-to-digital converter A0 and an output processing unit;
  • the control signal generation unit includes a control signal generation circuit and a level shifter 702;
  • control signal generating circuit and the output processing unit are integrated in the micro control unit 80;
  • the first photosensitive circuit includes a first photodiode D1; the cathode of the first photodiode D1 is electrically connected to the power supply voltage terminal VDD, and the first photodiode D1 is used to sense a red light signal to generate a corresponding first Photocurrent;
  • the second photosensitive circuit includes a second photodiode D2; the cathode of the second photodiode D2 is electrically connected to the power supply voltage terminal VDD, and the second photodiode D2 is used to sense a green light signal to generate a corresponding second photodiode D2. Photocurrent;
  • the third light-sensing circuit includes a third photodiode D3; the cathode of the third photodiode D3 is electrically connected to the power supply voltage terminal VDD, and the third photodiode D3 is used to sense blue light signals to generate corresponding third photodiodes. Photocurrent;
  • the fourth light-sensing circuit includes a fourth photodiode D4; the cathode of the fourth photodiode D4 is electrically connected to the power supply voltage terminal VDD, and the fourth photodiode D4 is used for sensing white light signals to generate corresponding fourth photodiodes. Photocurrent;
  • the photosensitive control subcircuit includes a first photosensitive control transistor TR, a second photosensitive control transistor TG, a third photosensitive control transistor TB, and a fourth photosensitive control transistor TW;
  • the capacitance control subcircuit includes a first capacitor Control transistor TG1, second capacitance control transistor TG2, third capacitance control transistor TG3, fourth capacitance control transistor TG4 and fifth capacitance control transistor TG5;
  • the conversion sub-circuit 31 includes an operational amplifier O0;
  • the gate of the first photosensitive control transistor TR is electrically connected to the first photosensitive control terminal KR, the source of the first photosensitive control transistor TR is electrically connected to the first photocurrent output terminal, and the drain of the first photosensitive control transistor TR pole is electrically connected to the inverting input terminal of the operational amplifier O0, and the first photocurrent output terminal is electrically connected to the anode of the first photodiode D1;
  • the gate of the second photosensitive control transistor TG is electrically connected to the second photosensitive control terminal KG, the source of the second photosensitive control transistor TG is electrically connected to the second photocurrent output terminal, and the drain of the second photosensitive control transistor TG pole is electrically connected to the inverting input terminal of the operational amplifier O0, and the second photocurrent output terminal is electrically connected to the anode of the second photodiode D2;
  • the gate of the third photosensitive control transistor TB is electrically connected to the third photosensitive control terminal KB, the source of the third photosensitive control transistor TB is electrically connected to the third photocurrent output terminal, and the drain of the third photosensitive control transistor TB pole is electrically connected to the inverting input terminal of the operational amplifier O0, and the third photocurrent output terminal is electrically connected to the anode of the third photodiode D3;
  • the gate of the fourth photosensitive control transistor TW is electrically connected to the fourth photosensitive control terminal KW, the source of the fourth photosensitive control transistor TW is electrically connected to the fourth photocurrent output terminal, and the drain of the fourth photosensitive control transistor TW pole is electrically connected to the inverting input terminal of the operational amplifier O0, and the fourth photocurrent output terminal is electrically connected to the anode of the fourth photodiode D4;
  • the gate of the first capacitance control transistor TG1 is electrically connected to the first capacitance control terminal G1, the source of the first capacitance control transistor TG1 is electrically connected to the inverting input terminal of the operational amplifier O0, and the drain of the first capacitance control transistor TG1
  • the pole is electrically connected to the first end of the first integrating capacitor CG1;
  • the gate of the second capacitance control transistor TG2 is electrically connected to the second capacitance control terminal G2, the source of the second capacitance control transistor TG2 is electrically connected to the inverting input terminal of the operational amplifier O0, and the drain of the second capacitance control transistor TG2
  • the pole is electrically connected to the first end of the second integrating capacitor CG2;
  • the gate of the third capacitance control transistor TG3 is electrically connected to the third capacitance control terminal G3, the source of the third capacitance control transistor TG3 is electrically connected to the inverting input terminal of the operational amplifier O0, and the drain of the third capacitance control transistor TG3
  • the pole is electrically connected to the first end of the third integrating capacitor CG3;
  • the gate of the fourth capacitance control transistor TG4 is electrically connected to the fourth capacitance control terminal G4, the source of the fourth capacitance control transistor TG4 is electrically connected to the inverting input terminal of the operational amplifier O0, and the drain of the fourth capacitance control transistor TG4 The pole is electrically connected to the first end of the fourth integrating capacitor CG4;
  • the second terminal of the first integrating capacitor CG1, the second terminal of the second integrating capacitor CG2, the second terminal of the third integrating capacitor CG3, the second terminal of the fourth integrating capacitor CG4 and the The second terminals of the fifth integrating capacitor CG5 are electrically connected to the output terminal O1 of the operational amplifier O0;
  • the first reset subcircuit includes a first reset transistor TR1, the second reset subcircuit includes a second reset transistor TR2, the third reset subcircuit includes a third reset transistor TR3, the fourth reset subcircuit includes a fourth reset transistor TR4, and the fifth reset subcircuit includes a fourth reset transistor TR4.
  • the reset subcircuit includes a fifth reset transistor TR5;
  • the gate of the first reset transistor TR1 is electrically connected to the reset control terminal SR, the source of the first reset transistor TR1 is electrically connected to the first end of the first integrating capacitor CG1, and the first reset The drain of the transistor TR1 is electrically connected to the second end of the first integrating capacitor CG1;
  • the gate of the second reset transistor TR2 is electrically connected to the reset control terminal SR, the source of the second reset transistor TR2 is electrically connected to the first end of the second integration capacitor CG2, and the second reset The drain of the transistor TR2 is electrically connected to the second terminal of the second integrating capacitor CG2;
  • the gate of the third reset transistor TR3 is electrically connected to the reset control terminal SR, the source of the third reset transistor TR3 is electrically connected to the first end of the third integration capacitor CG3, and the third reset The drain of the transistor TR3 is electrically connected to the second end of the third integrating capacitor CG3;
  • the gate of the fourth reset transistor TR4 is electrically connected to the reset control terminal SR, the source of the fourth reset transistor TR4 is electrically connected to the first end of the fourth integration capacitor CG4, and the fourth reset The drain of the transistor TR4 is electrically connected to the second end of the fourth integrating capacitor CG4;
  • the gate of the fifth reset transistor TR5 is electrically connected to the reset control terminal SR, the source of the fifth reset transistor TR5 is electrically connected to the first end of the fifth integration capacitor CG5, and the fifth reset The drain of the transistor TR5 is electrically connected to the second end of the fifth integrating capacitor CG5;
  • the non-inverting input terminal of the operational amplifier O0 is electrically connected to the reference voltage terminal CR, and the reference voltage terminal CR is used to provide a reference voltage Vref, and the voltage value of the reference voltage Vref is 2.0V;
  • the filter circuit includes a first filter capacitor C1, a filter resistor R0 and a second filter capacitor C2;
  • the first end of the first filter capacitor C1 is electrically connected to the output end of the operational amplifier O0, and the second end of the first filter capacitor C1 is grounded;
  • the first end of the filter resistor R0 is electrically connected to the output end of the operational amplifier O0, and the second end of the filter resistor R0 is electrically connected to the first end of the sampling switch S0;
  • the first end of the second filter capacitor C2 is electrically connected to the second end of the filter resistor R0, and the second end of the second filter capacitor C2 is grounded;
  • the control terminal of the sampling switch S0 is electrically connected to the sampling control terminal KD, the second terminal of the sampling switch S0 is electrically connected to the first terminal of the storage capacitor C0, and the second terminal of the storage capacitor C0 is grounded;
  • the second end of the sampling switch S0 is electrically connected to the input end of the analog-to-digital converter A0, and the output end of the analog-to-digital converter A0 is electrically connected to the micro control unit 80;
  • the analog-to-digital converter A0 is used to perform analog-to-digital conversion on the analog output voltage connected to its input terminal to obtain a corresponding output digital signal;
  • the output processing unit arranged in the micro control unit 80 is used to obtain the characteristics of the corresponding optical signal according to the output digital signal;
  • the control signal generation circuit arranged in the micro control unit 80 is electrically connected to the sampling control terminal KD, and is used to provide a sampling control signal for the sampling control terminal KD; the control signal generation circuit is also connected to the level
  • the converter 702 is electrically connected to provide the level shifter 702 with an input reset control signal, a first input photosensitive control signal, a second input photosensitive control signal, a third input photosensitive control signal, a fourth input photosensitive Inductive control signal, first input capacitance control signal, second input capacitance control signal, third input capacitance control signal, fourth input capacitance control signal and fifth input capacitance control signal;
  • the level shifter 702 is respectively connected with the reset control terminal SR, the first photosensitive control terminal KR, the second photosensitive control terminal KG, the third photosensitive control terminal KB, the fourth photosensitive control terminal KW, and the first capacitor control terminal.
  • the terminal G1, the second capacitor control terminal G2, the third capacitor control terminal G3, the fourth capacitor control terminal G4 and the fifth capacitor control terminal G5 are electrically connected, and are used to perform level conversion on the input reset control signal to obtain a reset control signal, and provide the reset control signal to the reset control terminal SR, and use it to perform level conversion on the first input photosensitive control signal to obtain a first photosensitive control signal, and transfer the first photosensitive
  • the sensing control signal is provided to the first photo sensing control terminal KR, and the second input photo sensing control signal is level-converted to obtain a second photo sensing control signal, and the second photo sensing control signal is provided to the second
  • the light-sensing control terminal KG performs level conversion on the third input light-sensing control signal to
  • the fourth input photosensitive control signal is level-converted to obtain a fourth photosensitive control signal, and the fourth photosensitive control signal is provided to the first photosensitive control terminal KW, and used to control the first input Perform level conversion on the capacitance control signal to obtain a first capacitance control signal, and provide the first capacitance control signal to the first capacitance control terminal G1, and perform level conversion on the second input capacitance control signal to obtain a second capacitance control signal capacitance control signal, and provide the second capacitance control signal to the second capacitance control terminal G2, perform level conversion on the third input capacitance control signal to obtain a third capacitance control signal, and transfer the third capacitance
  • the control signal is provided to the third capacitance control terminal G3, and the level conversion is performed on the fourth input capacitance control signal to obtain a fourth capacitance control signal, and the fourth capacitance control signal is provided to the fourth capacitance control terminal G4, performing level conversion on the fifth input capacitance control signal to obtain a fifth capacitance control signal, and providing
  • the micro control unit 80 can also include a first serial output interface Sc1 and a second serial output interface Sc2, and can transmit the light through the first serial output interface Sc1 and the second serial interface Sc2 The characteristics of the signal are output to the application unit, so that the application unit can obtain the data of the current ambient light according to the light signal.
  • the first serial output interface Sc1 can be an SPI interface (serial peripheral interface) or I 2 C (bidirectional two-wire synchronous serial bus) interface
  • the second serial output interface may be an SPI interface (Serial Peripheral Interface) or an I 2 C (bidirectional two-wire synchronous serial bus) interface, but not limited thereto.
  • the filter circuit includes a filter resistor and two filter capacitors, but the structure of each filter circuit is not limited to the above structure, the filter circuit only needs The purpose of filtering out high-frequency noise can be achieved, and the specific structure of the filter circuit can be selected according to actual conditions;
  • the filter circuit is a low-pass filter circuit, which can effectively filter out high-frequency noise, so that the output signal is stable and the noise fluctuation is reduced.
  • each photosensitive control transistor, each sampling control transistor and each reset transistor may be n-type transistors, but not limited thereto. In actual operation, the above transistors can also be replaced by p-type transistors.
  • each photodiode, each photosensitive control transistor, each capacitance control transistor and each reset transistor can be arranged on the display substrate, and the thin film on the display substrate can be fabricated.
  • the operational amplifier, the filter circuit, sampling switch, storage capacitor, analog-to-digital converter, micro control unit and level shifter can It is set on the circuit board or the display driving integrated circuit.
  • each photosensitive control transistor, each capacitance control transistor, and each reset transistor is manufactured by TFT (thin film transistor) technology, including LTPS (low temperature polysilicon) PMOS (P type metal-oxide-semiconductor transistor), LTPS NMOS (N-type metal-oxide-semiconductor transistor) and IGZO (indium gallium zinc oxide) oxide (oxide) etc.
  • TFT thin film transistor
  • PMOS P type metal-oxide-semiconductor transistor
  • LTPS NMOS N-type metal-oxide-semiconductor transistor
  • IGZO indium gallium zinc oxide
  • each reset transistor When the capacitance control transistor and each reset transistor are n-type transistors, when the potential of each light control signal is 7V, each light control transistor is turned on, and when the potential of each capacitance control signal is 7V, each capacitance control transistor is turned on , when the potential of each reset control signal is 7V, each reset transistor is turned on; when each photosensitive control transistor, each capacitance control transistor and each reset transistor are p-type transistors, when the potential of each photosensitive control signal is -7V , each photosensitive control transistor is turned on, and when the potential of each capacitance control signal is-7V, each capacitance control transistor is turned on, and when the potential of each reset control signal is-7V, each reset transistor is turned on;
  • the low voltage value and high voltage value of each control signal provided by the control unit 80 are 0V and 3V respectively.
  • the level shifter 70 is required to convert the 0V voltage to -7V voltage, and convert the 3.3V voltage to 7V voltage. To meet the requirements of each control transistor control level
  • the capacitance value of the first integration capacitor CG1, the capacitance value of the second integration capacitor CG2, the capacitance value of the third integration capacitor CG3, the capacitance value of the fourth integration capacitor are different from each other.
  • the capacitance value of each integration capacitor can be flexibly selected according to the current value range and integration time of the photocurrent generated by each photodiode.
  • the capacitance value of the first integration capacitor CG1 can be 0.1pF
  • the capacitance value of the second integration capacitor CG2 can be 1pF
  • the capacitance value of the third integration capacitor CG3 It can be 10pF
  • the capacitance value of the fourth integral capacitor CG4 can be 100pF
  • the capacitance value of the fifth integral capacitor CG5 can be 1nF, but not limited thereto;
  • the capacitance value of the first integrating capacitor CG1 and the capacitance value of the second integrating capacitor CG2 are relatively small, and the first integrating capacitor CG1 and the second integrating capacitor CG2 may be arranged on the display substrate;
  • the capacitance value of the third integration capacitor CG3, the capacitance value of the fourth integration capacitor CG4, and the capacitance value of the fifth integration capacitor CG5 are relatively large, and the third integration capacitor CG3 and the fourth integration capacitor CG4 And the fifth integrating capacitor CG5 may be disposed on an FPC (flexible printed circuit).
  • the capacitance value of at least part of the integration capacitor is less than 10pF, and the at least part of the integration capacitor can be arranged on the display substrate, and the sampling sub-circuit includes other than the at least part of the The integral capacitor other than the integral capacitor can be arranged on the circuit board or the driver integrated circuit.
  • the input voltage range of the analog-to-digital converter A0 is greater than or equal to VS3 and less than or equal to VS4, if the analog-to-digital converter A0 is an n-bit analog-to-digital Converter, the conversion accuracy of one LSB (least significant bit) can be obtained as (VS4-VS3)/2 n .
  • n 16bit
  • the input voltage range of the 16bit (bit) analog-to-digital converter is greater than or equal to 0V and Less than or equal to 3.64V, the conversion accuracy of one LSB is 55.5uV.
  • the converted digital signal has a high-precision linear relationship, wherein VS3 ⁇ VS1 ⁇ VS2 ⁇ VS4.
  • the input voltage range of the analog-to-digital converter is greater than or equal to the first voltage VS1 and less than the second voltage VS2.
  • VS1 may be 0.2V
  • VS2 may be 2.0V
  • VS3 can be 0V
  • VS4 can be 3.64V, that is, the input voltage range of the input analog-to-digital converter A0 is allowed to be greater than or equal to 0V and less than or equal to 3.64V, but when the input voltage range is greater than or equal to 0.2V and less than or equal to 2.0V, There is a high-precision linear relationship in the analog-to-digital conversion, and the precision is relatively high.
  • the high-precision voltage conversion range of the analog-to-digital converter A0 is the range of the input voltage that the analog-to-digital converter A0 can accurately perform analog-to-digital conversion; the range of the analog-to-digital converter A0
  • the voltage conversion range is the range of the input voltage that the analog-to-digital converter A0 can perform analog-to-digital conversion.
  • the high-precision voltage conversion range of the AD converter A0 may be greater than or equal to the first voltage VS1 and less than or equal to VS2, and the voltage conversion range of the AD converter A0 may be greater than or equal to VS3 and less than or equal to VS4.
  • the input voltage is the voltage input to the analog-to-digital converter A0.
  • each reset transistor is reset, on the premise that each reset transistor is turned off, before S0 changes from the on state to the off state, through the corresponding The time during which the photocurrent continues to charge the corresponding integral capacitor is the integral time.
  • V0 is the potential of the output terminal of the operational amplifier O0
  • D0 is the output digital signal output by the analog-to-digital converter A0.
  • the detection cycle includes the first sampling stage S1, the second sampling stage S2, and the third sampling stage S3 that are set successively. and a fourth sampling stage S4;
  • the first sampling period S1 includes the first sampling period S11, the second sampling period S12, the third sampling period S13, the fourth sampling period S14 and the fifth sampling period S15 set successively;
  • the second sampling period S2 includes the sixth sampling period S21, the seventh sampling period S22, the eighth sampling period S23, the ninth sampling period S24 and the tenth sampling period S25 set successively;
  • the third sampling period S3 includes the eleventh sampling period S31, the twelfth sampling period S32, the thirteenth sampling period S33, the fourteenth sampling period S34 and the fifteenth sampling period S35 which are successively set;
  • the fourth sampling period S4 includes the sixteenth sampling period S41, the seventeenth sampling period S42, the eighteenth sampling period S43, the nineteenth sampling period S44 and the twentieth sampling period S45 which are successively set;
  • the first sampling time period S1 includes the first reset time period and the first integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR1 is turned on, and the first terminal of CG1 is connected to the second terminal of CG1 to release the charge in CG1 and complete the integration Capacitor charge reset work
  • the reset control signal provided by SR changes from a high-level signal to a low-level signal
  • KD provides a high-level signal
  • TR1 is turned off
  • D1 converts the red light signal it receives into the first
  • the first photocurrent the first first photocurrent is written into the first terminal of the first integrating capacitor CG1 through the conductive TR and TG1
  • the first first photocurrent flows to the first integrating capacitor CG1, and the A voltage drop is formed on the first integration capacitor CG1, that is, the first first photocurrent starts to accumulate on the first integration capacitor CG1 to realize the integration function
  • S0 is turned on, and the integration voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref- (Ir1 ⁇ t0/Cz1), wherein, Vo1 is the potential of the output terminal of the operational amplifier O0 at the end of integration, Ir1 is the current value of the first first photocurrent, t0 is the integration time, and Cz1 is the capacitance value of CG1;
  • the signal provided by KR remains a high-level signal
  • KG, KB, and KW all provide a low-level signal
  • G2 provides a high-level signal
  • G1, G3, G4, and G5 all provide a low-level signal signal
  • TR is turned on, TG, TB and TW are turned off
  • TG2 is turned on, TG1, TG3, TG4 and TG5 are all turned off
  • the second sampling period S12 includes the second reset period and the second integration period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR2 is turned on
  • S0 is turned off
  • the first terminal of CG2 is connected to the second terminal of CG2 to release the charge in CG2 ;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR2 is turned off
  • S0 is turned on
  • D1 converts the red light signal it receives into the second first photocurrent.
  • Two first photocurrents are written into the first end of CG2 through the conductive TR and TG2; the second first photocurrent flows to the second integrating capacitor CG2, forming a voltage drop on the second integrating capacitor CG2, that is, the The second first photocurrent starts to accumulate on the second integrating capacitor CG2 to realize the integral function; S0 is turned on, and the integrated voltage is stored on the storage capacitor C0;
  • Vo1 is equal to Vref-(Ir2 ⁇ t0/Cz2), among which, Vo1
  • Ir2 is the current value of the second first photocurrent
  • t0 is the integration time
  • Cz2 is the capacitance value of CG2;
  • Two integration time periods the time during which S0 is continuously turned on
  • KR provides a high-level signal
  • KG, KB, and KW all provide a low-level signal
  • G3 provides a high-level signal
  • G1, G2, G4, and G5 all provide a low-level signal
  • TR leads TG, TB and TW are turned off, TG3 is turned on, TG1, TG2, TG4 and TG5 are all turned off
  • the third sampling time period S13 includes the third reset time period and the third integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-voltage level signal
  • TR3 is turned on, and the first terminal of CG3 is connected to the second terminal of CG3 to release the charge in CG3;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR3 is turned off
  • S0 is turned on
  • D1 converts the red light signal it receives into the third first photocurrent.
  • Three first photocurrents are written into the first terminal of CG3 through the conducting TR and TG3; the third first photocurrent flows to the third integration capacitor CG3, forming a voltage drop on CG3, that is, the third first photocurrent
  • a photocurrent starts to accumulate on the third integrating capacitor CG3 to realize the integrating function;
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0;
  • Vo1 is equal to Vref-(Ir3 ⁇ t0/Cz3), where Vo1 is at the end of the integrating
  • Ir3 is the current value of the third first photocurrent
  • t0 is the integration time
  • Cz3 is the capacitance value of CG3;
  • the integration time t0 is in the third integration time period , the time during
  • KR provides a high-level signal
  • KG, KB, and KW all provide a low-level signal
  • G4 provides a high-level signal
  • G1, G2, G3, and G5 all provide a low-level signal
  • TR leads to TG, TB and TW are turned off, TG4 is turned on, TG1, TG2, TG3 and TG5 are all turned off
  • the fourth sampling time period S14 includes the fourth reset time period and the fourth integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR4 is turned on, and the first terminal of CG4 is connected to the second terminal of CG4 to release the charge in CG4;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR4 is turned off
  • S0 is turned on
  • D1 converts the red light signal it receives into the fourth first photocurrent.
  • the four first photocurrents are written into the first end of CG4 through the conducting TR and TG4; the fourth first photocurrents start to accumulate on the fourth integrating capacitor CG4 to realize the integration function; S0 is turned on and the integrating
  • the voltage is stored on the storage capacitor C0; Vo1 is equal to Vref-(Ir4 ⁇ t0/Cz4), wherein Vo1 is the potential of the output terminal of the operational amplifier O0 at the end of integration, and Ir4 is the voltage of the fourth first photocurrent Current value, t0 is the integration time, Cz4 is the capacitance value of CG4; the integration time t0 is the time during which S0 is continuously turned on in the fourth integration period, for example, the integration time t0 can be 100us; at the end of the integration ,
  • the fifth sampling period S15 KR provides high-level signals, KG, KB and KW all provide low-level signals, G5 provides high-level signals, G1, G2, G3 and G4 all provide low-level signals, and TR leads TG, TB and TW are turned off, TG5 is turned on, TG1, TG2, TG3 and TG4 are all turned off;
  • the fifth sampling time period S15 includes the fifth reset time period and the fifth integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR5 is turned on, and the first terminal of CG5 is connected to the second terminal of CG5 to release the charge in CG5;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR5 is turned off
  • S0 is turned on
  • D1 converts the red light signal it receives into the fifth first photocurrent, which Five first photocurrents are written into the first end of CG5 through the conducting TR and TG5;
  • the fifth first photocurrent flows to the fifth integrating capacitor CG5, forming a voltage drop on CG5, that is, the fifth The first photocurrent starts to accumulate on the fifth integrating capacitor CG5 to realize the integrating function;
  • S0 is turned on, and the integrated voltage is saved to the storage capacitor C0;
  • Vo1 is equal to Vref-(Ir5 ⁇ t0/Cz5), where Vo1 is the integral
  • Ir5 is the current value of the fifth first photocurrent
  • t0 is the integration time
  • Cz5 is the capacitance value of CG5;
  • the integration time t0 is at the fifth integration time segment, the time that S0 is continuously
  • the sixth sampling time period S21 includes the sixth reset time period and the sixth integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR1 is turned on
  • S0 is turned off
  • the first terminal of CG1 is connected to the second terminal of CG1 to release the charge in CG1 ;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR1 is turned off
  • D2 converts the green light signal it receives into the first and second photocurrents
  • the first and second The photocurrent is written into the first end of CG1 through the turned-on TG and TG1
  • the first second photocurrent flows to the first integrating capacitor CG1, and a voltage drop is formed on CG1, that is, the first second photocurrent Start to accumulate on the first integral capacitor CG1 to realize the integral function
  • S0 is turned on, and the integral voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Ig1 ⁇ t0/Cz1), where Vo1 is the The potential of the output terminal of the operational amplifier O0, Ig1 is the current value of the first second photocurrent, t0 is the integration time, and Cz1 is the capacitance value of CG1;
  • the integration time t0 is in the sixth integration time period, S0 lasts Turn-on time, for
  • the input terminal of the digital converter A0, the analog-to-digital converter A0 performs analog-to-digital conversion on the analog output voltage, obtains the corresponding output digital signal, and writes the output digital signal into the micro control unit 80, the micro control unit
  • the output processing unit in 80 obtains the characteristics of the corresponding green light signal according to the output digital signal;
  • the seventh sampling period S22 In the seventh sampling period S22, KG provides a high-level signal, KR, KB, and KW all provide a low-level signal, G2 provides a high-level signal, G1, G3, G4, and G5 all provide a low-level signal, and TG conducts TR, TB and TW are turned off, TG2 is turned on, TG1, TG3, TG4 and TG5 are all turned off; the seventh sampling time period S22 includes the seventh reset time period and the seventh integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR2 is turned on, and the first terminal of CG2 is connected to the second terminal of CG2 to release the charge in CG2;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR2 is turned off
  • S0 is turned on
  • D2 converts the green light signal it receives into the second second photocurrent.
  • Two second photocurrents are written into the first terminal of CG2 through the turned-on TG and TG2; the second second photocurrent flows to the second integration capacitor CG2, forming a voltage drop on CG2, that is, the second The second photocurrent starts to accumulate on the second integrating capacitor CG2 to realize the integral function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0;
  • Vo1 is equal to Vref-(Ig2 ⁇ t0/Cz2), where Vo1 is the integral
  • Ig2 is the current value of the second photocurrent of the second
  • t0 is the integration time
  • Cz2 is the capacitance value of CG2;
  • the integration time t0 is at the seventh integration time segment, the time that S0
  • the eighth sampling period S23 includes the eighth reset period and the eighth integration period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR3 is turned on, and the first terminal of CG3 is connected to the second terminal of CG3 to release the charge in CG3;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR3 is turned off
  • S0 is turned on
  • D2 converts the green light signal it receives into the third second photocurrent.
  • Three second photocurrents are written into the first end of CG3 through the turned-on TG and TG3; the third second photocurrent flows to the third integration capacitor CG3, forming a voltage drop on CG3, that is, the third The second photocurrent starts to accumulate on the third integrating capacitor CG3 to realize the integral function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0; Vo1 is equal to Vref-(Ig3 ⁇ t0/Cz3), where Vo1 is the integral
  • Ig3 is the current value of the third second photocurrent
  • t0 is the integration time
  • Cz3 is the capacitance value of CG3; the integration time t0 is at the eighth integration time segment, the time that S0 is continuously
  • the ninth sampling period S24 includes the ninth reset time period and the ninth integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR4 is turned on, and the first terminal of CG4 is connected to the second terminal of CG4 to release the charge in CG4;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR4 is turned off
  • S0 is turned on
  • D2 converts the green light signal it receives into the fourth second photocurrent.
  • Four second photocurrents are written into the first end of CG4 through the turned-on TG and TG4; the fourth second photocurrent flows to the fourth integrating capacitor CG4, forming a voltage drop on CG4, that is, the fourth The second photocurrent starts to accumulate on the fourth integrating capacitor CG4 to realize the integral function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0; Vo1 is equal to Vref-(Ig4 ⁇ t0/Cz4), where Vo1 is the integral
  • Ig4 is the current value of the fourth second photocurrent
  • t0 is the integration time
  • the tenth sampling time period S25 includes the tenth reset time period and the tenth integration time period set successively;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR5 is turned on, and the first terminal of CG5 is connected to the second terminal of CG5 to release the charge in CG5;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR5 is turned off
  • S0 is turned on
  • D2 converts the green light signal it receives into the fifth second photocurrent.
  • Five second photocurrents are written into the first end of CG5 through the turned-on TG and TG5; the fifth second photocurrent flows to the fifth integrating capacitor CG5, forming a voltage drop on CG5, that is, the fifth The second photocurrent starts to accumulate on the fifth integrating capacitor CG5 to realize the integrating function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0; Vo1 is equal to Vref-(Ig5 ⁇ t0/Cz5), wherein Vo1 is the integral
  • Ig5 is the current value of the fifth second photocurrent
  • t0 is the integration time
  • the eleventh sampling period S31 In the eleventh sampling period S31, KB provides a high-level signal, KR, KG, and KW all provide a low-level signal, G1 provides a high-level signal, G2, G3, G4, and G5 all provide a low-level signal, and TB Turn on, TR, TG and TW are off, TG1 is on, TG2, TG3, TG4 and TG5 are all off; the eleventh sampling period S31 includes the eleventh reset period and the eleventh integration period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR1 is turned on, and the first terminal of CG1 is connected to the second terminal of CG1 to release the charge in CG1;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR1 is turned off
  • S0 is turned on
  • D3 converts the blue light signal it receives into the first third photocurrent, which
  • the first third photocurrent is written into the first end of CG1 through the turned-on TB and TG1;
  • the first third photocurrent flows to the first integrating capacitor CG1, forming a voltage drop on CG1, that is, the first The third photocurrent begins to accumulate on the first integrating capacitor CG1 to realize the integral function;
  • S0 is turned on, and the integrated voltage is saved to the storage capacitor C0;
  • Vo1 is equal to Vref-(Ib1 ⁇ t0/Cz1), where Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Ib1 is the current value of the first third photocurrent, t0 is the integration time, and Cz1 is the capacitance value of CG1;
  • Integral time period the time during which S0 is
  • KB provides high-level signals
  • KR, KG and KW all provide low-level signals
  • G2 provides high-level signals
  • G1, G3, G4 and G5 all provide low-level signals
  • the twelfth sampling period S32 includes the twelfth reset time period and the twelfth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR2 is turned on, and the first terminal of CG2 is connected to the second terminal of CG2 to release the charge in CG2;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR2 is turned off
  • S0 is turned on
  • D3 converts the blue light signal it receives into the second third photocurrent
  • the second third photocurrent is written into the first end of CG2 through the turned-on TB and TG2
  • the second third photocurrent flows to the second integration capacitor CG2, forming a voltage drop on CG2, that is, the second
  • the third photocurrent begins to accumulate on the second integrating capacitor CG2 to realize the integral function
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Ib2 ⁇ t0/Cz2), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Ib2 is the current value of the second and third photocurrent, t0 is the integration time, and Cz2 is the capacitance value of CG2; the integration time t0 is at the twelfth
  • the thirteenth sampling period S33 KB provides high-level signals, KR, KG and KW all provide low-level signals, G3 provides high-level signals, G1, G2, G4 and G5 all provide low-level signals, TB Turn on, TR, TG and TW are off, TG3 is on, TG1, TG2, TG4 and TG5 are all off; the thirteenth sampling period S33 includes the thirteenth reset time period and the thirteenth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR3 is turned on, and the first terminal of CG3 is connected to the second terminal of CG3 to release the charge in CG3;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR3 is turned off
  • S0 is turned on
  • D3 converts the blue light signal it receives into a third third photocurrent
  • the third third photocurrent is written into the first end of CG3 through the turned-on TB and TG3
  • the third third photocurrent flows to the third integrating capacitor CG3, forming a voltage drop on CG3, that is, the third
  • the third photocurrent begins to accumulate on the third integrating capacitor CG3 to realize the integral function
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Ib3 ⁇ t0/Cz3), wherein Vo1 is in The potential of the output end of the operational amplifier O0 when the integration ends, Ib3 is the current value of the third photocurrent, t0 is the integration time, and Cz3 is the capacitance value of CG3;
  • the integration time t0 is at the thirteenth photocurrent
  • KB provides a high-level signal
  • KR, KG, and KW all provide a low-level signal
  • G4 provides a high-level signal
  • G1, G2, G3, and G5 all provide a low-level signal
  • the fourteenth sampling time period S34 includes the fourteenth reset time period and the fourteenth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR4 is turned on, and the first terminal of CG4 is connected to the second terminal of CG4 to release the charge in CG4;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR4 is turned off
  • S0 is turned on
  • D3 converts the blue light signal it receives into the fourth third photocurrent
  • the fourth third photocurrent is written into the first end of CG4 through the turned-on TB and TG4
  • the fourth third photocurrent flows to the fourth integrating capacitor CG4, forming a voltage drop on CG4, that is, the fourth
  • the third photocurrent begins to accumulate on the fourth integrating capacitor CG4 to realize the integral function
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Ib4 ⁇ t0/Cz4), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Ib4 is the current value of the fourth photocurrent, t0 is the integration time, and Cz4 is the capacitance value of CG4;
  • Integral time period the time during which S0 is continuously turned on
  • the fifteenth sampling period S35 In the fifteenth sampling period S35, KB provides a high-level signal, KR, KG, and KW all provide a low-level signal, G5 provides a high-level signal, G1, G2, G3, and G4 all provide a low-level signal, and TB Turn on, TR, TG and TW are off, TG5 is on, TG1, TG2, TG3 and TG4 are all off; the fifteenth sampling period S35 includes the fifteenth reset period and the fifteenth integration period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR5 is turned on, and the first terminal of CG5 is connected to the second terminal of CG5 to release the charge in CG5;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR5 is turned off
  • S0 is turned on
  • D3 converts the received blue light signal into the fifth third photocurrent
  • the fifth third photocurrent is written into the first end of CG5 through the turned-on TB and TG5
  • the fifth third photocurrent flows to the fifth integration capacitor CG5, forming a voltage drop on CG5, that is, the fifth
  • the third photocurrent begins to accumulate on the fifth integrating capacitor CG5 to realize the integral function
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Ib5 ⁇ t0/Cz5), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Ib5 is the current value of the fifth photocurrent, t0 is the integration time, and Cz5 is the capacitance value of CG5;
  • the integration time t0 is at the fifteenth Integral time period, the
  • the sixteenth sampling period S41 In the sixteenth sampling period S41, KW provides a high-level signal, KR, KG, and KB all provide a low-level signal, G1 provides a high-level signal, G2, G3, G4, and G5 all provide a low-level signal, and TW Turn on, TR, TG and TB are off, TG1 is on, TG2, TG3, TG4 and TG5 are all off; the sixteenth sampling period S41 includes the sixteenth reset time period and the sixteenth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR1 is turned on, and the first terminal of CG1 is connected to the second terminal of CG1 to release the charge in CG1;
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR1 is turned off
  • S0 is turned on
  • D4 converts the white light signal it receives into the first fourth photocurrent
  • the first fourth photocurrent is written into the first end of CG1 through the turned-on TW and TG1
  • the first fourth photocurrent flows to the first integrating capacitor CG1, forming a voltage drop on CG1, that is, the fourth The first photocurrent starts to accumulate on the first integrating capacitor CG1 to realize the integral function
  • S0 is turned on, and the integrated voltage is saved to the storage capacitor C0
  • Vo1 is equal to Vref-(Iw1 ⁇ t0/Cz1), where Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Iw1 is the current value of the first fourth photocurrent, t0 is the integration time, and Cz1 is the capacitance value of CG1; Integral time period, the time during which S0 is continuously turned on, for example
  • KB provides a high-level signal
  • KR, KG, and KW all provide a low-level signal
  • G2 provides a high-level signal
  • G1, G3, G4, and G5 all provide a low-level signal
  • the seventeenth sampling period S42 includes the seventeenth reset time period and the seventeenth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR2 is turned on
  • S0 is turned off
  • the first terminal of CG2 is connected to the second terminal of CG2 to release the charge
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR2 is turned off
  • S0 is turned on
  • D4 converts the white light signal it receives into the second fourth photocurrent
  • the second fourth photocurrent is written into the first end of CG2 through the turned-on TW and TG2
  • the second fourth photocurrent flows to the second integrating capacitor CG2, forming a voltage drop on CG2, that is, the second
  • the fourth photocurrent begins to accumulate on the second integrating capacitor CG2 to realize the integral function
  • S0 is turned on, and the integrated voltage is stored on the storage capacitor C0
  • Vo1 is equal to Vref-(Iw2 ⁇ t0/Cz2), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Iw2 is the current value of the second fourth photocurrent, t0 is the integration time, and Cz2 is the capacitance value of CG2;
  • Integral time period the time during which S0 is continuously turned
  • the eighteenth sampling time period S33 includes the eighteenth reset time period and the eighteenth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR3 is turned on
  • S0 is turned off
  • the first terminal of CG3 is connected to the second terminal of CG3 to release the charge
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR3 is turned off
  • S0 is turned on
  • D4 converts the white light signal it receives into the third and fourth photocurrents.
  • the third fourth photocurrent is written into the first terminal of CG3 through the turned-on TW and TG3; the third fourth photocurrent flows to the third integration capacitor CG3, forming a voltage drop on CG3, that is, the third The fourth photocurrent starts to accumulate on the third integrating capacitor CG3 to realize the integral function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0; Vo1 is equal to Vref-(Iw3 ⁇ t0/Cz3), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Iw3 is the current value of the third and fourth photocurrents, t0 is the integration time, and Cz3 is the capacitance value of CG3; the integration time t0 is at the eighteenth
  • the nineteenth sampling period S44 KW provides a high-level signal, KR, KG and KB all provide a low-level signal, G4 provides a high-level signal, G1, G2, G3 and G5 all provide a low-level signal, TW Turn on, TR, TG and TB are off, TG4 is on, TG1, TG2, TG3 and TG5 are all off;
  • the nineteenth sampling period S44 includes the nineteenth reset period and the nineteenth integration period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR4 is turned on
  • S0 is turned off
  • the first terminal of CG4 is connected to the second terminal of CG4 to release the charge
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR4 is turned off
  • S0 is turned on
  • D4 converts the white light signal it receives into the fourth fourth photocurrent
  • the fourth fourth photocurrent is written into the first end of CG4 through the turned-on TW and TG4
  • the fourth fourth photocurrent flows to the fourth integrating capacitor CG4, forming a voltage drop on CG4, that is, the fourth The fourth photocurrent starts to accumulate on the fourth integrating capacitor CG1 to realize the integral function
  • S0 is turned on, and the integrated voltage is saved to the storage capacitor C0
  • Vo1 is equal to Vref-(Iw4 ⁇ t0/Cz4), wherein Vo1 is in The potential of the output terminal of the operational amplifier O0 when the integration ends, Ib4 is the current value of the fourth photocurrent, t0 is the integration time, and Cz4 is the capacitance value of CG4;
  • the integration time t0 is at the nineteenth Integral time period, the
  • the twentieth sampling period S45 KW provides a high-level signal, KR, KG, and KB all provide a low-level signal, G5 provides a high-level signal, G1, G2, G3, and G4 all provide a low-level signal, TW Turn on, TR, TG and TB are off, TG5 is on, TG1, TG2, TG3 and TG4 are all off;
  • the twentieth sampling time period S45 includes the twentieth reset time period and the twentieth integration time period set successively ;
  • SR provides a high-level signal
  • KD provides a low-level signal
  • TR5 is turned on
  • S0 is turned off
  • the first terminal of CG5 is connected to the second terminal of CG5 to release the power in CG5. charge
  • SR provides a low-level signal
  • KD provides a high-level signal
  • TR5 is turned off
  • S0 is turned on
  • D4 converts the eight-color light signals it receives into the fifth and fourth photocurrents.
  • the fifth fourth photocurrent is written into the first end of CG5 through the turned-on TW and TG5; the fifth fourth photocurrent flows to the fifth integration capacitor CG5, forming a voltage drop on CG5, that is, the fifth The fourth photocurrent begins to accumulate on the fifth integrating capacitor CG5 to realize the integral function; S0 is turned on, and the integrated voltage is saved to the storage capacitor C0; Vo1 is equal to Vref-(Iw5 ⁇ t0/Cz5), wherein Vo1 is in The electric potential of the output terminal of described operational amplifier O0 when integration finishes, Iw5 is the electric current value of described the 5th photoelectric current, t0 is integral time, and Cz5 is the capacitance value of CG5; Integral time period, the time during which S0 is continuously turned
  • At least one embodiment of the light detection module shown in FIG. 6 of the present disclosure is working.
  • S0 can be turned off, but not limited thereto.
  • the first terminal of CG1 is connected to the inverting input terminal of O0, the capacitance value of CG1 is 0.1pF, the integration time is 100us, and the high-precision voltage conversion range of digital-to-analog converter A0 is Greater than or equal to 0.2V and less than or equal to 2V, the photocurrent range that can be accurately detected by the first gear is greater than or equal to 200pA and less than or equal to 2000pA, and the current sampling accuracy is 0.06pA/LSB; among them, LSB is the least significant bit; And when the first gear is used for acquisition, the transfer coefficient is t0/Cz1, t0 is the integration time, and Cz1 is the capacitance value of the first integration capacitor CG1;
  • the first terminal of CG2 is connected to the inverting input terminal of O0, the capacitance value of CG2 is 1pF, the integration time is 100us, and the high-precision voltage conversion range of digital-to-analog converter A0 is greater than Equal to 0.2V but less than or equal to 2V, then the photocurrent range that can be accurately detected by the second gear is greater than or equal to 2nA and less than or equal to 20nA, and the current sampling accuracy is 0.56pA/LSB at this time; and when the second gear is used to collect , the transfer coefficient is t0/Cz2, t0 is the integration time, and Cz2 is the capacitance value of the second integration capacitor CG2;
  • the first terminal of CG3 is connected to the inverting input terminal of O0, the capacitance value of CG2 is 10pF, the integration time is 100us, and the high-precision voltage conversion range of digital-to-analog converter A0 is greater than equal to 0.2V but less than or equal to 2V, then the photocurrent range that can be accurately detected by the third gear is greater than or equal to 20nA and less than or equal to 200nA, and the current sampling accuracy is 5.6pA/LSB at this time; and when the third gear is used to collect , the transfer coefficient is t0/Cz3, t0 is the integration time, and Cz3 is the capacitance value of the third integration capacitor CG3;
  • the first terminal of CG4 is connected to the inverting input terminal of O0, the capacitance value of CG2 is 100pF, the integration time is 100us, and the high-precision voltage conversion range of digital-to-analog converter A0 is greater than Equal to 0.2V but less than or equal to 2V, the photocurrent range that can be accurately detected by the fourth gear is greater than or equal to 200nA and less than or equal to 2000nA, and the current sampling accuracy is 56pA/LSB at this time; and when the fourth gear is used for collection,
  • the transfer coefficient is t0/Cz4, t0 is the integration time, and Cz4 is the capacitance value of the fourth integration capacitor CG4;
  • the first terminal of CG5 is connected to the inverting input terminal of O0, the capacitance value of CG5 is 10pF, the integration time is 100us, and the high-precision voltage conversion range of digital-to-analog converter A0 is greater than Equal to 0.2V but less than or equal to 2V, then the photocurrent range that the fifth gear can accurately detect is greater than or equal to 2uA and less than or equal to 20uA, and the current sampling accuracy is 560pA/LSB at this time; and when the fifth gear is used for collection,
  • the transfer coefficient is t0/Cz5, t0 is the integration time, and Cz5 is the capacitance value of the fifth integration capacitor CG5;
  • the voltage of one LSB converted by the analog-to-digital converter A0 is 55.58uV/LSB, and the LSB is the least significant bit.
  • At least one embodiment of the light detection module shown in Figure 6 of the present disclosure can collect a photocurrent range of greater than or equal to 200pA and less than or equal to 20uA.
  • the acquisition accuracy and operational amplifier The OS leakage current of O0 (the OS leakage current of the operational amplifier O0 is the leakage current of the positive and negative input terminals of the operational amplifier O0) is related, that is, if the acquisition error is 10%, the OS leakage current of the operational amplifier O0 is at least an order of magnitude smaller .
  • a sampling cycle includes a first sampling phase, a second sampling phase, a third sampling phase and a fourth sampling phase. Sampling the first photocurrent corresponding to the red light signal, sampling the second photocurrent corresponding to the green light signal in the second sampling stage, sampling the third photocurrent corresponding to the blue light signal in the third sampling stage, and sampling the third photocurrent corresponding to the blue light signal in the fourth sampling stage Phase sampling corresponds to the fourth photocurrent of the white light signal;
  • Each sampling stage includes five sequentially set sampling time periods.
  • TG1, TG2, TG3, TG4, and TG5 are controlled to be turned on in sequence; the first sampling period included in each sampling stage During the time period, TG1 is turned on, TG2, TG3, TG4 and TG5 are turned off, and the first end of CG1 is connected to the inverting input end of the operational amplifier O0; the second sampling time included in each sampling stage In the period, TG2 is turned on, TG1, TG3, TG4 and TG5 are turned off, and the first end of CG2 is connected with the inverting input end of the operational amplifier O0; the third sampling period included in each sampling stage , TG3 is turned on, TG1, TG2, TG4 and TG5 are turned off, and the first terminal of RS3 is connected with the inverting input terminal of the operational amplifier O0; in the fourth sampling period included in each sampling stage , TG4 is turned on, TKG1, TG2,
  • the output digital signal output by the analog-to-digital converter A0 is judged, and when the output digital signal output by the analog-to-digital converter A0 corresponds to the input If the voltage value of the voltage is less than or equal to the first voltage VS1 (the high-precision voltage conversion range of the analog-to-digital converter A0 is greater than or equal to the first voltage VS1 and less than or equal to the second voltage VS2), the corresponding output digital signal is discarded until the When the voltage value of the input voltage corresponding to the output digital signal is in the high-precision voltage conversion range of the analog converter A0, record the current transfer coefficient (the transfer coefficient is related to the capacitance value and the integration time of the corresponding integration capacitor), And, the output digital signal output by the analog converter A0 is sent to the corresponding storage unit. After the entire sampling period is completed, the micro-control unit 80 can obtain the characteristics of each optical signal according to the transfer coefficient in the storage unit and the output digital
  • the light detection method described in the embodiment of the present disclosure is applied to the above light detection module, and the light detection method includes:
  • N light-sensing circuits respectively sense light signals of different colors and generate corresponding photocurrents
  • the control circuit controls to provide the photocurrent generated by each of the photosensitive circuits to the capacitance integral amplifier circuit in time-sharing, and controls the conversion parameters of the capacitance integral amplifier circuit;
  • the capacitance integral conversion circuit converts the photocurrent according to the conversion parameter and the integration time to obtain an analog output voltage
  • the processing circuit obtains the characteristics of the optical signal according to the analog output voltage.
  • the light detection method described in the embodiment of the present disclosure adopts the method of current integration through the capacitance integration conversion circuit, and converts the photocurrent according to the integration time, so that the parallel connection used by the light sensing circuit can be reduced by increasing the integration time.
  • the number of photodiodes reduces the area occupied by the photodiodes, thereby saving space and cost.
  • control circuit includes a photosensitive control subcircuit, a sampling subcircuit, and a capacitance control subcircuit;
  • sampling subcircuit includes M integrating capacitors; M is a positive integer;
  • the step of controlling the control circuit to provide the photocurrent generated by each photo-sensing circuit to the conversion circuit in time-sharing includes: the photo-sensing control sub-circuit controls the photo-current generated by each photo-sensing circuit under the control of the photo-sensing control signal in time-sharing The photocurrent is provided to the input end of the capacitance integration conversion circuit; the capacitance control subcircuit controls the first end of each integration capacitor to time-share with the input end of the capacitance integration conversion circuit under the control of the capacitance control signal connection between
  • the conversion parameter is the capacitance value of the integration capacitor currently connected to the input terminal of the capacitance integration conversion circuit.
  • the transfer coefficient of the capacitance integration circuit may be the ratio of the integration time to the capacitance value of the integration capacitor currently connected to the input terminal of the capacitance integration conversion circuit.
  • control circuit may include a photosensitive control subcircuit, a sampling subcircuit and a capacitance control subcircuit, and the photosensitive control subcircuit controls the time-sharing to provide the photocurrent generated by each photosensitive circuit to the capacitance integral conversion circuit.
  • the capacitance control subcircuit controls the integral capacitance connected to the input end of the capacitance integration conversion circuit.
  • the processing circuit includes an analog-to-digital converter and an output processing unit;
  • the analog-to-digital converter converts the analog output voltage into an output digital signal
  • the output processing unit obtains the feature of the optical signal according to the output digital signal.
  • the high-precision voltage conversion range of the analog-to-digital converter is the range of the input voltage that the analog-to-digital converter can accurately perform analog-to-digital conversion;
  • the voltage conversion range of the analog-to-digital converter is the range of the input voltage that the analog-to-digital converter A0 can perform analog-to-digital conversion; wherein, the input voltage is the voltage input to the analog-to-digital converter.
  • the high-precision voltage conversion range of the analog-to-digital converter is greater than or equal to the first voltage VS1 and less than or equal to the second voltage VS2, and the voltage conversion range of the analog-to-digital converter is greater than or equal to the second voltage VS2
  • the third voltage VS3 is less than or equal to the fourth voltage VS3; the fourth voltage VS3 is greater than the second voltage VS2; the third voltage VS3 is less than the first voltage VS1;
  • the output processing unit judges whether the voltage value of the input voltage corresponding to the output digital signal is within the high-precision voltage conversion range
  • the output processing unit determines that the voltage value of the input voltage corresponding to the output digital signal is less than the first voltage VS1 or greater than the second voltage VS2, the output processing unit determines that the input voltage corresponding to the output digital signal is If the voltage value is not within the high-precision voltage conversion range, the digital output signal is discarded;
  • the output processing unit determines that the voltage value of the input voltage corresponding to the output digital signal is greater than or equal to the first voltage VS1 and less than or equal to the second voltage VS2, the output processing unit determines that the input voltage corresponding to the output digital signal The voltage value of the voltage is within the high-precision voltage conversion range, and the output processing unit obtains the characteristics of the optical signal according to the digital output signal.
  • the voltage value of the input voltage corresponding to the output digital signal is less than the first voltage VS1 or greater than the second voltage VS2
  • the voltage value of the input voltage connected to the input terminal of the analog-to-digital converter exceeds Due to the high-precision voltage conversion range of the analog-to-digital converter, it is necessary to discard the output digital signal and use other integrating capacitors for re-sampling.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned light detection module.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

本公开提供一种光检测模组、光检测方法和显示装置。光检测模组包括N个光感电路、控制电路、电容积分转换电路和处理电路；N为正整数；N个光感电路分别感应不同颜色的光信号，产生相应的光电流；控制电路用于控制分时将各所述光感电路产生的光电流提供至电容积分放大电路，并用于控制电容积分放大电路的转换参数；电容积分转换电路用于根据转换参数和积分时间，对光电流进行转换，以得到模拟输出电压；处理电路根据模拟输出电压得到光信号的特征。本公开通过电容积分转换电路采用电流积分的方法，并根据积分时间对所述光电流进行转换，则可以通过增大积分时间来减少光感电路采用的相互并联的光电二极管的个数和面积，进而可以节省空间和成本。

Description

光检测模组、光检测方法和显示装置 技术领域
本公开涉及光检测技术领域，尤其涉及一种光检测模组、光检测方法和显示装置。
背景技术
相关的光检测模组可以检测到的光电流的值的范围较大，光感电路需要采用多个相互并联的光电二极管来产生电流值较大的光电流，导致成本高，并占用空间大。
发明内容
在一个方面中，本公开实施例提供了一种光检测模组，包括N个光感电路、控制电路、电容积分转换电路和处理电路；N为正整数；所述N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
所述控制电路用于控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并用于控制所述电容积分放大电路的转换参数；
所述电容积分转换电路用于根据所述转换参数和积分时间，对所述光电流进行积分转换，以得到模拟输出电压；
所述处理电路用于根据所述模拟输出电压得到所述光信号的特征。
可选的，所述电容积分转换电路包括转换子电路、采样子电路和采样控制子电路；所述控制电路包括光感控制子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
所述光感控制子电路用于在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述转换子电路的输入端；
所述电容控制子电路用于在电容控制信号的控制下，控制各积分电容的第一端分时与所述转换子电路的输入端之间连通；各所述积分电容的第二端与所述转换子电路的输出端电连接；
所述采样控制子电路用于在采样控制信号的控制下，控制所述转换子电 路的输出端与所述处理电路之间连通或断开；
所述转换子电路用于对所述光电流进行转换，得到并通过所述转换子电路的输出端输出所述模拟输出电压；
所述转换参数为当前与所述转换子电路的输入端之间连通的积分电容的电容值。
可选的，本公开至少一实施例所述的光检测模组还包括复位电路；所述复位电路包括M个复位子电路；
第m复位子电路分别与第m积分电容的第一端、所述第m积分电容的第二端和复位控制端电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制所述第m积分电容的第一端与所述第m积分电容的第二端之间连通，以释放所述第m积分电容中储存的电荷；
m为小于或等于M的正整数。
可选的，所述光感控制子电路包括N个光感控制晶体管；所述电容控制子电路包括M个电容控制晶体管；n为小于或等于N的正整数，m为小于或等于M的正整数；所述采样控制子电路包括采样开关和存储电容；
第n光感控制晶体管的控制极与第n光感控制端电连接，第n光感控制晶体管的第一极与第n光电流输出端电连接，第n光感控制晶体管的第二极与所述转换子电路的输入端电连接；所述第n光感控制端用于提供第n光感控制信号；
第m电容控制晶体管的控制极与第m电容控制端电连接，第m电容控制晶体管的第一极与所述转换子电路的输入端电连接，第m电容控制晶体管的第二极与第m积分电容的第一端电连接，第m积分电容的第二端与所述转换子电路的输出端电连接；所述第m电容控制端用于提供第m电容控制信号；
所述采样开关的控制端与采样控制端电连接，所述采样开关的第一端与所述转换子电路的输出端电连接，所述采样开关的第二端与所述处理电路电连接；
所述存储电容的第一端与所述采样开关的第二端电连接，所述存储电容的第二端与直流电压端电连接。
可选的，本公开至少一实施例所述的光检测模组还包括滤波电路；
所述滤波电路连接于所述转换子电路的输出端与所述采样开关的第一端之间，用于滤除所述模拟输出电压中的高频噪声，并将滤除高频噪声之后的模拟输出电压提供至所述采样开关的第一端。
可选的，第m复位子电路包括第m复位晶体管；
所述第m复位晶体管的控制极与所述复位控制端电连接，所述第m复位晶体管的第一极与所述第m积分电容的第一端电连接，所述第m复位晶体管的第二极与所述第m积分电容的第二端电连接。
可选的，所述N个光感电路、所述光感控制子电路、所述电容控制子电路和所述复位电路都设置于显示基板上。
可选的，至少部分所述积分电容的电容值小于10pF，所述至少部分所述积分电容设置于显示基板上，所述采样子电路包括的除了所述至少部分所述积分电容之外的积分电容设置于线路板或驱动集成电路上。
可选的，所述转换子电路包括运算放大器；所述运算放大器的反相输入端为所述转换子电路的输入端，所述运算放大器的输出端为所述转换子电路的输出端；
所述运算放大器的正相输入端与参考电压端电连接，所述参考电压端用于提供参考电压。
可选的，本公开至少一实施例所述的光检测模组还包括控制信号生成单元；
所述控制信号生成单元用于提供采样控制信号、光感控制信号、电容控制信号和复位控制信号。
可选的，所述处理电路包括模数转换器和输出处理单元；
所述模数转换器用于将所述模拟输出电压转换为输出数字信号；
所述输出处理单元与所述模数转换器电连接，用于接收所述输出数字信号，并根据所述输出数字信号得到所述光信号的特征。
可选的，所述光信号的特征包括光强、亮度、色坐标、色温中的至少一个。
可选的，本公开至少一实施例所述的光检测模组还包括微控制单元；所述控制信号生成单元包括控制信号生成电路和电平转换器；
所述控制信号生成电路用于提供采样控制信号、输入光感控制信号、输入电容控制信号和输入复位控制信号；
所述电平转换器与所述控制信号生成电路电连接，用于对所述输入光感控制信号进行电平转换，以生成所述光感控制信号，对所述输入电容控制信号进行电平转换，以生成所述电容控制信号，对所述输入复位控制信号进行电平转换，以生成所述复位控制信号；
所述输出处理单元和所述控制信号生成电路设置于所述微控制单元中。
可选的，所述光检测模组还包括滤波电路；
所述微控制单元、所述电平转换器、所述模数转换器、所述滤波电路，以及，所述电容积分转换电路包括的转换子电路和采样控制子电路都设置于线路板或驱动集成电路上。
可选的，第n光感电路包括第n光电二极管；n为小于或等于N的正整数；
所述第n光电二极管的阴极与电源电压端电连接，所述第n光电二极管的阳极用于提供第n光电流；
所述电源电压端用于提供电源电压信号。
在第二个方面中，本公开实施例还提供了一种光检测方法，应用于上述的光检测模组，所述光检测方法包括：
N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
控制电路控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并控制所述电容积分放大电路的转换参数；
电容积分转换电路根据所述转换参数和积分时间，对所述光电流进行转换，以得到模拟输出电压；
处理电路根据所述模拟输出电压得到所述光信号的特征。
可选的，所述控制电路包括光感控制子电路、采样子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
所述控制电路控制分时将各所述光感电路产生的光电流提供至转换电路步骤包括：所述光感控制子电路在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述电容积分转换电路的输入端；所述电容控 制子电路在电容控制信号的控制下，控制各积分电容的第一端分时与所述电容积分转换电路的输入端之间连通；
所述转换参数为当前与所述电容积分转换电路的输入端之间连通的积分电容的电容值。
可选的，所述处理电路包括模数转换器和输出处理单元；
所述处理电路根据所述模拟输出电压得到所述光信号的特征步骤包括：
所述模数转换器将所述模拟输出电压转换为输出数字信号；
所述输出处理单元根据所述输出数字信号得到所述光信号的特征。
可选的，所述模数转换器的高精度电压转换范围为大于等于第一电压VS1而小于等于第二电压VS2；
所述输出处理单元根据所述输出数字信号得到所述光信号的特征步骤包括：
所述输出处理单元判断所述输出数字信号对应的输入电压的电压值是否在所述高精度电压转换范围内；所述输入电压为输入所述模数转换器的电压；
当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值小于第一电压VS1或大于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值不在所述高精度电压转换范围内，放弃所述数字输出信号；
当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值大于等于第一电压VS1而小于等于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值在所述高精度电压转换范围内，所述输出处理单元根据所述数字输出信号得到所述光信号的特征。
本公开实施例还提供了一种显示装置，包括上述的光检测模组。
附图说明
图1是本公开实施例所述的光检测模组的结构图；
图2是本公开至少一实施例所述的光检测模组的结构图；
图3是本公开至少一实施例所述的光检测模组的结构图；
图4是本公开至少一实施例所述的光检测模组的结构图；
图5是本公开至少一实施例所述的光检测模组的结构图；
图6是本公开至少一实施例所述的光检测模组的电路图；
图7是本公开如图6所示的光检测模组的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的光检测模组包括N个光感电路、控制电路、电容积分转换电路和处理电路；N为正整数；所述N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
所述控制电路用于控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并用于控制所述电容积分放大电路的转换参数；
所述电容积分转换电路用于根据所述转换参数和积分时间，对所述光电流进行积分转换，以得到模拟输出电压；
所述处理电路用于根据所述模拟输出电压得到所述光信号的特征。
本公开实施例所述的光检测模组通过控制电路分时将各光感电路产生的光电流提供至电容积分放大电路，并控制所述电容积分放大电路的转换参数，电容积分转换电路采用电流积分的方法，根据转换参数和积分时间对所述光电流进行转换，得到模拟输出电压，处理电路根据模拟输出电压得到光信号的特征。
本公开实施例所述的光检测模组通过电容积分转换电路采用电流电容积 分原理，将光电流转换成采样电压(所述采样电压即所述模拟输出电压)，所述模拟输出电压的电压值的变化量的绝对值与所述光电流的变化量的绝对值之间的比值为所述电容积分转换电路的转移系数，所述转移系数与积分电容的电容值和积分时间相关，随着积分时间的增大，较小的光电流也能累积到可以采集的采样电压，所以可以通过增大积分时间来，降低对光感电路产生的光电流的大小的要求，即能够减少光感电路包括的并联的光电二极管的个数，进而可以节省空间和成本。
本公开实施例采用小电容积分的方法将光电二极管的光电流转换成可模数转换的采样电压，可以采集到更小的光电流，即几十pA级的漏电流，减少了光电二极管并联的数量，降低了光电二极管占用的面积。
在本公开至少一实施例中，所述电容积分放大电路的积分时间也即对所述光电流进行积分转换的时间。
在本公开至少一实施例中，以N等于4来说明，但是实际操作时，N可以为任意正整数，N的取值可以根据实际情况选定。
如图1所示，本公开实施例所述的光检测模组包括第一光感电路11、第二光感电路12、第三光感电路13、第四光感电路14、控制电路21、电容积分转换电路22和处理电路23；
所述第一光感电路11用于感应红色光信号，产生第一光电流；
所述第二光感电路12用于感应绿色光信号，产生第二光电流；
所述第三光感电路13用于感应蓝色光信号，产生第三光电流；
所述第四光感电路14用于感应白色光信号，产生第四光电流；
所述控制电路21分别与所述第一光感电路11、所述第二光感电路12、所述第三光感电路13、所述第四光感电路14和所述电容积分转换电路22电连接，用于控制分时将所述第一光电流、所述第二光电流、所述第三光电流、所述第四光电流提供至所述电容积分放大电路22，并用于控制所述电容积分放大电路22的转换参数；
所述电容积分转换电路22用于根据所述转换参数和积分时间，对所述第一光电流进行转换，以得到相应的第一模拟输出电压，对所述第二光电流进行转换，得到相应的第二模拟输出电压，对所述第三光电流进行转换，得到 相应的第三模拟输出电压，对所述第四光电流进行转换，得到相应的第四模拟输出电压；
所述处理电路23与所述电容积分转换电路22电连接，用于根据所述第一模拟输出电压得到所述红色光信号的特征，根据所述第二模拟输出电压得到所述绿色光信号的特征，根据所述第三模拟输出电压得到所述蓝色光信号的特征，根据所述第四模拟输出电压得到所述白色光信号的特征。
在本公开至少一实施例中，所述电容积分转换电路包括转换子电路、采样子电路和采样控制子电路；所述控制电路包括光感控制子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
所述光感控制子电路用于在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述转换子电路的输入端；
所述电容控制子电路用于在电容控制信号的控制下，控制各积分电容的第一端分时与所述转换子电路的输入端之间连通；各所述积分电容的第二端与所述转换子电路的输出端电连接；
所述采样控制子电路用于在采样控制信号的控制下，控制所述转换子电路的输出端与所述处理电路之间连通或断开；
所述转换子电路用于对所述光电流进行转换，得到并通过所述转换子电路的输出端输出所述模拟输出电压；
所述转换参数为当前与所述转换子电路的输入端之间连通的积分电容的电容值。
在具体实施时，所述电容积分转换电路可以包括转换子电路、采样子电路和采样控制子电路，所述控制电路可以包括光感控制子电路和电容控制子电路，采样子电路可以包括M个积分电容；光感控制子电路控制分时将各光感电路产生的光电流提供至转换子电路的输入端，电容控制子电路控制各积分电容分时与转换子电路的输入端之间连通，采样控制子电路控制转换子电路的输出端与处理电路之间连通或断开，转换子电路将光电流转换为相应的模拟输出电压。
在本公开至少一实施例中，以M等于5来说明，但是实际操作时，N可以为正整数，M的取值可以根据实际情况选定。
可选的，当光感电路产生的光电流小到几十pA时，就需要较小的积分电容(pF级)来积分，市场上小电容比较少，精度差，因此本公开实施例将pF级小电容采用半导体工艺制作在显示基板上。而如果将具有较大容值的电容制作在显示基板上，需要大的制作面积，所以本公开实施例采用具有较大容值的标准电容，并将具有较大容值的标准电容集成在线路板或驱动集成电路上。
在具体实施时，电容值小的积分电容可以设置于显示基板上，由于电容值较大的积分电容的极板的尺寸较大，因此可以将电容值较大的积分电容设置于线路板或驱动集成电路上。
如图2所示，在图1所示的光检测模组的至少一实施例的基础上，所述电容积分转换电路包括转换子电路31、采样子电路和采样控制子电路33；所述控制电路包括光感控制子电路41和电容控制子电路42；所述采样子电路包括第一积分电容CG1、第二积分电容CG2、第三积分电容CG3、第四积分电容CG4和第五积分电容CG5；
所述光感控制子电路41分别与第一光感电路11、第二光感电路12、第三光感电路13、第四光感电路14和所述转换子电路31的输入端电连接，用于在光感控制信号的控制下，控制分时将第一光感电路11产生的第一光电流、第二光感子电路12产生的第二光电流、第三光感电路13产生的第三光电流、第四光感电路14产生的第四光电流，提供至所述转换子电路31的输入端；
所述电容控制子电路42分别与第一积分电容CG1的第一端、第二积分电容CG2的第一端、第三积分电容CG3的第一端、第四积分电容CG4的第一端、第五积分电容CG5的第一端和所述转换子电路31的输入端电连接，用于在电容控制信号的控制下，控制第一积分电容CG1的第一端、第二积分电容CG2的第一端、第三积分电容CG3的第一端、第四积分电容CG4的第一端分时与所述转换子电路31的输入端之间连通；所述第一积分电容CG1的第二端、所述第二积分电容CG2的第二端、所述第三积分电容CG3的第二端、所述第四积分电容CG4的第二端和所述第五积分电容CG5的第二端分别与所述转换子电路31的输出端电连接；
所述采样控制子电路33分别与转换子电路31的输出端和所述处理电路 23电连接，用于在采样控制信号的控制下，控制所述转换子电路31的输出端与所述处理电路23之间连通或断开；
所述转换子电路31用于对各所述光电流进行转换，得到并通过所述转换子电路31的输出端输出所述模拟输出电压；
所述转换参数为当前与所述转换子电路31的输入端之间连通的积分电容的电容值。
本公开如图2所示的光检测模组的至少一实施例在工作时，光感控制子电路41控制提供光电流至所述转换子电路31的输入端的光感子电路，所述电容控制子电路42控制与所述转换子电路31的输入端之间连通的积分电容，采样控制子电路33控制所述转换子电路31的输出端是否与所述处理电路23之间连通，转换子电路对各光电流进行转换，得到模拟输出电压。
本公开至少一实施例所述的光检测模组还可以包括复位电路；所述复位电路包括M个复位子电路；
第m复位子电路分别与第m积分电容的第一端、所述第m积分电容的第二端和复位控制端电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制所述第m积分电容的第一端与所述第m积分电容的第二端之间连通，以释放所述第m积分电容中储存的电荷；
m为小于或等于M的正整数。
在具体实施时，所述光检测模组还可以包括复位电路，复位电路包括M各复位子电路，第m复位子电路在积分之前，控制所述第m积分电容的第一端与所述第m积分电容的第二端之间连通，以释放所述第m积分电容中储存的电荷，以免影响采样结果。
如图3所示，在图2所示的光检测模组的至少一实施例的基础上，本公开至少一实施例所述的光检测模组还可以包括复位电路；所述复位电路包括第一复位子电路51、第二复位子电路52、第三复位子电路53、第四复位子电路54和第五复位子电路55；
所述第一复位子电路51分别与第一积分电容CG1的第一端、所述第一积分电容CG1的第二端和复位控制端SR电连接，用于在所述复位控制端SR提供的复位控制信号的控制下，控制所述第一积分电容CG1的第一端与所述 第一积分电容CG1的第二端之间连通，以释放所述第一积分电容CG1中存储的电荷；
所述第一复位子电路52分别与第二积分电容CG2的第一端、所述第二积分电容CG2的第二端和复位控制端SR电连接，用于在所述复位控制端SR提供的复位控制信号的控制下，控制所述第二积分电容CG2的第一端与所述第二积分电容CG2的第二端之间连通，以释放所述第二积分电容CG2中存储的电荷；
所述第三复位子电路53分别与第三积分电容CG3的第一端、所述第三积分电容CG3的第二端和复位控制端SR电连接，用于在所述复位控制端SR提供的复位控制信号的控制下，控制所述第三积分电容CG3的第一端与所述第三积分电容CG3的第二端之间连通，以释放所述第三积分电容CG3中存储的电荷；
所述第四复位子电路54分别与第四积分电容CG4的第一端、所述第四积分电容CG4的第二端和复位控制端SR电连接，用于在所述复位控制端SR提供的复位控制信号的控制下，控制所述第四积分电容CG4的第一端与所述第四积分电容CG4的第二端之间连通，以释放所述第四积分电容CG4中存储的电荷；
所述第五复位子电路55分别与第五积分电容CG5的第一端、所述第五积分电容CG5的第二端和复位控制端SR电连接，用于在所述复位控制端SR提供的复位控制信号的控制下，控制所述第五积分电容CG5的第一端与所述第五积分电容CG5的第二端之间连通，以释放所述第五积分电容CG5中存储的电荷。
本公开如图3所示的光检测模组的至少一实施例在工作时，
第一复位子电路51在第一积分电容CG1的第一端与所述转换子电路31的输入端之间由断开至连通之前，控制所述第一积分电容CG1的第一端与所述第一积分电容CG1的第二端之间连通，以释放所述第一积分电容CG1中储存的电荷，以免影响采样结果；
第二复位子电路52在第二积分电容CG2的第一端与所述转换子电路31的输入端之间由断开至连通之前，控制所述第二积分电容CG2的第一端与所 述第二积分电容CG2的第二端之间连通，以释放所述第二积分电容CG2中储存的电荷，以免影响采样结果；
第三复位子电路53在第三积分电容CG3的第一端与所述转换子电路31的输入端之间由断开至连通之前，控制所述第三积分电容CG3的第一端与所述第三积分电容CG3的第二端之间连通，以释放所述第三积分电容CG3中储存的电荷，以免影响采样结果；
第四复位子电路54在第四积分电容CG4的第一端与所述转换子电路31的输入端之间由断开至连通之前，控制所述第四积分电容CG4的第一端与所述第四积分电容CG4的第二端之间连通，以释放所述第四积分电容CG4中储存的电荷，以免影响采样结果；
第五复位子电路55在第五积分电容CG5的第一端与所述转换子电路31的输入端之间由断开至连通之前，控制所述第五积分电容CG5的第一端与所述第五积分电容CG5的第二端之间连通，以释放所述第五积分电容CG5中储存的电荷，以免影响采样结果。
可选的，所述光感控制子电路包括N个光感控制晶体管；所述电容控制子电路包括M个电容控制晶体管；n为小于或等于N的正整数，m为小于或等于M的正整数；所述采样控制子电路包括采样开关和存储电容；
第n光感控制晶体管的控制极与第n光感控制端电连接，第n光感控制晶体管的第一极与第n光电流输出端电连接，第n光感控制晶体管的第二极与所述转换子电路的输入端电连接；所述第n光感控制端用于提供第n光感控制信号；
第m电容控制晶体管的控制极与第m电容控制端电连接，第m电容控制晶体管的第一极与所述转换子电路的输入端电连接，第m电容控制晶体管的第二极与第m积分电容的第一端电连接，第m积分电容的第二端与所述转换子电路的输出端电连接；所述第m电容控制端用于提供第m电容控制信号；
所述采样开关的控制端与采样控制端电连接，所述采样开关的第一端与所述转换子电路的输出端电连接，所述采样开关的第二端与所述处理电路电连接；
所述存储电容的第一端与所述采样开关的第二端电连接，所述存储电容 的第二端与直流电压端电连接。
可选的，所述直流电压端可以为地端，但不以此为限。
本公开至少一实施例所述的光检测模组还可以包括滤波电路；
所述滤波电路连接于所述转换子电路的输出端与所述采样开关的第一端之间，用于滤除所述模拟输出电压中的高频噪声，并将滤除高频噪声之后的模拟输出电压提供至所述采样开关的第一端。
在本公开至少一实施例中，所述滤波电路可以为低通滤波电路，可以有效滤除模拟输出电压中的高频噪声，使得输出信号稳定，噪声波动减小。
如图4所示，在图3所示的光检测模组的至少一实施例的基础上，所述采样控制子电路33包括采样开关S0和存储电容C0；本公开所述的光检测模组的至少一实施例还包括滤波电路60；
所述采样开关S0的控制端与采样控制端KD电连接，所述采样开关S0的第一端通过所述滤波电路60与所述转换子电路31的输出端电连接，所述采样开关S0的第二端与所述处理电路23电连接；
所述存储电容C0的第一端与所述采样开关S0的第二端电连接，所述存储电容C0的第二端与地端电连接；
所述滤波电路60连接于所述转换子电路31的输出端与所述采样开关S0的第一端之间，用于滤除所述模拟输出电压中的高频噪声，并将滤除高频噪声之后的模拟输出电压提供至所述采样开关S0的第一端。
可选的，第m复位子电路包括第m复位晶体管；
所述第m复位晶体管的控制极与所述复位控制端电连接，所述第m复位晶体管的第一极与所述第m积分电容的第一端电连接，所述第m复位晶体管的第二极与所述第m积分电容的第二端电连接。
在本公开至少一实施例中，所述N个光感电路、所述光感控制子电路、所述电容控制子电路和所述复位电路可以都设置于显示基板上。
可选的，所述转换子电路包括运算放大器；所述运算放大器的反相输入端为所述转换子电路的输入端，所述运算放大器的输出端为所述转换子电路的输出端；
所述运算放大器的正相输入端与参考电压端电连接，所述参考电压端用 于提供参考电压。
在具体实施时，所述参考电压的电压值可以为1.5V或2V，但不以此为限，所述参考电压的电压值可以根据数模转换器的输入电压确定。
本公开至少一实施例所述的光检测模组还可以包括控制信号生成单元；
所述控制信号生成单元用于提供采样控制信号、光感控制信号、电容控制信号和复位控制信号。
可选的，所述控制信号生成单元可以包括控制信号生成电路和电平转换器；
所述控制信号生成电路用于提供采样控制信号、输入光感控制信号、输入电容控制信号和输入复位控制信号；
所述电平转换器与所述控制信号生成电路电连接，用于对所述输入光感控制信号进行电平转换，以生成所述光感控制信号，对所述输入电容控制信号进行电平转换，以生成所述电容控制信号，对所述输入复位控制信号进行电平转换，以生成所述复位控制信号。
可选的，所述处理电路包括模数转换器和输出处理单元；
所述模数转换器用于将所述模拟输出电压转换为输出数字信号；
所述输出处理单元与所述模数转换器电连接，用于接收所述输出数字信号，并根据所述输出数字信号得到所述光信号的特征，并将所述光信号的特征信息传送给应用单元，以便所述应用单元能够根据所述光信号获得当前环境光的数据。
在本公开至少一实施例中，所述光信号的特征可以包括光强、亮度、色坐标、色温中的至少一个，但不以此为限。
在具体实施时，所述输出处理单元可以为算法单元，对所述输出数字信号进行处理，判断所述输出数字信号的有效性，将所述输出数字信号转换为对应于光强和亮度的数字信号，同时根据对应于不同颜色的输出数字信号计算色坐标或色温等光学特征参数，以满足应用单元使用。
如图5所示，在图4所示的光检测模组的至少一实施例的基础上，本公开至少一实施例所述的光检测模组还可以包括控制信号生成单元；所述处理电路包括模数转换器A0和输出处理单元72；所述控制信号生成单元包括控 制信号生成电路701和电平转换器702；
所述控制信号生成电路701分别与所述采样控制端KD和所述电平转换器702电连接，用于为所述采样控制端KD提供采样控制信号，并用于向所述电平转换器702提供输入光感控制信号，输入电容控制信号和输入复位控制信号；
所述电平转换器702分别与复位控制端SR、所述光感控制子电路41、所述电容控制子电路42和复位控制端SR电连接，用于对所述输入光感控制信号进行电平转换，以生成所述光感控制信号，对所述输入电容控制信号进行电平转换，以生成所述电容控制信号，对所述输入复位控制信号进行电平转换，以生成所述复位控制信号，并将所述光感控制信号提供至所述光感控制子电路41，将所述电容控制信号提供至所述电容控制子电路42，将所述复位控制信号提供至所述复位控制端SR；
所述模数转换器A0与所述采样开关S0的第二端电连接，用于将所述模拟输出电压转换为输出数字信号；
所述输出处理单元72与所述模数转换器A0电连接，用于接收所述输出数字信号，并根据所述输出数字信号得到所述光信号的特征。
在本公开至少一实施例中，当各光感控制晶体管、各电容控制晶体管、各复位晶体管为n型晶体管时，并各光感控制信号的电位、各电容控制信号的电位、各复位控制信号的电位为7V时，各光感控制晶体管、各电容控制晶体管、各复位晶体管导通，当各光感控制晶体管、各电容控制晶体管、各复位晶体管为p型晶体管时，当各光感控制信号、各电容控制信号的电位、各复位控制信号的电位为-7V时，各光感控制晶体管、各电容控制晶体管、各复位晶体管导通；而所述控制信号生成电路701提供的各控制信号的低电压值、高电压值分别为0V、3V，此时需要所述电平转换器70将0V电压转换为-7V电压，将3.3V电压转换为7V电压，以满足各光感控制晶体管控制电平、各电容控制晶体管控制电平、各复位晶体管控制电平的要求。
本公开至少一实施例所述的光检测模组还可以包括微控制单元；所述控制信号生成电路和所述输出处理单元都设置于所述微控制单元中。
可选的，所述光检测模组还可以包括滤波电路；
所述微控制单元、所述电平转换器、所述模数转换器、所述滤波电路，以及，所述电容积分转换电路包括的转换子电路和采样控制子电路可以都设置于线路板或驱动集成电路上。
可选的，第n光感电路包括第n光电二极管；n为小于或等于N的正整数；
所述第n光电二极管的阴极与电源电压端电连接，所述第n光电二极管的阳极用于提供第n光电流；
所述电源电压端用于提供电源电压信号。
如图6所示，在图4所示的光检测模组的至少一实施例的基础上，本公开至少一实施例所述的光检测模组还可以包括控制信号生成单元和微控制单元80；所述处理电路包括模数转换器A0和输出处理单元；
所述控制信号生成单元包括控制信号生成电路和电平转换器702；
所述控制信号生成电路和所述输出处理单元集成于所述微控制单元80中；
所述第一光感电路包括第一光电二极管D1；所述第一光电二极管D1的阴极与电源电压端VDD电连接，所述第一光电二极管D1用于感应红色光信号，产生相应的第一光电流；
所述第二光感电路包括第二光电二极管D2；所述第二光电二极管D2的阴极与电源电压端VDD电连接，所述第二光电二极管D2用于感应绿色光信号，产生相应的第二光电流；
所述第三光感电路包括第三光电二极管D3；所述第三光电二极管D3的阴极与电源电压端VDD电连接，所述第三光电二极管D3用于感应蓝色光信号，产生相应的第三光电流；
所述第四光感电路包括第四光电二极管D4；所述第四光电二极管D4的阴极与电源电压端VDD电连接，所述第四光电二极管D4用于感应白色光信号，产生相应的第四光电流；
所述光感控制子电路包括第一光感控制晶体管TR、第二光感控制晶体管TG、第三光感控制晶体管TB和第四光感控制晶体管TW；所述电容控制子电路包括第一电容控制晶体管TG1、第二电容控制晶体管TG2、第三电容控 制晶体管TG3、第四电容控制晶体管TG4和第五电容控制晶体管TG5；所述转换子电路31包括运算放大器O0；
第一光感控制晶体管TR的栅极与第一光感控制端KR电连接，第一光感控制晶体管TR的源极与第一光电流输出端电连接，第一光感控制晶体管TR的漏极与所述运算放大器O0的反相输入端电连接，所述第一光电流输出端与所述第一光电二极管D1的阳极电连接；
第二光感控制晶体管TG的栅极与第二光感控制端KG电连接，第二光感控制晶体管TG的源极与第二光电流输出端电连接，第二光感控制晶体管TG的漏极与所述运算放大器O0的反相输入端电连接，所述第二光电流输出端与所述第二光电二极管D2的阳极电连接；
第三光感控制晶体管TB的栅极与第三光感控制端KB电连接，第三光感控制晶体管TB的源极与第三光电流输出端电连接，第三光感控制晶体管TB的漏极与所述运算放大器O0的反相输入端电连接，所述第三光电流输出端与所述第三光电二极管D3的阳极电连接；
第四光感控制晶体管TW的栅极与第四光感控制端KW电连接，第四光感控制晶体管TW的源极与第四光电流输出端电连接，第四光感控制晶体管TW的漏极与所述运算放大器O0的反相输入端电连接，所述第四光电流输出端与所述第四光电二极管D4的阳极电连接；
第一电容控制晶体管TG1的栅极与第一电容控制端G1电连接，第一电容控制晶体管TG1的源极与所述运算放大器O0的反相输入端电连接，第一电容控制晶体管TG1的漏极与第一积分电容CG1的第一端电连接；
第二电容控制晶体管TG2的栅极与第二电容控制端G2电连接，第二电容控制晶体管TG2的源极与所述运算放大器O0的反相输入端电连接，第二电容控制晶体管TG2的漏极与第二积分电容CG2的第一端电连接；
第三电容控制晶体管TG3的栅极与第三电容控制端G3电连接，第三电容控制晶体管TG3的源极与所述运算放大器O0的反相输入端电连接，第三电容控制晶体管TG3的漏极与第三积分电容CG3的第一端电连接；
第四电容控制晶体管TG4的栅极与第四电容控制端G4电连接，第四电容控制晶体管TG4的源极与所述运算放大器O0的反相输入端电连接，第四 电容控制晶体管TG4的漏极与第四积分电容CG4的第一端电连接；
所述第一积分电容CG1的第二端、所述第二积分电容CG2的第二端、所述第三积分电容CG3的第二端、所述第四积分电容CG4的第二端和所述第五积分电容CG5的第二端都与所述运算放大器O0的输出端O1电连接；
第一复位子电路包括第一复位晶体管TR1，第二复位子电路包括第二复位晶体管TR2,第三复位子电路包括第三复位晶体管TR3，第四复位子电路包括第四复位晶体管TR4，第五复位子电路包括第五复位晶体管TR5；
所述第一复位晶体管TR1的栅极与所述复位控制端SR电连接，所述第一复位晶体管TR1的源极与所述第一积分电容CG1的第一端电连接，所述第一复位晶体管TR1的漏极与所述第一积分电容CG1的第二端电连接；
所述第二复位晶体管TR2的栅极与所述复位控制端SR电连接，所述第二复位晶体管TR2的源极与所述第二积分电容CG2的第一端电连接，所述第二复位晶体管TR2的漏极与所述第二积分电容CG2的第二端电连接；
所述第三复位晶体管TR3的栅极与所述复位控制端SR电连接，所述第三复位晶体管TR3的源极与所述第三积分电容CG3的第一端电连接，所述第三复位晶体管TR3的漏极与所述第三积分电容CG3的第二端电连接；
所述第四复位晶体管TR4的栅极与所述复位控制端SR电连接，所述第四复位晶体管TR4的源极与所述第四积分电容CG4的第一端电连接，所述第四复位晶体管TR4的漏极与所述第四积分电容CG4的第二端电连接；
所述第五复位晶体管TR5的栅极与所述复位控制端SR电连接，所述第五复位晶体管TR5的源极与所述第五积分电容CG5的第一端电连接，所述第五复位晶体管TR5的漏极与所述第五积分电容CG5的第二端电连接；
所述运算放大器O0的正相输入端与参考电压端CR电连接，所述参考电压端CR用于提供参考电压Vref，所述参考电压Vref的电压值为2.0V；
所述滤波电路包括第一滤波电容C1、滤波电阻R0和第二滤波电容C2；
第一滤波电容C1的第一端与所述运算放大器O0的输出端电连接，第一滤波电容C1的第二端接地；
滤波电阻R0的第一端与所述运算放大器O0的输出端电连接，滤波电阻R0的第二端与采样开关S0的第一端电连接；
第二滤波电容C2的第一端与滤波电阻R0的第二端电连接，第二滤波电容C2的第二端接地；
采样开关S0的控制端与采样控制端KD电连接，采样开关S0的第二端与存储电容C0的第一端电连接，存储电容C0的第二端接地；
采样开关S0的第二端与模数转换器A0的输入端电连接，模数转换器A0的输出端与所述微控制单元80电连接；
所述模数转换器A0用于将其输入端接入的模拟输出电压进行模数转换，得到相应的输出数字信号；
设置于所述微控制单元80中的输出处理单元用于根据所述输出数字信号得到相应的光信号的特征；
设置于所述微控制单元80中的控制信号生成电路与所述采样控制端KD电连接，用于为所述采样控制端KD提供采样控制信号；所述控制信号生成电路还与所述电平转换器702电连接，用于为所述电平转换器702提供输入复位控制信号、第一输入光感控制信号、第二输入光感控制信号、第三输入光感控制信号、第四输入光感控制信号、第一输入电容控制信号、第二输入电容控制信号、第三输入电容控制信号、第四输入电容控制信号和第五输入电容控制信号；
所述电平转换器702分别与复位控制端SR、第一光感控制端KR、第二光感控制端KG、第三光感控制端KB、第四光感控制端KW、第一电容控制端G1、第二电容控制端G2、第三电容控制端G3、第四电容控制端G4和第五电容控制端G5电连接，用于对所述输入复位控制信号进行电平转换，得到复位控制信号，并将所述复位控制信号提供至所述复位控制端SR，并用于对所述第一输入光感控制信号进行电平转换，得到第一光感控制信号，并将所述第一光感控制信号提供至第一光感控制端KR，对所述第二输入光感控制信号进行电平转换，得到第二光感控制信号，并将所述第二光感控制信号提供至第二光感控制端KG，对所述第三输入光感控制信号进行电平转换，得到第三光感控制信号，并将所述第三光感控制信号提供至第三光感控制端KB，对所述第四输入光感控制信号进行电平转换，得到第四光感控制信号，并将所述第四光感控制信号提供至第一光感控制端KW，并用于对所述第一输入 电容控制信号进行电平转换，得到第一电容控制信号，并将所述第一电容控制信号提供至第一电容控制端G1，对所述第二输入电容控制信号进行电平转换，得到第二电容控制信号，并将所述第二电容控制信号提供至第二电容控制端G2，对所述第三输入电容控制信号进行电平转换，得到第三电容控制信号，并将所述第三电容控制信号提供至第三电容控制端G3，对所述第四输入电容控制信号进行电平转换，得到第四电容控制信号，并将所述第四电容控制信号提供至第四电容控制端G4，对所述第五输入电容控制信号进行电平转换，得到第五电容控制信号，并将所述第五电容控制信号提供至第五电容控制端G5；
所述微控制单元80还可以包括第一串行输出接口Sc1和第二串行输出接口Sc2，并可以通过所述第一串行输出接口Sc1和所述第二串行接口Sc2将所述光信号的特征输出至应用单元，以便所述应用单元能够根据所述光信号获得当前环境光的数据。
在图6所示的光检测模组的至少一实施例中，所述第一串行输出接口Sc1可以为SPI接口(串行外设接口)或I 2C(双向二线制同步串行总线)接口，所述第二串行输出接口可以为SPI接口(串行外设接口)或I 2C(双向二线制同步串行总线)接口，但不以此为限。
在图6所示的光检测模组的至少一实施例中，所述滤波电路包括一个滤波电阻和两个滤波电容，但是所述各滤波电路的结构并不限于上述结构，所述滤波电路只要能达到滤除高频噪声的目的即可，所述滤波电路的具体结构可以根据实际情况选定；
所述滤波电路为低通滤波电路，可以有效滤除高频噪声，使得输出信号稳定，噪声波动减小。
在图6所示的光检测模组的至少一实施例中，各光感控制晶体管、各采样控制晶体管和各复位晶体管可以都为n型晶体管，但不以此为限。在实际操作时，以上各晶体管也可以被替换为p型晶体管。
在图6所示的光检测模组的至少一实施例中，各光电二极管、各光感控制晶体管、各电容控制晶体管和各复位晶体管可以设置于显示基板上，可以在制作显示基板上的薄膜晶体管的同时，制作各光感控制晶体管、各电容控 制晶体管和各复位晶体管；所述运算放大器、所述滤波电路、采样开关、存储电容、模数转换器、微控制单元和电平转换器可以设置于线路板或显示驱动集成电路上。
在图6所示的光检测模组的至少一实施例中，当各光感控制晶体管、各电容控制晶体管和各复位晶体管采用TFT(薄膜晶体管)工艺制作，包括LTPS(低温多晶硅)PMOS(P型金属-氧化物-半导体晶体管)、LTPS NMOS(N型金属-氧化物-半导体晶体管)和IGZO(铟镓锌氧化物)oxide(氧化物)等工艺制作，则当各光感控制晶体管、各电容控制晶体管和各复位晶体管为n型晶体管时，当各光感控制信号的电位为7V时，各光感控制晶体管导通，当各电容控制信号的电位为7V时，各电容控制晶体管导通，当各复位控制信号的电位为7V时，各复位晶体管导通；当各光感控制晶体管、各电容控制晶体管和各复位晶体管为p型晶体管时，当各光感控制信号的电位为-7V时，各光感控制晶体管导通，当各电容控制信号的电位为-7V时，各电容控制晶体管导通，当各复位控制信号的电位为-7V时，各复位晶体管导通；所述微控制单元80提供的各控制信号的低电压值、高电压值分别为0V、3V，此时需要所述电平转换器70将0V电压转换为-7V电压，将3.3V电压转换为7V电压，以满足各控制晶体管控制电平的要求。
在图6所示的光检测模组的至少一实施例中，第一积分电容CG1的电容值、第二积分电容CG2的电容值、第三积分电容CG3的电容值、所述第四积分电容CG4的电容值和所述第五积分电容CG5的电容值互不相同。
在具体实施时，各积分电容的电容值可以根据各光电二极管产生的光电流的电流值范围和积分时间灵活选定。
在图6所示的光检测模组的至少一实施例中，第一积分电容CG1的电容值可以为0.1pF，第二积分电容CG2的电容值可以为1pF，第三积分电容CG3的电容值可以为10pF，第四积分电容CG4的电容值可以为100pF，第五积分电容CG5的电容值可以为1nF，但不以此为限；
所述第一积分电容CG1的电容值和所述第二积分电容CG2的电容值较小，所述第一积分电容CG1和所述第二积分电容CG2可以设置于所述显示基板上；
所述第三积分电容CG3的电容值、所述第四积分电容CG4的电容值和所述第五积分电容CG5的电容值较大，所述第三积分电容CG3、所述第四积分电容CG4和所述第五积分电容CG5可以设置于FPC(柔性电路板)上。
在本公开至少一实施例中，至少部分所述积分电容的电容值小于10pF，所述至少部分所述积分电容可以设置于显示基板上，所述采样子电路包括的除了所述至少部分所述积分电容之外的积分电容可以设置于线路板或驱动集成电路上。
在图6所示的光检测模组的至少一实施例中，所述模数转换器A0的输入电压范围为大于等于VS3而小于等于VS4，如果所述模数转换器A0是n位模数转换器，可以得到一个LSB(最低有效位)的转换精度为(VS4-VS3)/2 n.例如，当n等于16时，16bit(位)模数转换器的输入电压范围为大于等于0V而小于等于3.64V，则一个LSB的转换精度为55.5uV。但模数转换器A0在输入电压范围为大于等于VS1而小于等于VS2时，转换成的数字信号存在高精度线性关系，其中，VS3<VS1<VS2<VS4。
为了确保模数转换精度，模数转换器的输入电压范围为大于等于第一电压VS1而小于第二电压VS2，在本公开至少一实施例中，VS1可以为0.2V,VS2可以为2.0V，VS3可以为0V，VS4可以为3.64V，即允许输入模数转换器A0的输入电压范围为大于等于0V而小于等于3.64V，但是在输入电压范围为大于等于0.2V而小于等于2.0V时，模数转换存在高精度线性关系，精度比较高。
在本公开至少一实施例中，所述模数转换器A0的高精度电压转换范围为所述模数转换器A0能够准确进行模数转换的输入电压的范围；所述模数转换器A0的电压转换范围为所述模数转换器A0能够进行模数转换的输入电压的范围。例如，所述模数转换器A0的高精度电压转换范围可以为大于等于第一电压VS1而小于等于VS2，所述模数转换器A0的电压转换范围可以为大于等于VS3而小于等于VS4。其中，所述输入电压为输入所述模数转换器A0的电压。
本公开如图6所示的光检测模组在工作时，在各复位晶体管进行复位之后，在各复位晶体管关断的前提下，在S0由导通状态变为关断状态之前，通 过相应的光电流为相应的积分电容持续充电的时间为积分时间。
在图7中，V0为所述运算放大器O0的输出端的电位,标号为D0的为所述模数转换器A0输出的输出数字信号。
如图7所示，本公开如图6所示的光检测模组的至少一实施例在工作时，检测周期包括先后设置的第一采样阶段S1、第二采样阶段S2、第三采样阶段S3和第四采样阶段S4；
第一采样阶段S1包括先后设置的第一采样时间段S11、第二采样时间段S12、第三采样时间段S13、第四采样时间段S14和第五采样时间段S15；
第二采样阶段S2包括先后设置的第六采样时间段S21、第七采样时间段S22、第八采样时间段S23、第九采样时间段S24和第十采样时间段S25；
第三采样阶段S3包括先后设置的第十一采样时间段S31、第十二采样时间段S32、第十三采样时间段S33、第十四采样时间段S34和第十五采样时间段S35；
第四采样阶段S4包括先后设置的第十六采样时间段S41、第十七采样时间段S42、第十八采样时间段S43、第十九采样时间段S44和第二十采样时间段S45；
在第一采样时间段S11，KR提供高电平信号，KG、KB和KW都提供低电平信号，G1提供高电平信号，G2、G3、G4和G5都提供低电平信号，TR导通，TG、TB和TW关断，TG1导通，TG2、TG3、TG4和TG5都关断；第一采样时间段S1包括先后设置的第一复位时间段和第一积分时间段；
在第一复位时间段，SR提供高电平信号，KD提供低电平信号，TR1导通，CG1的第一端与CG1的第二端之间连通，以释放CG1中的电荷，完成对积分电容的电荷复位工作；
在第一积分时间段，SR提供的复位控制信号由高电平信号变为低电平信号，KD提供高电平信号，TR1关断，D1将其接收到的红色光信号转换为第一个第一光电流，该第一个第一光电流经过导通的TR和TG1写入第一积分电容CG1的第一端；所述第一个第一光电流流向第一积分电容CG1，在CG1上形成压降，即所述第一个第一光电流开始在第一积分电容CG1上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref- (Ir1×t0/Cz1)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ir1为所述第一个第一光电流的电流值，t0为积分时间，Cz1为CG1的电容值；积分时间t0为在所述第一积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的红色光信号的特征；
在第二采样时间段S12，KR提供的信号保持为高电平信号，KG、KB和KW都提供低电平信号，G2提供高电平信号，G1、G3、G4和G5都提供低电平信号，TR导通，TG、TB和TW关断，TG2导通，TG1、TG3、TG4和TG5都关断；第二采样时间段S12包括先后设置的第二复位时间段和第二积分时间段；
在第二复位时间段，SR提供高电平信号，KD提供低电平信号，TR2导通，S0关断，CG2的第一端与CG2的第二端之间连通，以释放CG2中的电荷；
在第二积分时间段，SR提供低电平信号，KD提供高电平信号，TR2关断，S0导通，D1将其接收到的红色光信号转换为第二个第一光电流，该第二个第一光电流经过导通的TR和TG2写入CG2的第一端；该第二个第一光电流流向第二积分电容CG2，在第二积分电容CG2上形成压降，即所述第二个第一光电流开始在第二积分电容CG2上累积，实现积分功能；S0导通，将积分电压保存在存储电容C0上；Vo1等于Vref-(Ir2×t0/Cz2)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ir2为所述第二个第一光电流的电流值，t0为积分时间，Cz2为CG2的电容值；积分时间t0为在所述第二积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将 所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的红色光信号的特征；
在第三采样时间段S13，KR提供高电平信号，KG、KB和KW都提供低电平信号，G3提供高电平信号，G1、G2、G4和G5都提供低电平信号，TR导通，TG、TB和TW关断，TG3导通，TG1、TG2、TG4和TG5都关断；第三采样时间段S13包括先后设置的第三复位时间段和第三积分时间段；
在第三复位时间段，SR提供高电平信号，KD提供低电压平号，TR3导通，CG3的第一端与CG3的第二端之间连通，以释放CG3中的电荷；
在第三积分时间段，SR提供低电平信号，KD提供高电平信号，TR3关断，S0导通，D1将其接收到的红色光信号转换为第三个第一光电流，该第三个第一光电流经过导通的TR和TG3写入CG3的第一端；该第三个第一光电流流向第三积分电容CG3，在CG3上形成压降，即所述第三个第一光电流开始在第三积分电容CG3上累积，实现积分功能；S0导通，将积分电压保存在存储电容C0上；Vo1等于Vref-(Ir3×t0/Cz3)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ir3为所述第三个第一光电流的电流值，t0为积分时间，Cz3为CG3的电容值；积分时间t0为在所述第三积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的红色光信号的特征；
在第四采样时间段S14，KR提供高电平信号，KG、KB和KW都提供低电平信号，G4提供高电平信号，G1、G2、G3和G5都提供低电平信号，TR导通，TG、TB和TW关断，TG4导通，TG1、TG2、TG3和TG5都关断；第四采样时间段S14包括先后设置的第四复位时间段和第四积分时间段；
在第四复位时间段，SR提供高电平信号，KD提供低电平信号，TR4导通，CG4的第一端与CG4的第二端之间连通，以释放CG4中的电荷；
在第四积分时间段，SR提供低电平信号，KD提供高电平信号，TR4关 断，S0导通，D1将其接收到的红色光信号转换为第四个第一光电流，该第四个第一光电流经过导通的TR和TG4写入CG4的第一端；所述第四个第一光电流开始在第四积分电容CG4上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ir4×t0/Cz4)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ir4为所述第四个第一光电流的电流值，t0为积分时间，Cz4为CG4的电容值；积分时间t0为在所述第四积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的红色光信号的特征；
在第五采样时间段S15，KR提供高电平信号，KG、KB和KW都提供低电平信号，G5提供高电平信号，G1、G2、G3和G4都提供低电平信号，TR导通，TG、TB和TW关断，TG5导通，TG1、TG2、TG3和TG4都关断；第五采样时间段S15包括先后设置的第五复位时间段和第五积分时间段；
在第五复位时间段，SR提供高电平信号，KD提供低电平信号，TR5导通，CG5的第一端与CG5的第二端之间连通，以释放CG5中的电荷；
在第五积分时间段，SR提供低电平信号，KD提供高电平信号，TR5关断，S0导通，D1将其接收到的红色光信号转换为第五个第一光电流，该第五个第一光电流经过导通的TR和TG5写入CG5的第一端；所述第五个第一光电流流向第五积分电容CG5，在CG5上形成压降，即所述第五个第一光电流开始在第五积分电容CG5上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ir5×t0/Cz5)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ir5为所述第五个第一光电流的电流值，t0为积分时间，Cz5为CG5的电容值；积分时间t0为在所述第五积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所 述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的红色光信号的特征；
在第六采样时间段S21，KG提供高电平信号，KR、KB和KW都提供低电平信号，G1提供高电平信号，G2、G3、G4和G5都提供低电平信号，TG导通，TR、TB和TW关断，TG1导通，TG2、TG3、TG4和TG5都关断；第六采样时间段S21包括先后设置的第六复位时间段和第六积分时间段；
在第六复位时间段，SR提供高电平信号，KD提供低电平信号，TR1导通，S0关断，CG1的第一端与CG1的第二端之间连通，以释放CG1中的电荷；
在第六积分时间段，SR提供低电平信号，KD提供高电平信号，TR1关断，D2将其接收到的绿色光信号转换为第一个第二光电流，该第一个第二光电流经过导通的TG和TG1写入CG1的第一端；所述第一个第二光电流流向第一积分电容CG1，在CG1上形成压降，即所述第一个第二光电流开始在第一积分电容CG1上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ig1×t0/Cz1)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ig1为所述第一个第二光电流的电流值，t0为积分时间，Cz1为CG1的电容值；积分时间t0为在所述第六积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的绿色光信号的特征；
在第七采样时间段S22，KG提供高电平信号，KR、KB和KW都提供低电平信号，G2提供高电平信号，G1、G3、G4和G5都提供低电平信号，TG导通，TR、TB和TW关断，TG2导通，TG1、TG3、TG4和TG5都关断；第七采样时间段S22包括先后设置的第七复位时间段和第七积分时间段；
在第七复位时间段，SR提供高电平信号，KD提供低电平信号，TR2导 通，CG2的第一端与CG2的第二端之间连通，以释放CG2中的电荷；
在第七积分时间段，SR提供低电平信号，KD提供高电平信号，TR2关断，S0导通，D2将其接收到的绿色光信号转换为第二个第二光电流，该第二个第二光电流经过导通的TG和TG2写入CG2的第一端；所述第二个第二光电流流向第二积分电容CG2，在CG2上形成压降，即所述第二个第二光电流开始在第二积分电容CG2上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ig2×t0/Cz2)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ig2为所述第二个第二光电流的电流值，t0为积分时间，Cz2为CG2的电容值；积分时间t0为在所述第七积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的绿色光信号的特征；
在第八采样时间段S23，KG提供高电平信号，KR、KB和KW都提供低电平信号，G3提供高电平信号，而G1、G2、G4和G5都提供低电平信号，TG导通，TR、TB和TW关断，TG3导通，TG1、TG2、TG4和TG5都关断；第八采样时间段S23包括先后设置的第八复位时间段和第八积分时间段；
在第八复位时间段，SR提供高电平信号，KD提供低电平信号，TR3导通，CG3的第一端与CG3的第二端之间连通，以释放CG3中的电荷；
在第八积分时间段，SR提供低电平信号，KD提供高电平信号，TR3关断，S0导通，D2将其接收到的绿色光信号转换为第三个第二光电流，该第三个第二光电流经过导通的TG和TG3写入CG3的第一端；所述第三个第二光电流流向第三积分电容CG3，在CG3上形成压降，即所述第三个第二光电流开始在第三积分电容CG3上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ig3×t0/Cz3)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ig3为所述第三个第二光电流的电流值，t0为积分时间，Cz3为CG3的电容值；积分时间t0为在所述第八积分 时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的绿色光信号的特征；
在第九采样时间段S24，KG提供高电平信号，KR、KB和KW都提供低电平信号，G4提供高电平信号，G1、G2、G3和G5都提供低电平信号，TG导通，TR、TB和TW关断，TG4导通，TG1、TG2、TG3和TG5都关断；第九采样时间段S24包括先后设置的第九复位时间段和第九积分时间段；
在第九复位时间段，SR提供高电平信号，KD提供低电平信号，TR4导通，CG4的第一端与CG4的第二端之间连通，以释放CG4中的电荷；
在第九积分时间段，SR提供低电平信号，KD提供高电平信号，TR4关断，S0导通，D2将其接收到的绿色光信号转换为第四个第二光电流，该第四个第二光电流经过导通的TG和TG4写入CG4的第一端；所述第四个第二光电流流向第四积分电容CG4，在CG4上形成压降，即所述第四个第二光电流开始在第四积分电容CG4上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ig4×t0/Cz4)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ig4为所述第四个第二光电流的电流值，t0为积分时间，Cz4为CG4的电容值；积分时间t0为在所述第九积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的绿色光信号的特征；
在第十采样时间段S25，KG提供高电平信号，KR、KB和KW都提供低电平信号，G5提供高电平信号，G1、G2、G3和G4都提供低电平信号，TG导通，TR、TB和TW关断，TG5导通，TG1、TG2、TG3和TG4都关断； 第十采样时间段S25包括先后设置的第十复位时间段和第十积分时间段；
在第十复位时间段，SR提供高电平信号，KD提供低电平信号，TR5导通，CG5的第一端与CG5的第二端之间连通，以释放CG5中的电荷；
在第十积分时间段，SR提供低电平信号，KD提供高电平信号，TR5关断，S0导通，D2将其接收到的绿色光信号转换为第五个第二光电流，该第五个第二光电流经过导通的TG和TG5写入CG5的第一端；所述第五个第二光电流流向第五积分电容CG5，在CG5上形成压降，即所述第五个第二光电流开始在第五积分电容CG5上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ig5×t0/Cz5)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ig5为所述第五个第二光电流的电流值，t0为积分时间，Cz5为CG5的电容值；积分时间t0为在所述第十积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的绿色光信号的特征；
在第十一采样时间段S31，KB提供高电平信号，KR、KG和KW都提供低电平信号，G1提供高电平信号，G2、G3、G4和G5都提供低电平信号，TB导通，TR、TG和TW关断，TG1导通，TG2、TG3、TG4和TG5都关断；第十一采样时间段S31包括先后设置的第十一复位时间段和第十一积分时间段；
在第十一复位时间段，SR提供高电平信号，KD提供低电平信号，TR1导通，CG1的第一端与CG1的第二端之间连通，以释放CG1中的电荷；
在第十一积分时间段，SR提供低电平信号，KD提供高电平信号，TR1关断，S0导通，D3将其接收到的蓝色光信号转换为第一个第三光电流，该第一个第三光电流经过导通的TB和TG1写入CG1的第一端；所述第一个第三光电流流向第一积分电容CG1，在CG1上形成压降，即所述第一个第三光电流开始在第一积分电容CG1上累积，实现积分功能；S0导通，将积分电压 保存到存储电容C0上；Vo1等于Vref-(Ib1×t0/Cz1)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib1为所述第一个第三光电流的电流值，t0为积分时间，Cz1为CG1的电容值；积分时间t0为在所述第十一积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的蓝色光信号的特征；
在第十二采样时间段S32，KB提供高电平信号，KR、KG和KW都提供低电平信号，G2提供高电平信号，G1、G3、G4和G5都提供低电平信号，TB导通，TR、TG和TW关断，TG2导通，TG1、TG3、TG4和TG5都关断；第十二采样时间段S32包括先后设置的第十二复位时间段和第十二积分时间段；
在第十二复位时间段，SR提供高电平信号，KD提供低电平信号，TR2导通，CG2的第一端与CG2的第二端之间连通，以释放CG2中的电荷；
在第十二积分时间段，SR提供低电平信号，KD提供高电平信号，TR2关断，S0导通，D3将其接收到的蓝色光信号转换为第二个第三光电流，该第二个第三光电流经过导通的TB和TG2写入CG2的第一端；所述第二个第三光电流流向第二积分电容CG2，在CG2上形成压降，即所述第二个第三光电流开始在第二积分电容CG2上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ib2×t0/Cz2)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib2为所述第二个第三光电流的电流值，t0为积分时间，Cz2为CG2的电容值；积分时间t0为在所述第十二积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根 据所述输出数字信号得到相应的蓝色光信号的特征；
在第十三采样时间段S33，KB提供高电平信号，KR、KG和KW都提供低电平信号，G3提供高电平信号，G1、G2、G4和G5都提供低电平信号，TB导通，TR、TG和TW关断，TG3导通，TG1、TG2、TG4和TG5都关断；第十三采样时间段S33包括先后设置的第十三复位时间段和第十三积分时间段；
在第十三复位时间段，SR提供高电平信号，KD提供低电平信号，TR3导通，CG3的第一端与CG3的第二端之间连通，以释放CG3中的电荷；
在第十三积分时间段，SR提供低电平信号，KD提供高电平信号，TR3关断，S0导通，D3将其接收到的蓝色光信号转换为第三个第三光电流，该第三个第三光电流经过导通的TB和TG3写入CG3的第一端；所述第三个第三光电流流向第三积分电容CG3，在CG3上形成压降，即所述第三个第三光电流开始在第三积分电容CG3上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ib3×t0/Cz3)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib3为所述第三个第三光电流的电流值，t0为积分时间，Cz3为CG3的电容值；积分时间t0为在所述第十三积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的蓝色光信号的特征；
在第十四采样时间段S34，KB提供高电平信号，KR、KG和KW都提供低电平信号，G4提供高电平信号，G1、G2、G3和G5都提供低电平信号，TB导通，TR、TG和TW关断，TG4导通，TG1、TG2、TG3和TG5都关断；第十四采样时间段S34包括先后设置的第十四复位时间段和第十四积分时间段；
在第十四复位时间段，SR提供高电平信号，KD提供低电平信号，TR4导通，CG4的第一端与CG4的第二端之间连通，以释放CG4中的电荷；
在第十四积分时间段，SR提供低电平信号，KD提供高电平信号，TR4关断，S0导通，D3将其接收到的蓝色光信号转换为第四个第三光电流，该第四个第三光电流经过导通的TB和TG4写入CG4的第一端；所述第四个第三光电流流向第四积分电容CG4，在CG4上形成压降，即所述第四个第三光电流开始在第四积分电容CG4上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ib4×t0/Cz4)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib4为所述第四个第三光电流的电流值，t0为积分时间，Cz4为CG4的电容值；积分时间t0为在所述第十四积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的蓝色光信号的特征；
在第十五采样时间段S35，KB提供高电平信号，KR、KG和KW都提供低电平信号，G5提供高电平信号，G1、G2、G3和G4都提供低电平信号，TB导通，TR、TG和TW关断，TG5导通，TG1、TG2、TG3和TG4都关断；第十五采样时间段S35包括先后设置的第十五复位时间段和第十五积分时间段；
在第十五复位时间段，SR提供高电平信号，KD提供低电平信号，TR5导通，CG5的第一端与CG5的第二端之间连通，以释放CG5中的电荷；
在第十五积分时间段，SR提供低电平信号，KD提供高电平信号，TR5关断，S0导通，D3将其接收到的蓝色光信号转换为第五个第三光电流，该第五个第三光电流经过导通的TB和TG5写入CG5的第一端；所述第五个第三光电流流向第五积分电容CG5，在CG5上形成压降，即所述第五个第三光电流开始在第五积分电容CG5上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Ib5×t0/Cz5)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib5为所述第五个第三光电流的电流值，t0为积分时间，Cz5为CG5的电容值；积分时间t0为在所述第十五 积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的蓝色光信号的特征；
在第十六采样时间段S41，KW提供高电平信号，KR、KG和KB都提供低电平信号，G1提供高电平信号，G2、G3、G4和G5都提供低电平信号，TW导通，TR、TG和TB关断，TG1导通，TG2、TG3、TG4和TG5都关断；第十六采样时间段S41包括先后设置的第十六复位时间段和第十六积分时间段；
在第十六复位时间段，SR提供高电平信号，KD提供低电平信号，TR1导通，CG1的第一端与CG1的第二端之间连通，以释放CG1中的电荷；
在第十六积分时间段，SR提供低电平信号，KD提供高电平信号，TR1关断，S0导通，D4将其接收到的白色光信号转换为第一个第四光电流，该第一个第四光电流经过导通的TW和TG1写入CG1的第一端；所述第一个第四光电流流向第一积分电容CG1，在CG1上形成压降，即所述第四个第一光电流开始在第一积分电容CG1上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Iw1×t0/Cz1)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Iw1为所述第一个第四光电流的电流值，t0为积分时间，Cz1为CG1的电容值；积分时间t0为在所述第十六积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的白色光信号的特征；
在第十七采样时间段S42，KB提供高电平信号，KR、KG和KW都提供低电平信号，G2提供高电平信号，G1、G3、G4和G5都提供低电平信号， TW导通，TR、TG和TB关断，TG2导通，TG1、TG3、TG4和TG5都关断；第十七采样时间段S42包括先后设置的第十七复位时间段和第十七积分时间段；
在第十七复位时间段，SR提供高电平信号，KD提供低电平信号，TR2导通，S0关断，CG2的第一端与CG2的第二端之间连通，以释放CG2中的电荷；
在第十七积分时间段，SR提供低电平信号，KD提供高电平信号，TR2关断，S0导通，D4将其接收到的白色光信号转换为第二个第四光电流，该第二个第四光电流经过导通的TW和TG2写入CG2的第一端；所述第二个第四光电流流向第二积分电容CG2，在CG2上形成压降，即所述第二个第四光电流开始在第二积分电容CG2上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Iw2×t0/Cz2)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Iw2为所述第二个第四光电流的电流值，t0为积分时间，Cz2为CG2的电容值；积分时间t0为在所述第十七积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的白色光信号的特征；
在第十八采样时间段S43，KW提供高电平信号，KR、KG和KB都提供低电平信号，G3提供高电平信号，G1、G2、G4和G5都提供低电平信号，TB导通，TR、TG和TW关断，TG3导通，TG1、TG2、TG4和TG5都关断；第十八采样时间段S33包括先后设置的第十八复位时间段和第十八积分时间段；
在第十八复位时间段，SR提供高电平信号，KD提供低电平信号，TR3导通，S0关断，CG3的第一端与CG3的第二端之间连通，以释放CG3中的电荷；
在第十八积分时间段，SR提供低电平信号，KD提供高电平信号，TR3 关断，S0导通，D4将其接收到的白色光信号转换为第三个第四光电流，该第三个第四光电流经过导通的TW和TG3写入CG3的第一端；所述第三个第四光电流流向第三积分电容CG3，在CG3上形成压降，即所述第三个第四光电流开始在第三积分电容CG3上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Iw3×t0/Cz3)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Iw3为所述第三个第四光电流的电流值，t0为积分时间，Cz3为CG3的电容值；积分时间t0为在所述第十八积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的白色光信号的特征；
在第十九采样时间段S44，KW提供高电平信号，KR、KG和KB都提供低电平信号，G4提供高电平信号，G1、G2、G3和G5都提供低电平信号，TW导通，TR、TG和TB关断，TG4导通，TG1、TG2、TG3和TG5都关断；第十九采样时间段S44包括先后设置的第十九复位时间段和第十九积分时间段；
在第十九复位时间段，SR提供高电平信号，KD提供低电平信号，TR4导通，S0关断，CG4的第一端与CG4的第二端之间连通，以释放CG4中的电荷；
在第十九积分时间段，SR提供低电平信号，KD提供高电平信号，TR4关断，S0导通，D4将其接收到的白色光信号转换为第四个第四光电流，该第四个第四光电流经过导通的TW和TG4写入CG4的第一端；所述第四个第四光电流流向第四积分电容CG4，在CG4上形成压降，即所述第四个第四光电流开始在第四积分电容CG1上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Iw4×t0/Cz4)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Ib4为所述第四个第三光电流的电流值，t0为积分时间，Cz4为CG4的电容值；积分时间t0为在所述第十 九积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的白色光信号的特征；
在第二十采样时间段S45，KW提供高电平信号，KR、KG和KB都提供低电平信号，G5提供高电平信号，G1、G2、G3和G4都提供低电平信号，TW导通，TR、TG和TB关断，TG5导通，TG1、TG2、TG3和TG4都关断；第二十采样时间段S45包括先后设置的第二十复位时间段和第二十积分时间段；
在第二十复位时间段，SR提供高电平信号，KD提供低电平信号，TR5导通，S0关断，CG5的第一端与CG5的第二端之间连通，以释放CG5中的电荷；
在第二十积分时间段，SR提供低电平信号，KD提供高电平信号，TR5关断，S0导通，D4将其接收到的八色光信号转换为第五个第四光电流，该第五个第四光电流经过导通的TW和TG5写入CG5的第一端；所述第五个第四光电流流向第五积分电容CG5，在CG5上形成压降，即所述第五个第四光电流开始在第五积分电容CG5上累积，实现积分功能；S0导通，将积分电压保存到存储电容C0上；Vo1等于Vref-(Iw5×t0/Cz5)，其中，Vo1为在积分结束时所述运算放大器O0的输出端的电位，Iw5为所述第五个第四光电流的电流值，t0为积分时间，Cz5为CG5的电容值；积分时间t0为在所述第二十积分时间段，S0持续导通的时间，例如，所述积分时间t0可以为100us；在积分结束时，所述运算放大器O0输出的模拟输出电压的电压值即为Vo1，所述模拟输出电压经过滤波电路后写入模数转换器A0的输入端，模数转换器A0对所述模拟输出电压进行模数转换，得到相应的输出数字信号，并将所述输出数字信号写入微控制单元80，所述微控制单元80中的输出处理单元根据所述输出数字信号得到相应的白色光信号的特征。
本公开如图6所示的光检测模组的至少一实施例在工作时，当KD提供 低电平信号时，S0可以关断，但不以此为限。
当所述模数转换器A0的电压转换范围为大于等于0V而小于等于3.64V，所述模数转换器A0输出的输出数字信号的位数为16时，本公开如图6所示的光检测模组的至少一实施例在工作时，
当采用第一档位采集时，CG1的第一端与O0的反相输入端之间连通，CG1的电容值为0.1pF，积分时间为100us，数模转换器A0的高精度电压转换范围为大于等于0.2V而小于等于2V，则该第一档位能够准确检测的光电流范围为大于等于200pA而小于等于2000pA，此时电流采样精度为0.06pA/LSB；其中，LSB为最低有效位；并当采用第一档位采集时，转移系数为t0/Cz1，t0为积分时间，Cz1为第一积分电容CG1的电容值；
当采用第二档位采集时，CG2的第一端与O0的反相输入端之间连通，CG2的电容值为1pF，积分时间为100us，数模转换器A0的高精度电压转换范围为大于等于0.2V而小于等于2V，则该第二档位能够准确检测的光电流范围为大于等于2nA而小于等于20nA，此时电流采样精度为0.56pA/LSB；并当采用第二档位采集时，转移系数为t0/Cz2，t0为积分时间，Cz2为第二积分电容CG2的电容值；
当采用第三档位采集时，CG3的第一端与O0的反相输入端之间连通，CG2的电容值为10pF，积分时间为100us，数模转换器A0的高精度电压转换范围为大于等于0.2V而小于等于2V，则该第三档位能够准确检测的光电流范围为大于等于20nA而小于等于200nA，此时电流采样精度为5.6pA/LSB；并当采用第三档位采集时，转移系数为t0/Cz3，t0为积分时间，Cz3为第三积分电容CG3的电容值；
当采用第四档位采集时，CG4的第一端与O0的反相输入端之间连通，CG2的电容值为100pF，积分时间为100us，数模转换器A0的高精度电压转换范围为大于等于0.2V而小于等于2V，则该第四档位能够准确检测的光电流范围为大于等于200nA而小于等于2000nA，此时电流采样精度为56pA/LSB；并当采用第四档位采集时，转移系数为t0/Cz4，t0为积分时间，Cz4为第四积分电容CG4的电容值；
当采用第五档位采集时，CG5的第一端与O0的反相输入端之间连通， CG5的电容值为10pF，积分时间为100us，数模转换器A0的高精度电压转换范围为大于等于0.2V而小于等于2V，则该第五档位能够准确检测的光电流范围为大于等于2uA而小于等于20uA，此时电流采样精度为560pA/LSB；并当采用第五档位采集时，转移系数为t0/Cz5，t0为积分时间，Cz5为第五积分电容CG5的电容值；
所述模数转换器A0的转换一个LSB的电压为55.58uV/LSB，LSB为最低有效位。
由上可知，本公开如图6所示的光检测模组的至少一实施例能够采集的光电流范围为大于等于200pA而小于等于20uA，为了能够检测到200pA的光电流，采集精度和运算放大器O0的OS漏电流(所述运算放大器O0的OS漏电流为运算放大器O0的正负输入端漏电流)相关，即如果采集误差为10％时，则运算放大器O0的OS漏电流至少小一个数量级。
本公开如图6所示的光检测模组的至少一实施例在工作时，一个采样周期包括第一采样阶段、第二采样阶段、第三采样阶段和第四采样阶段，在第一采样阶段采样对应于红色光信号的第一光电流，在第二采样阶段采样对应于绿色光信号的第二光电流，在第三采样阶段采样对应于蓝色光信号的第三光电流，在第四采样阶段采样对应于白色光信号的第四光电流；
每个采样阶段包括五个依次设置的采样时间段，在依次设置的五个采样时间段中，控制TG1、TG2、TG3、TG4、TG5依次导通；在每个采样阶段包括的第一个采样时间段中，TG1导通，TG2、TG3、TG4和TG5关断，CG1的第一端与所述运算放大器O0的反相输入端之间连通；在每个采样阶段包括的第二个采样时间段中，TG2导通，TG1、TG3、TG4和TG5关断，CG2的第一端与所述运算放大器O0的反相输入端之间连通；在每个采样阶段包括的第三个采样时间段中，TG3导通，TG1、TG2、TG4和TG5关断，RS3的第一端与所述运算放大器O0的反相输入端之间连通；在每个采样阶段包括的第四个采样时间段中，TG4导通，TKG1、TG2、TG3和TG5关断，CG4的第一端与所述运算放大器O0的反相输入端之间连通；在每个采样阶段包括的第五个采样时间段中，TG5导通，TKG1、TG2、TG3和TG4关断，CG5的第一端与所述运算放大器O0的反相输入端之间连通；
在每次积分结束，所述模拟转换器A0输出输出数字信号时，对所述模数转换器A0输出的输出数字信号进行判断，当所述模数转换器A0输出的输出数字信号对应的输入电压的电压值小于等于第一电压VS1(所述模数转换器A0的高精度电压转换范围为大于等于第一电压VS1而小于等于第二电压VS2)，则放弃相应的输出数字信号，直至所述输出数字信号对应的输入电压的电压值在所述模拟转换器A0的高精度电压转换范围时，记录当前的转移系数(所述转移系数与相应的积分电容的电容值和积分时间相关)，以及，将所述模拟转换器A0输出的输出数字信号传送至对应的存储单元中。在整个采样周期完成后，所述微控制单元80根据所述存储单元中的转移系数以及输出数字信号，可以得到各光信号的特征。
本公开实施例所述的光检测方法，应用于上述的光检测模组，所述光检测方法包括：
N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
控制电路控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并控制所述电容积分放大电路的转换参数；
电容积分转换电路根据所述转换参数和积分时间，对所述光电流进行转换，以得到模拟输出电压；
处理电路根据所述模拟输出电压得到所述光信号的特征。
本公开实施例所述的光检测方法通过电容积分转换电路采用电流积分的方法，并根据积分时间对所述光电流进行转换，则可以通过增大积分时间来减少光感电路采用的相互并联的光电二极管的个数，减低了光电二极管占用的面积，进而可以节省空间和成本。
在本公开至少一实施例中，所述控制电路包括光感控制子电路、采样子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
所述控制电路控制分时将各所述光感电路产生的光电流提供至转换电路步骤包括：所述光感控制子电路在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述电容积分转换电路的输入端；所述电容控制子电路在电容控制信号的控制下，控制各积分电容的第一端分时与所述电容积分转换电路的输入端之间连通；
所述转换参数为当前与所述电容积分转换电路的输入端之间连通的积分电容的电容值。
在本公开至少一实施例中，所述电容积分电路的转移系数可以为积分时间与当前与所述电容积分转换电路的输入端之间连通的积分电容的电容值的比值。
在具体实施时，所述控制电路可以包括光感控制子电路、采样子电路和电容控制子电路，光感控制子电路控制分时将各光感电路产生的光电流提供至电容积分转换电路的输入端，电容控制子电路控制与电容积分转换电路的输入端连通的积分电容。
可选的，所述处理电路包括模数转换器和输出处理单元；
所述处理电路根据所述模拟输出电压得到所述光信号的特征步骤包括：
所述模数转换器将所述模拟输出电压转换为输出数字信号；
所述输出处理单元根据所述输出数字信号得到所述光信号的特征。
在本公开至少一实施例中，所述模数转换器的高精度电压转换范围为所述模数转换器能够准确进行模数转换的输入电压的范围；所述模数转换器的电压转换范围为所述模数转换器A0能够进行模数转换的输入电压的范围；其中，所述输入电压为输入所述模数转换器的电压。
在本公开至少一实施例中，所述模数转换器的高精度电压转换范围为大于等于第一电压VS1而小于等于第二电压VS2，所述模数转换器的电压转换范围为大于等于第三电压VS3而小于等于第四电压VS3；第四电压VS3大于第二电压VS2；所述第三电压VS3小于所述第一电压VS1；
所述输出处理单元根据所述输出数字信号得到所述光信号的特征步骤包括：
所述输出处理单元判断所述输出数字信号对应的输入电压的电压值是否在所述高精度电压转换范围内；
当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值小于第一电压VS1或大于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值不在所述高精度电压转换范围内，放弃所述数字输出信号；
当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值大于等于第一电压VS1而小于等于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值在所述高精度电压转换范围内，所述输出处理单元根据所述数字输出信号得到所述光信号的特征。
在具体实施时，当所述输出数字信号对应的输入电压的电压值小于第一电压VS1或大于第二电压VS2时，所述模数转换器的输入端接入的输入电压的电压值超出了所述模数转换器的高精度电压转换范围，因此需要放弃该输出数字信号，采用其他的积分电容重新进行采样。
本公开实施例所述的显示装置包括上述的光检测模组。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种光检测模组，包括N个光感电路、控制电路、电容积分转换电路和处理电路；N为正整数；所述N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
    所述控制电路用于控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并用于控制所述电容积分放大电路的转换参数；
    所述电容积分转换电路用于根据所述转换参数和积分时间，对所述光电流进行积分转换，以得到模拟输出电压；
    所述处理电路用于根据所述模拟输出电压得到所述光信号的特征。
  2. 如权利要求1所述的光检测模组，其中，所述电容积分转换电路包括转换子电路、采样子电路和采样控制子电路；所述控制电路包括光感控制子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
    所述光感控制子电路用于在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述转换子电路的输入端；
    所述电容控制子电路用于在电容控制信号的控制下，控制各积分电容的第一端分时与所述转换子电路的输入端之间连通；各所述积分电容的第二端与所述转换子电路的输出端电连接；
    所述采样控制子电路用于在采样控制信号的控制下，控制所述转换子电路的输出端与所述处理电路之间连通或断开；
    所述转换子电路用于对所述光电流进行转换，得到并通过所述转换子电路的输出端输出所述模拟输出电压；
    所述转换参数为当前与所述转换子电路的输入端之间连通的积分电容的电容值。
  3. 如权利要求2所述的光检测模组，其中，还包括复位电路；所述复位电路包括M个复位子电路；
    第m复位子电路分别与第m积分电容的第一端、所述第m积分电容的第二端和复位控制端电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制所述第m积分电容的第一端与所述第m积分电容的第二端之间 连通，以释放所述第m积分电容中储存的电荷；
    m为小于或等于M的正整数。
  4. 如权利要求2所述的光检测模组，其中，所述光感控制子电路包括N个光感控制晶体管；所述电容控制子电路包括M个电容控制晶体管；n为小于或等于N的正整数，m为小于或等于M的正整数；所述采样控制子电路包括采样开关和存储电容；
    第n光感控制晶体管的控制极与第n光感控制端电连接，第n光感控制晶体管的第一极与第n光电流输出端电连接，第n光感控制晶体管的第二极与所述转换子电路的输入端电连接；所述第n光感控制端用于提供第n光感控制信号；
    第m电容控制晶体管的控制极与第m电容控制端电连接，第m电容控制晶体管的第一极与所述转换子电路的输入端电连接，第m电容控制晶体管的第二极与第m积分电容的第一端电连接，第m积分电容的第二端与所述转换子电路的输出端电连接；所述第m电容控制端用于提供第m电容控制信号；
    所述采样开关的控制端与采样控制端电连接，所述采样开关的第一端与所述转换子电路的输出端电连接，所述采样开关的第二端与所述处理电路电连接；
    所述存储电容的第一端与所述采样开关的第二端电连接，所述存储电容的第二端与直流电压端电连接。
  5. 如权利要求4所述的光检测模组，其中，还包括滤波电路；
    所述滤波电路连接于所述转换子电路的输出端与所述采样开关的第一端之间，用于滤除所述模拟输出电压中的高频噪声，并将滤除高频噪声之后的模拟输出电压提供至所述采样开关的第一端。
  6. 如权利要求3所述的光检测模组，其中，第m复位子电路包括第m复位晶体管；
    所述第m复位晶体管的控制极与所述复位控制端电连接，所述第m复位晶体管的第一极与所述第m积分电容的第一端电连接，所述第m复位晶体管的第二极与所述第m积分电容的第二端电连接。
  7. 如权利要求3所述的光检测模组，其中，所述N个光感电路、所述 光感控制子电路、所述电容控制子电路和所述复位电路都设置于显示基板上。
  8. 如权利要求2所述的光检测模组，其中，至少部分所述积分电容的电容值小于10pF，所述至少部分所述积分电容设置于显示基板上，所述采样子电路包括的除了所述至少部分所述积分电容之外的积分电容设置于线路板或驱动集成电路上。
  9. 如权利要求2至8中任一权利要求所述的光检测模组，其中，所述转换子电路包括运算放大器；所述运算放大器的反相输入端为所述转换子电路的输入端，所述运算放大器的输出端为所述转换子电路的输出端；
    所述运算放大器的正相输入端与参考电压端电连接，所述参考电压端用于提供参考电压。
  10. 如权利要求2至8中任一权利要求所述的光检测模组，其中，还包括控制信号生成单元；
    所述控制信号生成单元用于提供采样控制信号、光感控制信号、电容控制信号和复位控制信号。
  11. 如权利要求10所述的光检测模组，其中，所述处理电路包括模数转换器和输出处理单元；
    所述模数转换器用于将所述模拟输出电压转换为输出数字信号；
    所述输出处理单元与所述模数转换器电连接，用于接收所述输出数字信号，并根据所述输出数字信号得到所述光信号的特征。
  12. 如权利要求1至8中任一权利要求所述的光检测模组，其中，所述光信号的特征包括光强、亮度、色坐标、色温中的至少一个。
  13. 如权利要求10所述的光检测模组，其中，还包括微控制单元；所述控制信号生成单元包括控制信号生成电路和电平转换器；
    所述控制信号生成电路用于提供采样控制信号、输入光感控制信号、输入电容控制信号和输入复位控制信号；
    所述电平转换器与所述控制信号生成电路电连接，用于对所述输入光感控制信号进行电平转换，以生成所述光感控制信号，对所述输入电容控制信号进行电平转换，以生成所述电容控制信号，对所述输入复位控制信号进行电平转换，以生成所述复位控制信号；
    所述输出处理单元和所述控制信号生成电路设置于所述微控制单元中。
  14. 如权利要求13所述的光检测模组，其中，所述光检测模组还包括滤波电路；
    所述微控制单元、所述电平转换器、所述模数转换器、所述滤波电路，以及，所述电容积分转换电路包括的转换子电路和采样控制子电路都设置于线路板或驱动集成电路上。
  15. 如权利要求1至8中任一权利要求所述的光检测模组，其中，第n光感电路包括第n光电二极管；n为小于或等于N的正整数；
    所述第n光电二极管的阴极与电源电压端电连接，所述第n光电二极管的阳极用于提供第n光电流；
    所述电源电压端用于提供电源电压信号。
  16. 一种光检测方法，应用于如权利要求1至15中任一权利要求所述的光检测模组，所述光检测方法包括：
    N个光感电路分别感应不同颜色的光信号，产生相应的光电流；
    控制电路控制分时将各所述光感电路产生的光电流提供至所述电容积分放大电路，并控制所述电容积分放大电路的转换参数；
    电容积分转换电路根据所述转换参数和积分时间，对所述光电流进行转换，以得到模拟输出电压；
    处理电路根据所述模拟输出电压得到所述光信号的特征。
  17. 如权利要求16所述的光检测方法，其中，所述控制电路包括光感控制子电路、采样子电路和电容控制子电路；所述采样子电路包括M个积分电容；M为正整数；
    所述控制电路控制分时将各所述光感电路产生的光电流提供至转换电路步骤包括：所述光感控制子电路在光感控制信号的控制下，控制分时将各光感电路产生的光电流，提供至所述电容积分转换电路的输入端；所述电容控制子电路在电容控制信号的控制下，控制各积分电容的第一端分时与所述电容积分转换电路的输入端之间连通；
    所述转换参数为当前与所述电容积分转换电路的输入端之间连通的积分电容的电容值。
  18. 如权利要求16或17所述的光检测方法，其中，所述处理电路包括模数转换器和输出处理单元；
    所述处理电路根据所述模拟输出电压得到所述光信号的特征步骤包括：
    所述模数转换器将所述模拟输出电压转换为输出数字信号；
    所述输出处理单元根据所述输出数字信号得到所述光信号的特征。
  19. 如权利要求18所述的光检测方法，其中，所述模数转换器的高精度电压转换范围为大于等于第一电压VS1而小于等于第二电压VS2；
    所述输出处理单元根据所述输出数字信号得到所述光信号的特征步骤包括：
    所述输出处理单元判断所述输出数字信号对应的输入电压的电压值是否在所述高精度电压转换范围内；所述输入电压为输入所述模数转换器的电压；
    当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值小于第一电压VS1或大于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值不在所述高精度电压转换范围内，放弃所述数字输出信号；
    当所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值大于等于第一电压VS1而小于等于第二电压VS2时，所述输出处理单元判断得到所述输出数字信号对应的输入电压的电压值在所述高精度电压转换范围内，所述输出处理单元根据所述数字输出信号得到所述光信号的特征。
  20. 一种显示装置，包括如权利要求1至15中任一权利要求所述的光检测模组。
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CN1209930A (zh) * 1996-10-31 1999-03-03 马库斯·伯姆 用于短期曝光的彩色图象传感器
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