WO2022227882A1 - 一种单通道忆阻器及其制备方法 - Google Patents

一种单通道忆阻器及其制备方法 Download PDF

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WO2022227882A1
WO2022227882A1 PCT/CN2022/080051 CN2022080051W WO2022227882A1 WO 2022227882 A1 WO2022227882 A1 WO 2022227882A1 CN 2022080051 W CN2022080051 W CN 2022080051W WO 2022227882 A1 WO2022227882 A1 WO 2022227882A1
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functional layer
memristor
channel
functional
substrate
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PCT/CN2022/080051
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French (fr)
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孙华军
王涛
白娜
缪向水
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

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  • the invention belongs to the technical field of microelectronic devices, and more particularly, relates to a single-channel memristor and a preparation method thereof.
  • Memristors based on non-volatile resistive switches are the most anticipated next-generation memories, and multi-value tunability of conductance will shine in neuromorphic computing, filtering, logic and memory-computing integrated device applications.
  • memristors the most important factors hindering their commercialization progress are the complexity of their mechanisms and the instability of their properties.
  • the resistance switching mechanism of memristor is mainly divided into conductive filament mechanism, thermochemical mechanism and pure electronic effect.
  • the conductive filament mechanism is the most widely applicable and widely recognized mechanism.
  • the internal vacancies migrate under the action of the electric field to form conductive filaments, and the formation and rupture of the conductive filaments lead to the resistance state switching of the device.
  • the fracture and generation positions of the conductive filaments change with the distribution of the electric field, so the on-off position is not fixed each time, the morphology of the conductive filaments also changes with the progress of the cycle, and the device performance deteriorates.
  • the purpose of the present invention is to provide a single-channel memristor and a preparation method thereof, wherein by improving the structure of the memristive device, a first functional layer and a second functional layer are stacked
  • the formed stacked functional layer due to the lattice mismatch between the first functional layer and the second functional layer (the degree of lattice mismatch between the ideal lattices is not less than 5%), so using the interface mismatch, close to the perfect lattice.
  • Defects such as vacancies and dangling bonds formed at the interface of memristive materials build conductive filaments, thereby confining the conductive filaments at the interface to form single-channel conductive filaments.
  • the morphology and on-off positions of the single-channel conductive filaments are relative fixed, so the consistency problem of memristive devices can be solved.
  • the present invention focuses on the shaping and positioning of the conductive filaments of the memristor. By preparing a single-channel memristor, the purpose of locating the breaking and forming positions of the conductive filaments and shaping the morphology of the conductive filaments is achieved. The preparation provides important theoretical guidance and technical support.
  • a single-channel memristor which is characterized by comprising a substrate, a functional layer on the substrate, and two electrodes connected to the functional layer;
  • the functional layer is a stack structure formed by stacking a first functional layer (1) and a second functional layer (2), and is located between the two electrodes;
  • the electrode is in contact with the first functional layer (1) or the second functional layer (2) immediately adjacent to the substrate, but not in contact with the substrate;
  • the first memristive material used in the first functional layer (1) and the second memristive material used in the second functional layer (2) are both internally defect-free crystalline materials, and both have crystalline materials.
  • Lattice mismatch, and the lattice mismatch degree is not less than 5%; thus, based on the action of voltage, conductive filaments will be formed on the interface of the first functional layer (1) and the second functional layer (2) , and the conductive wire is only located at the interface of the first functional layer (1) and the second functional layer (2), so as to realize the single-channel memristive function.
  • the memristive materials used in the first functional layer (1) and the second functional layer (2) are HfO 2 , TiO 2 , Al 2 O 3 , SiO 2 , ZrO 2 , Two different materials in Ta2O5 ;
  • Both the first functional layer (1) and the second functional layer (2) are formed by deposition through an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • the thickness of any one of the first functional layers (1) and any one of the second functional layers (2) is greater than 1 nm.
  • the total number of layers of the first functional layer (1) and the second functional layer (2) is 2 to 11 layers.
  • the electrode material used for the electrode is an inert electrode material, preferably selected from Pt, TiN, TaN, TiW, Au, and W.
  • the projections of the two electrodes on the plane where the substrate surface is located are separated by a distance of 1 nm to 500 nm.
  • the present invention provides the above-mentioned method for preparing a single-channel memristor, which is characterized in that a first memristive material and a second memristive material are alternately deposited on a substrate to form a first functional layer A stacked functional layer stacked with the second functional layer; then, through an etching process, an electrode hole is etched on the stacked functional layer, and the electrode hole is as deep as the first functional layer or the second functional layer adjacent to the substrate, However, the first functional layer or the second functional layer immediately adjacent to the substrate is not etched; then electrode material is deposited in the electrode hole, thereby obtaining a single-channel memristor.
  • the present invention compared with the prior art, using the first memristive material and the second memristive material with a lattice mismatch degree of not less than 5%, due to the lattice mismatch, the The electric field drives few vacancies at the interface to form single-channel conductive filaments on the interface, which reduces the randomness of the formation of conductive filaments, and realizes the shape of the conductive filaments and the positioning of on-off positions (the specific thickness of the interface, Affected by various factors such as material type and preparation process, there is no fixed value, generally around a few nanometers).
  • the lateral structure is adopted, which reduces the difficulty of device preparation.
  • the device prepared in the present invention can realize the regulation of multi-layer interface conductive filaments (this is because multi-layer stacking will generate multiple interfaces, and multiple interfaces can control multiple interfaces) Conductive filaments) to realize step-type regulation of resistance state.
  • the single-channel memristor in the present invention is based on the conductive filament principle of the memristor, adopts a planar device, and uses two alternately deposited memristive materials with a near-perfect lattice with very few vacancies and dangling bonds at the interface. Defects form conductive filaments driven by an electric field.
  • the present invention can achieve the following beneficial effects:
  • the present invention drives few vacancies at the interface to form conductive filaments through an electric field to form a single-channel conductive filament, thereby reducing the randomness of the conductive filaments and realizing the shape of the conductive filaments and the change of the on-off position. Positioning, and then achieve the consistency improvement of memristive devices.
  • the resistive switching device prepared by the present invention has relatively high high and low resistance states and low power consumption.
  • the present invention adopts a horizontal structure, which greatly reduces the complexity of the preparation process compared with the vertical device, does not need to consider the contact problem of the multi-layer interface, and is beneficial to the large-scale integration of the device.
  • the device prepared by the present invention can realize the on-off of the conductive filaments at the multi-layer interface through electric field regulation, thereby realizing the step regulation of the resistance state.
  • the shaping and positioning of the conductive filaments needs to realize the positioning of the formation and breakage positions of the conductive filaments and the shaping of the conductive filaments.
  • the idea chosen by most researchers is to guide the formation of the conductive paths at a certain position to reduce randomness, but the present invention
  • the idea is to control the conduction channel to form a single channel, which essentially reduces the randomness of the conduction path.
  • the present invention proposes three innovations, one is to confine the conductive filaments in a plane to reduce the randomness of one dimension; That is, except near the interface, there are no defects inside the material; it can preferably be realized by ALD process) so that the oxygen vacancies inside the single-layer memristive material are very few, and it is difficult to form conductive filaments; the third is to use two kinds of lattice mismatch
  • the interface of the memristive material serves as the formation site of the conductive path.
  • the conductive channel formed is a single channel. Compared with multiple conductive channels, the randomness of a single channel is greatly reduced, so the shaping and positioning of the conductive filaments can be achieved.
  • the memristive material used may preferably be a very common material in the preparation of memristors, as long as the degree of lattice mismatch between them is not less than 5%; and through the design of multi-layer stacking, it is possible to The modulation of multi-resistance states is realized.
  • the etching and forming of the electrode hole is also very important. When etching, it must be ensured that the lowermost functional layer cannot be etched, and the interface between the functional layer and the substrate cannot be introduced.
  • the present invention also preferably controls the electrode lateral spacing (that is, the distance of the projection of the electrodes on the plane of the substrate surface) to be 1 nm to 500 nm, so as to facilitate the normal process of device initialization (this is because there are few vacancies at the interface, and the electrode lateral spacing is If it is too large, it will easily lead to a very high initial resistance, so that the device cannot be initialized; of course, if the electrode lateral spacing is too small, it will also impose strict requirements on the device fabrication process and affect the device yield).
  • the present invention focuses on the shaping and positioning of the conductive filaments of the memristor.
  • the purpose of locating the breaking and forming positions of the conductive filaments and shaping the morphology of the conductive filaments can be achieved.
  • the preparation of the resistor provides important theoretical guidance and technical support.
  • the present invention adopts a very simple structure compatible with the CMOS process, so that single-channel conductive filaments are generated inside the device, thereby reducing the randomness of on-off and improving the consistency.
  • FIG. 1 is a schematic cross-sectional view of a single-channel memristor unit provided in Example 1 of the present invention.
  • Example 2 is the memristor characteristic curve of the single-channel memristor unit provided in Example 1 of the present invention (during detection, the test probes are tied to the left and right electrodes, and the conductive paths are directly limited by the interface of each functional layer in the device).
  • FIG. 3 is a schematic diagram of the resistance switching mechanism of the single-channel memristor unit provided in Example 1 of the present invention.
  • 1 is the first functional layer (ie, the first functional layer), 2 is the second functional layer (ie, the second functional layer), and 3 is the electrode.
  • the single-channel memristor in the present invention in general, as shown in FIG. 1, includes electrodes 3 and stacked functional layers (ie, stacked first functional layers 1, second functional layers 2), and the functional layers are stacked on the substrate and sandwiched between two electrodes.
  • the functional layer is formed by alternately stacking two memristive materials with near-perfect lattices and mismatched interfaces (the first functional layer 1 and the second functional layer 2 have almost no defects inside, and the defects are concentrated at the mismatched interface, so that the Oxygen vacancies are generated at the interface), the electrode 3 is deposited in the etching hole of the functional layer, and the lower end contacts the lowermost functional layer.
  • two functional layers can be deposited alternately on the substrate, electrodes are deposited in the etching holes of the functional layers, and the bottom of the electrodes is embedded in the bottom functional layer.
  • Embodiment 1 A single-channel memristor and its preparation method
  • the present invention adopts a lateral device structure, and uses an electric field to drive the vacancies of the memristive material interface to form conductive filaments, and the conductive path is limited to the interface of the memristive material to achieve the effect of a single-channel memristor. Specific instructions.
  • the memristor includes electrodes 3 and stacked functional layers (ie, stacked functional layers 1 and 2).
  • the layers are stacked on a substrate and sandwiched between two electrodes.
  • the functional layer is formed by alternately stacking two types of memristive materials with mismatched interfaces.
  • the electrodes are deposited in the etched holes of the functional layer.
  • the bottom of the electrode is embedded in the bottommost functional layer.
  • the left and right electrodes and the functional layer sandwiched in the middle form a sandwich. structure.
  • the functional layer is composed of a stack of two interface-mismatched, near-perfect lattice memristive materials selected from two different materials: HfO 2 , TiO 2 , Al 2 O 3 , SiO 2 , ZrO 2 , and Ta 2 O 5 . s material. More specifically, in this embodiment, HfO 2 and Al 2 O 3 are used; the thickness of the single-layer functional layer is greater than 1 nm, and the number of stacked layers is 2 to 11 layers; more specifically, in this embodiment, the single-layer functional layer is The layer thickness was 5 nm, and the number of stacked layers was 2.
  • the electrode material adopts an inert electrode, which is selected from Pt, TiN, TaN, TiW, Au, and W.
  • the lateral distance between the electrodes is 1 nm to 500 nm. More specifically, in this embodiment, the lateral distance between the electrodes is selected as 100 nm.
  • the near-perfect lattice memristive materials HfO 2 and Al 2 O 3 have very few oxygen vacancies, but the interface mismatch causes defects such as a relatively small amount of vacancies and dangling bonds near the interface during the deposition process, and the inert electrode does not participate in conduction.
  • the vacancies at the interface move directionally and connect the conductive filaments formed.
  • the conductive filaments formed are Single-channel, compared with multiple conductive filaments in common memristors, the morphology and on-off position of single-channel conductive filaments are relatively fixed, which improves consistency; by adjusting the voltage applied on the electrodes, multiple The control of the on-off of the conductive wire at the layer interface realizes the step control of the resistance value.
  • a preparation method of a single-channel memristor comprises: alternately depositing functional layers on a substrate, pattern transfer, etching of the functional layers, and electrode preparation.
  • the substrate is Si/SiO 2
  • HfO 2 is deposited on the surface of SiO 2
  • Al 2 O 3 is deposited on the surface
  • electrode Pt is deposited in the etching hole of the functional layer, and the bottom of the electrode is embedded with the bottommost HfO 2 .
  • Atomic layer deposition is used to prepare a functional layer 1 on the cleaned substrate.
  • the functional layer 1 is HfO 2 with a thickness of 5 nm.
  • the deposition temperature of the Hf source is 80 degrees Celsius
  • the temperature of the reaction chamber is 300 degrees
  • the flow rate of nitrogen gas is 0.5sccm
  • the reaction chamber pressure is 100mTorr
  • the background vacuum is 10 -4 Pa.
  • Atomic layer deposition is used to prepare a functional layer 2 on the functional layer 1.
  • the functional layer 2 is specifically Al 2 O 3 with a thickness of 5 nm.
  • the deposition Al source temperature is normal temperature
  • the reaction chamber temperature is 250 degrees Celsius
  • the nitrogen flow rate is 0.5 sccm
  • the reaction chamber pressure is 100 mTorr
  • the background vacuum is 10 -4 Pa.
  • the electrode area was exposed on the sample on which the second functional layer was grown.
  • the size of the electrode was 30 ⁇ m ⁇ 30 ⁇ m, and the lateral distance between the left and right electrodes of the device was 100 nm; Baking, exposure, development and other steps.
  • RIE process a reserved pattern is etched on the sample after the EBL process, specifically: under the background vacuum of 7 ⁇ 10 -4 Pa, Ar gas is used as the etching gas, the power is 150w, and the etching time is 5min.
  • the upper electrode is sputtered, and the electrode is specifically Pt, and the thickness is 50 nm. 5 ⁇ 10 -5 Pa, the working pressure is 0.5Pa, the DC sputtering power is 35w, and the sputtering time is 350s.
  • the memristive characteristic curve of the prepared device is tested, and the result is shown in Figure 2, from which it can be seen that the Pt(50nm)/Al 2 O 3 (5nm)/HfO 2 (5nm)/Pt(50nm) device can achieve
  • the resistive switching function proves that a conductive path can be formed at the interface, and the power consumption of the device is very low due to the relatively high resistance state of the device.
  • each layer can be flexibly adjusted.
  • the memristive material used to construct the functional layer as long as the degree of lattice mismatch is not less than 5%; for example, in addition to the Si/SiO 2 substrate, other known substrates in the prior art can also be used; , in addition to the ALD process, other process methods can also be used to realize the preparation of the memristive material crystals in the first functional layer 1 and the second functional layer 2, such as PLD and other methods.

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Abstract

一种单通道忆阻器及其制备方法，单通道忆阻器包括由第一功能层(1)和第二功能层(2)堆叠形成的功能层；其中，第一功能层(1)所采用的第一忆阻材料与第二功能层(2)所采用的第二忆阻材料之间存在晶格失配，且晶格失配度不低于5％；由此基于电压作用，在第一功能层(1)和第二功能层(2)的界面上将能够形成导电丝，从而实现单通道忆阻功能。设置第一功能层(1)和第二功能层(2)，利用界面不匹配的、接近完美晶格的忆阻材料界面处形成的空位、悬挂键等缺陷，构建导电细丝，从而将导电细丝限制在界面处，形成单通道的导电细丝，单通道的导电丝的形貌和通断位置相对固定，因此可以解决忆阻器件的一致性问题。

Description

一种单通道忆阻器及其制备方法 【技术领域】
本发明属于微电子器件技术领域，更具体地，涉及一种单通道忆阻器及其制备方法。
【背景技术】
信息时代数据密集型、计算密集型产业的兴起，伴随着近年来的云端服务的普及浪潮，对数据的运算效率和存储的速度与密度提出更高要求。基于非易失性阻变的忆阻器是最受期待下一代存储器，电导多值可调性将在神经形态计算、滤波、逻辑和存算一体器件应用中大放异彩。对于忆阻器来说，阻碍其商业化进展的最重要因素是其机理的复杂性和性能的不稳定。忆阻器的阻变机理按目前研究，主要分为导电丝型机理、热化学机制和纯电子效应，其中导电细丝机制是适用范围最广、认可最为广泛的机制，通常认为金属原子或材料内部空位在电场作用下迁移组成导电细丝，而导电细丝的生成和断裂导致器件的阻态切换。导电细丝的断裂和生成位置随电场分布而变化，因此造成每次通断位置不固定，导电丝形貌也会随着循环的进行而发生变化，器件性能发生恶化。
目前有部分文献对单通道忆阻器进行研究，如Jeehwan Kim等人(详见Choi S,Tan S H,Li Z,et al.SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations[J].Nature materials,2018,17(4):335-340.)在Si上外延生长单晶SiGe层，利用单晶SiGe层材料的位错将金属导电细丝限制在一个一维通道中，避免导电细丝的随机生长，实现单通道忆阻器；但通常此类文献采取的方法比较复杂且不与CMOS工艺兼容。河南大学的魏凌等人(中国专利 申请《一种细丝机制的小面积电极阻变存储器及其制备方法》，CN109980083A)公开了一种小面积电极阻变存储器的制备方法，通过制备热击穿电压比较小的绝缘介质层，实现电极通路产生位置的控制，但测试过程中探针的尺寸在微米级别，热击穿通路的尺寸具有很大随机性，导电通路的随机性仍然比较大；中国科学院苏州纳米技术与纳米仿生研究所的杜刚等人(中国专利申请《阻变存储器及其制备方法》，CN106299108A)公开了一种阻变存储器及其制备方法，利用导电凸起阵列增加导电细丝在凸起处生长的概率，一定程度上降低导电通路形成和断裂的随机性，但导电通路在不断的循环操作过程中，仍然会发生形貌异变导致一致性变差，并且制备工艺相对复杂，容易引入杂质影响阻变性能。北京大学的蔡一茂等人(中国专利申请《有机阻变存储器及其制备方法》，CN103258958A)公开了一种有机阻变存储器及其制备方法，在两个聚对二甲苯层的界面处进行局部氧化修饰，从而形成有利于导电通道形成的薄弱区域，可以人为控制导电通路的位置与尺寸，但这种方法只针对于特定的有机材料。所以，研究一种调控尺寸与导电细丝尺寸接近、适用于常见忆阻材料、能实现高性能、低功耗的可控导电通路的忆阻器是非常迫切的需求。
【发明内容】
针对现有技术的以上缺陷或改进需求，本发明的目的在于提供一种单通道忆阻器及其制备方法，其中通过对忆阻器件结构的改进，利用第一功能层和第二功能层堆叠形成的堆叠功能层，由于第一功能层和第二功能层晶格不匹配(理想晶格间的晶格失配度不低于5％)，如此利用界面不匹配的、接近完美晶格的忆阻材料界面处形成的空位、悬挂键等缺陷，构建导电细丝，从而将导电细丝限制在界面处，形成单通道的导电细丝，单通道的导电丝的形貌和通断位置相对固定，因此可以解决忆阻器件的一致性问题。本发明聚焦于忆阻器导电细丝的定型定位，通过制备单通道忆阻器， 以达到定位导电细丝的断裂和形成位置、定型导电细丝形貌的目的，对高性能忆阻器的制备提供重要的理论指导和技术支撑。
为实现上述目的，按照本发明的一个方面，提供了一种单通道忆阻器，其特征在于，包括基底、位于所述基底上的功能层、以及与所述功能层相连的两个电极；其中，所述功能层是由第一功能层(1)和第二功能层(2)堆叠形成的堆叠结构，且位于所述两个电极之间；
对于任意一个电极，该电极均与紧邻所述基底的第一功能层(1)或第二功能层(2)相接触，但不与所述基底相接触；
所述第一功能层(1)所采用的第一忆阻材料，与所述第二功能层(2)所采用的第二忆阻材料，均为内部无缺陷的晶体材料，两者存在晶格失配，且晶格失配度不低于5％；由此基于电压作用，在所述第一功能层(1)和所述第二功能层(2)的界面上将能够形成导电丝，且导电丝仅位于所述第一功能层(1)和所述第二功能层(2)的界面处，从而实现单通道忆阻功能。
作为本发明的进一步优选，所述第一功能层(1)和所述第二功能层(2)所采用的忆阻材料为HfO 2、TiO 2、Al 2O 3、SiO 2、ZrO 2、Ta 2O 5中的两种不同的材料；
所述第一功能层(1)和所述第二功能层(2)均是通过原子层沉积(ALD)工艺沉积形成的。
作为本发明的进一步优选，所述功能层中，任意一个第一功能层(1)和任意一个第二功能层(2)的厚度均大于1nm。
作为本发明的进一步优选，所述功能层中，所述第一功能层(1)和所述第二功能层(2)的总层数为2～11层。
作为本发明的进一步优选，所述电极采用的电极材料为惰性电极材料，优选选自Pt、TiN、TaN、TiW、Au、W。
作为本发明的进一步优选，所述两个电极在基底表面所在平面上的投 影，两者相距1nm～500nm。
按照本发明的另一方面，本发明提供了上述单通道忆阻器的制备方法，其特征在于，是先在基底上交替沉积第一忆阻材料和第二忆阻材料以形成第一功能层和第二功能层堆叠的堆叠功能层；接着，通过刻蚀工艺，在所述堆叠功能层上刻蚀出电极孔，该电极孔深达与基底紧邻的第一功能层或第二功能层，但未刻穿与基底紧邻的第一功能层或第二功能层；然后在所述电极孔内沉积电极材料，从而得到单通道忆阻器。
通过本发明所构思的以上技术方案，与现有技术相比，利用晶格失配度不低于5％的第一忆阻材料和第二忆阻材料，由于晶格失配，能够在它们的界面上通过电场驱使界面处很少的空位形成单通道导电细丝，降低了导电细丝形成的随机性，实现了导电细丝形貌的定型和通断位置的定位(界面的具体厚度，受材料种类、制备工艺各种因素的影响，没有固定值，一般在几个纳米左右)。其次，采用横向结构，降低了器件制备的难度，只需要在衬底表面沉积对应薄膜，进行刻蚀，最后沉积两个电极即可(两电极间的横向距离可预先设定，可进一步通过对应的图案化处理实现不同横向距离)；另外，本发明中制备的器件，可以实现多层界面导电细丝的调控(这是由于多层堆叠会产生多个界面，多个界面就可以调控多个导电细丝)，实现阻态的阶梯型调控。
在忆阻器的现有技术中，导电细丝形貌和通断位置相对随机的变化，导致了忆阻器阻变特性的循环恶化，通常的忆阻器内部往往存在多根导电细丝，大大提高了通断随机性的概率，在多次操作之后，往往容易出现阻态和操作电压的漂移。本发明中的单通道忆阻器，基于忆阻器的导电细丝原理，采用平面器件，使用两种交替沉积的、接近完美晶格的忆阻材料界面处含量极少的空位、悬挂键等缺陷，在电场驱使下形成导电细丝。由于界面处的空位稀少且导电细丝局限于界面处，因而可以形成单通道，相比常见的导电细丝机制的忆阻器，单通道的导电细丝通断位置、形貌相对固 定，因而大大降低忆阻器件的一致性问题；极少的空位形成的薄弱导电细丝，器件的功耗大大降低；通过电场调制，可以实现多个界面的导电细丝通断控制，进而可以实现阶梯的阻态调制。
具体来说，本发明能够取得以下有益效果：
(1)本发明通过电场驱使界面处的很少的空位形成导电细丝，形成单通道导电细丝，因而可以降低导电细丝的随机性，实现导电细丝形貌的定型和通断位置的定位，进而实现忆阻器件的一致性提升。
(2)本发明所制备阻变器件具有相对较高的高低阻态，功耗很低。
(3)本发明采用横向结构，相对纵向器件，大大降低了制备工艺的复杂性，无需考虑多层界面的接触问题，有利于器件的大规模集成。
(4)本发明制备器件可以通过电场调控实现多层界面的导电细丝通断，进而实现阻态的阶梯调控。
导电细丝的定型定位需要实现导电细丝形成和断裂位置的定位和导电细丝形貌的定型，大部分研究者选择的思路是引导导电通路在某位置的形成来降低随机性，但本发明的思路在于控制导电通道形成单通道，从本质上降低导电通路的随机性。为了实现上述目的，本发明提出三点创新，一是将导电细丝局限在平面内，降低一个维度的随机性；二是采用的忆阻材料均为接近完美晶格的晶态忆阻材料(即，除界面附近外，材料内部无缺陷；可优选通过ALD工艺实现)这样在单层忆阻材料内部的氧空位非常少，很难形成导电细丝；三是采用两种晶格失配的忆阻材料的界面作为导电通路的形成位置。基于上述三点创新，在横向电场的作用下，相比于单层忆阻材料的内部，在晶格失配的界面处更容易生成导电通路，并且该导电通路只能局限于平面内，降低一个维度的随机性，由于界面处的空位非常少，形成的导电通道为单通道，而单通道相比多根导电通路，随机性大大下降，因而可以做到导电细丝的定型和定位。在本发明中，采用的忆阻材料可优选是忆阻器制备中非常常见的材料，只要它们之间的晶格失配度不低于5％ 即可；并且通过多层堆叠的设计，可以实现多阻态的调制。
另外，在本发明中，电极孔的刻蚀成形也是非常重要的，刻蚀时要保证不能刻穿最下层的功能层，确保不能引入功能层与衬底之间的界面影响。本发明还优选将电极横向间距(即，电极在基底表面所在平面上的投影的距离)控制为1nm～500nm，以便于器件初始化的正常进行(这是因为界面处的空位很少，电极横向间距过大时，容易导致极高的初始电阻，从而使器件无法进行初始化；当然，电极横向间距过小也会对器件制备工艺提出严苛的要求，影响器件成品率)。
综上，本发明聚焦于忆阻器导电细丝的定型定位，通过制备单通道忆阻器，以达到定位导电细丝的断裂和形成位置、定型导电细丝形貌的目的，对高性能忆阻器的制备提供重要的理论指导和技术支撑。另外，本发明采用非常简单的、与CMOS工艺兼容的结构，使得器件内部生成单通道的导电细丝，进而降低通断随机性，实现一致性的提升。
【附图说明】
图1是本发明实例1所提供的单通道忆阻器单元的剖面示意图。
图2是本发明实例1所提供的单通道忆阻器单元的忆阻特性曲线(检测时，测试探针扎在左右电极上，直接通过器件中各功能层的界面来限制导电通路)。
图3是本发明实例1所提供的单通道忆阻器单元的阻变机理示意图。
图1中各附图标记的含义如下：1为第一功能层(即，功能层一)，2为第二功能层(即，功能层二)，3为电极。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体 实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
本发明中的单通道忆阻器，总的来说，如图1所示，包括电极3和堆叠的功能层(即，堆叠的第一功能层1、第二功能层2)，功能层堆叠在基片上，并夹在两个电极之间。功能层由两种接近完美晶格、界面不匹配的忆阻材料交替堆叠而成(第一功能层1和第二功能层2的内部几乎没有缺陷，缺陷集中在失配的界面处，从而能够在界面处产生氧空位)，电极3是沉积在功能层的刻蚀孔内的，下端接触最下面的一层功能层。
在制备时，可以将两种功能层交替沉积在基片上，电极沉积在功能层的刻蚀孔内，电极底部嵌入最底层的功能层。
以下为具体实施例：
实施例1：一种单通道忆阻器及其制备方法
本发明采用横向器件结构，并使用电场驱使忆阻材料界面匮乏的空位形成导电细丝，将导电通路局限于忆阻材料的界面处，以达到单通道忆阻器的效果，以下结合附图进行具体说明。
图1为本发明实施例提供的一种单通道忆阻器的结构示意图，具体的，该忆阻器包括电极3和堆叠的功能层(即，堆叠的功能层1、功能层2)，功能层堆叠在基片上，并夹在两个电极之间。功能层由两种界面不匹配的忆阻材料交替堆叠而成，电极是沉积在功能层的刻蚀孔内的，电极底部嵌入最底层的功能层，左右电极和夹在中间的功能层形成三明治结构。
功能层由两种界面不匹配的、接近完美晶格的忆阻材料堆叠构成，材料选择为HfO 2、TiO 2、Al 2O 3、SiO 2、ZrO 2、Ta 2O 5中的两种不同的材料。更具体的，在本实施例中使用的是HfO 2和Al 2O 3；单层功能层厚度大于1nm，堆叠层数为2～11层；更具体的，在本实施例中，单层功能层厚度为5nm，堆叠层数为2层。电极材料采用惰性电极，选自Pt、TiN、TaN、TiW、Au、 W。更具体的，本实施例中选用Pt。电极之间的横向距离(即，针对电极在衬底表面所在平面上的投影，投影边缘的最短间距)为1nm～500nm。更具体的，在本实施例中，电极之间的横向距离选用100nm。
接近完美晶格的忆阻材料HfO 2和Al 2O 3中的氧空位非常少，但界面不匹配造成沉积过程中，界面附近存在比较少量的空位和悬挂键等缺陷，且惰性电极不参与导电细丝的形成，在电场驱使下，界面处的空位定向移动并连接行成的导电细丝，由于空位的数量比较稀少，并且导电细丝只能生成在界面附近，因此形成的导电细丝为单通道，相比常见忆阻器中的多根导电细丝，单通道导电细丝的形貌和通断位置相对固定，实现了一致性的提升；通过调节电极上施加的电压，可以实现多层界面导电丝通断的调控，实现阻值的阶梯调控。
一种单通道忆阻器的制备方法，所述方法包括：在衬底上交替沉积功能层、图形转移、功能层刻蚀以及电极制备。以Pt(50nm)/Al 2O 3(5nm)/HfO 2(5nm)/Pt(50nm)器件为例，衬底为Si/SiO 2，HfO 2沉积于SiO 2的表面，Al 2O 3沉积于HfO 2的表面，电极Pt沉积在功能层的刻蚀孔内，电极底部嵌入最底层的HfO 2。
以下来具体阐释所述单通道忆阻器的制备方法：
(1)衬底清洗：
将长有绝缘层SiO 2的Si衬底浸没在实验用分析纯丙酮中，放入功率为60w的超声清洗机中，超声10分钟；再将该样品浸入实验用分析纯乙醇中，超声10分钟；再将该样品浸入去离子水中，超声3分钟，氮气枪吹干备用。
(2)功能层一制备：
使用原子层沉积ALD，在清洗过的衬底上制备功能层一，所述功能层一具体为HfO 2，厚度为5nm，沉积Hf源温度为80摄氏度，反应腔室温度为300度，氮气流速0.5sccm，反应腔压强100mTorr，背景真空度为10 -4Pa。
(3)功能层二制备：
使用原子层沉积ALD，在功能层一上制备功能层二，所述功能层二具体为Al 2O 3，厚度为5nm，沉积Al源温度为常温，反应腔室温度为250摄氏度，氮气流速0.5sccm，反应腔压强100mTorr，背景真空度为10 -4Pa。
(4)图形转移：
使用电子束曝光EBL工艺，在生长了功能层二的样品上曝光出电极区域，电极的尺寸为30μm×30μm，器件的左右电极之间的横向距离为100nm；EBL的具体工艺包括匀胶、前烘、曝光、显影等步骤。
(5)刻蚀：
使用RIE工艺，在EBL工艺后的样品上，刻蚀出预留图案，具体为：在7×10 -4Pa的背景真空下，以Ar气为刻蚀气体，功率为150w，刻蚀时间为5min。
(6)电极制备
使用磁控溅射工艺，在刻蚀工艺后得到的样品上，溅射上电极，所述电极具体为Pt，厚度为50nm，磁控溅射的工艺条件为：Ar气氛围下，背景真空为5×10 -5Pa，工作压强为0.5Pa，直流溅射功率为35w，溅射时间为350s。
(7)剥离
将电极制备工艺后的样品，放入实验用分析纯丙酮中，振荡至图形完全清晰，依次用分析纯乙醇和去离子水清洗，氮气枪吹干，至此完全得到所述Pt(50nm)/Al 2O 3(5nm)/HfO 2(5nm)/Pt(50nm)器件。
对制得的器件检测其忆阻特性曲线，结果如图2所示，从中可见，所述Pt(50nm)/Al 2O 3(5nm)/HfO 2(5nm)/Pt(50nm)器件可以实现阻变功能，证明了界面处可以形成导电通路，并且由于器件的阻态相对较高，器件的功耗非常低。
上述实施例仅为示例，材料的具体种类及各个层厚度均可以灵活调整。例如，用于构建功能层的忆阻材料，只要晶格失配度不低于5％即可；又例 如，除了Si/SiO 2基底外，还可以采用其他现有技术已知的基底；另外，除了ALD工艺外，也可以采用其他工艺方法实现第一功能层1、第二功能层2中忆阻材料晶体的制备，例如PLD等方法。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种单通道忆阻器，其特征在于，包括基底、位于所述基底上的功能层、以及与所述功能层相连的两个电极；其中，所述功能层是由第一功能层(1)和第二功能层(2)堆叠形成的堆叠结构，且位于所述两个电极之间；
    对于任意一个电极，该电极均与紧邻所述基底的第一功能层(1)或第二功能层(2)相接触，但不与所述基底相接触；
    所述第一功能层(1)所采用的第一忆阻材料，与所述第二功能层(2)所采用的第二忆阻材料，均为内部无缺陷的晶体材料，两者存在晶格失配，且晶格失配度不低于5％；由此基于电压作用，在所述第一功能层(1)和所述第二功能层(2)的界面上将能够形成导电丝，且导电丝仅位于所述第一功能层(1)和所述第二功能层(2)的界面处，从而实现单通道忆阻功能。
  2. 如权利要求1所述单通道忆阻器，其特征在于，所述第一功能层(1)和所述第二功能层(2)所采用的忆阻材料为HfO 2、TiO 2、Al 2O 3、SiO 2、ZrO 2、Ta 2O 5中的两种不同的材料；
    所述第一功能层(1)和所述第二功能层(2)均是通过原子层沉积(ALD)工艺沉积形成的。
  3. 如权利要求1所述单通道忆阻器，其特征在于，所述功能层中，任意一个第一功能层(1)和任意一个第二功能层(2)的厚度均大于1nm。
  4. 如权利要求1所述单通道忆阻器，其特征在于，所述功能层中，所述第一功能层(1)和所述第二功能层(2)的总层数为2～11层。
  5. 如权利要求1所述单通道忆阻器，其特征在于，所述电极采用的电极材料为惰性电极材料，优选选自Pt、TiN、TaN、TiW、Au、W。
  6. 如权利要求1所述单通道忆阻器，其特征在于，所述两个电极在基 底表面所在平面上的投影，两者相距1nm～500nm。
  7. 如权利要求1－6任意一项所述单通道忆阻器的制备方法，其特征在于，是先在基底上交替沉积第一忆阻材料和第二忆阻材料以形成第一功能层和第二功能层堆叠的堆叠功能层；接着，通过刻蚀工艺，在所述堆叠功能层上刻蚀出电极孔，该电极孔深达与基底紧邻的第一功能层或第二功能层，但未刻穿与基底紧邻的第一功能层或第二功能层；然后在所述电极孔内沉积电极材料，从而得到单通道忆阻器。
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