WO2022095604A1 - 一种基于界面掺杂的忆阻器及其制备方法 - Google Patents

一种基于界面掺杂的忆阻器及其制备方法 Download PDF

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WO2022095604A1
WO2022095604A1 PCT/CN2021/118128 CN2021118128W WO2022095604A1 WO 2022095604 A1 WO2022095604 A1 WO 2022095604A1 CN 2021118128 W CN2021118128 W CN 2021118128W WO 2022095604 A1 WO2022095604 A1 WO 2022095604A1
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interface
memristor
doping
functional layer
layer
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French (fr)
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程晓敏
朱云来
缪向水
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention belongs to the technical field of integrated microelectronic devices, and relates to a memristor based on interface doping and a preparation method thereof.
  • memristor As one of the strong competitors in the next generation of new memory, memristor has attracted extensive attention due to its excellent performance, such as low power consumption, high storage density, simple structure, high speed, multi-value and multi-dimensional storage and so on.
  • the application prospect of memristor is quite broad, and it is mainly used in resistive memory, artificial neural network simulation and new programmable logic circuit.
  • the resistance transition mechanism of memristors based on transition metal oxides is mainly based on the redistribution of defects in the film caused by the migration of oxygen ions, forming conductive filaments based on oxygen vacancies. High and low resistance change.
  • Oxygen vacancy conductive filament memristor structure usually has a certain asymmetry, which generally includes a relatively active metal electrode, such as Ti, Al, etc., and a less active inert electrode, such as Pt, Au, etc., the device performance It exhibits bipolar resistance transition characteristics.
  • C to C cycle to cycle
  • D to D switching characteristics between cells
  • the method to improve the performance of the memristor is mainly to do a small amount of uniform doping on the entire oxide functional layer, and introduce defects in the functional layer to generate a local electric field, which is conducive to the directional growth of oxygen vacancies, and has a negative impact on the C to C consistency of the device.
  • the occupancy of impurity atoms in the entire functional layer is very random during the doping process of such methods, and the consistency of performance D to D between unit devices cannot be effectively guaranteed.
  • the purpose of the present invention is to provide a memristor based on interface doping and a preparation method thereof.
  • a memristor based on interface doping and a preparation method thereof Different from conventional memristors, by doping a selected suitable interface, On the one hand, the growth of the conductive wire can be promoted, and on the other hand, the connection and disconnection of the conductive wire can be stabilized, and the consistency and stability of the device can be greatly improved.
  • One aspect of the present invention provides an interface-doped memristor, the memristor adopts a sandwich-like structure, that is, a lower electrode-functional layer-upper electrode; the functional layer is a metal oxide, and the upper electrode and the functional layer are between The interface is uniformly doped.
  • the selected functional layer may be a metal oxide, wherein the metal oxide includes an oxide of Hf, an oxide of Zr, an oxide of Al, an oxide of Ta or an oxide of Ti.
  • a relatively active electrode is selected for the lower electrode, which includes Ta, Hf, Al, Ti, and TiN, but the metal in the functional layer metal oxide needs to be inconsistent.
  • the upper electrode is an inert electrode including Pt, Pd or Au.
  • the elements doped at the interface can be non-metal elements N, F and H, and can also be metal elements Al, Zr, Ta, Hf, Ni, Fe, Ti, Sc, Ru and Au, but the metal electrodes and Doping elements need to be inconsistent.
  • the interface doping ratio is 2% to 15%.
  • the thickness of the lower electrode is 50 nm to 200 nm
  • the thickness of the functional layer is 5 nm to 50 nm
  • the thickness of the upper electrode is 50 nm to 200 nm.
  • the present invention proposes a method of doping at a certain interface of the memristor instead of the entire dielectric layer to improve the uniformity and reliability of the device.
  • the interfacial doping creates more defects at the interface, which induces the growth of oxygen vacancies in this direction.
  • the impurity atoms in the interface doped device are only distributed in the interface, and the randomness of its occupancy is greatly reduced.
  • the interface between the dielectric layer and the inert electrode is selected for doping.
  • the conductive wire When a bias voltage is applied, the conductive wire will first grow at the doping interface, and then grow towards the active electrode, which plays a role in the growth of the conductive wire. The role of guiding; when reverse bias is applied, the conductive wire breaks first in the undoped area. When the conductive wire is formed, the conductive wire formed on the doped interface will be thicker. When the conductive wire is broken, the conductive wire at the undoped interface will be preferentially broken, thereby stabilizing the conductive wire and effectively improving the device. C to C consistency and reliability.
  • the method has the advantages of simple process, easy preparation, and greatly improved device performance, which further promotes the commercialization of memristors.
  • a method for preparing an interface-doped memristor is provided, and the specific steps of the preparation method are as follows:
  • metal oxides are grown by atomic layer deposition, magnetron sputtering, molecular beam epitaxy, pulsed laser deposition, thermal evaporation or electrochemical growth, and after growth is completed A layer of doped metal oxide is grown to achieve doping at the interface between the functional layer and the inert electrode;
  • An inert upper electrode is prepared on the functional layer, thereby obtaining a high-performance memristor based on interfacial doped oxide.
  • the present invention can achieve the following beneficial effects:
  • the process used in the memristor based on interface doping control of the present invention is simple and convenient, and compatible with the existing semiconductor preparation technology; compared with the performance of the existing memristor, there are three obvious advantages: (1 ) Doping is introduced at the interface. Compared with the doping of the entire functional layer, the impurity atoms in the interface-doped device are only distributed in the interface, and the randomness of its occupancy is greatly reduced; (2) The process of Set will cause the interface layer to produce more There are many oxygen vacancies, and the conductive wire will be thicker in this layer. Doping is introduced at the interface between the inert metal and the functional layer. When a bias voltage is applied, the conductive wire will first grow at the doping interface, and then grow towards the active electrode.
  • the growth of the conductive wire plays a role of directional guidance; (3) when a reverse bias is applied (Reset process), the conductive wire breaks first in the undoped area, because the oxygen vacancy formation energy of the undoped dielectric layer is higher than that of the doped dielectric layer.
  • the formation energy of oxygen vacancies in the doped dielectric layer is large, so the high resistance state stability of the device can be increased, the randomness of the formation and breakage of the conductive wire is greatly reduced, and the consistency of the switching characteristics of the device is improved.
  • 1 is a schematic structural diagram of an existing conventional capacitive-like memristor
  • FIG. 2 is a schematic structural diagram of the memristor after interface doping according to the present invention.
  • Figure 3(a) is the XPS diagram of O 1s of the existing TiN/HfO 2 /Pt memristor
  • Fig. 3 (b) is the XPS diagram of O 1s of TiN/HfO 2 /HfO 2 :Al/Pt memristor according to the embodiment of the present invention
  • Figure 4(a) is the IV curve of the existing TiN/HfO 2 /Pt memristor under 100 consecutive voltage sweeps;
  • Fig. 4 (b) is the IV curve diagram of TiN/HfO 2 /HfO 2 :Al/Pt memristor under 100 consecutive voltage sweeps according to the embodiment of the present invention
  • Figure 5(a) is a statistical diagram of the frequency accumulation distribution of the high-resistance state and the low-resistance state of the existing TiN/HfO 2 /Pt memristor;
  • Fig. 5 (b) is the frequency accumulation distribution statistics diagram of the high resistance state and the low resistance state of the TiN/HfO 2 /HfO 2 :Al/Pt memristor according to the embodiment of the present invention
  • Figure 6(a) is a statistical diagram of the frequency cumulative distribution of the Set voltage and the Reset voltage of the existing TiN/HfO 2 /Pt memristor;
  • Fig. 6 (b) is the frequency accumulation distribution statistics diagram of the Set voltage and the Reset voltage of the TiN/HfO 2 /HfO 2 :Al/Pt memristor according to the embodiment of the present invention
  • Figure 7(a) is the pulse cycle performance test characteristics of the existing TiN/HfO 2 /Pt memristor
  • Fig. 7 (b) is the pulse cycle performance test characteristic of TiN/HfO 2 /HfO 2 :Al/Pt memristor according to the embodiment of the present invention.
  • Fig. 8 is the data retention characteristic of TiN/HfO 2 /HfO 2 :Al/Pt memristor at 85°C;
  • Substrate 2. Lower electrode, 3. Functional layer, 4. Upper electrode, 5. Doping layer.
  • the invention provides a memristor with interface doping, which adopts a sandwich-like structure, that is, a lower electrode 2-functional layer 3-upper electrode 4; the functional layer is a metal oxide, and the interface between the upper electrode and the functional layer is uniform Doping to form a doped layer 5 .
  • the selected functional layer may be a metal oxide, wherein the metal oxide includes an oxide of Hf, an oxide of Zr, an oxide of Al, an oxide of Ta, or an oxide of Ti.
  • a relatively active electrode is selected for the lower electrode, including Ta, Hf, Al, Ti, and TiN, but the metal in the metal oxide of the functional layer needs to be kept inconsistent.
  • the upper electrode is an inert electrode including Pt, Pd or Au.
  • the elements doped at the interface can be non-metallic elements N, F and H, and can also be elements among metal elements Al, Zr, Ta, Hf, Ni, Fe, Ti, Sc, Ru and Au, but the metal electrodes and Doping elements need to be inconsistent.
  • the interface doping ratio is 2% to 15%.
  • the thickness of the lower electrode is 50 nm ⁇ 200 nm
  • the thickness of the functional layer is 5 nm ⁇ 50 nm
  • the thickness of the upper electrode is 50 nm ⁇ 200 nm.
  • the present invention also provides a preparation method of the interface doped memristor, and the specific steps of the preparation method are as follows:
  • An inert upper electrode 4 is prepared on the functional layer 3, thereby obtaining a high-performance memristor based on interfacial doped oxide.
  • the memristor unit structure prepared by the prior art is a sandwich structure, the functional layer is selected from HfO 2 , the doping element is selected from Al, and the upper and lower electrodes are respectively selected from Pt and TiN.
  • the preparation method is as follows:
  • a silicon wafer with a crystal phase of (100) and a thickness of 500 ⁇ m was selected, and a 1 ⁇ m-thick SiO 2 thin film layer was thermally grown on its surface, which was the substrate 1 . Cut it into 1 ⁇ 1 cm pieces, take two pieces and put them in a beaker containing an appropriate amount of acetone, ultrasonically clean them for 15 minutes with a power of 40W, then take them out and put them in a beaker containing an appropriate amount of anhydrous ethanol, and again Ultrasonic cleaning was performed for 15 minutes, and finally, the organic matter on the surface of the sample was washed with deionized water, and dried with a nitrogen gun.
  • step (2) using ultraviolet lithography to prepare a pattern on the sample in step (1), wherein the photolithography process steps are: uniform glue, pre-baking, pre-exposure, post-baking, post-exploding, and developing;
  • Atomic layer deposition was used to grow a 120cycles HfO 2 layer with a thickness of about 8 nm on the sample of step (2); the ALD temperature was set to 250 °C, the Hf source was tetrakis (dimethylamino) hafnium (TDMAHF), and the Al source was used With trimethylauminum (TMA), the oxygen source is water.
  • ALD Atomic layer deposition
  • step (2) using the photolithography process of step (2) to perform overlay etching to prepare an upper electrode pattern, and the electrode size is 100 ⁇ m;
  • Magnetron sputtering is used to grow a Pt layer of 100 nm on the sample processed in step (5), and then a peeling process is performed on the sample, and the same as step (4), the upper electrode 4 can be obtained.
  • the memristor unit structure prepared in this experimental example is a sandwich structure, the functional layer is HfO 2 , the doping element is Al, and the upper and lower electrodes are Pt and TiN respectively.
  • the preparation method is as follows:
  • a silicon wafer with a crystal phase of (100) and a thickness of 500 ⁇ m was selected, and a 1 ⁇ m-thick SiO 2 thin film layer was thermally grown on its surface, which was the substrate 1 . Cut it into 1 ⁇ 1 cm pieces, take two pieces and put them in a beaker containing an appropriate amount of acetone, ultrasonically clean them for 15 minutes with a power of 40W, then take them out and put them in a beaker containing an appropriate amount of anhydrous ethanol, and again Ultrasonic cleaning was performed for 15 minutes, and finally, the organic matter on the surface of the sample was washed with deionized water, and dried with a nitrogen gun.
  • step (2) using ultraviolet lithography to prepare a pattern on the sample in step (1), wherein the photolithography process steps are: uniform glue, pre-baking, pre-exposure, post-baking, post-exploding, and developing;
  • Atomic layer deposition is used to grow the HfO 2 layer of 95 cycles on the sample in step (2), and then continue to grow the HfO 2 :Al layer of 25 cycles, wherein the doping concentration of Al is 4.3%, and the total The thickness is also about 8 nm, the ALD temperature is set to 250 °C, tetrakis (dimethylamino) hafnium (TDMAHF) is used as the Hf source, trimethylauminum (TMA) is used as the Al source, and water is used as the oxygen source.
  • TDMAHF tetrakis (dimethylamino) hafnium
  • TMA trimethylauminum
  • water is used as the oxygen source.
  • step (2) using the photolithography process of step (2) to perform overlay etching to prepare an upper electrode pattern, and the electrode size is 100 ⁇ m;
  • Magnetron sputtering is used to grow a Pt layer of 100 nm on the sample processed in step (5), and then a peeling process is performed on the sample, and the same as step (4), the upper electrode 4 can be obtained.
  • TiN/HfO 2 /HfO 2 :Al/Pt memristor unit is prepared on the sample after completing the above steps, as shown in FIG. 2 .
  • Figures 3(a) and 3(b) are the XPS measurements of the O 1s of the as-prepared HfO 2 and HfO 2 :Al, respectively, the peak corresponding to 531.70 eV is the oxygen vacancy in the film, Figure 3(b) The area of the peak corresponding to the oxygen vacancies is significantly higher than that in Fig. 3(a), indicating that the concentration of oxygen vacancies in the film increases after Al-doping; this is consistent with the introduction of doping at the interface described in the invention, which will lead to more oxygen vacancies at the interface. Consistent. The increase of the oxygen vacancy concentration at the interface will affect the formation and breakage of the conductive filaments in the device.
  • the conductive filaments will be thicker in this layer; when a bias voltage is applied, the conductive filaments will first grow at the doping interface, and then grow toward the active electrode. , which plays a role in directional guidance for the growth of conductive filaments.
  • the conductive wire breaks first in the undoped area. Since the formation energy of oxygen vacancies in the undoped dielectric layer is larger than that of the doped dielectric layer, the high resistance state of the device Relatively improved stability.
  • Fig. 4(a) and Fig. 4(b) are the IV diagrams of TiN/HfO 2 /Pt and TiN/HfO 2 /HfO 2 :Al/Pt memristors under 100 consecutive voltage sweeps, respectively, where the upper The electrode Pt is grounded, the lower electrode TiN is connected to the forward voltage, the voltage sweep is in the range of 2V to -2V, and the limit current is 1mA. It can be seen from the figure that the sweep curve in Figure 4(b) is compared with Figure 4(a) There is no obvious fluctuation in , indicating that the device after interface doping is more stable in DC voltage sweep;
  • Fig. 5(a) and Fig. 5(b) are the frequency cumulative distribution statistics of the high resistance state and the low resistance state of TiN/HfO 2 /Pt and TiN/HfO 2 /HfO 2 :Al/Pt memristor, respectively Figure, the high and low resistance values are extracted from Figure 4, where ⁇ / ⁇ is the resistance state change rate, ⁇ is the standard deviation of the resistance state, ⁇ is the average value of the resistance state, we can get the TiN/HfO 2 /Pt memristor The change rates ⁇ / ⁇ of the high and low resistance states are 106.5% and 12.8%, respectively, while the change rates ⁇ / ⁇ of the high and low resistance states of TiN/HfO 2 /HfO 2 :Al/Pt are 24.4% and 6.4%, respectively. It can be seen that , After interface doping, the consistency of high and low resistance states of the device is greatly improved;
  • Fig. 6(a) and Fig. 6(b) are the frequency accumulation distribution statistics of Set voltage and Reset voltage of TiN/HfO 2 /Pt and TiN/HfO 2 /HfO 2 :Al/Pt memristors, respectively, Both Set voltage and Reset voltage are extracted from Fig.
  • Figure 7(a) and Figure 7(b) are the pulse cycle performance test results of TiN/HfO 2 /Pt and TiN/HfO 2 /HfO 2 :Al/Pt memristors, respectively, TiN/HfO 2 /Pt
  • the pulse width of the Set pulse applied by the memristor is 90ns and the amplitude is 0.9V.
  • the pulse width of the Reset pulse is 200ns and the amplitude is -1.1V.
  • the TiN/HfO 2 /HfO 2 :Al/Pt memristor applied The pulse width of the Set pulse is 90ns and the amplitude is 0.9V, and the pulse width of the Reset pulse is 200ns and the amplitude is -1.2V. It can be seen from the figure that the TiN/HfO 2 /Pt memristor can maintain 10 5 cycles, but the high resistance state is very unstable, while the TiN/HfO 2 /HfO 2 :Al/Pt memristor can maintain 10 6 cycles cycle, and the high and low resistance states are very stable, with a higher cycle life;
  • Figure 8 shows the data retention characteristics of the TiN/HfO 2 /HfO 2 :Al/Pt memristor at 85°C.
  • the reading operation voltage in the high resistance state (low resistance state) is 0.1V. It can be seen from the figure It is found that the device can be maintained for 10 4 s at 85 degrees Celsius. According to the Arrhenius equation, it can be inferred that the high and low resistance values of the device can be maintained for more than 10 years.
  • the interfacial Al-doped TiN/HfO 2 /HfO 2 :Al/Pt memristor has obvious high and low resistance state consistency and operating voltage consistency
  • the device also has good cycle characteristics and retention characteristics, and the overall performance of the device has been greatly improved.
  • the basic principle is that after the interface of HfO 2 and Pt is doped with aluminum, the oxygen vacancies in the interface layer increase. During the Set operation, the conductive wire will be thicker in the HfO 2 : Al layer; when a forward bias is applied on the TiN electrode.
  • the conductive wire When pressed, the conductive wire grows on the HfO 2 : Al layer first, and then grows to the TiN layer, which plays a directional guiding role for the growth of the conductive wire.
  • a reverse bias voltage Reset process
  • the conductive wire is first broken in the HfO 2 region. Since the formation energy of oxygen vacancies in the HfO 2 layer is larger than that in the HfO 2 :Al layer, the thermal stability is relatively high. Better, the device has better high resistance state stability. Therefore, this example verifies that the performance of memristor devices can be effectively improved based on interfacial doping in this application.

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Abstract

本发明公开了一种基于界面掺杂的忆阻器及其制备方法，属于集成微电子器件技术领域。忆阻器包括上电极、功能层和下电极，功能层为金属氧化物，上电极和功能层之间的界面为均匀掺杂。本发明通过对忆阻器中关键的功能层和电极之间的界面进行改进，在惰性电极和功能层之间的界面进行均匀掺杂，会导致界面层产生更多的氧空位，导电丝在该层会比较粗壮，利于稳定导电丝生长；由于未掺杂的介质层氧空位形成能要比掺杂后的介质层氧空位形成能大，热稳定相对较好，因此可以提高器件的高阻态稳定性，使得导电丝形成和断裂的随机性大大减小，提高了忆阻器的开关稳定性和一致性。

Description

一种基于界面掺杂的忆阻器及其制备方法 【技术领域】
本发明属于集成微电子器件技术领域，是一种基于界面掺杂的忆阻器及其制备方法。
【背景技术】
忆阻器作为下一代新型存储器中有力竞争者之一，其优异的性能吸引了广泛的关注，如低功耗、高存储密度、结构简单、速度快、多值和多维存储等等。忆阻器的应用前景相当广泛，目前主要用于阻变存储器、人工神经网络模拟和新型可编程逻辑电路中。
其中，在众多的忆阻器介质材料中，二元金属氧化物的种类更多，在器件性能上相对优异，且制备工艺与半导体工艺兼容，因此引起了广泛的研究。基于过渡金属氧化物的忆阻器的电阻转变机理主要是基于氧离子的迁移导致的薄膜内部缺陷的再分布，形成了基于氧空位的导电丝，因此氧空位导电丝的通断控制着器件的高低阻转变。氧空位导电细丝忆阻器结构通常具有一定的非对称性，其一般包括一个比较活泼的金属电极，如Ti、Al等，和一个活性较低的惰性电极，如Pt、Au等，器件性能表现出双极性的电阻转变特性。由于氧空位导电丝的形成和断开具有很大的随机性，因此此类忆阻器的单元每次擦写(cycle to cycle，C to C)的开关一致性及单元之间的开关特性(device to device，D to D)一致性都较差，导致整个阵列或芯片的可靠性难以提高，阻碍了器件的进一步发展。一般情况下，对于忆阻器阵列或芯片而言，C to C的一致性是D to D一致性的基础，C to C一致性的优化是提高忆阻器芯片性能的关键。
目前，改善忆阻器性能的方法主要是对整层氧化物功能层进行微量均匀掺杂，在功能层中引入缺陷产生局域电场，有利于氧空位定向生长，对 器件的C to C一致性有一定的改善。然而，此类方法在掺杂过程中杂质原子在整个功能层中的占位具有很大的随机性，单元器件之间性能D to D的一致性仍不能得到有效保证。
【发明内容】
针对现有技术存在的问题和改进需要，本发明的目的在于提供一种基于界面掺杂的忆阻器及其制备方法，区别于常规忆阻器，通过对选定的合适界面进行掺杂，一方面可以促进导电丝的生长，另一方面又可以稳定导电丝的连通和断开，在器件的一致性、稳定性上可获得很大的提升。
本发明一方面提供了一种界面掺杂的忆阻器，所述忆阻器选用类三明治结构，即下电极-功能层-上电极；功能层为金属氧化物，上电极和功能层之间的界面为均匀掺杂。
优选地，所选功能层可为金属氧化物，其中金属氧化物包括Hf的氧化物、Zr的氧化物、Al的氧化物、Ta的氧化物或Ti的氧化物。
优选地，下电极选用较为活泼的电极，其中包括Ta、Hf、Al、Ti、TiN，但其与功能层金属氧化物中的金属需保持不一致。上电极为惰性电极，包括Pt、Pd或Au。
优选地，界面所掺杂元素可为非金属元素N、F和H，也可为金属元素Al、Zr、Ta、Hf、Ni、Fe、Ti、Sc、Ru和Au中元素，但是金属电极和掺杂元素需不一致。
优选地，界面掺杂比例为2％～15％。
优选地，下电极的厚度为50nm～200nm，所述功能层的厚度为5nm～50nm，上电极的厚度为50nm～200nm。
本发明提出在忆阻器的某个界面进行掺杂而不是整个介质层的方法提升器件的一致性和可靠性。相比于未掺杂忆阻器，由于界面掺杂会在界面处产生更多的缺陷，会定向诱导氧空位沿着该方向生长。相比于整个功能层掺杂，界面掺杂的器件中杂质原子只分布在界面中，其占位随机性大大 减小。此外，在本发明中，选择介质层和惰性电极之间的界面进行掺杂，当外加偏压时导电丝首先会在掺杂界面生长，然后向活性电极生长，对导电丝生长起到一个定向引导的作用；当外加反向偏压时，导电丝在未掺杂区域先断裂。在形成导电丝时，掺杂的界面上形成的导电丝会更加粗壮，在导电丝断裂时，会优先断裂未掺杂的界面处的导电丝，从而起到稳定导电丝的作用，有效提高器件的C to C一致性和可靠性。该方法工艺简单，制备容易，且器件性能获得很大的提升，对忆阻器商业化有进一步的推动作用。
按照本发明的另一方面，提供了一种界面掺杂的忆阻器的制备方法，该制备方法具体步骤如下：
(1)在衬底上制备活性下电极；
(2)制备功能层，并进行界面掺杂：利用原子层沉积法、磁控溅射法、分子束外延法、脉冲激光沉积法、热蒸发法或电化学生长金属氧化物，生长完后再生长一层掺杂的金属氧化物，从而实现在功能层和惰性电极界面掺杂；
(3)在所述功能层上制备惰性上电极，从而得到基于界面掺杂氧化物的高性能忆阻器。
综上所述，本发明能够取得以下有益效果：
本发明所述的基于界面掺杂调控的忆阻器所使用的工艺操作简单、方便，并且与现有半导体制备技术兼容；与现有忆阻器的性能相比有三点明显的优势：(1)界面引入掺杂，相比于整个功能层掺杂，界面掺杂的器件中杂质原子只分布在界面中，其占位随机性大大减小；(2)Set过程中会导致界面层产生更多的氧空位，导电丝在该层会比较粗壮，在惰性金属和功能层之间的界面引入掺杂，当外加偏压时导电丝首先会在掺杂界面生长，然后向活性电极生长，对导电丝生长起到一个定向引导的作用；(3)当外加反向偏压(Reset过程)时，导电丝在未掺杂区域先断裂，由于未掺杂的 介质层氧空位形成能要比掺杂后的介质层氧空位形成能大，因此可以增加器件的高阻态稳定性，导电丝形成和断裂的随机性大大减小，提高器件开关特性的一致性。
【附图说明】
图1是现有常规的类电容式忆阻器结构示意图；
图2是本发明所述的界面掺杂后的忆阻器结构示意图；
图3(a)是现有TiN/HfO 2/Pt忆阻器的O 1s的XPS图；
图3(b)是本发明实施例TiN/HfO 2/HfO 2:Al/Pt忆阻器的O 1s的XPS图；
图4(a)是现有TiN/HfO 2/Pt忆阻器100次连续电压扫描下的I-V曲线图；
图4(b)是本发明实施例TiN/HfO 2/HfO 2:Al/Pt忆阻器100次连续电压扫描下的I-V曲线图；
图5(a)是现有TiN/HfO 2/Pt忆阻器的高阻态和低阻态的频率累积分布统计图；
图5(b)是本发明实施例TiN/HfO 2/HfO 2:Al/Pt忆阻器的高阻态和低阻态的频率累积分布统计图；
图6(a)是现有TiN/HfO 2/Pt忆阻器的Set电压和Reset电压的频率累积分布统计图；
图6(b)是本发明实施例TiN/HfO 2/HfO 2:Al/Pt忆阻器的Set电压和Reset电压的频率累积分布统计图；
图7(a)是现有TiN/HfO 2/Pt忆阻器的脉冲循环性能测试特性；
图7(b)是本发明实施例TiN/HfO 2/HfO 2:Al/Pt忆阻器的脉冲循环性能测试特性；
图8是TiN/HfO 2/HfO 2:Al/Pt忆阻器在85℃下的数据保持特性；
附图标记
1、衬底，2、下电极，3、功能层，4、上电极，5、掺杂层。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
本发明提供了一种界面掺杂的忆阻器，选用类三明治结构，即下电极2-功能层3-上电极4；功能层为金属氧化物，上电极和功能层之间的界面为均匀掺杂，形成掺杂层5。
具体地，所选功能层可为金属氧化物，其中金属氧化物包括Hf的氧化物、Zr的氧化物、Al的氧化物、Ta的氧化物或Ti的氧化物。
具体地，下电极选用较为活泼的电极，其中包括Ta、Hf、Al、Ti、TiN，但其与功能层金属氧化物中的金属需保持不一致。上电极为惰性电极，包括Pt、Pd或Au。
具体地，界面所掺杂元素可为非金属元素N、F和H，也可为金属元素Al、Zr、Ta、Hf、Ni、Fe、Ti、Sc、Ru和Au中元素，但是金属电极和掺杂元素需不一致。
具体地，界面掺杂比例为2％～15％。
具体地，下电极的厚度为50nm～200nm，所述功能层的厚度为5nm～50nm，上电极的厚度为50nm～200nm。
本发明还提供了一种界面掺杂的忆阻器的制备方法，该制备方法具体步骤如下：
(1)在衬底1上制备活性下电极2；
(2)制备功能层3，并进行界面掺杂：利用原子层沉积法、磁控溅射法、分子束外延法、脉冲激光沉积法、热蒸发法或电化学生长金属氧化物，生长完后再生长一层掺杂的金属氧化物，从而实现在功能层和惰性电极界 面掺杂；
(3)在所述功能层3上制备惰性上电极4，从而得到基于界面掺杂氧化物的高性能忆阻器。
采用现有技术制备的忆阻器单元结构为三明治结构，功能层选用HfO 2，掺杂元素选用Al，上下电极分别采用Pt和TiN。制备方法具体为：
选取晶相为(100)，厚度为500μm的硅片，在其表面热生长一层1μm厚的SiO 2薄膜层，为衬底1。将其切成1×1cm大小的样片，取两片样片放入盛有适量丙酮的烧杯中，超声清洗15分钟，功率为40W，然后取出再置入盛有适量无水乙醇的烧杯中，再次超声清洗15分钟，最后取出用去离子水洗去样片表面的有机物，并用氮气枪吹干。
(1)取清洗干净的样片，在其表面利用PECVD生长一层100nm的TiN层即下电极2。然后清洗表面；
(2)利用紫外光刻在步骤(1)的样品上光刻制备图形，其中，光刻工艺步骤分别为：匀胶、前烘、前曝、后烘、后爆、显影；
(3)利用原子层沉积(ALD)在步骤(2)的样片上生长120cycles的HfO 2层，约8nm厚；ALD温度设置为250℃，Hf源用tetrakis(dimethylamino)hafnium(TDMAHF)，Al源用trimethylauminum(TMA)，氧源用水。
(4)生长完后将样片置入盛有适量的丙酮中浸泡半小时，再置入盛有适量的无水乙醇中浸泡十五分钟，然后用去离子水洗净表面的氧化物及光刻胶，最后用氮气枪吹干，完成剥离工艺；
(5)利用步骤(2)的光刻工艺进行套刻，制备上电极图形，电极尺寸为100μm；
(6)在步骤(5)处理后的样片上利用磁控溅射生长100nm的Pt层，然后对样片进行剥离工艺，同步骤(4)，即可得到上电极4。
(7)完成上述步骤后在样片上即制备出了TiN/HfO 2/Pt忆阻器的单元，如图1所示。
实施例1
本实验例中制备的忆阻器单元结构为三明治结构，功能层选用HfO 2，掺杂元素选用Al，上下电极分别采用Pt和TiN。制备方法具体为：
选取晶相为(100)，厚度为500μm的硅片，在其表面热生长一层1μm厚的SiO 2薄膜层，为衬底1。将其切成1×1cm大小的样片，取两片样片放入盛有适量丙酮的烧杯中，超声清洗15分钟，功率为40W，然后取出再置入盛有适量无水乙醇的烧杯中，再次超声清洗15分钟，最后取出用去离子水洗去样片表面的有机物，并用氮气枪吹干。
(1)取清洗干净的样片，在其表面利用PECVD生长一层100nm的TiN层即下电极2。然后清洗表面；
(2)利用紫外光刻在步骤(1)的样品上光刻制备图形，其中，光刻工艺步骤分别为：匀胶、前烘、前曝、后烘、后爆、显影；
(3)利用原子层沉积(ALD)在步骤(2)的样片上利用ALD先生长95cycles的HfO 2层，然后继续生长25cycles的HfO 2:Al层，其中Al的掺杂浓度为4.3％，总厚度也约为8nm，ALD温度设置为250℃，Hf源用tetrakis(dimethylamino)hafnium(TDMAHF)，Al源用trimethylauminum(TMA)，氧源用水。
(4)生长完后将样片置入盛有适量的丙酮中浸泡半小时，再置入盛有适量的无水乙醇中浸泡十五分钟，然后用去离子水洗净表面的氧化物及光刻胶，最后用氮气枪吹干，完成剥离工艺；
(5)利用步骤(2)的光刻工艺进行套刻，制备上电极图形，电极尺寸为100μm；
(6)在步骤(5)处理后的样片上利用磁控溅射生长100nm的Pt层，然后对样片进行剥离工艺，同步骤(4)，即可得到上电极4。
(7)完成上述步骤后在样片上即制备出了TiN/HfO 2/HfO 2:Al/Pt忆阻器单元，如图2所示。
进行薄膜表征和器件电学性能测量，所有电学性能皆采用Agilent B1500A半导体分析测试仪测量：
(1)图3(a)和图3(b)分别为制备的HfO 2和HfO 2:Al的O 1s的XPS测量，531.70eV所对应的峰为薄膜中的氧空位，图3(b)中氧空位对应的峰的面积明显高于图3(a)中的面积，说明掺Al后薄膜中的氧空位浓度增加；这与发明所述界面引入掺杂，会导致界面产生更多氧空位一致。界面氧空位浓度增加会影响器件中导电丝的形成和断裂，在Set操作时，导电丝在该层会比较粗壮；当外加偏压时导电丝首先会在掺杂界面生长，然后向活性电极生长，对导电丝生长起到一个定向引导的作用。另外，当外加反向偏压时，导电丝在未掺杂区域先断裂，由于未掺杂的介质层氧空位形成能要比掺杂后的介质层氧空位形成能大，器件的高阻态稳定性相对提升。
(2)图4(a)和图4(b)分别为TiN/HfO 2/Pt和TiN/HfO 2/HfO 2:Al/Pt忆阻器100次的连续电压扫描下的I-V图，其中上电极Pt接地，下电极TiN接正向电压，电压扫描为范围为2V～-2V，限制电流为1mA，从图上可以看出，图4(b)中的扫描曲线相比图4(a)的没有出现明显的波动，说明经过界面掺杂后的器件在在直流电压扫描时更稳定；
(3)图5(a)和图5(b)分别为TiN/HfO 2/Pt和TiN/HfO 2/HfO 2:Al/Pt忆阻器的高阻态和低阻态的频率累积分布统计图，高低阻值从图4中提取，其中δ/μ为阻态变化率，δ为阻态的标准差，μ为阻态的平均值，可以得出TiN/HfO 2/Pt忆阻器的高低阻态的变化率δ/μ分别为106.5％和12.8％，而TiN/HfO 2/HfO 2:Al/Pt的高低阻态的变化率δ/μ分别为24.4％和6.4％，可以看出，经过界面掺杂后，器件的高低阻态的一致性都有很大的提升；
(4)图6(a)和图6(b)分别为TiN/HfO 2/Pt和TiN/HfO 2/HfO 2:Al/Pt忆阻器的Set电压和Reset电压的频率累积分布统计图，Set电压和Reset电压值皆从图4中提取，其中δ/μ为操作电压变化率，δ为操作电压的标准差，μ为操作电压的平均值，可以得出TiN/HfO 2/Pt忆阻器的Set和Reset电压的变化率 δ/μ分别为12.4％和33.6％，而TiN/HfO 2/HfO 2:Al/Pt的Set和Reset电压的变化率δ/μ分别为4.4％和6.4％，说明经过界面掺杂后，器件的Set和Reset电压的一致性也有很大的提升；
(5)图7(a)和图7(b)分别为TiN/HfO 2/Pt和TiN/HfO 2/HfO 2:Al/Pt忆阻器的脉冲循环性能测试结果，TiN/HfO 2/Pt忆阻器所施加的Set脉冲脉宽为90ns，幅值为0.9V，Reset脉冲脉宽为200ns，幅值为-1.1V，TiN/HfO 2/HfO 2:Al/Pt忆阻器所施加的Set脉冲脉宽为90ns，幅值为0.9V，Reset脉冲脉宽为200ns，幅值为-1.2V。从图上可以看出，TiN/HfO 2/Pt忆阻器可以保持10 5cycles，但是高阻态很不稳定，而TiN/HfO 2/HfO 2:Al/Pt忆阻器可以保持10 6cycle循环，且高低阻态都十分稳定，具有更高的循环寿命；
(6)图8为TiN/HfO 2/HfO 2:Al/Pt忆阻器在85℃下的数据保持特性，高阻态(低阻态)读取操作电压为0.1V，从图上可以看出，器件在85摄氏度下可以保持10 4s，根据Arrhenius equation可推断出器件高低阻值均可以保持在10年以上。
基于以上电学测量，我们可以发现，相比TiN/HfO 2/Pt，基于界面Al掺杂的TiN/HfO 2/HfO 2:Al/Pt忆阻器的高低阻态一致性、操作电压一致性明显提升；此外该器件还具有良好的循环特性和保持特性，器件整体性能上得到了很大的改善。其基本原理在于，在HfO 2和Pt的界面掺杂铝后，界面层的氧空位增多，在Set操作时，导电丝在HfO 2:Al层会比较粗壮；当在TiN电极上施加正向偏压时，导电丝首先会在HfO 2:Al层生长，然后向TiN生长，对导电丝生长起到一个定向引导的作用。另外，当TiN上外加反向偏压(Reset过程)时，导电丝在HfO 2区域先断裂，由于HfO 2层氧空位形成能要比HfO 2:Al层氧空位形成能大，热稳定性相对更好，器件高阻态稳定性更好。因此，该实施例验证了本申请中基于界面掺杂可以有效地改善忆阻器器件的性能。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种基于界面掺杂的忆阻器，其特征在于，该忆阻器自上而下包括上电极、功能层和下电极，所述功能层为金属氧化物，上电极和功能层之间的界面为均匀掺杂。
  2. 如权利要求1所述的基于界面掺杂的忆阻器，其特征在于，所述金属氧化物为Hf的氧化物、Zr的氧化物、Al的氧化物、Ta的氧化物或Ti的氧化物。
  3. 如权利要求1所述的基于界面掺杂的忆阻器，其特征在于，所述下电极为活性电极，包括Ta、Hf、Al、Ti或TiN，但其与功能层金属氧化物中的金属需保持不一致；所述上电极为惰性电极，包括Pt、Pd或Au。
  4. 如权利要求1所述的基于界面掺杂的忆阻器，其特征在于，掺杂为非金属元素N、H、F，或者金属元素Al、Zr、Ta、Hf、Ni、Fe、Ti、Sc、Ru、Au，但是金属氧化物中的金属和掺杂元素需保持不一致。
  5. 如权利要求1所述的基于界面掺杂的忆阻器，其特征在于，界面掺杂比例为2％～15％。
  6. 如权利要求1所述的基于界面掺杂的忆阻器，其特征在于，所述下电极的厚度为50nm～200nm，所述功能层的厚度为5nm～50nm，上电极的厚度为50nm～200nm。
  7. 一种制备如权利要求1至6任一项所述的基于界面掺杂的忆阻器的方法，其特征在于，包括以下步骤：
    (1)在衬底上制备下电极；
    (2)制备功能层：利用原子层沉积法、磁控溅射法、分子束外延法、脉冲激光沉积法、热蒸发法或电化学生长金属氧化物，生长完后再生长一层掺杂的金属氧化物，实现在功能层和上电极界面掺杂；
    (3)在所述功能层上制备上电极，得到基于界面掺杂的忆阻器。
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