WO2023115357A1 - 阻变存储器及其制造方法 - Google Patents

阻变存储器及其制造方法 Download PDF

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WO2023115357A1
WO2023115357A1 PCT/CN2021/140220 CN2021140220W WO2023115357A1 WO 2023115357 A1 WO2023115357 A1 WO 2023115357A1 CN 2021140220 W CN2021140220 W CN 2021140220W WO 2023115357 A1 WO2023115357 A1 WO 2023115357A1
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electrode
conductive material
electrodes
resistive
layer
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PCT/CN2021/140220
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English (en)
French (fr)
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刘希夏
周雪
王校杰
秦青
焦慧芳
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华为技术有限公司
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Priority to CN202180037278.4A priority Critical patent/CN116649018A/zh
Priority to PCT/CN2021/140220 priority patent/WO2023115357A1/zh
Publication of WO2023115357A1 publication Critical patent/WO2023115357A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present disclosure relates to the field of electronics, and more specifically relates to a resistive memory and a manufacturing method thereof.
  • resistive memory As a new type of non-volatile memory, resistive memory has the advantages of simple structure, good compatibility of complementary metal oxide semiconductor (CMOS) process, stackable, multi-valued storage, high on-off ratio and Advantages such as good miniaturization have received more and more attention.
  • CMOS complementary metal oxide semiconductor
  • a conventional resistive variable memory has a sandwich structure including a top electrode, a resistive variable dielectric layer and a bottom electrode.
  • Conventional RRAMs include conductive bridge RRAMs based on metal conductive wires and oxygen-deficient vacancy RRAMs.
  • One conventional RRAM uses metal nanocrystals at the bottom electrode of the memory cell. That is, a metal film is deposited between the bottom electrode of the memory cell and the resistive dielectric layer, and the metal film is rapidly annealed at high temperature to disperse the metal film into metal nanocrystals with a certain size and shape. The cracking of metal thin films is random, so the size and distribution of metal nanocrystals are uncontrollable, and conventional resistive memory has the problem of poor performance consistency.
  • embodiments of the present disclosure aim to provide a resistive variable memory, a chip, an electronic device, and an electronic device for improving storage performance.
  • a resistive variable memory includes a first electrode layer; a resistive variable dielectric layer; and a second electrode layer.
  • the resistive variable dielectric layer is located between the first electrode layer and the second electrode layer.
  • the second electrode layer includes an insulating layer; a plurality of through holes located in the insulating layer; and a plurality of second electrodes.
  • Each of the plurality of second electrodes is at least partially located in one of the plurality of through holes, and the plurality of second electrodes are insulated from each other.
  • conductive filaments can be uniformly and consistently formed in time and space between the first electrode and the second electrode in the resistive variable memory, thereby ensuring the storage of each resistive variable memory.
  • the storage performance of the nodes is substantially consistent with each other and the performance of each storage node remains substantially stable during long-term use.
  • the RRAM of the present disclosure can significantly improve the performance consistency and stability of the RRAM.
  • the second electrode is in contact with the resistive variable dielectric layer.
  • the insulating layer is in contact with the resistive variable dielectric layer.
  • the second electrode includes a conductive part and an insulating post.
  • the conductive part has a ring structure or a sleeve structure.
  • An inner through hole is arranged inside the annular structure.
  • the sleeve structure is provided with grooves.
  • the insulating post is located in the groove or the inner through hole.
  • the ring structure or the sleeve structure has a shape of a circular ring or a rectangular ring in a cross section parallel to the second electrode layer.
  • the second electrode includes a first conductive material and a second conductive material.
  • the second conductive material is different from the first conductive material.
  • the second conductive material and the first conductive material are alternately arranged in the through hole.
  • a dimension of the second conductive material in a first direction perpendicular to the insulating layer is larger than a dimension of the first conductive material in the first direction.
  • the second conductive material protrudes closer to the first electrode layer, so that the local electric field strength formed at the top of the second conductive material is larger, and the conductive filaments can be gathered on the second conductive material.
  • the sharp tip is formed, so that the generation of conductive filaments can be more concentrated and uniform, and the overall performance of the memory can be improved.
  • the use of conductive materials can be reduced to save costs.
  • the plurality of second electrodes are evenly arranged in the second electrode layer.
  • the total surface area of the plurality of second electrodes in contact with the resistive variable dielectric layer is not higher than 60%, 50%, 40%, 30%, 20% or 10% of the surface area of the second electrode layer in contact with the resistive variable dielectric layer %.
  • the resistive variable memory is a conductive bridge resistive variable memory
  • the first electrode includes active metal materials such as silver, copper, titanium, aluminum, etc.
  • the resistive variable dielectric layer includes tantalum oxide, oxide Silicon, zirconia, cadmium oxide, germanium oxide, germanium sulfide, germanium telluride, germanium selenide, copper sulfide, copper telluride, silver sulfide or combinations thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal Nitride, amorphous carbon or combinations thereof.
  • the RRAM is an oxygen-deficient vacancy RRAM
  • the first electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon, or a combination thereof
  • the resistive The variable dielectric layer includes hafnium oxide, tantalum oxide, aluminum oxide, titanium oxide or a combination thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon or a combination thereof.
  • the first electrode layer is shared by a plurality of memory cells and coupled to a bit line.
  • the multiple second electrodes are respectively part of the corresponding multiple memory cells, and the multiple second electrodes are respectively coupled to the corresponding multiple gate tubes or transistors.
  • the resistive variable dielectric layer is configured to generate at least one conductive filament in response to a voltage between the first electrode layer and at least one second electrode of the second electrode layer.
  • a chip is provided.
  • the chip includes the resistive variable memory according to the first aspect.
  • an electronic device includes the resistive variable memory according to the first aspect.
  • an electronic device includes a power supply device and the resistive variable memory according to the first aspect, and is powered by the power supply device.
  • a method of manufacturing a resistive memory includes forming an insulating layer on the support layer; forming a plurality of through holes in the insulating layer; and forming a plurality of second electrodes in at least a portion of the plurality of through holes.
  • the second electrode is at least partially located in one of the plurality of through holes.
  • the method also includes forming a resistive variable dielectric layer on the insulating layer; and forming a first electrode layer on the resistive variable dielectric layer.
  • conductive filaments can be uniformly and consistently formed in time and space between the first electrode and the second electrode in the resistive variable memory, thereby ensuring the storage of each resistive variable memory.
  • the storage performance of the nodes is substantially consistent with each other and the performance of each storage node remains substantially stable during long-term use.
  • the RRAM of the present disclosure can significantly improve the performance consistency and stability of the RRAM.
  • forming the multiple through holes in the insulating layer includes etching the insulating layer to form the multiple through holes.
  • forming a plurality of second electrodes in at least a part of the plurality of through holes includes: depositing a conductive material on the insulating layer and in the plurality of through holes; depositing a conductive material on the surface of the conductive material Depositing an insulating material to form an intermediate structure; and polishing the intermediate structure until the insulating layer is exposed, so as to form a plurality of second electrodes.
  • the electrode surface can be made flush with the insulating surface, ensuring that the distances between the second electrodes and the first electrodes are basically the same, thereby further improving the performance consistency and stability of the RRAM.
  • a ring structure or a sleeve structure can be formed. This reduces the area of the second electrode facing the first electrode, so that compared with the randomness of the location of the conductive filaments of the large-area second electrode, the generation of conductive filaments can be more concentrated and uniform, thereby improving Overall performance of the memory.
  • the use of conductive materials can be reduced to save costs.
  • the ring structure or the sleeve structure has a shape of a circular ring or a rectangular ring in a cross section parallel to the second electrode layer.
  • forming a plurality of second electrodes in at least a part of the plurality of through holes includes: depositing a conductive material in the plurality of through holes and on the surface of the insulating layer , until the conductive material completely fills the plurality of through holes; polishing the conductive material above the surface of the insulating layer until the insulating layer is exposed, so as to form a plurality of second electrodes.
  • the electrode surface can be made flush with the insulating surface, ensuring that the distances between the second electrodes and the first electrodes are basically the same, thereby further improving the performance consistency and stability of the RRAM.
  • forming a plurality of second electrodes in at least a part of the plurality of through holes includes: alternately depositing the first conductive material and the second electrode on the insulating layer and in the plurality of through holes Conductive material, the second conductive material is different from the first conductive material and forms a groove in the through hole; the first conductive material and the second conductive material under the groove are etched to form an intermediate through hole; the first conductive material or on the surface of the second conductive material and deposit an insulating material in the middle through hole to form an intermediate structure; polish the intermediate structure until the insulating layer is exposed; and selectively etch the first conductive material to form a plurality of first conductive materials.
  • two electrodes are alternately depositing the first conductive material and the second electrode on the insulating layer and in the plurality of through holes.
  • the electrode surface and the insulating surface can be made flush, ensuring that the distance of the second conductive material in each second electrode relative to the first electrode is basically the same, thereby further improving the consistency of the performance of the RRAM sex and stability.
  • the second conductive material protrudes compared with the first conductive material and is closer to the first electrode layer, so that the local electric field strength formed on the top of the second conductive material is greater, which can make the conductive material
  • the filaments are gathered and formed at the tip of the second conductive material, so that the conductive filaments can be produced more concentrated and uniform, and the overall performance of the memory can be improved.
  • the use of conductive materials can be reduced to save costs.
  • the plurality of second electrodes are uniformly arranged in the second electrode layer.
  • the total surface area of the plurality of second electrodes in contact with the resistive variable dielectric layer is not higher than 60%, 50%, 40%, 30%, 20% or 10% of the surface area of the second electrode layer in contact with the resistive variable dielectric layer %.
  • the resistive variable memory is a conductive bridge resistive variable memory
  • the first electrode includes active metal materials such as silver, copper, titanium, aluminum, etc.
  • the resistive variable dielectric layer includes tantalum oxide, oxide Silicon, zirconia, cadmium oxide, germanium oxide, germanium sulfide, germanium telluride, germanium selenide, copper sulfide, copper telluride, silver sulfide or combinations thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal Nitride, amorphous carbon or combinations thereof.
  • the RRAM is an oxygen-deficient vacancy RRAM
  • the first electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon, or a combination thereof
  • the resistive The variable dielectric layer includes hafnium oxide, tantalum oxide, aluminum oxide, titanium oxide or a combination thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon or a combination thereof.
  • FIG. 1 shows a schematic structural diagram of a resistive switch unit of a conventional resistive switchable memory
  • FIG. 2 shows a schematic diagram of forming conductive filaments of a resistive variable unit of a conventional resistive variable memory
  • Fig. 3 shows a schematic circuit diagram of some memory cells of a resistive variable memory
  • FIG. 4 shows a schematic circuit diagram of some memory cells of another resistive variable memory
  • FIG. 5A shows a schematic structural diagram of a resistive variable memory according to some embodiments of the present disclosure
  • Figure 5B shows a schematic structural view of the ring structure and the sleeve structure of the second electrode in Figure 5A;
  • FIG. 6 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure
  • FIG. 7 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure.
  • FIG. 8 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure
  • FIG. 9 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure.
  • FIG. 10 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure
  • FIG. 11 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure
  • FIG. 12 shows a schematic diagram of a partial process structure for manufacturing a resistive memory according to other embodiments of the present disclosure.
  • FIG. 13 shows a flowchart of a method for manufacturing a resistive memory according to some embodiments of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.
  • a resistive variable memory generally includes a plurality of memory cells, and each memory cell includes a resistive variable cell.
  • the resistive variable unit is a sandwich structure, and a resistive variable dielectric layer is arranged between the top electrode and the bottom electrode.
  • a conductive thread penetrating through the resistive variable dielectric layer is generated between the top electrode and the bottom electrode to change the resistance between the top electrode and the bottom electrode, thereby changing the information storage state of the memory cell of the resistive variable memory .
  • a conventional resistive variable memory is a conductive bridge resistive variable memory, which changes the information storage state of a memory cell of the resistive variable memory by forming a metal conductive wire between a top electrode and a bottom electrode.
  • RRAM oxygen-deficient vacancy RRAM, which forms a conduction between the top and bottom electrodes by ionizing freely mobile O2- under the action of an electric field and forming positively charged vacancies in situ.
  • the channel is used to change the resistance of the storage unit of the resistive variable memory, thereby changing the information storage state of the storage unit of the resistive variable memory.
  • FIG. 1 shows a schematic structural diagram of a resistive switch unit 100 in a storage unit of a conventional resistive switchable memory.
  • the resistive variable memory includes a plurality of memory cells, and each memory cell includes a resistive variable cell.
  • the resistive variable unit 100 has a sandwich structure and is composed of a top electrode 110 , a resistive variable dielectric layer 120 and a bottom electrode 130 .
  • the operation mode of RRAM 100 is divided into two types: unipolar and bipolar.
  • the unipolar operation behavior depends on the magnitude of the applied voltage rather than the voltage polarity, while the bipolar operation behavior depends on the applied voltage. polarity of the voltage. Compared to bipolar operation behavior, unipolar has higher power consumption, less stability and consistency.
  • the storage mechanism of the RRAM 100 mainly includes a conductive bridge RRAM based on metal conductive filaments and an RRAM based on oxygen-deficient vacancy conductive filaments.
  • the specific storage mechanism of the RRAM is mainly determined by the specific material selection of each layer.
  • FIG. 2 shows a schematic diagram of conductive filaments formed by resistive switching units of a conventional resistive variable memory 200 .
  • the resistive variable memory 200 includes five resistive variable cells, which respectively correspond to position 1, position 2, position 3, position 4 and position 5 in FIG. 2 .
  • the resistive variable memory 200 includes a plate-shaped top electrode 202, a bottom electrode 204, and a dielectric material (not shown) between the top electrode 202 and the bottom electrode 204, and each resistive variable unit is separated by an insulating layer 206 in the bottom electrode 204. .
  • the location of the conductive filament is completely determined by the location and number of defects randomly generated during the deposition process of the resistive dielectric layer, resulting in uncontrollable location of the conductive filament, and the formation of The thickness of the conductive filament is uncontrollable, which will lead to an uncontrollable resistance value of the RRAM.
  • the fracture condition and thickness of the conductive thread 210 at position 1, the conductive thread 220 at position 2, the conductive thread 230 at position 3, the conductive thread 240 at position 4, and the conductive thread 250 at position 5 are different, which will lead to The resistance values of the resistors between the top electrode 202 and the bottom electrode 204 are different.
  • Both the formation and breakage of the conductive filaments determine the resistance state of the resistive variable dielectric layer, thereby determining the information storage state of the resistive variable memory 200 .
  • the formation of conductive filaments is formed by the migration of metal cations or O2- , and the ion migration is affected by the properties of the material itself (such as the electrode potential of the metal electrode material, the dielectric constant of the dielectric material, the interface and bulk defect distribution of the dielectric material, etc. ), programming conditions, local temperature field inside the device, etc., lead to the randomness of ion generation and migration randomness, and finally lead to the performance inconsistency of the RRAM 100 and the stability of the device.
  • Inconsistency includes device-to-device (D2D) and cycle-to-cycle (C2C) inconsistency of RRAM.
  • Stability issues include durability issues and data retention issues. Therefore, it is desirable to improve the controllability and uniformity of the conductive filament formation of the RRAM.
  • a conventional resistive memory uses metal nanocrystals at the bottom electrodes of resistive cells in its memory cells. That is, a metal film is deposited between the bottom electrode of the resistive variable unit and the resistive variable dielectric layer, and the metal film is subjected to high-temperature rapid annealing to disperse the metal film into metal nanocrystals with a certain size and shape.
  • the prominent metal nanocrystal position has a certain local electric field enhancement effect, and the enhanced electric field position can promote the migration of ions, thereby enhancing the ability to control the position of the conductive filament.
  • metal nanocrystals require high-temperature pyrolysis of metal thin films between 400°C and 800°C, which is not conducive to the integration of downstream processes in the manufacture of resistive memory. Moreover, the cracking of metal thin films is random, so the size and distribution of metal nanocrystals are uncontrollable, and the improvement of non-uniformity and stability of device performance is limited.
  • Another conventional RRAM uses ordered metal cone electrodes.
  • the pyramidal cone electrode template is fabricated by etching the inverted pyramid shape on the silicon wafer, the inverted pyramid electrode is prepared after depositing a metal film on the template, and the metal pyramid cone electrode is transferred to the substrate of the resistive variable memory by transfer and lift-off technology.
  • the size and distribution of metal cone electrodes prepared by templates are more controllable.
  • the metal pyramid cone electrode has a position-based electric field enhancement effect, which can enhance the Schottky emission of electrons at the tip of the tower, and then control the generation position of the conductive filament.
  • this solution needs to prepare pyramidal cone electrode templates by etching process.
  • the size of the prepared pyramidal cone electrodes is relatively large (for example, greater than 1 micron), and the distance between pyramid particles is relatively large (for example, greater than 1 micron), which is not conducive to resistive memory. Device scaling.
  • the local electric field enhancement effect is only reflected in the spire of the pyramidal cone electrode, the remaining area of the pyramidal cone electrode and the interval area of the pyramidal cone electrode are still plate electrodes, and the generation of conductive filaments at the plate electrode is inevitable and still has Randomness, so there is limited improvement to the non-uniformity and stability of RRAM.
  • the resistive variable memory includes a plurality of memory cells, each memory cell includes a resistive variable cell, the resistive variable cell includes a first electrode layer and a second electrode layer, a plurality of through holes are provided in the second electrode layer and the A plurality of second electrodes are arranged in a plurality of through holes, so that the second electrodes can be located at desired positions.
  • the conductive thread When a conductive thread is generated between the electrode and the first electrode on the opposite side, the conductive thread basically appears at the above-mentioned desired position. This can reduce the randomness of the generation of the conductive filaments and improve the uniformity of the shape of the conductive filaments, thereby improving the performance consistency of the RRAM and improving the stability of the conductive filament devices. In addition, it can effectively reduce the demand for external current, which helps to reduce energy consumption.
  • the RRAM according to the embodiments of the present disclosure can also be compatible with back-end processes.
  • FIG. 3 shows a schematic circuit diagram of a partial storage unit 300 of a resistive variable memory.
  • Part of the storage unit 300 is a single-transistor single-resistance variable unit structure, and exemplarily includes four storage units C1 , C2 , C3 and C4 .
  • the RRAM may include more storage units.
  • each memory cell includes a transistor and a resistive switching unit coupled to the transistor.
  • the memory cell C1 includes a transistor T1 and a resistive switching unit R1, the gate of the transistor T1 is coupled to the word line WL, the source of the transistor T1 is coupled to the source line SL and the drain of the transistor T1 is coupled to the resistive switching unit R1.
  • the memory cell C1 can operate in a write mode or a read mode.
  • the write mode when writing "1" (SET), the word line WL is connected to the high level V dd , the bit line BL is connected to the write voltage V w1 , and the source line SL is connected to the ground.
  • the word line WL is connected to the high level V dd , the bit line BL is connected to the ground, and the source line SL is connected to the write voltage V w2 .
  • the write voltage V w1 and the write voltage V w2 are opposite in voltage polarity, and the amplitude depends on the specific parameters of the RRAM, and may be the same or different.
  • FIG. 4 shows a schematic circuit diagram of another storage unit 400 of another RRAM.
  • Part of the storage unit 400 is a single selector single resistive variable unit structure, and exemplarily includes four storage units C11 , C12 , C13 and C14 .
  • the RRAM may include more storage units.
  • each memory cell includes a gate transistor and a resistive switching unit coupled with the gate transistor.
  • the memory cell C11 includes a gate transistor S11 and a resistive switch unit R11, one end of the gate transistor S11 is coupled to the word line WL, and one end of the gate transistor S11 is coupled to one end coupled to the resistive switch unit R11 , such as the top electrode or the first electrode.
  • the other end of the resistive switching unit R11 is coupled to the bit line BL.
  • the memory cell C11 may operate in a write mode or a read mode. For example, in the write mode, when writing "1" (SET), the word line WL of the memory cell C11 is connected to the write voltage V w1 , and the bit line BL is grounded. When writing "0" (RESET), the word line WL of the memory cell C11 is grounded, and the bit line BL is connected to the write voltage V w2 .
  • the write voltage V w1 and the write voltage V w2 are opposite in voltage polarity, and the amplitude depends on the specific parameters of the RRAM, and may be the same or different.
  • FIG. 5A shows a schematic structural diagram of some resistive switching cells in a resistive switching memory 500 according to some embodiments of the present disclosure.
  • the resistive memory 500 may include a plurality of storage units, each storage unit includes a resistive unit, and each resistive unit is used to store one bit of data. For example, when it is in the low resistance state, it stores the value "0", and when it is in the high resistance state, it stores the value "1".
  • FIG. 5A only shows structures of some resistive switching units of the resistive switching memory 500 .
  • the resistive variable memory 500 includes a first electrode layer 510 , a resistive variable dielectric layer 520 and a second electrode layer 530 .
  • the resistive variable dielectric layer 520 is located between the first electrode layer 510 and the second electrode layer 530 .
  • the second electrode layer 530 includes an insulating layer 540, a plurality of through holes and a plurality of second electrodes. A plurality of through holes are located in the insulating layer 540 .
  • the first electrode layer 510 can be coupled to other devices, for example, devices coupled to bit lines in FIG. Interconnects are coupled to other devices, such as transistors in FIG. 3 . This disclosure is not limited in this regard.
  • the first electrode layer 510 is shown as a whole as the first electrode in FIG. 5A , this is only illustrative and does not limit the scope of the present disclosure.
  • the first electrode layer 510 may also include a plurality of first electrodes corresponding to a plurality of second electrodes.
  • the plurality of second electrodes may be, for example, one end of the corresponding plurality of resistive switching units (including the resistive switching unit R11) in the plurality of memory cells C11...C14 in FIG.
  • the first electrode layer may be one end of a plurality of memory cells connected to the same bit line BL.
  • a second electrode may be one end of the resistive switching unit R11 connected to the gate transistor S11, and the first electrode layer may be one end of the memory cells C11 and C13 connected to the bit line BL.
  • the plurality of second electrodes may be, for example, one end of the corresponding plurality of resistive switching units (including the resistive switching unit R1) among the plurality of memory cells C1...C4 in FIG. 3 connected to a plurality of transistors , and the first electrode layer may be one end of a plurality of memory cells connected to the same bit line BL.
  • a second electrode may be one end of the resistive switch unit R1 connected to the transistor T1
  • the first electrode layer may be one end of the memory cells C1 and C3 connected to the bit line BL.
  • the first electrode is one end of the resistive variable unit for receiving a signal from the bit line BL
  • the second electrode is one end connected to a selection device such as a gate or transistor.
  • the RRAM 500 is a conductive bridge RRAM, wherein the first electrode comprises an electrode having an ionization energy between 570kJ/mol-740kJ/mol and an electrode potential between -1.7eV and +0.8eV.
  • Chemically active metallic materials such as silver, copper, titanium or combinations thereof.
  • the resistance variable dielectric layer includes tantalum oxide, silicon oxide, zirconium oxide, cadmium oxide, germanium oxide, germanium sulfide, germanium telluride, germanium selenide, copper sulfide, copper telluride, silver sulfide or a combination thereof.
  • the second electrode comprises an electrochemically inert metal material with an ionization energy greater than 740 kJ/mol or an electrode potential greater than 0.8 eV, such as platinum, iridium, tantalum, tungsten, conductive metal nitrides, amorphous carbon, or combinations thereof.
  • the RRAM 500 is an oxygen-deficient vacancy RRAM
  • the first electrode includes an electrochemically inert metal material with an ionization energy greater than 740 kJ/mol or an electrode potential greater than 0.8 eV, such as platinum, iridium, tantalum, Tungsten, conductive metal nitride, amorphous carbon or a combination thereof
  • the resistive dielectric layer includes hafnium oxide, tantalum oxide, aluminum oxide, titanium oxide or a combination thereof
  • the second electrode includes an ionization energy greater than 740kJ/mol or an electrode potential
  • Electrochemically inert metal materials greater than 0.8 eV such as platinum, iridium, tantalum, tungsten, conductive metal nitrides, amorphous carbon, or combinations thereof.
  • each second electrode may correspond to one end of a resistive variable unit, and each second electrode and the opposite first electrode may constitute a resistive variable unit for storing one bit of information.
  • the position of the second electrode can be determined as desired. Since the positions of the second electrodes are determined, for example, each second electrode gathers on the surface of a predetermined area of the second electrode layer, so the conductive thread is formed on the surface of the predetermined area.
  • the RRAM of the present disclosure can significantly improve the performance consistency and stability of the RRAM.
  • the second electrode 544 may include a first electrode surface facing the resistive variable dielectric layer 520 .
  • the insulating layer 540 includes a first insulating surface facing the resistive variable dielectric layer, and the first insulating surface is flush with the first electrode surface.
  • the first electrode surface of the second electrode is flush with the first insulating surface of the insulating layer 540 , this is only illustrative and does not limit the scope of the present disclosure.
  • the first electrode surface of the second electrode may not be flush with the first insulating surface of the insulating layer 540 , for example, be higher or lower than the first insulating surface of the insulating layer.
  • the second electrode 544 may have a conductive part 543 and an insulating post 542 .
  • the conductive part 543 has a sleeve structure, and the sleeve structure is provided with a groove, and the insulating post 542 is located in the groove.
  • the conductive part 543 may have a ring structure.
  • the ring structure has openings at both the first insulating surface and the second insulating surface opposite to the first insulating surface of the insulating layer 540 , and internal through-holes are provided inside.
  • the insulating column 542 may extend through the inner through hole.
  • FIG. 5B shows a schematic structural diagram of the ring structure and the sleeve structure of the second electrode 544 .
  • a top view 544 - 1 of a second electrode 544 having a sleeve structure and a perspective view 544 - 2 of the second electrode 544 are shown in FIG. 5B .
  • the second electrode 544 may have a ring-shaped electrode, that is, the height of the insulating post 542 is the same as that of the conductive part 543 , so that the insulating post 542 extends through the second electrode 544 in the vertical direction.
  • the ring structure or sleeve structure has the shape of a circular ring, a rectangular ring in a section parallel to the second electrode layer.
  • the conductive portion 543 may also have other cross-sectional shapes.
  • the area of the second electrode facing the first electrode can be reduced, so that compared with the randomness of the position of the conductive wire of the second electrode with a large area, the conductive wire can be made The result is more aggregated and uniform, thereby improving the overall performance of the memory, such as consistency and stability as described above.
  • the use of metal materials can be reduced to save costs.
  • the conductive part 543 may completely fill the through hole without the insulating post 542 .
  • a plurality of second electrodes are uniformly arranged in the second electrode layer 530 .
  • the total surface area of the plurality of second electrodes in contact with the resistive variable dielectric layer is not higher than 60%, 50%, 40%, 30%, 20% or 10% of the surface area of the second electrode layer in contact with the resistive variable dielectric layer %. It has been found that if the density of the second electrode in the second electrode layer is high, there may be a problem of ion diffusion during processing. In addition, since the resistance performance is related to temperature, the high density of the second electrode may also cause thermal crosstalk to affect the resistance value. By limiting the density of the plurality of second electrodes in the second electrode layer 530 , it can be ensured that ion diffusion and thermal crosstalk during processing will not significantly affect the performance of the RRAM.
  • FIG. 6 shows a schematic diagram of a partial process structure for manufacturing a resistive variable memory according to other embodiments of the present disclosure.
  • the second insulating layer 600 may be formed on a support substrate or other substrate.
  • the second insulating layer 600 may be deposited by methods such as physical vapor deposition or atomic layer deposition. It can be understood that other formation or growth methods can also be used to form the second insulating layer 600 .
  • FIG. 7 shows a schematic diagram of a partial process structure for manufacturing a RRAM according to other embodiments of the present disclosure.
  • the plurality of through holes 720 may be etched in the second insulating layer 600 to form the insulating layer 710 having the plurality of through holes 720 . It can be understood that other insulating material removal processes can also be used to form the plurality of through holes.
  • FIG. 8 shows a schematic diagram of a partial process structure for manufacturing a RRAM according to other embodiments of the present disclosure.
  • a stack of multiple conductive materials may be deposited on the surface of the insulating layer 710, for example, a first conductive material 810 is deposited on the surface of the insulating layer 710 and a first conductive material 810 is deposited on the surface of the insulating layer 710.
  • a second conductive material 820 is deposited thereon.
  • the first conductive material 810 and the second conductive material 820 may be alternately deposited to form a stack of more layers of conductive material.
  • the portion of the multilayer conductive material in the through hole has a groove, such as groove 830 . It is understood that other conductive material forming processes may also be used to form the stack of multiple layers of conductive material.
  • FIG. 9 shows a schematic diagram of a partial process structure for manufacturing a RRAM according to other embodiments of the present disclosure.
  • the multiple layers of conductive materials in the groove 830 such as the first conductive material 810 and the second conductive material 820 , may be directional etched away by an etching process.
  • an insulating material 910 may be deposited on the surface of the above-mentioned etched structure.
  • etching and deposition processes are used here, other material removal and material formation processes may be used.
  • FIG. 10 shows a schematic diagram of a partial process structure for manufacturing a RRAM according to other embodiments of the present disclosure.
  • a polishing process may be used to remove the portion above the insulating layer 710 until the insulating layer 710 and the insulating pillars 911 are exposed, and the electrodes of the first conductive material 810 and the second conductive material 820 The surface is flush with the surfaces of the insulating layer 710 and the insulating post 911 .
  • FIG. 11 shows a schematic diagram of a partial process structure for manufacturing a resistive variable memory according to other embodiments of the present disclosure.
  • a selective etchant may be used after the intermediate structure shown in FIG. 10 to etch away part of the first conductive material 811 , so that the second conductive material 820 protrudes compared to the first conductive material 810 . That is, the size of the second conductive material 820 in the first direction (horizontal direction) perpendicular to the insulating layer 710 is larger than the size of the first conductive material 810 in the first direction to form a sawtooth-shaped second electrode.
  • the second conductive material 820 is closer to the first electrode layer, the conductive filaments can be formed at the tip of the second conductive material 820, so that the conductive filaments can be formed The result is more aggregated and uniform, improving the overall performance of the memory.
  • the use of metal materials can be reduced to save costs.
  • the first conductive material 810 may not be etched, but the entirety of the first conductive material 810 and the second conductive material 820 may be used as the second electrode. It can be understood that in the case of depositing more layers of second conductive material 820 in FIG. 8 , more protruding second conductive materials can be formed in FIG. 11 .
  • FIG. 12 shows a schematic diagram of a partial process structure for manufacturing a RRAM according to other embodiments of the present disclosure.
  • a resistive variable dielectric layer 1220 may be deposited on the structure of FIG. 11
  • a first electrode layer 1210 may be deposited on the resistive variable dielectric layer 1220 .
  • the first electrode layer 1210 may be integrally formed and include a single first electrode.
  • the first electrode layer 1210 may include a plurality of first electrodes corresponding to a plurality of second electrodes.
  • a plurality of uniform and stable conductive filaments 1230 can be formed between the second conductive material 820 and the first electrode layer 1210 based on the voltages on the first electrode layer 1210 and the plurality of second electrodes.
  • the etching and deposition processes can be scaled down along with the process nodes, the through-hole size, electrode size, and material thickness of the RRAM can be adjusted accordingly, thereby improving integration and reducing power consumption. Since the processing techniques of the structures shown in FIGS. 6-12 may not involve the use of high-temperature processes such as pyrolysis, the pressure of subsequent processes can be reduced and compatible with them.
  • the second electrode since the second electrode is regular, uniform, flat and has a relatively small conductive filament formation area, it can effectively control the current supply position and maximize the control of metal cations or oxygen
  • the generation site of the defect vacancies thereby reducing the randomness of the generation of conductive filaments and improving the uniformity of the shape of the conductive filaments, thereby improving the performance consistency of the resistive variable memory, for example, the consistency of D2D and C2C.
  • the stability of RRAM such as persistence and data retention, can be improved.
  • the RRAM shown in FIG. 5A and FIG. 12 can also effectively reduce the demand for external current and help reduce energy consumption.
  • FIG. 13 shows a flow chart of a method 1300 for manufacturing a resistive variable memory according to some embodiments of the present disclosure.
  • the method shown in FIG. 13 can be used to manufacture the RRAM shown in FIG. 5A and FIG. 12 , so the aspects described with respect to FIGS. 5A-12 can be selectively applied to the method 1300 .
  • an insulating layer is formed on the support layer.
  • the supporting layer may be, for example, a semiconductor substrate or other supporting base layers.
  • the insulating layer may be formed using deposition, such as physical vapor deposition or atomic layer deposition. This disclosure is not limited in this regard.
  • a plurality of vias are formed in the insulating layer.
  • the insulating layer may be etched to form a plurality of through holes.
  • the etching process it is possible to ensure that the position of the second electrode is at the desired position and that the size of the second electrode is the designed size, thereby ensuring the consistency of the performance of the second electrode corresponding to each memory cell, thereby further improving the performance of the memory consistency and stability.
  • other insulating material removal processes may also be used to form a plurality of through holes by removing part of the insulating material.
  • a plurality of second electrodes are formed in at least a portion of the plurality of through holes.
  • the second electrode is at least partially located in one of the plurality of through holes.
  • a conductive material may be deposited on the insulating layer and in the plurality of through-holes, an insulating material may be deposited on the surface of the conductive material to form an intermediate structure, and the intermediate structure may be polished until the insulating layer is exposed to A plurality of second electrodes are formed.
  • the electrode surface can be made flush with the insulating surface, ensuring that the distances between the second electrodes and the first electrodes are basically the same, thereby further improving the performance consistency and stability of the RRAM.
  • a ring structure or a sleeve structure can be formed. This reduces the area of the second electrode facing the first electrode, so that compared with the randomness of the location of the conductive filaments of the large-area second electrode, the generation of conductive filaments can be more concentrated and uniform, thereby improving Overall performance of the memory.
  • the use of metal materials can be reduced to save costs.
  • the ring structure or the sleeve structure has a shape of a circular ring or a rectangular ring in a cross section parallel to the second electrode layer.
  • a conductive material is deposited in the plurality of through holes and on the surface of the insulating layer until the conductive material completely fills the plurality of through holes; for the conductive material above the surface of the insulating layer Polishing is performed until the insulating layer is exposed to form a plurality of second electrodes.
  • forming a plurality of second electrodes in at least a part of the plurality of through holes includes alternately depositing a first conductive material and a second conductive material on the insulating layer and in the plurality of through holes, the second conductive material The material is different from the first conductive material and a groove is formed in the through hole; the first conductive material and the second conductive material under the groove are etched to form an intermediate through hole; on the surface of the first conductive material or the second conductive material depositing an insulating material on and in the middle through hole to form an intermediate structure; polishing the intermediate structure until the insulating layer is exposed; and selectively etching the first conductive material to form a plurality of second electrodes.
  • the electrode surface and the insulating surface can be made flush, ensuring that the distance of the second conductive material in each second electrode relative to the first electrode is basically the same, thereby further improving the consistency of the performance of the RRAM sex and stability.
  • the second conductive material protrude compared to the first conductive material, in other words, the second conductive material is closer to the first electrode layer, the conductive filaments can be gathered at the tip of the second conductive material, so that the conductive filaments can be formed The result is more aggregated and uniform, improving the overall performance of the memory.
  • the use of metal materials can be reduced to save costs.
  • the plurality of second electrodes are uniformly arranged in the second electrode layer.
  • the total surface area of the plurality of second electrodes in contact with the resistive variable dielectric layer is not higher than 60%, 50%, 40%, 30%, 20% or 10% of the surface area of the second electrode layer in contact with the resistive variable dielectric layer %.
  • a resistive variable dielectric layer is formed on the insulating layer.
  • the resistive switching dielectric layer is formed using deposition, such as physical vapor deposition or atomic layer deposition. This disclosure is not limited in this regard.
  • a first electrode layer is formed on the resistive variable dielectric layer.
  • the resistive switching dielectric layer is formed using deposition, such as physical vapor deposition or atomic layer deposition.
  • the first electrode layer may also be grown by other methods, which is not limited in the present disclosure.
  • the resistive variable memory is a conductive bridge resistive variable memory
  • the first electrode involved in the method 1300 includes silver, copper, titanium or a combination thereof
  • the resistive variable dielectric layer includes tantalum oxide, silicon oxide, zirconium oxide, Cadmium oxide, germanium oxide, germanium sulfide, germanium telluride, germanium selenide, copper sulfide, copper telluride, silver sulfide or combinations thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon or combinations thereof.
  • the resistive variable memory is an oxygen-deficient vacancy resistive variable memory
  • the first electrode involved in the method 1300 includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon or a combination thereof
  • the electrical layer includes hafnium oxide, tantalum oxide, aluminum oxide, titanium oxide or a combination thereof
  • the second electrode includes platinum, iridium, tantalum, tungsten, conductive metal nitride, amorphous carbon or a combination thereof.

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Abstract

本公开涉及一种阻变存储器及其制造方法。阻变存储器包括三明治结构的第一电极层、第二电极层和位于第一电极层和第二电极层之间的阻变介电层。第二电极层中包括多个贯通孔并且在多个贯通孔中填充电极材料，可以形成环状电极或锯齿电极。由于在目标位置设置目标尺寸的电极，因此第二电极规则、均匀、平整并且具有相对较小的导电丝形成面积，从而可以有效控制电流提供位置，最大限度地控制金属阳离子或氧缺陷空位的产生位点。进而降低导电丝的产生随机性以及提升导电丝的形状均一性，从而提升阻变存储器的性能一致性，例如D2D和C2C的一致性。

Description

阻变存储器及其制造方法 技术领域
本公开涉及电子领域，更具体而言涉及阻变存储器及其制造方法。
背景技术
随着集成电路工艺发展到28纳米以下的节点，传统的闪存存储器等非易失存储器的发展遇到了瓶颈。一个重要原因是随着隧穿氧化层沟道的缩短，短沟道效应变得愈发明显，闪存存储器的控制栅极对浮栅中的电子控制能力变弱，导致电荷的隧穿泄漏变得越来越严重，直接影响了闪存存储器的器件耐久性和数据保持能力。阻变存储器作为一种新型的非易失存储器，具有结构简单、互补型金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺兼容性好、可堆叠、可实现多值存储、开关态比值高以及微缩性良好等优点受到了越来越多的关注。
常规阻变存储器具有三明治结构，其包括顶电极、阻变介电层和底电极。常规的阻变存储器包括以金属导电丝为主的导电桥阻变存储器和氧缺陷空位阻变存储器。一种常规的阻变存储器在存储单元的底电极处使用金属纳米晶。即，在存储单元的底电极和阻变介电层之间沉积一层金属薄膜，对金属薄膜进行高温快速退火，使金属薄膜分散成具有一定大小和形状的金属纳米晶。金属薄膜的裂解具有随机性，因此金属纳米晶的大小和分布不可控，常规阻变存储器存在性能一致性较差的问题。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种阻变存储器、芯片、电子装置和电子设备，用于改进存储性能。
根据本公开的第一方面，提供一种阻变存储器。阻变存储器包括第一电极层；阻变介电层；以及第二电极层。阻变介电层位于第一电极层和第二电极层之间。第二电极层包括绝缘层；多个贯通孔，位于绝缘层中；以及多个第二电极。多个第二电极中的每个第二电极至少部分地位于多个贯通孔中的一个贯通孔中，并且多个第二电极彼此绝缘。通过使用刻蚀所形成的贯通孔并且在贯通孔中沉积电极，可以根据期望确定第二电极的位置。由于第二电极的位置是确定的，因此阻变存储器中可以在第一电极和第二电极之间在时间上和空间上都可以均匀和一致的形成导电丝，从而确保阻变存储器的各个存储节点的存储性能彼此基本上一致并且各个存储节点在长时间使用期间的性能保持基本上稳定。相比于通过高温裂解或金属锥转移形成的常规阻变存储器，本公开的阻变存储器可以显著提高阻变存储器的性能的一致性和稳定性。
在第一方面的一种可能实现方式中，第二电极与阻变介电层相接触。绝缘层与阻变介电层相接触。通过使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。
在第一方面的一种可能实现方式中，第二电极包括导电部和绝缘柱。导电部具有环状结构或套结构。环状结构内部设置有内贯通孔。套结构设置有凹槽。绝缘柱位于凹槽或内贯通孔中。通过使用环状结构或套结构，可以减小与第一电极相面对的第二电极的面积，从而相 比于大面积第二电极的导电丝产生的位置的随机性，可以使得导电丝的产生更为聚集和均匀，从而提升存储器的一致性、稳定性。此外，还可以降低电流，减小功耗以及减少电极材料的使用节省成本。在第一方面的一种可能实现方式中，环状结构或套结构在与第二电极层平行的截面中具有圆环、矩形环的形状。
在第一方面的一种可能实现方式中，第二电极包括第一导电材料和第二导电材料。第二导电材料与第一导电材料不同。第二导电材料和第一导电材料在贯通孔中交替布置。第二导电材料在垂直于绝缘层中的第一方向上的尺寸大于第一导电材料在第一方向上的尺寸。通过使得第二导电材料相比于第一导电材料突出，更接近于第一电极层，从而在第二导电材料顶端所形成的局域电场强度更大，可以使得导电丝聚集在第二导电材料的尖端形成，从而可以使得导电丝的产生更为聚集和均匀，提升存储器的整体性能。此外，还可以减少导电材料的使用节省成本。
在第一方面的一些可能实现方式中，多个第二电极被均匀布置在第二电极层中。多个第二电极与阻变介电层接触的总表面面积不高于第二电极层与阻变介电层接触的表面面积的60％、50％、40％、30％、20％或10％。通过限制第二电极在第二电极层中的密度，可以确保加工过程中的离子扩散和热串扰不会显著影响阻变存储器的性能。
在第一方面的一种可能实现方式中，阻变存储器为导电桥阻变存储器，其中第一电极包括银、铜、钛、铝等活泼性金属材料，阻变介电层包括氧化钽、氧化硅、氧化锆、氧化镉、氧化锗、硫化锗、碲化锗、硒化锗、硫化铜、碲化铜、硫化银或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
在第一方面的一种可能实现方式中，阻变存储器为氧缺陷空位阻变存储器，其中第一电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物，阻变介电层包括氧化铪、氧化钽、氧化铝、氧化钛或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
在第一方面的一种可能实现方式中，第一电极层为多个存储单元共有并且耦合至位线。多个第二电极分别是相应多个存储单元的一部分，并且多个第二电极分别耦合至相应的多个选通管或晶体管。
在第一方面的一种可能实现方式中，阻变介电层被配置成响应于第一电极层和第二电极层中的至少一个第二电极之间的电压，生成至少一个导电丝。
根据本公开的第二方面，提供一种芯片。该芯片包括根据第一方面的阻变存储器。
根据本公开的第三方面，提供一种电子装置。该电子装置包括根据第一方面的阻变存储器。
根据本公开的第四方面，提供一种电子设备。电子设备包括供电装置和根据第一方面的阻变存储器，由供电装置供电。
根据本公开的第五方面，提供一种制造阻变存储器的方法。该方法包括在支撑层上形成绝缘层；在绝缘层中形成多个贯通孔；以及在多个贯通孔中的至少一部分中形成多个第二电极。第二电极至少部分地位于多个贯通孔中的一个贯通孔中。该方法还包括在绝缘层上形成阻变介电层；以及在阻变介电层上形成第一电极层。通过使用刻蚀所形成的贯通孔并且在贯通孔中沉积电极，可以根据期望确定第二电极的位置。由于第二电极的位置是确定的，因此阻变存储器中可以在第一电极和第二电极之间在时间上和空间上都可以均匀和一致的形成导电丝，从而确保阻变存储器的各个存储节点的存储性能彼此基本上一致并且各个存储节点在 长时间使用期间的性能保持基本上稳定。相比于通过高温裂解或金属锥转移形成的常规阻变存储器，本公开的阻变存储器可以显著提高阻变存储器的性能的一致性和稳定性。
在第五方面的一种可能实现方式中，在绝缘层中形成多个贯通孔包括对绝缘层进行刻蚀以形成多个贯通孔。通过使用刻蚀工艺，可以确保第二电极的位置处于期望位置并且确保第二电极的尺寸为设计尺寸，从而确保与各个存储单元对应的第二电极的性能的一致性，从而进一步提高存储器的性能的一致性和稳定性。
在第五方面的一种可能实现方式中，在多个贯通孔中的至少一部分中形成多个第二电极包括：在绝缘层上和在多个贯通孔中沉积导电材料；在导电材料的表面上沉积绝缘材料以形成中间结构；以及对中间结构进行抛光，直至露出绝缘层，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。此外，通过使用上述方式，可以形成环状结构或套结构。这减小与第一电极相面对的第二电极的面积，从而相比于大面积第二电极的导电丝产生的位置的随机性，可以使得导电丝的产生更为聚集和均匀，从而提升存储器的整体性能。此外，还可以减少导电材料的使用以节省成本。在第五方面的一种可能实现方式中，环状结构或套结构在与第二电极层平行的截面中具有圆环、矩形环的形状。
在第五方面的一种可能实现方式中，在多个贯通孔中的至少一部分中形成多个第二电极包括：在所述多个贯通孔中和在所述绝缘层的表面上沉积导电材料，直至导电材料完全填充所述多个贯通孔；对在所述绝缘层表面上方的导电材料进行抛光，直至露出绝缘层，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。
在第五方面的一种可能实现方式中，在多个贯通孔中的至少一部分中形成多个第二电极包括：在绝缘层上和在多个贯通孔中交替沉积第一导电材料和第二导电材料，第二导电材料与第一导电材料不同并且在贯通孔中形成凹槽；对凹槽下方的第一导电材料和第二导电材料进行刻蚀以形成中间贯通孔；在第一导电材料或第二导电材料的表面上并且在中间贯通孔中沉积绝缘材料以形成中间结构；对中间结构进行抛光，直至露出绝缘层；以及对第一导电材料进行选择性刻蚀，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极中的第二导电材料相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。此外，通过使得第二电极中，第二导电材料相比于第一导电材料突出，更接近于第一电极层，从而在第二导电材料顶端所形成的局域电场强度更大，可以使得导电丝聚集在第二导电材料的尖端形成，从而可以使得导电丝的产生更为聚集和均匀，提升存储器的整体性能。此外，还可以减少导电材料的使用节省成本。
在第五方面的一些可能实现方式中，多个第二电极被均匀布置在第二电极层中。多个第二电极与阻变介电层接触的总表面面积不高于第二电极层与阻变介电层接触的表面面积的60％、50％、40％、30％、20％或10％。通过限制第二电极在第二电极层中的密度，可以确保加工过程中的离子扩散和热串扰不会显著影响阻变存储器的性能。
在第五方面的一种可能实现方式中，阻变存储器为导电桥阻变存储器，其中第一电极包括银、铜、钛、铝等活泼性金属材料，阻变介电层包括氧化钽、氧化硅、氧化锆、氧化镉、 氧化锗、硫化锗、碲化锗、硒化锗、硫化铜、碲化铜、硫化银或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
在第五方面的一种可能实现方式中，阻变存储器为氧缺陷空位阻变存储器，其中第一电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物，阻变介电层包括氧化铪、氧化钽、氧化铝、氧化钛或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了常规阻变存储器的阻变单元的结构示意图；
图2示出了常规阻变存储器的阻变单元的形成导电丝的示意图；
图3示出了一种阻变存储器的部分存储单元的电路示意图；
图4示出了另一种阻变存储器的部分存储单元的电路示意图；
图5A示出了根据本公开的一些实施例的阻变存储器的结构示意图；
图5B示出了图5A中的第二电极的环状结构和套结构的结构示意图；
图6示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图7示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图8示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图9示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图10示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图11示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；
图12示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图；以及
图13示出了根据本公开的一些实施例的用于制造阻变存储器的方法的流程图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
阻变存储器通常包括多个存储单元，每个存储单元包括阻变单元。阻变单元为三明治结构，顶电极和底电极之间设有阻变介电层。在阻变存储器的操作过程中，顶电极和底电极之间产生贯穿阻变介电层的导电丝以改变顶电极和底电极之间的电阻，从而改变阻变存储器的存储单元的信息存储状态。一种常规阻变存储器为导电桥阻变存储器，其通过在顶电极和底电极之间形成金属导电丝来改变阻变存储器的存储单元的信息存储状态。另一种常规阻变存储器为氧缺陷空位阻变存储器，其通过在电场作用下电离出自由移动的O 2-并且在原位置形成带正电的空位，来在顶电极和底电极之间形成导带通道以改变阻变存储器的存储单元的电阻，从而改变阻变存储器的存储单元的信息存储状态。
图1示出了常规阻变存储器的存储单元中的阻变单元100的结构示意图。阻变存储器包括多个存储器单元，每个存储单元包括一个阻变单元。阻变单元100为三明治结构，由顶电极110、阻变介电层120和底电极130组成。阻变存储器100的操作方式分为单极性和双极性两种，单极性的操作行为取决于施加电压的幅值而非电压极性，而双极性的操作行为则取决于所施加电压的极性。相比于双极性的操作行为，单极性的能耗较高、稳定性和一致性较差。阻变存储器100的存储机制主要包含以金属导电丝为主的导电桥阻变存储器和以氧缺陷空位导电丝为主的氧缺陷空位阻变存储器。阻变存储器的具体存储机制主要由各层的具体材料选择决定。
图2示出了常规阻变存储器200的阻变单元形成导电丝的示意图。在图2中，阻变存储器200包括五个阻变单元，其分别对应于图2中的位置1、位置2、位置3、位置4和位置5。阻变存储器200包括板状的顶电极202、底电极204以及位于顶电极202和底电极204之间的介电材料(未示出)，各个阻变单元由底电极204中的绝缘层206间隔。由于板状电极各位置产生的电场较为均一，导致导电丝的产生位置完全由阻变介电层在沉积过程中随机产生的缺陷位置和数量决定，导致导电丝产生的位置不可控，以及形成的导电丝的粗细不可控，这会导致阻变存储器的阻值不可控。如图2所示，位置1的导电丝210、位置2的导电丝220、位置3的导电丝230、位置4的导电丝240和位置5的导电丝250的断裂状况和粗细不同，这会导致顶电极202和底电极204之间的电阻阻值不同。导电丝的形成与断裂都决定了阻变介电层的电阻状态，从而决定了阻变存储器200的信息存储状态。但是导电丝的形成是由金属阳离子或O 2-迁移形成的，离子迁移受材料本身性质(如金属电极材料的电极势、介电材料的介电常数、介电材料的界面和体缺陷分布等)、编程条件、器件内部的局域温度场等影响，导致了离子产生的随机性以及迁移随机性，最终导致了阻变存储器100的性能非一致性问题，以及器件的稳定性问题。非一致性包含阻变存储器的器件和器件之间(device-to-device，D2D)和周期之间(cycle-to-cycle，C2C)的非一致性。稳定性问题包括耐久性问题和数据保持能力问题。因此，期望提升阻变存储器的导电丝形成的控制能力和均一性。
如上所述，诸如导电桥阻变存储器和氧缺陷空位阻变存储器之类的常规阻变存储器存在性能一致性以及稳定性较差的问题。具体而言，一种常规的阻变存储器在其存储单元中的阻变单元的底电极处使用金属纳米晶。即，在阻变单元的底电极和阻变介电层之间沉积一层金属薄膜，对金属薄膜进行高温快速退火，使金属薄膜分散成具有一定大小和形状的金属纳米晶。突出的金属纳米晶位置相比于原有平板金属电极具有一定的局域电场增强效果，增强的电场位置处可以促进离子的迁移，进而增强对导电丝产生位置的控制能力。然而，金属纳米晶需要金属薄膜在400℃-800℃之间的高温裂解,不利于阻变存储器制造的后道工艺集成。而且，金属薄膜的裂解具有随机性，因此金属纳米晶的大小和分布不可控，对器件性能的非 一致性和稳定性的改善有限。另一种常规的阻变存储器使用有序金属锥电极。通过在硅片上刻蚀倒金字塔形貌制作金字塔锥电极模板，在该模板上沉积金属薄膜后制备倒金字塔电极，通过转移及剥离技术将金属金字塔锥电极转移到制作阻变存储器的基底上。相比于纳米晶的大小和分布不可控，通过模板制备的金属锥电极的大小和分布更加可控。此外，相比于平板电极，金属金字塔锥电极具有基于位置的电场增强效果，能够增强电子在塔尖位置的肖特基发射，进而控制导电丝的产生位置。但该方案需要通过刻蚀工艺制备金字塔锥电极模板，所制备的金字塔锥电极的尺寸较大(例如大于1微米),且金字塔颗粒的间距较大(例如大于1微米)，不利于阻变存储器器件的微缩。此外，局部电场增强效果仅体现在金字塔锥电极的塔尖处，金字塔锥电极的其余区域和金字塔锥电极的间隔区域仍为板状电极，板状电极处的导电丝的产生不可避免并且仍具有随机性，因此对阻变存储器的非一致性和稳定性的改善有限。
在本公开中，阻变存储器包括多个存储单元，每个存储单元包括阻变单元，阻变单元包括第一电极层和第二电极层，在第二电极层中设置多个贯通孔并且在多个贯通孔中设置多个第二电极，可以使得第二电极处于期望位置。当该电极与对面的第一电极之间产生导电丝时，导电丝基本上出现上述期望位置处。这样可以降低导电丝的产生随机性以及提升导电丝的形状均一性，从而提升阻变存储器的性能一致性，并且提升导电丝器件的稳定性。此外，还可以有效降低对外加电流的需求，有助于降低能耗。此外，根据本公开的实施例的阻变存储器还可以与后道工艺兼容。
图3示出了一种阻变存储器的部分存储单元300的电路示意图。部分存储单元300为单晶体管单阻变单元架构，并且示例性地包括四个存储单元C1、C2、C3和C4。可以理解，阻变存储器可以包括更多个存储单元。在图3中，每个存储单元包括一个晶体管和与该晶体管耦合的阻变单元。以存储单元C1为例，存储单元C1包括晶体管T1和阻变单元R1，晶体管T1的栅极耦合至字线WL，晶体管T1的源极耦合至源线SL并且晶体管T1的漏极耦合至阻变单元R1的一端，例如底电极或第二电极。阻变单元R1的另一端，例如顶电极或第一电极，耦合至位线BL。存储单元C1可以在写模式或读模式下操作。例如，在写模式中，在写“1”(SET)时，字线WL接高电平V dd，位线BL接写电压V w1，源线SL接地。在写“0”(RESET)时，字线WL接高电平V dd，位线BL接地，源线SL接写电压V w2。写电压V w1和写电压V w2电压极性相反，幅值取决于阻变存储器的具体参数，可以相同也可以不同。
图4示出了另一种阻变存储器的部分存储单元400的电路示意图。部分存储单元400为单选择器单阻变单元架构，并且示例性地包括四个存储单元C11、C12、C13和C14。可以理解，阻变存储器可以包括更多个存储单元。在图4中，每个存储单元包括一个选通管和与该选通管耦合的阻变单元。以存储单元C11为例，存储单元C11包括选通管S11和阻变单元R11，选通管S11的一端耦合至字线WL，并且选通管S11的一端耦合至耦合至阻变单元R11的一端，例如顶电极或第一电极。阻变单元R11的另一端，例如底电极或第二电极，耦合至位线BL。存储单元C11可以在写模式或读模式下操作。例如，在写模式中，在写“1”(SET)时，存储单元C11的字线WL接写电压V w1，位线BL接地。在写“0”(RESET)时，存储单元C11的字线WL接地，位线BL接写电压V w2。写电压V w1和写电压V w2电压极性相反，幅值取决于阻变存储器的具体参数，可以相同也可以不同。
图5A示出了根据本公开的一些实施例的阻变存储器500中的一些阻变单元的结构示意图。阻变存储器500可以包括多个存储单元，每个存储单元包括一个阻变单元，并且每个阻变单元用于存储一个比特的数据。例如当其为低阻态时，存储值“0”，而其为高阻态时，其 存储值“1”。为了便于理解，图5A中仅示出了阻变存储器500的一些阻变单元的结构。阻变存储器500包括第一电极层510、阻变介电层520以及第二电极层530。阻变介电层520位于第一电极层510和第二电极层530之间。第二电极层530包括绝缘层540、多个贯通孔和多个第二电极。多个贯通孔位于绝缘层540中。在一个实施例中，第一电极层510可以例如通过互连线耦合至其它器件，例如图3中的位线所耦合的器件，第二电极层530中的多个第二电极可以通过多个互连线耦合至另一些器件，例如图3中的多个晶体管。本公开对此不进行限制。虽然在图5A中将第一电极层510作为第一电极整体示出，但是这仅是示意而非对本公开的范围进行限制。在另一些实施例中，第一电极层510也可以包括与多个第二电极对应的多个第一电极。参见图4，多个第二电极例如可以是图4中的多个存储单元C11……C14中的相应多个阻变单元(包括阻变单元R11)的分别连接多个选通管的一端，而第一电极层可以是多个存储单元的连接到相同位线BL的一端。例如，一个第二电极可以是阻变单元R11的连接选通管S11的一端，第一电极层可以是存储单元C11和C13连接到位线BL的一端。类似地，参见图3，多个第二电极例如可以是图3中的多个存储单元C1……C4中的相应多个阻变单元(包括阻变单元R1)的分别连接多个晶体管的一端，而第一电极层可以是多个存储单元的连接到相同位线BL的一端。例如，一个第二电极可以是阻变单元R1的连接晶体管T1的一端，第一电极层可以是存储单元C1和C3连接到位线BL的一端。第一电极是阻变单元中用于接收位线BL的信号的一端，而第二电极则是连接至诸如选通管或晶体管之类的选择器件的一端。
在一个实施例中，阻变存储器500为导电桥阻变存储器，其中第一电极包括电离能在570kJ/mol-740kJ/mol之间并且电极势在-1.7eV和+0.8eV之间的的电化学活性金属材料，诸如银、铜、钛或其组合物。阻变介电层包括氧化钽、氧化硅、氧化锆、氧化镉、氧化锗、硫化锗、碲化锗、硒化锗、硫化铜、碲化铜、硫化银或其组合物。第二电极包括电离能大于740kJ/mol或电极势大于0.8eV的电化学惰性金属材料，例如铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
在另一个实施例中，阻变存储器500为氧缺陷空位阻变存储器，其中第一电极包括电离能大于740kJ/mol或电极势大于0.8eV的电化学惰性金属材料，例如铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物，阻变介电层包括氧化铪、氧化钽、氧化铝、氧化钛或其组合物，第二电极包括电离能大于740kJ/mol或电极势大于0.8eV的电化学惰性金属材料，例如铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
以多个第二电极中的一个第二电极544为例进行说明，第二电极544至少部分地位于多个贯通孔中的一个贯通孔中，并且多个第二电极彼此绝缘。在图5A中，每个第二电极可以对应于一个阻变单元的一个端部，并且每个第二电极和相对的第一电极可以构成一个阻变单元以用于存储一个比特的信息。通过使用刻蚀所形成的贯通孔并且在贯通孔中沉积电极，可以根据期望确定第二电极的位置。由于第二电极的位置是确定的，例如每个第二电极聚集在第二电极层的预定区域的表面，因此导电丝在该预定区域的表面形成。当施加的电压保持一致时，阻变存储器中可以在第一电极和第二电极之间形成在时间上和空间上都可以均匀和一致的导电丝，从而确保阻变存储器的各个存储节点的存储性能彼此基本上一致并且各个存储节点在长时间使用期间的性能保持基本上稳定。相比于通过高温裂解或金属锥转移形成的常规阻变存储器，本公开的阻变存储器可以显著提高阻变存储器的性能的一致性和稳定性。
在图5A中，第二电极544可以包括与阻变介电层520相面对的第一电极表面。绝缘层 540包括与阻变介电层相面对的第一绝缘表面，第一绝缘表面与第一电极表面平齐。通过使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极510的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。虽然在图5A中示出将第二电极的第一电极表面与绝缘层540的第一绝缘表面平齐，但这仅是示意而非对本公开的范围进行限制。在一些实施例中，第二电极的第一电极表面可以与绝缘层540的第一绝缘表面不平齐，例如比绝缘层的第一绝缘表面更高或更低。
在图5A中，第二电极544可以具有导电部543和绝缘柱542。导电部543具有套结构，套结构设置有凹槽，绝缘柱542位于凹槽中。备选地，导电部543可以具有环状结构。相比于套结构，环状结构在绝缘层540的第一绝缘表面和与第一绝缘表面相对的第二绝缘表面处均具有开口，并且内部设置有内贯通孔。在内贯通孔中，绝缘柱542可以延伸贯通内贯通孔。图5B示出了第二电极544的环状结构和套结构的结构示意图。在图5B中示出了具有套结构的第二电极544的俯视图544-1和第二电极544的立体图544-2。在另一些实施例中，第二电极544可以具有环状电极，即，绝缘柱542的高度与导电部543相同，从而绝缘柱542在竖直方向上延伸贯穿第二电极544。环状结构或套结构在与第二电极层平行的截面中具有圆环、矩形环的形状。备选地，导电部543也可以具有其它截面形状。通过使用环状结构或套结构，可以减小与第一电极相面对的第二电极的面积，从而相比于大面积第二电极的导电丝产生的位置的随机性，可以使得导电丝的产生更为聚集和均匀，从而提升存储器的整体性能，例如如上所述的一致性和稳定性。此外，还可以减少金属材料的使用节省成本。备选地，导电部543可以完全填充贯通孔而不具有绝缘柱542。
在一个实施例中，多个第二电极被均匀布置在第二电极层530中。多个第二电极与阻变介电层接触的总表面面积不高于第二电极层与阻变介电层接触的表面面积的60％、50％、40％、30％、20％或10％。研究发现，如果第二电极层中的第二电极的密度较高，可能会在加工过程中产生离子扩散的问题。此外，由于电阻性能与温度相关，第二电极的密度较高还可能会导致热串扰从而影响阻值的问题。通过限制多个第二电极在第二电极层530中的密度，可以确保加工过程中的离子扩散和热串扰不会显著影响阻变存储器的性能。
图6示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在支撑衬底或其它衬底上形成第二绝缘层600。例如，可以通过物理气相沉积或原子层沉积之类的方法沉积第二绝缘层600。可以理解，也可以使用其它形成或生长方法来形成第二绝缘层600。
图7示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在形成第二绝缘层600之后，在第二绝缘层600中刻蚀多个贯通孔720以形成具有多个贯通孔720的绝缘层710。可以理解，也可以使用其它绝缘材料去除工艺来形成多个贯通孔。
图8示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在形成绝缘层710之后，在绝缘层710的表面上沉积多层导电材料的堆叠，例如在绝缘层710的表面上沉积第一导电材料810并且在第一导电材料810上沉积第二导电材料820。虽然在此仅示出了沉积两层导电材料，但是这仅是示意而非对本公开的范围进行限制。在一些实施例中，可以交替沉积第一导电材料810和第二导电材料820以形成更多层导电材料的堆叠。多层导电材料在贯通孔中的部分具有凹槽，例如凹槽830。可以理解，也可以使用其它导电材料形成工艺来形成多层导电材料的堆叠。
图9示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在交替沉积多层导电材料的堆叠之后，通过刻蚀工艺定向刻蚀掉凹槽830中的多层导电材料，例如第一导电材料810和第二导电材料820。在此之后，可以在上述刻蚀之后的结构的表面上沉积绝缘材料910。虽然在此使用刻蚀工艺和沉积工艺，但是可以使用其它材料去除工艺和材料形成工艺。
图10示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在形成绝缘材料910之后使用抛光工艺来去除绝缘层710之上的部分，直至露出绝缘层710和绝缘柱911，并且第一导电材料810和第二导电材料820的电极表面与绝缘层710和绝缘柱911的表面平齐。
图11示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在图10所示的中间结构之后使用选择性刻蚀剂来刻蚀掉部分第一导电材料811，从而使得第二导电材料820相比于第一导电材料810突出。即，第二导电材料820在垂直于绝缘层710中的第一方向(水平方向)上的尺寸大于第一导电材料810在第一方向上的尺寸，以形成锯齿状的第二电极。通过使得第二导电材料相比于第一导电材料突出，换言之第二导电材料820更接近于第一电极层，可以使得导电丝聚集在第二导电材料820的尖端形成，从而可以使得导电丝的产生更为聚集和均匀，提升存储器的整体性能。此外，还可以减少金属材料的使用节省成本。备选地，也可以不刻蚀第一导电材料810，而将第一导电材料810和第二导电材料820整体用作第二电极。可以理解，在图8中沉积更多层第二导电材料820的情形下，图11可以形成更多个突出的第二导电材料。
图12示出了根据本公开的另一些实施例的用于制造阻变存储器的部分工艺结构示意图。在一个实施例中，可以在图11的结构上沉积阻变介电层1220，并且在阻变介电层1220上沉积第一电极层1210。第一电极层1210可以整体形成，并且包括单个第一电极。备选地，第一电极层1210可以包括与多个第二电极对应的多个第一电极。阻变存储器在操作时，可以基于在第一电极层1210和多个第二电极上的电压，在第二导电材料820与第一电极层1210之间形成均匀和稳定的多个导电丝1230。此外，由于刻蚀和沉积工艺可以随着工艺节点微缩，因此，阻变存储器的贯通孔尺寸、电极尺寸和材料厚度均可以相应地调控，从而提高集成度和降低功耗。由于图6-图12所示的结构的加工工艺可以均不涉及使用诸如高温裂解之类的高温工艺，因此可以减轻后道工艺的压力，并且可以与其兼容。
在图5A和图12所示的阻变存储器中，由于第二电极规则、均匀、平整并且具有相对较小的导电丝形成面积，因此可以有效控制电流提供位置，最大限度地控制金属阳离子或氧缺陷空位的产生位点，进而降低导电丝的产生随机性以及提升导电丝的形状均一性，从而提升阻变存储器的性能一致性，例如，D2D和C2C的一致性。此外还可以提升阻变存储器的稳定性，例如持久性和数据保持能力。此外，图5A和图12所示的阻变存储器还可以有效降低对外加电流的需求，有助于降低能耗。
图13示出了根据本公开的一些实施例的用于制造阻变存储器的方法1300的流程图。图13所示的方法可以用于制造图5A和图12所示的阻变存储器，因此关于图5A-图12所描述的方面可以选择性地应用于方法1300。
在1302，在支撑层上形成绝缘层。在一个实施例中，支撑层例如可以半导体衬底或其它可以支撑的基底层。可以使用沉积，例如物理气相沉积或原子层沉积，来形成绝缘层。本公开对此不进行限制。
在1304，在绝缘层中形成多个贯通孔。在一个实施例中，例如可以对绝缘层进行刻蚀以形成多个贯通孔。通过使用刻蚀工艺，可以确保第二电极的位置处于期望位置并且确保第二电极的尺寸为设计尺寸，从而确保与各个存储单元对应的第二电极的性能的一致性，从而进一步提高存储器的性能的一致性和稳定性。可以理解，也可以使用其它绝缘材料去除工艺来通过去除部分绝缘材料以形成多个贯通孔。
在1306，在多个贯通孔中的至少一部分中形成多个第二电极。第二电极至少部分地位于多个贯通孔中的一个贯通孔中。在一个实施例中，例如可以在绝缘层上和在多个贯通孔中沉积导电材料，在导电材料的表面上沉积绝缘材料以形成中间结构，以及对中间结构进行抛光，直至露出绝缘层，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。此外，通过使用上述方式，可以形成环状结构或套结构。这减小与第一电极相面对的第二电极的面积，从而相比于大面积第二电极的导电丝产生的位置的随机性，可以使得导电丝的产生更为聚集和均匀，从而提升存储器的整体性能。此外，还可以减少金属材料的使用节省成本。在第五方面的一种可能实现方式中，环状结构或套结构在与第二电极层平行的截面中具有圆环、矩形环的形状。
在一个实施例中，在所述多个贯通孔中和在所述绝缘层的表面上沉积导电材料，直至导电材料完全填充所述多个贯通孔；对在所述绝缘层表面上方的导电材料进行抛光，直至露出绝缘层，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。
在另一实施例中，在多个贯通孔中的至少一部分中形成多个第二电极包括在绝缘层上和在多个贯通孔中交替沉积第一导电材料和第二导电材料，第二导电材料与第一导电材料不同并且在贯通孔中形成凹槽；对凹槽下方的第一导电材料和第二导电材料进行蚀刻以形成中间贯通孔；在第一导电材料或第二导电材料的表面上并且在中间贯通孔中沉积绝缘材料以形成中间结构；对中间结构进行抛光，直至露出绝缘层；以及对第一导电材料进行选择性刻蚀，以形成多个第二电极。通过使用沉积和抛光工艺，可以使得电极表面和绝缘表面平齐，确保了各个第二电极中的第二导电材料相对于第一电极的距离基本上一致，从而进一步提升阻变存储器的性能的一致性和稳定性。此外，通过使得第二导电材料相比于第一导电材料突出，换言之第二导电材料更接近于第一电极层，可以使得导电丝聚集在第二导电材料的尖端形成，从而可以使得导电丝的产生更为聚集和均匀，提升存储器的整体性能。此外，还可以减少金属材料的使用节省成本。
在一些实施例中，多个第二电极被均匀布置在第二电极层中。多个第二电极与阻变介电层接触的总表面面积不高于第二电极层与阻变介电层接触的表面面积的60％、50％、40％、30％、20％或10％。通过限制第二电极在第二电极层中的密度，可以确保加工过程中的离子扩散和热串扰不会显著影响阻变存储器的性能。
在1308，在绝缘层上形成阻变介电层。在一个实施例中，以使用沉积，例如物理气相沉积或原子层沉积，来形成阻变介电层。本公开对此不进行限制。在1310，在阻变介电层上形成第一电极层。在一个实施例中，以使用沉积，例如物理气相沉积或原子层沉积，来形成阻变介电层。备选地，也可以通过其它方法来生长第一电极层，本公开对此不进行限制。在一个实施例中，阻变存储器为导电桥阻变存储器，方法1300中涉及的第一电极包括银、铜、钛 或其组合物，阻变介电层包括氧化钽、氧化硅、氧化锆、氧化镉、氧化锗、硫化锗、碲化锗、硒化锗、硫化铜、碲化铜、硫化银或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。在一个实施例中，阻变存储器为氧缺陷空位阻变存储器，方法1300中涉及的第一电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物，阻变介电层包括氧化铪、氧化钽、氧化铝、氧化钛或其组合物，第二电极包括铂、铱、钽、钨、导电金属氮化物、非晶碳或其组合物。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (12)

  1. 一种阻变存储器，包括：
    第一电极层；
    阻变介电层；以及
    第二电极层，所述阻变介电层位于所述第一电极层和所述第二电极层之间，所述第二电极层包括：
    绝缘层；
    多个贯通孔，位于所述绝缘层中；以及
    多个第二电极，所述多个第二电极中的每个第二电极至少部分地位于所述多个贯通孔中的一个贯通孔中，并且所述多个第二电极彼此绝缘。
  2. 根据权利要求1所述的阻变存储器，其中所述第二电极与所述阻变介电层相接触；以及
    所述绝缘层与所述阻变介电层相接触。
  3. 根据权利要求1或2所述的阻变存储器，其中所述第二电极包括：
    导电部，具有环状结构或套结构，所述环状结构内部设置有内贯通孔，所述套结构设置有凹槽；以及
    绝缘柱，位于所述凹槽或所述内贯通孔中。
  4. 根据权利要求1或2所述的阻变存储器，其中所述第二电极包括：
    第一导电材料；以及
    第二导电材料，所述第二导电材料与所述第一导电材料不同，所述第二导电材料和所述第一导电材料在所述贯通孔中交替布置，所述第二导电材料在垂直于所述绝缘层中的第一方向上的尺寸大于所述第一导电材料在所述第一方向上的尺寸。
  5. 根据权利要求1-4中任一项所述的阻变存储器，其中所述多个第二电极被均匀布置在所述第二电极层中；以及
    所述多个第二电极与所述阻变介电层接触的总表面面积不高于第二电极层与所述阻变介电层接触的表面面积的60％。
  6. 根据权利要求1-5中任一项所述的阻变存储器，其中所述第一电极层为多个存储单元共有并且耦合至位线；以及
    所述多个第二电极分别是相应的所述多个存储单元的一部分，并且所述多个第二电极分别耦合至相应的多个选通管或晶体管。
  7. 根据权利要求1-6中任一项所述的阻变存储器，其中所述阻变介电层被配置成响应于所述第一电极层和所述第二电极层中的至少一个第二电极之间的电压，生成至少一个导电丝。
  8. 一种电子设备，包括
    供电装置；以及
    根据权利要求1-7中任一项所述的阻变存储器，由所述供电装置供电。
  9. 一种制造阻变存储器的方法，包括：
    在支撑层上形成绝缘层；
    在所述绝缘层中形成多个贯通孔；
    在所述多个贯通孔中的至少一部分中形成多个第二电极，所述第二电极至少部分地位于 所述多个贯通孔中的一个贯通孔中；
    在所述绝缘层上形成阻变介电层；以及
    在所述阻变介电层上形成第一电极层。
  10. 根据权利要求9所述的方法，其中在所述绝缘层中形成多个贯通孔包括对所述绝缘层进行刻蚀以形成所述多个贯通孔。
  11. 根据权利要求9或10所述的方法，其中在所述多个贯通孔中的至少一部分中形成多个第二电极包括：
    在所述绝缘层上和在所述多个贯通孔中沉积导电材料；
    在所述导电材料的表面上沉积绝缘材料以形成中间结构；以及
    对所述中间结构进行抛光，直至露出所述绝缘层，以形成所述多个第二电极。
  12. 根据权利要求9或10所述的方法，其中在所述多个贯通孔中的至少一部分中形成多个第二电极包括：
    在所述绝缘层上和在所述多个贯通孔中交替沉积第一导电材料和第二导电材料，所述第二导电材料与所述第一导电材料不同并且在所述贯通孔中形成凹槽；
    对所述凹槽下方的所述第一导电材料和所述第二导电材料进行刻蚀以形成中间贯通孔；
    在所述第一导电材料或所述第二导电材料的表面上并且在所述中间贯通孔中沉积绝缘材料以形成中间结构；
    对所述中间结构进行抛光，直至露出所述绝缘层；以及
    对所述第一导电材料进行选择性刻蚀，以形成所述多个第二电极。
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CN111769196A (zh) * 2020-07-17 2020-10-13 厦门半导体工业技术研发有限公司 阻变存储器、阻变元件及其制备方法
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WO2014158793A1 (en) * 2013-03-13 2014-10-02 Microchip Technology Incorporated Memory cell with trench-shaped bottom electrode
CN110718569A (zh) * 2019-09-02 2020-01-21 北京大学 一种基于阻变存储器的1t2r存储单元及其制备方法
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