WO2022227134A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2022227134A1
WO2022227134A1 PCT/CN2021/094388 CN2021094388W WO2022227134A1 WO 2022227134 A1 WO2022227134 A1 WO 2022227134A1 CN 2021094388 W CN2021094388 W CN 2021094388W WO 2022227134 A1 WO2022227134 A1 WO 2022227134A1
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WIPO (PCT)
Prior art keywords
inner core
array substrate
layer
rough surface
electrode
Prior art date
Application number
PCT/CN2021/094388
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English (en)
French (fr)
Inventor
吕晓文
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/419,668 priority Critical patent/US11506946B1/en
Publication of WO2022227134A1 publication Critical patent/WO2022227134A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
    • G02F1/133723—Polyimide, polyamide-imide
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • liquid crystal display technology In the field of display technology, liquid crystal display technology is the most mature, and liquid crystal display technology has penetrated deeply into modern life.
  • the liquid crystal display panel has the advantages of lightness, thinness, power saving, soft picture, etc., and is widely used in the field of display technology.
  • the liquid crystal display panel includes an array substrate and a color filter substrate arranged oppositely, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate.
  • it is usually necessary to set a specific alignment direction for the liquid crystal molecules in the liquid crystal layer that is, the surface of the array substrate close to the liquid crystal layer and the surface of the color filter substrate close to the liquid crystal layer. layer to provide a pre-tilt angle to the liquid crystal molecules, so that the arrangement of the liquid crystal molecules in the initial state presents a certain regularity.
  • the alignment liquid is first transferred to the surface of the array substrate close to the liquid crystal layer and the surface of the color filter substrate close to the liquid crystal layer, and then cured to form a film.
  • via holes are provided in many positions.
  • a protective layer is usually provided on the drain electrode of the thin film transistor, the pixel electrode is provided on the protective layer, and the via hole is opened on the protective layer to enable the pixels
  • the electrode is connected to the drain electrode. Due to the existence of the via hole, the surface of the pixel electrode is actually uneven, that is, the position corresponding to the pixel electrode and the via hole may be recessed downward to form a groove.
  • the above-mentioned grooves are usually small and smooth.
  • the problem of alignment liquid accumulation will occur in the grooves due to the mobility of the alignment liquid and the effect of molecular tension.
  • the spacer on the array substrate Post Spacer, PS
  • the problem of alignment liquid accumulation in the above-mentioned grooves is particularly serious, so that the thickness of the alignment layer at the grooves after curing and film formation may be thicker than the alignment layers at other positions, resulting in an uneven overall thickness of the alignment layer. defects, thereby reducing the display quality of the liquid crystal display panel.
  • the present application provides an array substrate and a liquid crystal display panel, so as to improve the problem of uneven overall thickness of the alignment layer near the array substrate in the existing liquid crystal display panel, thereby improving the display quality of the liquid crystal display panel.
  • the present application provides an array substrate, the array substrate comprising:
  • a first electrode layer disposed on the base substrate, and the first electrode layer includes a source electrode and a drain electrode arranged at intervals;
  • a protective layer disposed on the base substrate and covering the first electrode layer, the protective layer is provided with a via hole at a position corresponding to the drain;
  • the second electrode layer is disposed on the first electrode layer and the protective layer, the second electrode layer includes a pixel electrode, and the pixel electrode includes a connected pixel electrode body and a conducting portion, and the pixel electrode body is disposed on the protective layer, and the conducting portion is connected to the drain through the via hole;
  • the conducting portion is provided with a rough surface for draining the alignment liquid.
  • At least one side of the conducting portion away from the first electrode layer and the protective layer has a rough surface.
  • the conduction part includes a connected peripheral body and an inner core body, the outer peripheral body is disposed on the protective layer, the inner core is filled in the via hole, and the The outer body is wound around the inner core body; the outer body and/or the inner core body are provided with rough surfaces.
  • At least one side of the outer body away from the first electrode layer and the protective layer has a rough surface; and/or, the inner core body is at least away from the first electrode layer and the protective layer.
  • One side of the protective layer has a rough surface.
  • both the outer peripheral body and the inner core body are provided with the rough surface; the outer peripheral body and the inner core body are both continuous and uninterrupted structures, and the outer peripheral body and the inner core body are both continuous and uninterrupted structures.
  • the rough surfaces of the inner core are all provided with channels and/or raised structures.
  • the peripheral body is provided with the rough surface, the peripheral body is a continuous and uninterrupted structure, and the rough surface of the peripheral body is provided with channels and/or protrusions structure; the inner core body is a continuous unbroken structure without roughening treatment.
  • At least one of the peripheral body and the inner core body is a discontinuous structure, and the discontinuous structure includes a plurality of sub-sections, and the plurality of sub-sections are spaced apart from each other and electrically connected to each other. Sexual conduction.
  • the outer body is the discontinuous structure
  • the inner core body is a continuous and unbroken structure without roughening
  • the peripheral body is the discontinuous structure; the inner core is a continuous and uninterrupted structure, and the inner core is provided with a rough surface, and the inner core is The rough surface is provided with channels and/or raised structures.
  • the pixel electrode body is provided with a rough surface for draining the alignment liquid.
  • the surface of at least one side of the pixel electrode body away from the first electrode layer and the protective layer is rough.
  • the pixel electrode body is a multi-domain structure; the pixel electrode further includes a connection line, and the conduction part is connected to the pixel electrode body through the connection line.
  • the present application provides a display panel, the liquid crystal display panel includes an array substrate, and the array substrate includes:
  • a first electrode layer disposed on the base substrate, and the first electrode layer includes a source electrode and a drain electrode arranged at intervals;
  • a protective layer disposed on the base substrate and covering the first electrode layer, the protective layer is provided with a via hole at a position corresponding to the drain;
  • the second electrode layer is disposed on the first electrode layer and the protective layer, the second electrode layer includes a pixel electrode, and the pixel electrode includes a connected pixel electrode body and a conducting portion, and the pixel electrode body is disposed on the protective layer, and the conducting portion is connected to the drain through the via hole;
  • the conducting portion is provided with a rough surface for draining the alignment liquid.
  • At least one side of the conducting portion away from the first electrode layer and the protective layer has a rough surface.
  • the conduction part includes a connected peripheral body and an inner core body, the outer peripheral body is disposed on the protective layer, the inner core is filled in the via hole, and the The outer body is wound around the inner core body; the outer body and/or the inner core body are provided with rough surfaces.
  • both the outer peripheral body and the inner core body are provided with the rough surface; the outer peripheral body and the inner core body are both continuous and uninterrupted structures, and the outer peripheral body and the inner core body are both continuous and uninterrupted structures.
  • the rough surfaces of the inner core are all provided with channels and/or raised structures.
  • the peripheral body is provided with the rough surface, the peripheral body is a continuous and uninterrupted structure, and the rough surface of the peripheral body is provided with channels and/or protrusions structure; the inner core body is a continuous unbroken structure without roughening treatment.
  • At least one of the peripheral body and the inner core body is a discontinuous structure, and the discontinuous structure includes a plurality of sub-sections, and the plurality of sub-sections are spaced apart from each other and electrically connected to each other. Sexual conduction.
  • the outer body is the discontinuous structure
  • the inner core body is a continuous and unbroken structure without roughening
  • the peripheral body is the discontinuous structure; the inner core is a continuous and uninterrupted structure, and the inner core is provided with a rough surface, and the inner core is The rough surface is provided with channels and/or raised structures.
  • the present application provides an array substrate and a liquid crystal display panel.
  • the array substrate includes a base substrate, a first electrode layer, a protective layer and a second electrode layer arranged in sequence, wherein the second electrode layer includes a pixel electrode, and the pixel electrode It includes a connected pixel electrode body and a conducting portion, wherein the conducting portion is provided with a rough surface to improve the wettability and fluidity of the alignment liquid at the conducting portion to achieve the purpose of drainage, so that the alignment liquid is solidified and formed into a film.
  • the thickness of the formed alignment layer is uniform, which effectively avoids the problem of uneven brightness (Mura) of the liquid crystal display panel caused by the accumulation of redundant alignment liquid at the conduction portion, thereby improving the display quality of the liquid crystal display panel.
  • Mura uneven brightness
  • FIG. 1 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present application.
  • FIG. 2 is a top view of a conduction portion provided in an embodiment of the present application.
  • FIG. 3 is a top view of a conduction portion provided in another embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of an array substrate provided in another embodiment of the present application.
  • FIG. 5 is a top view of a conduction portion provided in another embodiment of the present application.
  • FIG. 6 is a top view of a conduction portion provided in another embodiment of the present application.
  • FIG. 7 is a top view of a pixel electrode provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a liquid crystal display panel provided in an embodiment of the present application.
  • the present application provides an array substrate, which can be applied to a liquid crystal display panel to improve the problem of uneven overall thickness of the alignment layer in the prior art due to the accumulation of redundant alignment liquids.
  • the array substrate may be a top grid array substrate or a bottom grid array substrate. The following description will be given by taking the top grid array substrate as an example.
  • the array substrate 100 includes: a base substrate 1 , a light shielding layer 2 , a buffer layer 3 , a semiconductor layer 4 , a gate insulating layer 5 , a gate layer 6 , an interlayer insulating layer 7 , and a first electrode layer 8, protective layer 9 and second electrode layer.
  • the substrate The substrate 1 may be a rigid substrate, and an example material of the rigid substrate is glass.
  • the light-shielding layer 2 is arranged on the base substrate 1, and the light-shielding layer 2 is a patterned single-layer or laminated structure.
  • the material of the light-shielding layer 2 is a light-tight conductive material, such as molybdenum (Mo),
  • a single metal such as aluminum (Al), copper (Cu), and titanium (Ti) can also be an alloy material such as a molybdenum-titanium-nickel (MoTiNi) alloy.
  • the preparation method of the light-shielding layer 2 can refer to the prior art, which will not be repeated here.
  • the buffer layer 3 is disposed on the base substrate 1 and completely covers the light shielding layer 2 .
  • the buffer layer 3 can be a single-layer structure or a laminated structure, and its material can be at least one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiOxNy), wherein x and y are positive integers .
  • the preparation method of the buffer layer 3 may refer to the prior art, which will not be repeated here.
  • the material of the semiconductor layer 4 may be, for example, a semiconductor material such as polycrystalline silicon and amorphous silicon.
  • the semiconductor layer 4 includes an active region, and the structural composition of the active region can refer to the prior art.
  • the active region includes a channel region 41 and a first doped region 42 and a second doped region located on both sides of the channel region 41 .
  • the ion doping type and doping concentration of the impurity region 43 , the first impurity region 42 and the second impurity region 43 can be selected according to actual needs.
  • the preparation method of the semiconductor layer 4 may refer to the prior art, which will not be repeated here.
  • the gate insulating layer 5 is disposed on the buffer layer 3 and covers the semiconductor layer 4 .
  • the gate insulating layer 5 may have a single-layer structure or a stacked-layer structure, and the material of the gate insulating layer 5 may be at least one of SiOx, SiNx, and SiOxNy.
  • the example gate insulating layer 5 has a stacked structure formed by alternately stacking SiOx layers and SiNx layers in sequence.
  • the preparation method of the gate insulating layer 5 may refer to the prior art, and details are not described herein again.
  • the gate layer 6 is disposed on the gate insulating layer 5, and the position of the gate layer 6 corresponds to the channel region.
  • the gate layer 6 may be a single-layer structure or a stacked structure, and the material of the gate layer 6 may be conductive materials such as metal, metal oxide, alloy, etc., for example, the material of the gate layer 6 is copper.
  • the preparation method of the gate layer 6 may refer to the prior art, which will not be repeated here.
  • the interlayer insulating layer 7 is disposed on the gate insulating layer 5 and covers the gate layer 6 .
  • the interlayer insulating layer 7 may be a single-layer structure or a stacked layer structure, and the material of the interlayer insulating layer 7 may be one of silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). at least one.
  • the preparation method of the interlayer insulating layer 7 may refer to the prior art, which will not be repeated here.
  • the first electrode layer 8 is disposed on the interlayer insulating layer 7 .
  • the first electrode layer 8 may be a single-layer structure or a laminated structure, and the material of the first electrode layer 8 may be a conductive material such as metal, metal oxide, alloy, or the like.
  • the first electrode layer 8 includes a source electrode 81 and a drain electrode 82 spaced apart, wherein the source electrode 81 passes through the interlayer insulating layer 7 and the gate insulating layer 5 to be connected to the first doped region 42 , and the drain electrode 82 passes through The interlayer insulating layer 7 and the gate insulating layer 5 are connected to the second doped region 43 .
  • the prior art which will not be repeated here.
  • the protective layer 9 is disposed on the interlayer insulating layer 7 and covers the first electrode layer 8 .
  • the protective layer 9 is a planarization layer, which has the functions of improving the surface flatness of the layer structure and insulating the first electrode layer 8 and the second electrode layer from each other.
  • the protective layer 9 can be a single-layer structure or a laminated structure, and the material of the protective layer 9 can be an organic film (Polymer Film on the array substrate side). Array, PFA).
  • the protective layer 9 is provided with via holes 91 at positions corresponding to the drain electrodes 82 .
  • the preparation method of the protective layer 9 may refer to the prior art, which will not be repeated here; in addition, the protective layer 9 may also be a passivation layer, an interlayer insulating layer, or the like.
  • the second electrode layer is disposed on the first electrode layer 8 and the protective layer 9 .
  • the second electrode layer may have a single-layer structure or a stacked structure, and the material of the second electrode layer may be a transparent metal oxide, such as indium tin oxide (In2O3:Sn, ITO).
  • a transparent metal oxide such as indium tin oxide (In2O3:Sn, ITO).
  • the second electrode layer includes a pixel electrode 10 , and the pixel electrode 10 is disposed on the protective layer 9 to be insulated from the first electrode layer 8 .
  • the pixel electrode 10 includes a connected pixel electrode body (not shown in FIG. 1 ) and a conducting portion 101 .
  • the pixel electrode body is disposed on the protective layer 9 , and the conducting portion 101 is connected to the drain 82 through the via hole 91 .
  • the conduction part 101 includes an outer body 101a and an inner core body 101b, and the outer body 101a and the inner core body 101b are connected as a whole.
  • the peripheral body 101 a is disposed on the protective layer 9 , and the inner core body 101 b is filled in the via hole 91 .
  • a (Physical Vapor Deposition, PVD) process can be used first to deposit a second electrode material layer on the protective layer 9 to form an entire second electrode material layer, and then a yellow light process technology and etching process can be used.
  • the patterned structure is prepared by etching process. Due to the existence of the via hole 91, after the second electrode material layer is deposited to form a whole surface, the surface of the second electrode material layer is often uneven, that is, the position corresponding to the via hole 91 on the second electrode material layer will be uneven. There is a problem that the grooves 102 are formed by being recessed downward. Because the groove 102 is small and the surface is smooth, when the alignment layer is prepared on the second electrode layer, the problem of alignment liquid accumulation will occur at the groove 102 , thereby causing the defect that the overall thickness of the alignment layer is not uniform.
  • the conducting portion 101 is provided with a rough surface for draining the redundant alignment liquid at the groove 102 .
  • the conducting portion 101 has a rough surface at least on one side away from the first electrode layer 8 and the protective layer 9 to serve as a drainage structure for the alignment liquid, and has the function of draining the redundant alignment liquid at the groove 102.
  • a channel and/or Raised structure to achieve the purpose of surface roughness.
  • the surface of the outer body 101a may be rough at least on the side away from the first electrode layer 8 and the protective layer 9; it may also be that the inner core 101b has a rough surface at least on the side away from the first electrode layer 8 and the protective layer 9; or The outer body 101a has a rough surface at least on the side away from the first electrode layer 8 and the protective layer 9 , and the inner core 101b has a rough surface at least on the side away from the first electrode layer 8 and the protective layer 9 .
  • the surface of the outer body 101 a away from the first electrode layer 8 and the protective layer 9 is rough, and the surface of the inner core 101 b away from the first electrode layer 8 and the protective layer 9 is rough.
  • the outer body 101a and the inner core body 101b are both continuous and uninterrupted structures.
  • a plurality of spaced and parallel first grooves are formed on the surface of the outer body 101a away from the first electrode layer 8 and the protective layer 9.
  • a plurality of second channels 104 spaced apart and parallel to each other are provided on the surface of the inner core 101b away from the first electrode layer 8 and the protective layer 9 on the side surface of the channel 103 .
  • Each of the first channels 103 forms an included angle ⁇ with the horizontal direction
  • each of the second channels 104 forms an included angle ⁇ with the horizontal direction.
  • the angles of the included angle ⁇ and the included angle ⁇ are both exemplified as 45 degrees.
  • the first channel and the second channel can be prepared by a yellow light manufacturing process and an etching process, and preferably, the first channel and the second channel are prepared by using the same mask.
  • the shape, size, arrangement and other property parameters of the first channel and the second channel are not specifically limited, and can be selected according to actual needs, and only need to meet the conditions: under the premise of normal operation of the array substrate, the grooves can be drained. alignment fluid.
  • the shape, size and arrangement of the first channel and the second channel may be the same or different.
  • the property parameters (such as: shape, size, arrangement, etc.) of the plurality of first channels may be the same or different; similarly, the property parameters (such as: shape of the plurality of second channels) , size, arrangement, etc.) can be the same or different.
  • the angle values of the included angle ⁇ and the included angle ⁇ are not specifically limited, and can be any value within the range of 0 degrees to 180 degrees.
  • the included angle ⁇ and the included angle ⁇ can be 0 degrees, 15 degrees, 20 degrees, and 30 degrees, respectively. , 45 degrees, 60 degrees, 80 degrees, 90 degrees, 100 degrees, 115 degrees, 135 degrees, 155 degrees, 180 degrees and other integer values, and the angle value can also be a non-integer value.
  • the included angle ⁇ and the included angle ⁇ may be the same or different.
  • first channel and/or the second channel can be replaced with a protruding structure, or a protruding structure can be provided in the first channel and/or the second channel (eg, on the trench wall), or the adjacent Protrusion structures are arranged between the first channels and/or between the adjacent second grooves.
  • the peripheral body 101a is a continuous and uninterrupted structure, and at least one channel and/or at least one protrusion is provided on the side surface of the peripheral body 101a away from the first electrode layer 8 and the protective layer 9 Structure; the inner core 101b is a continuous and unbroken structure without roughening.
  • the outer body 101a and the inner core 101b are both continuous and uninterrupted structures.
  • the plurality of first channels 103 are distributed in a divergent state centered on the inner core 101b, that is, the plurality of first channels 103 extend in different directions.
  • the inner core 101b is a continuous and uninterrupted structure without rough treatment. The advantage of this design is that it can effectively drain the redundant alignment liquid at the inner core 101b without reducing the contact resistance of the inner core 101b.
  • At least one of the peripheral body 101a and the inner core body 101b is a discontinuous structure, and the discontinuous structure includes a plurality of sub-sections, and the plurality of sub-sections are spaced apart from each other and are electrically conductive to each other Pass.
  • FIG. 4 shows an array substrate according to another embodiment of the present application, which is different from the array substrate shown in FIG. 1 only in that the layout of the conducting parts 101 is different.
  • the outer body 101 a and the inner core body 101 b are both discontinuous structures, wherein the outer body 101 a is composed of a plurality of outer body sub-sections 105 that are spaced apart and parallel to each other, The plurality of peripheral body sub-sections 105 are arranged along the horizontal direction and are electrically connected to each other, and there are first gaps 106 between adjacent peripheral body sub-sections 105 .
  • the inner core 101b includes a plurality of inner core sub-sections 107 that are spaced apart and parallel to each other.
  • the plurality of inner core sub-sections 107 are arranged along the horizontal direction and are electrically connected to each other. There is a second gap 108 therebetween.
  • property parameters such as: shape, size, arrangement, etc.
  • Property parameters such as: shape, size, arrangement, etc.
  • the number, shape, size and arrangement of the first slits and the second slits are not specifically limited, and can be selected according to actual needs.
  • the second slits can also be arranged in the vertical direction, and the first slits and the second slits
  • the gap width is 2.5 microns.
  • the angle between the first slit and the horizontal direction, and the angle between the second slit and the horizontal direction are not specifically limited, and can be any value within the range of 0 degrees to 180 degrees, for example, it can be 0 Integer values such as degrees, 15 degrees, 20 degrees, 30 degrees, 45 degrees, 60 degrees, 80 degrees, 90 degrees, 100 degrees, 115 degrees, 135 degrees, 155 degrees, 180 degrees, and may also be non-integer values.
  • the peripheral body 101 a is a discontinuous structure
  • the peripheral body 101 a is composed of a plurality of peripheral body sub-sections 105 spaced apart from each other
  • the inner core body 101 b is inside the plurality of peripheral body sub-sections 105
  • the center is distributed in a divergent state, that is, a plurality of peripheral body sub-sections 105 extend in different directions, and there are first gaps 106 between adjacent peripheral body sub-sections 105 .
  • the inner core 101b is a continuous and uninterrupted structure without rough treatment. The advantage of this design is that it can effectively drain the redundant alignment liquid at the inner core 101b without reducing the contact resistance of the inner core 101b.
  • the peripheral body 101 a is a discontinuous structure, the peripheral body 101 a is composed of a plurality of peripheral body sub-sections 105 spaced apart from each other, and the plurality of peripheral body sub-sections 105 have an inner core body 101 b
  • the center is distributed in a divergent state, that is, a plurality of peripheral body sub-sections 105 extend in different directions, and there are first gaps 106 between adjacent peripheral body sub-sections 105 .
  • the inner core body 101b is a continuous and uninterrupted structure, and a plurality of second channels 104 spaced apart and parallel to each other are provided on the surface of the inner core body 101b away from the first electrode layer and the protective layer.
  • a plurality of second channels 104 Arranged along the horizontal direction, each of the second channels 104 is perpendicular to the horizontal direction.
  • the pixel electrode body may have a multi-domain structure.
  • the pixel electrode 10 includes a conducting portion 101 , a pixel electrode body 109 and a connecting line 110 , and the conducting portion 101 is connected to the pixel electrode body 109 through the connecting line 110 .
  • the conducting portion 101 is composed of a connected outer body 101a and an inner core body 101b, and the outer body 101a is wound around the inner core body 101b.
  • the pixel electrode body 109 has a four-piece structure.
  • the pixel electrode body 109 includes a first trunk electrode 109a, a second trunk electrode 109b and a plurality of branch electrodes 109c.
  • the first trunk electrode 109a and the second trunk electrode 109b are perpendicular to each other and have a cross shape.
  • Each domain is provided with a plurality of mutually spaced and parallel branch electrodes 109c, the branch electrodes 109c in each domain extend in the same direction, and the branch electrodes 109c in different domains have different extension directions, and the adjacent chips are about the first backbone.
  • the electrode 109a or the second trunk electrode 109b is symmetrical, and the two chips on the diagonal line are centrally symmetric about the intersection between the first trunk electrode 109a and the second trunk electrode 109b.
  • the pixel electrode body 109 may also have other multi-chip structures, for example, the pixel electrode body 109 is an eight-chip structure, which is not specifically limited here, and can be selected according to actual needs.
  • the array substrate of the embodiments of the present application also includes other known structures, such as: data lines connected to the drain, scan lines connected to the gate, common electrodes, passivation layers, capacitors Electrodes, etc., can be arranged by those skilled in the art as required.
  • the embodiments of the present application also provide a liquid crystal display panel, and the liquid crystal display panel may be a conventional liquid crystal display panel or a multi-domain liquid crystal display panel.
  • the liquid crystal display panel 1000 includes: an array substrate 100 , a color filter substrate 200 , a liquid crystal layer 300 , a first alignment layer 400 and a second alignment layer 500 .
  • the array substrate 100 is any one of the array substrates 100 disclosed in the embodiments of this application.
  • An example of a material of the first alignment layer 400 is polyimide, and the first alignment layer 400 is disposed on the side of the array substrate 100 close to the liquid crystal layer 300 .
  • the color filter substrate 200 is disposed opposite to the array substrate 100 , and the liquid crystal layer 300 is sandwiched between the array substrate 100 and the color filter substrate 200 .
  • An example of a material of the second alignment layer 500 is polyimide, and the second alignment layer 500 is disposed on the side of the color filter substrate 200 close to the liquid crystal layer 300 .
  • liquid crystal display panel of the embodiment of the present application may also include some other known structures, such as: a spacer (Post Spacer, PS), polarizer, etc.
  • a spacer Post Spacer, PS
  • polarizer etc.
  • the liquid crystal display panels of the embodiments of the present application can be applied to various electronic products with display functions, such as mobile phones, computers, digital cameras, digital video cameras, game consoles, audio reproduction devices, information terminals, and smart wearable devices.
  • Any product or component with a display function such as equipment, smart weighing electronic scales, on-board monitors, TV sets, etc., where the smart wearable devices can be smart bracelets, smart watches, smart glasses, etc.

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Abstract

一种阵列基板(100)及液晶显示面板，阵列基板(100)包括依次设置的衬底基板(1)、第一电极层(8)、保护层(9)和第二电极层，其中，第二电极层包括像素电极(10)，像素电极(10)包括相连的像素电极本体和导通部(101)，导通部(101)设置有粗糙面以用于引流导通部(101)处的冗余配向液，使得配向液固化成膜后所形成的配向层厚度均匀。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
在显示技术领域，液晶显示技术发展最为成熟，液晶显示技术已深入渗透至现代生活中。液晶显示面板具有轻薄、省电、画面柔和等优点，其在显示技术领域应用广泛。液晶显示面板包括相对设置的阵列基板和彩膜基板，以及夹设于阵列基板和彩膜基板之间的液晶层。为了使液晶显示面板具有理想的响应速度及显示效果，通常需要对液晶层中的液晶分子设置特定的配向方向，即在阵列基板靠近液晶层的表面以及彩膜基板靠近液晶层的表面分别设置配向层以向液晶分子提供预倾角，从而促使液晶分子在初始状态的排列呈现一定规律。
 技术问题
在配向层的制备过程中，配向液先被转印至阵列基板靠近液晶层的表面以及彩膜基板靠近液晶层的表面，然后固化成膜。在液晶显示面板的阵列基板中，很多位置都设有过孔，例如：在薄膜晶体管的漏极上通常设有保护层，保护层上设有像素电极，保护层上开设有过孔以使像素电极与漏极相连，由于过孔的存在，所以实际上像素电极的表面并不平整，即在像素电极与过孔相对应的位置处会存在向下凹陷而形成凹槽的问题。上述凹槽通常较小且表面光滑，当在像素电极上制备配向层时，基于配向液的流动性以及分子张力作用，所述凹槽处会出现配向液堆积的问题。对于间垫物形成于彩膜基板(Post Spacer On Color Filter, POC)上的液晶显示面板来说，由于阵列基板上无间垫物(Post Spacer, PS)引流配向液，所以上述凹槽处配向液堆积的问题尤为严重，使得固化成膜后凹槽处配向层的厚度可能厚于其他位置处的配向层，造成配向层整体厚度不均匀的缺陷，进而降低液晶显示面板的显示品质。
 技术解决方案
本申请提供了一种阵列基板及液晶显示面板，以改善现有液晶显示面板中靠近阵列基板一侧的配向层整体厚度不均匀的问题，从而提高液晶显示面板的显示品质。
第一方面，本申请提供了一种阵列基板，所述阵列基板包括：
衬底基板；
第一电极层，设置于所述衬底基板上，所述第一电极层包括间隔设置的源极和漏极；
保护层，设置于所述衬底基板上，并且覆盖所述第一电极层，所述保护层在与所述漏极相对应的位置处设有过孔；以及
第二电极层，设置于所述第一电极层及所述保护层上，所述第二电极层包括像素电极，所述像素电极包括相连的像素电极本体和导通部，所述像素电极本体设置于所述保护层上，所述导通部穿过所述过孔与所述漏极相连；
其中，所述导通部设置有粗糙面以用于引流配向液。
在本申请的一些实施例中，所述导通部至少远离所述第一电极层和所述保护层的一侧表面粗糙。
在本申请的一些实施例中，所述导通部包括相连的外围体和内芯体，所述外围体设置于所述保护层上，所述内芯填充于所述过孔内，并且所述外围体绕设于所述内芯体的周围；所述外围体和/或所述内芯体设置有粗糙面。
在本申请的一些实施例中，所述外围体至少远离所述第一电极层和所述保护层的一侧表面粗糙；和/或，所述内芯体至少远离所述第一电极层和所述保护层的一侧表面粗糙。
在本申请的一些实施例中，所述外围体和所述内芯体均设置有所述粗糙面；所述外围体和所述内芯体均为连续不间断结构，所述外围体和所述内芯体的所述粗糙面均设置有沟道和/或凸起结构。
在本申请的一些实施例中，所述外围体设置有所述粗糙面，且所述外围体为连续不间断结构，且所述外围体的所述粗糙面设有沟道和/或凸起结构；所述内芯体为未经粗糙处理的连续不间断结构。
在本申请的一些实施例中，所述外围体和所述内芯体中的至少一者为间断结构，所述间断结构包括多个子部，所述多个子部彼此之间间隔设置且相互电性导通。
在本申请的一些实施例中，所述外围体为所述间断结构，所述内芯体为未经粗糙处理的连续不间断结构。
在本申请的一些实施例中，所述外围体为所述间断结构；所述内芯体为连续不间断结构，且所述内芯体设置有粗糙面，且所述内芯体的所述粗糙面设有沟道和/或凸起结构。
在本申请的一些实施例中，所述像素电极本体设置有粗糙面以用于引流配向液。
在本申请的一些实施例中，所述像素电极本体至少远离所述第一电极层和所述保护层的一侧表面粗糙。
在本申请的一些实施例中，所述像素电极本体为多畴结构；所述像素电极还包括连接线，所述导通部通过所述连接线与所述像素电极本体相连。
第二方面，本申请提供了一种显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括：
衬底基板；
第一电极层，设置于所述衬底基板上，所述第一电极层包括间隔设置的源极和漏极；
保护层，设置于所述衬底基板上，并且覆盖所述第一电极层，所述保护层在与所述漏极相对应的位置处设有过孔；以及
第二电极层，设置于所述第一电极层及所述保护层上，所述第二电极层包括像素电极，所述像素电极包括相连的像素电极本体和导通部，所述像素电极本体设置于所述保护层上，所述导通部穿过所述过孔与所述漏极相连；
其中，所述导通部设置有粗糙面以用于引流配向液。
在本申请的一些实施例中，所述导通部至少远离所述第一电极层和所述保护层的一侧表面粗糙。
在本申请的一些实施例中，所述导通部包括相连的外围体和内芯体，所述外围体设置于所述保护层上，所述内芯填充于所述过孔内，并且所述外围体绕设于所述内芯体的周围；所述外围体和/或所述内芯体设置有粗糙面。
在本申请的一些实施例中，所述外围体和所述内芯体均设置有所述粗糙面；所述外围体和所述内芯体均为连续不间断结构，所述外围体和所述内芯体的所述粗糙面均设置有沟道和/或凸起结构。
在本申请的一些实施例中，所述外围体设置有所述粗糙面，且所述外围体为连续不间断结构，且所述外围体的所述粗糙面设有沟道和/或凸起结构；所述内芯体为未经粗糙处理的连续不间断结构。
在本申请的一些实施例中，所述外围体和所述内芯体中的至少一者为间断结构，所述间断结构包括多个子部，所述多个子部彼此之间间隔设置且相互电性导通。
在本申请的一些实施例中，所述外围体为所述间断结构，所述内芯体为未经粗糙处理的连续不间断结构。
在本申请的一些实施例中，所述外围体为所述间断结构；所述内芯体为连续不间断结构，且所述内芯体设置有粗糙面，且所述内芯体的所述粗糙面设有沟道和/或凸起结构。
 有益效果
本申请提供了一种阵列基板及液晶显示面板，所述阵列基板包括依次设置的衬底基板、第一电极层、保护层和第二电极层，其中，第二电极层包括像素电极，像素电极包括相连的像素电极本体和导通部，其中，所述导通部设置有粗糙面以提高导通部处配向液的浸润性和流动性而达到引流的目的，使得配向液固化成膜后所形成的配向层厚度均匀，有效避免因导通部处冗余配向液堆积而造成液晶显示面板亮度不均匀(Mura)的问题，进而提升液晶显示面板的显示品质。
 附图说明
图1是本申请一个实施例中提供的阵列基板的截面示意图。
图2是本申请一个实施例中提供的导通部的俯视图。
图3是本申请另一个实施例中提供的导通部的俯视图。
图4是本申请另一个实施例中提供的阵列基板的截面示意图。
图5是本申请另一个实施例中提供的导通部的俯视图。
图6是本申请另一个实施例中提供的导通部的俯视图。
图7是本申请一个实施例中提供的像素电极的俯视图。
图8是本申请一个实施例中提供的液晶显示面板的结构示意图。
 本发明的实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。
在本申请的描述中，需要理解的是，术语“上”、“下”、“水平”、“竖直”、“一侧”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请提供了一种阵列基板，所述阵列基板能够应用于液晶显示面板中，以改善现有技术中因冗余配向液堆积而造成配向层整体厚度不均匀的问题。所述阵列基板可以是顶栅式阵列基板，也可以是底栅式阵列基板，下面以顶栅式阵列基板为例进行说明。
如图1所示，所述阵列基板100包括：衬底基板1、遮光层2、缓冲层3、半导体层4、栅极绝缘层5、栅极层6、层间绝缘层7、第一电极层8、保护层9以及第二电极层。
具体的，衬底基板1可以是刚性衬底，示例刚性衬底的材料为玻璃。
遮光层2设置于衬底基板1上，遮光层2为图案化的单层或叠层结构，遮光层2的材料为不透光导电材料，不透光导电材料例如可以是钼(Mo)、铝(Al)、铜(Cu) 、钛(Ti)等单种金属，也可以是诸如钼钛镍(MoTiNi)合金之类的合金材料。遮光层2的制备方法可以参照现有技术，在此不再赘述。
缓冲层3设置于衬底基板1上，并且完全覆盖遮光层2。缓冲层3可以是单层结构或叠层结构，其材料可以是氧化硅(SiOx)、氮化硅(SiNx)以及氮氧化硅(SiOxNy)中的至少一种，其中，x和y为正整数。缓冲层3的制备方法可以参照现有技术，在此不再赘述。
半导体层4的材料例如可以是多晶硅、非晶硅等半导体材料。半导体层4包括有源区，有源区的结构组成可以参照现有技术，作为示例，有源区包括沟道区41以及位于沟道区41两侧的第一掺杂区42和第二掺杂区43，第一掺杂区42和第二掺杂区43的离子掺杂类型和掺杂浓度可以根据实际需要自行选择。半导体层4的制备方法可以参照现有技术，在此不再赘述。
栅极绝缘层5设置于缓冲层3上，并覆盖半导体层4。栅极绝缘层5可以是单层结构或叠层结构，栅极绝缘层5的材料可以是SiOx、SiNx以及 SiOxNy中的至少一种。示例栅极绝缘层5是SiOx层和SiNx层依次交替层叠设置而形成的叠层结构。栅极绝缘层5的制备方法可以参照现有技术，在此不再赘述。
栅极层6设置于栅极绝缘层5上，且栅极层6的位置对应于沟道区。栅极层6可以是单层结构或叠层结构，栅极层6的材料可以是金属、金属氧化物、合金等导电材料，示例栅极层6的材料为铜。栅极层6的制备方法可以参照现有技术，在此不再赘述。
层间绝缘层7设置于栅极绝缘层5上，并覆盖栅极层6。层间绝缘层7可以是单层结构或叠层结构，层间绝缘层7的材料可以是氧化硅(SiO x)、氮化硅(SiN x)以及氮氧化硅(SiO xN y)中的至少一种。层间绝缘层7的制备方法可以参照现有技术，在此不再赘述。
第一电极层8设置于层间绝缘层7上。第一电极层8可以是单层结构或叠层结构，第一电极层8的材料可以是金属、金属氧化物、合金等导电材料。第一电极层8包括间隔设置的源极81和漏极82，其中，源极81穿过层间绝缘层7和栅极绝缘层5以与第一掺杂区42连接，漏极82穿过层间绝缘层7和栅极绝缘层5以与第二掺杂区43连接。第一电极层8的制备方法可以参照现有技术，在此不再赘述。
保护层9设置于层间绝缘层7上，并覆盖第一电极层8。在本申请实施例中，保护层9为平坦化层，具有提高层结构表面平整度、使第一电极层8和第二电极层彼此绝缘的作用。保护层9可以单层结构或叠层结构，保护层9的材料可以是阵列基板侧有机膜(Polymer Film on Array, PFA)。保护层9在与漏极82相对应的位置设有过孔91。保护层9的制备方法可以参照现有技术，在此不再赘述；此外，保护层9也可以是钝化层、层间绝缘层等。
第二电极层设置于第一电极层8及保护层9上。第二电极层可以是单层结构或叠层结构，第二电极层的材料可以是透明的金属氧化物，如氧化铟锡(In2O3:Sn, ITO)。第二电极层的制备方法可以参照现有技术，在此不再赘述。
第二电极层包括像素电极10，像素电极10设置于保护层9上以与第一电极层8相绝缘。像素电极10包括相连的像素电极本体(图1中未标示)和导通部101，像素电极本体设置于保护层9上，导通部101穿过过孔91与漏极82相连。导通部101包括外围体101a和内芯体101b，外围体101a和内芯体101b连为一体。外围体101a设置于保护层9上，内芯体101b填充于过孔91内。
需要说明的是，在制备第二电极层的过程中，可以先采用(Physical Vapor Deposition, PVD)工艺在保护层9上沉积形成整面的第二电极材料层，然后采用黄光制程工艺和刻蚀工艺制备图案化结构。由于过孔91的存在，所以当沉积形成整面的第二电极材料层后，第二电极材料层的表面往往并不平整，即第二电极材料层上与过孔91相对应的位置处会存在向下凹陷而形成凹槽102的问题。因为凹槽102较小且表面光滑，所以当在第二电极层上制备配向层时，凹槽102处会出现配向液堆积的问题，进而造成配向层整体厚度不均匀的缺陷。
基于此，导通部101设置有粗糙面以用于引流凹槽102处的冗余配向液。导通部101至少远离第一电极层8和保护层9的一侧表面粗糙以作为配向液的引流结构，具有引流凹槽102处冗余配向液的作用，例如可以通过设置沟道和/或凸起结构来达到表面粗糙的目的。此外，可以是外围体101a至少远离第一电极层8和保护层9的一侧表面粗糙；也可以是内芯体101b至少远离第一电极层8和保护层9的一侧表面粗糙；也可以是外围体101a至少远离第一电极层8和保护层9的一侧表面粗糙，且内芯体101b至少远离第一电极层8和保护层9的一侧表面粗糙。
如图1和图2所示，外围体101a远离第一电极层8和保护层9的一侧表面粗糙，且内芯体101b远离第一电极层8和保护层9的一侧表面粗糙。外围体101a和内芯体101b均为连续不间断结构，在水平方向上，外围体101a远离第一电极层8和保护层9的一侧表面上设有多个相互间隔且平行的第一沟道103，内芯体101b远离第一电极层8和保护层9的一侧表面上设有多个相互间隔且平行的第二沟道104。各个第一沟道103与水平方向形成夹角α，各个第二沟道104与水平方向形成夹角β，夹角α和夹角β的角度均示例为45度。
需要说明的是，第一沟道和第二沟道可以采用黄光制程工艺和刻蚀工艺制备，优选第一沟道和第二沟道采用同一光罩制备。第一沟道和第二沟道的形状、尺寸、排列方式等性质参数均不作具体限定，可以依据实际需要自行选择，仅需满足条件：在阵列基板正常工作的前提下，能够引流凹槽处的配向液。第一沟道和第二沟道的形状、尺寸以及排列方式可以相同，也可以不相同。多个第一沟道彼此之间的性质参数(如：形状、尺寸、排列方式等)可以相同，也可以不相同；同理，多个第二沟道彼此之间的性质参数(如：形状、尺寸、排列方式等)可以相同，也可以不相同。
夹角α和夹角β的角度值不作具体限定，可以在0度至180度的范围内任意取值，例如夹角α和夹角β可以分别是0度、15度、20度、30度、45度、60度、80度、90度、100度、115度、135度、155度、180度等整数值，角度值也可以是非整数值。夹角α和夹角β可以相同，也可以不相同。
此外，可以将第一沟道和/或第二沟道替换为凸起结构，或者在第一沟道内和/或第二沟道内(如：沟壁上)设置凸起结构，或者在相邻第一沟道之间和/或相邻第二凹槽之间设置凸起结构。
在本申请的一些实施例中，外围体101a为连续不间断结构，且外围体101a远离第一电极层8和保护层9的一侧表面上设有至少一个沟道和/或至少一个凸起结构；内芯体101b为未经粗糙处理的连续不间断结构。
作为示例，如图3所示，外围体101a和内芯体101b均为连续不间断结构，在水平方向上，外围体101a远离第一电极层和保护层的一侧表面上设有多个相互间隔的第一沟道103，多个第一沟道103以内芯体101b为中心呈发散状态分布，即多个第一沟道103沿着不同方向延伸。内芯体101b为未经粗糙处理的连续不间断结构，这样设计的优点在于：既能有效引流内芯体101b处的冗余配向液，又不会降低内芯体101b的接触阻抗。
在本申请的一些实施例中，外围体101a和内芯体101b中的至少一者为间断结构，所述间断结构包括多个子部，所述多个子部彼此之间间隔设置且相互电性导通。
作为示例，图4示出了本申请另一个实施例的阵列基板，其与图1所示阵列基板的区别之处仅在于：导通部101的布设不相同。如图4所示，在阵列基板100的导通部101中，外围体101a和内芯体101b均为间断结构，其中，外围体101a由多个相互间隔且平行的外围体子部105组成，多个外围体子部105沿着水平方向排列且彼此之间电性导通，相邻外围体子部105之间具有第一缝隙106。内芯体101b包括多个相互间隔且平行的内芯体子部107，多个内芯体子部107沿着水平方向排列且彼此之间电性导通，相邻内芯体子部107之间具有第二缝隙108。
需要说明的是，多个外围体子部彼此之间的性质参数(如：形状、尺寸、排列方式等)可以相同，也可以不相同；同理，多个内芯体子部彼此之间的性质参数(如：形状、尺寸、排列方式等)可以相同，也可以不相同。
第一缝隙和第二缝隙的数量、形状、尺寸和排列方式均不作具体限定，可依据实际需要自行选择，例如第二缝隙也可以沿着竖直方向排列，又如第一缝隙和第二缝隙的隙宽均为2.5微米。
此外，第一缝隙与水平方向之间的夹角度数，以及第二缝隙与水平方向之间的夹角度数不作具体限定，可以在0度至180度的范围内任意取值，例如可以是0度、15度、20度、30度、45度、60度、80度、90度、100度、115度、135度、155度、180度等整数值，也可以是非整数值。
作为示例，如图5所示，在导通部101中，外围体101a为间断结构，外围体101a由多个相互间隔的外围体子部105组成，多个外围体子部105以内芯体101b为中心呈发散状态分布，即多个外围体子部105沿着不同方向延伸，相邻外围体子部105之间具有第一缝隙106。内芯体101b为未经粗糙处理的连续不间断结构，这样设计的优点在于：既能有效引流内芯体101b处的冗余配向液，又不会降低内芯体101b的接触阻抗。
作为示例，如图6所示，在导通部101中，外围体101a为间断结构，外围体101a由多个相互间隔的外围体子部105组成，多个外围体子部105以内芯体101b为中心呈发散状态分布，即多个外围体子部105沿着不同方向延伸，相邻外围体子部105之间具有第一缝隙106。内芯体101b为连续不间断结构，且内芯体101b远离第一电极层和保护层的一侧表面上设有多个相互间隔且平行的第二沟道104，多个第二沟道104沿着水平方向排列，各个第二沟道104与水平方向相垂直。
在本申请的一些实施例中，像素电极本体至少远离第一电极层和保护层的一侧表面粗糙，以进一步引流导通部处的冗余配向液，例如像素电极本体可以是多畴结构。
作为示例，如图7所示，像素电极10包括导通部101、像素电极本体109以及连接线110，导通部101通过连接线110与像素电极本体109连接。导通部101由相连的外围体101a和内芯体101b组成，外围体101a绕设于内芯体101b的周围。像素电极本体109为四筹结构，像素电极本体109包括第一主干电极109a、第二主干电极109b以及多个分支电极109c，第一主干电极109a与第二主干电极109b相垂直且呈十字形，从而形成田字形排布的四个畴。每一畴内均设有多个相互间隔且平行的分支电极109c，每一畴内分支电极109c的延伸方向相同，不同畴内分支电极109c的延伸方向不相同，且相邻筹关于第一主干电极109a或第二主干电极109b对称，处于对角线的两个筹关于第一主干电极109a与第二主干电极109b之间的相交处呈中心对称。
需要说明的是，像素电极本体109也可以是其他的多筹结构，例如像素电极本体109为八筹结构，在此不作具体限定，可以依据实际需要自行选择。
本领域技术人员可以理解的是，本申请实施例的阵列基板还包括其他一些已知结构，如：与漏极连接的数据线、与栅极连接的扫描线、公共电极、钝化层、电容电极等，本领域技术人员可以自行依需布设。
本申请实施例还提供了一种液晶显示面板，所述液晶显示面板可以是常规液晶显示面板，也可以是多畴液晶显示面板。如图8所示，所述液晶显示面板1000包括：阵列基板100、彩膜基板200、液晶层300、第一配向层400以及第二配向层500。
阵列基板100是本申请实施例中公开的任意一种阵列基板100。
第一配向层400的材料示例为聚酰亚胺，第一配向层400设置于阵列基板100靠近液晶层300的一侧上。彩膜基板200与阵列基板100相对设置，液晶层300夹设于阵列基板100与彩膜基板200之间。第二配向层500的材料示例为聚酰亚胺，第二配向层500设置于彩膜基板200靠近液晶层300的一侧上。
本领域技术人员可以理解的是，本申请实施例的液晶显示面板还可以包括其他一些已知结构，如：间垫物(Post Spacer, PS)、偏光片等。
本申请实施例的液晶显示面板可以应用于各种具有显示功能的电子产品中，电子产品例如可以是手机、电脑、数码相机、数码摄像机、游戏机、音频再生装置、信息终端机、智能可穿戴设备、智能称重电子秤、车载显示器、电视机等任何具有显示功能的产品或部件，其中，所述智能可穿戴设备可为智能手环、智能手表、智能眼镜等。
本申请已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    衬底基板；
    第一电极层，设置于所述衬底基板上，所述第一电极层包括间隔设置的源极和漏极；
    保护层，设置于所述衬底基板上，并且覆盖所述第一电极层，所述保护层在与所述漏极相对应的位置处设有过孔；以及
    第二电极层，设置于所述第一电极层及所述保护层上，所述第二电极层包括像素电极，所述像素电极包括相连的像素电极本体和导通部，所述像素电极本体设置于所述保护层上，所述导通部穿过所述过孔与所述漏极相连；
    其中，所述导通部设置有粗糙面以用于引流配向液。
  2. 根据权利要求1所述的阵列基板，其中，所述导通部至少远离所述第一电极层和所述保护层的一侧表面粗糙。
  3. 根据权利要求1所述的阵列基板，其中，所述导通部包括相连的外围体和内芯体，所述外围体设置于所述保护层上，所述内芯填充于所述过孔内，并且所述外围体绕设于所述内芯体的周围；所述外围体和/或所述内芯体设置有粗糙面。
  4. 根据权利要求3所述的阵列基板，其中，所述外围体至少远离所述第一电极层和所述保护层的一侧表面粗糙；和/或，所述内芯体至少远离所述第一电极层和所述保护层的一侧表面粗糙。
  5. 根据权利要求3所述的阵列基板，其中，所述外围体和所述内芯体均设置有所述粗糙面；所述外围体和所述内芯体均为连续不间断结构，所述外围体和所述内芯体的所述粗糙面均设置有沟道和/或凸起结构。
  6. 根据权利要求3所述的阵列基板，其中，所述外围体设置有所述粗糙面，且所述外围体为连续不间断结构，且所述外围体的所述粗糙面设有沟道和/或凸起结构；所述内芯体为未经粗糙处理的连续不间断结构。
  7. 根据权利要求3所述的阵列基板，其中，所述外围体和所述内芯体中的至少一者为间断结构，所述间断结构包括多个子部，所述多个子部彼此之间间隔设置且相互电性导通。
  8. 根据权利要求7所述的阵列基板，其中，所述外围体为所述间断结构，所述内芯体为未经粗糙处理的连续不间断结构。
  9. 根据权利要求7所述的阵列基板，其中，所述外围体为所述间断结构；所述内芯体为连续不间断结构，且所述内芯体设置有粗糙面，且所述内芯体的所述粗糙面设有沟道和/或凸起结构。
  10. 根据权利要求1所述的阵列基板，其中，所述像素电极本体设置有粗糙面以用于引流配向液。
  11. 根据权利要求10所述的阵列基板，其中，所述像素电极本体至少远离所述第一电极层和所述保护层的一侧表面粗糙。
  12. 根据权利要求11所述的阵列基板，其中，所述像素电极本体为多畴结构；所述像素电极还包括连接线，所述导通部通过所述连接线与所述像素电极本体相连。
  13. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板，所述阵列基板包括：
    衬底基板；
    第一电极层，设置于所述衬底基板上，所述第一电极层包括间隔设置的源极和漏极；
    保护层，设置于所述衬底基板上，并且覆盖所述第一电极层，所述保护层在与所述漏极相对应的位置处设有过孔；以及
    第二电极层，设置于所述第一电极层及所述保护层上，所述第二电极层包括像素电极，所述像素电极包括相连的像素电极本体和导通部，所述像素电极本体设置于所述保护层上，所述导通部穿过所述过孔与所述漏极相连；
    其中，所述导通部设置有粗糙面以用于引流配向液。
  14. 根据权利要求13所述的阵列基板，其中，所述导通部至少远离所述第一电极层和所述保护层的一侧表面粗糙。
  15. 根据权利要求13所述的阵列基板，其中，所述导通部包括相连的外围体和内芯体，所述外围体设置于所述保护层上，所述内芯填充于所述过孔内，并且所述外围体绕设于所述内芯体的周围；所述外围体和/或所述内芯体设置有粗糙面。
  16. 根据权利要求15所述的阵列基板，其中，所述外围体和所述内芯体均设置有所述粗糙面；所述外围体和所述内芯体均为连续不间断结构，所述外围体和所述内芯体的所述粗糙面均设置有沟道和/或凸起结构。
  17. 根据权利要求15所述的阵列基板，其中，所述外围体设置有所述粗糙面，且所述外围体为连续不间断结构，且所述外围体的所述粗糙面设有沟道和/或凸起结构；所述内芯体为未经粗糙处理的连续不间断结构。
  18. 根据权利要求15所述的阵列基板，其中，所述外围体和所述内芯体中的至少一者为间断结构，所述间断结构包括多个子部，所述多个子部彼此之间间隔设置且相互电性导通。
  19. 根据权利要求18所述的阵列基板，其中，所述外围体为所述间断结构，所述内芯体为未经粗糙处理的连续不间断结构。
  20. 根据权利要求18所述的阵列基板，其中，所述外围体为所述间断结构；所述内芯体为连续不间断结构，且所述内芯体设置有粗糙面，且所述内芯体的所述粗糙面设有沟道和/或凸起结构。
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