WO2022221986A1 - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- WO2022221986A1 WO2022221986A1 PCT/CN2021/088066 CN2021088066W WO2022221986A1 WO 2022221986 A1 WO2022221986 A1 WO 2022221986A1 CN 2021088066 W CN2021088066 W CN 2021088066W WO 2022221986 A1 WO2022221986 A1 WO 2022221986A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 219
- 239000002184 metal Substances 0.000 claims abstract description 219
- 239000000463 material Substances 0.000 claims abstract description 50
- 239000010410 layer Substances 0.000 claims description 711
- 238000002955 isolation Methods 0.000 claims description 38
- 239000011229 interlayer Substances 0.000 claims description 29
- 230000004913 activation Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 2
- DUFGEJIQSSMEIU-UHFFFAOYSA-N [N].[Si]=O Chemical compound [N].[Si]=O DUFGEJIQSSMEIU-UHFFFAOYSA-N 0.000 claims 1
- AUEPDNOBDJYBBK-UHFFFAOYSA-N [Si].[C-]#[O+] Chemical compound [Si].[C-]#[O+] AUEPDNOBDJYBBK-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 35
- 238000005516 engineering process Methods 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- ADKPKEZZYOUGBZ-UHFFFAOYSA-N [C].[O].[Si] Chemical compound [C].[O].[Si] ADKPKEZZYOUGBZ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
Definitions
- FIG. 1 is a structural diagram of a semiconductor device prepared by a low-temperature hybrid bonding technology in the semiconductor field. As shown in FIG. 1, the semiconductor device is obtained by bonding two sub-devices 101. Each sub-device 101 includes a semiconductor substrate 103, an insulating layer 104, a metal wiring layer 105, an insulating layer 106 and a metal layer 107, and the metal layer 107 is embedded in the insulating layer 106 .
- the method further includes: on the first insulating layer of the first initial device Make a first bonding intermediate layer on the surface of the first bonding intermediate layer; make a groove on the first bonding intermediate layer and the first insulating layer; make a first metal layer inside the groove; The surface of the intermediate layer is bonded to obtain a first chip.
- the semiconductor device 200 can be obtained by bonding a first sub-device 201 and a second sub-device 202 .
- the first sub-device 201 includes a first insulating layer 201-1, a first metal layer 201-2, a first bonding intermediate layer 201-3 and a first sidewall insulating layer 201-31, and the second sub-device 202 includes a first interlayer 201-3.
- the material of the first diffusion barrier layer 201-5 includes but is not limited to titanium, tantalum, titanium nitride, and tantalum nitride.
- the method of fabricating the layer may be physical vapor deposition, the material of the first metal layer 201-2 may be copper, and the fabrication method may be, for example, electroplating. For the specific description thereof, reference may be made to the description of the relevant embodiments, which will not be repeated here.
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Abstract
Description
Claims (18)
- 一种半导体装置,其特征在于,包括第一芯片和第二芯片,所述第一芯片包括第一接合中间层(201-3)和第一金属层(201-2),所述第一接合中间层(201-3)上设置有开口,所述第一金属层(201-2)通过所述第一接合中间层(201-3)上的开口暴露于所述第一接合中间层(201-3)的表面;所述第二芯片包括第二接合中间层(202-3)和第二金属层(202-2),所述第二接合中间层(202-3)上设置有开口,所述第二金属层(202-2)通过所述第二接合中间层(202-3)上的开口暴露于所述第二接合中间层(202-3)的表面;所述第一接合中间层(201-3)和所述第二接合中间层(202-3)的材料包括能够通过去掉表面氧化层形成悬挂键的材料;所述第一接合中间层(201-3)与所述第二接合中间层(202-3)键合,所述第一金属层(201-2)与所述第二金属层(202-2)键合。
- 根据权利要求1所述的半导体装置,其特征在于,所述第一接合中间层(201-3)位于所述第一芯片的有源面,所述第二接合中间层(202-3)位于所述第二芯片的有源面。
- 根据权利要求1或2所述的半导体装置,其特征在于,所述第一接合中间层(201-3)与所述第一金属层(201-2)之间设置有第一侧壁绝缘层(201-31),所述第二接合中间层(202-3)与所述第二金属层(202-2)之间设置有第二侧壁绝缘层(202-31),所述第一侧壁绝缘层(201-31)为所述第一接合中间层(201-3)形成的氧化物绝缘层或氮化物绝缘层,所述第二侧壁绝缘层(202-31)为所述第二接合中间层(202-3)形成的氧化物绝缘层或氮化物绝缘层。
- 根据权利要求3所述的半导体装置,其特征在于,所述第一金属层(201-2)与所述第一侧壁绝缘层(201-31)之间设置有第一隔离层(201-4),所述第二金属层(202-2)与所述第二侧壁绝缘层(202-31)之间设置有第二隔离层(202-4),所述第一隔离层(201-4)和所述第二隔离层(202-4)的材料为绝缘材料。
- 根据权利要求4所述的半导体装置,其特征在于,所述第一隔离层(201-4)或所述第二隔离层(202-4)的材料包括以下任意一种:二氧化硅、氮化硅、硅氮氧、硅碳氮、氧化铝和硅碳氧。
- 根据权利要求4或5所述的半导体装置,其特征在于,所述半导体装置还包括第一绝缘层(201-1)、第二绝缘层(202-1)、第三绝缘层(201-6)、第四绝缘层(202-6)、第一金属布线层(201-7)、第二金属布线层(202-7)、第一扩散阻挡层(201-5)和第二扩散阻挡层(202-5);所述第一金属布线层(201-7)位于所述第三绝缘层(201-6)的凹槽中,所述第一绝缘层(201-1)覆盖在所述第三绝缘层(201-6)的表面以及覆盖在所述第一金属布线层(201-7)的一部分表面,所述第一金属布线层(201-7)的另一部分表面、所述第一绝缘层(201-1)与所述第一金属层(201-2)之间以及所述第一金属层(201-2)与所述第一隔离层(201-4)之间设置有所述扩散阻挡层(201-5);所述第二金属布线层(202-7)位于所述第四绝缘层(202-6)的凹槽中,所述第二绝缘层(202-1)覆盖在所述第四绝缘层(202-6)的表面以及覆盖在所述第二金属 布线层(202-7)的一部分表面,所述第二金属布线层(202-7)的另一部分表面、所述第二绝缘层(202-1)与所述第二金属层(202-2)之间以及所述第二金属层(202-2)与所述第二隔离层(202-4)之间设置有所述扩散阻挡层(202-5)。
- 根据权利要求6所述的方法,其特征在于,所述半导体装置还包括第一半导体衬底(201-8)和第二半导体衬底(202-8),其中,所述第三绝缘层(201-6)覆盖于所述第一半导体衬底(201-8)的表面,所述第四绝缘层(202-6)覆盖于所述第二半导体衬底(202-8)的表面。
- 根据权利要求1至7中任一项所述的半导体装置,其特征在于,所述第一接合中间层(201-3)和所述第二接合中间层(202-3)的厚度在5纳米至500纳米内。
- 根据权利要求1至8中任一项所述的半导体装置,其特征在于,所述第一接合中间层(201-3)或所述第二接合中间层(202-3)的材料包括以下任意一种:硅、碳化硅、锗、氮化铝。
- 一种半导体装置,其特征在于,包括第一芯片和第二芯片,所述第一芯片包括第一接合中间层(201-3)和第一金属层(201-2),所述第一接合中间层(201-3)上设置有开口,所述第一金属层(201-2)通过所述第一接合中间层(201-3)上的开口暴露于所述第一接合中间层(201-3)的表面;所述第二芯片包括第二接合中间层(202-3)和第二金属层(202-2),所述第二接合中间层(202-3)上设置有开口,所述第二金属层(202-2)通过所述第二接合中间层(202-3)上的开口暴露于所述第二接合中间层(202-3)的表面;所述第一接合中间层(201-3)和所述第二接合中间层(202-3)的材料包括以下任意一种:硅、碳化硅、氮化铝、锗;所述第一接合中间层(201-3)与所述第二接合中间层(202-3)键合,所述第一金属层(201-2)与所述第二金属层(202-2)键合。
- 一种半导体装置的制造方法,其特征在于,包括:在真空环境中对第一芯片的第一表面进行表面活化处理,所述第一芯片包括第一绝缘层(201-1)、第一金属层(201-2)和第一接合中间层(201-3),所述第一金属层(201-2)位于所述第一绝缘层(201-1)的凹槽中,所述第一接合中间层(201-3)覆盖在所述第一绝缘层(201-1)表面,所述第一接合中间层(201-3)上设置有开口,所述第一金属层(201-2)通过所述第一接合中间层(201-3)上的开口暴露于所述第一接合中间层(201-3)的表面,所述第一接合中间层(201-3)的材料包括能够通过去掉表面氧化层形成悬挂键的材料,所述第一表面包括所述第一接合中间层(201-3)显露出的表面和所述第一金属层(201-2)显露出的表面;所述表面活化处理包括去除第一金属层(201-2)表面的氧化层和第一接合中间层(201-3)表面的氧化层;在所述真空环境中对第二芯片的第二表面进行表面活化处理,所述第二芯片包括第二绝缘层(202-1)、第二金属层(202-2)和第二接合中间层(202-3),所述第二金属层(202-2)位于所述第二绝缘层(202-1)的凹槽中,所述第二接合中间层(202-3)覆盖在所述第二绝缘层(202-1)表面,所述第二接合中间层(202-3)上设置有开口,所述第二金属层(202-2)通过所述第二接合中间层(202-3)上的开口暴露于所述第二接合中间层(202-3)的表面,所述第二接合中间层(202-3)的材料包括能够通过 去掉表面氧化层形成悬挂键的材料,所述第二表面包括所述第二接合中间层(202-3)显露出的表面和所述第二金属层(202-1)显露出的表面;所述表面活化处理包括去除第二金属层(202-2)表面的氧化层和第二接合中间层(202-3)表面的氧化层;将所述第一芯片进行表面活化处理后的第一表面和所述第二芯片进行表面活化处理后的第二表面对位;对所述第一芯片和所述第二芯片施加压力,以使得所述第一金属层(201-2)与所述第二金属层(202-2)键合,以及使得所述第一接合中间层(201-3)与所述第二接合中间层(202-3)键合。
- 根据权利要求11所述的方法,其特征在于,在真空环境中对第一芯片的第一表面进行表面活化处理之前,所述方法还包括:在第一初始装置的所述第一绝缘层(201-1)的表面制作所述第一接合中间层(201-3);在所述第一接合中间层(201-3)和所述第一绝缘层(201-1)上制作凹槽;在所述凹槽内部制作所述第一金属层(201-2);去除所述第一接合中间层(201-3)上的所有层,以露出所述第一接合中间层(201-3)的表面,得到所述第一芯片。
- 根据权利要求12所述的方法,其特征在于,在所述凹槽内部制作所述第一金属层(201-2)之前,所述方法还包括:在所述第一接合中间层(201-3)的表面以及在所述第一接合中间层(201-3)与所述第一金属层(201-2)之间形成第一侧壁绝缘层(201-31)。
- 根据权利要求12或13所述的方法,其特征在于,所述第一金属层(201-2)露出的表面高于所述第一接合中间层(201-3)显露的表面。
- 根据权利要求12至14中任一项所述的方法,其特征在于,所述在所述第一接合中间层(201-3)和所述第一绝缘层(201-1)上制作凹槽,包括:在所述第一接合中间层(201-3)上制作第一凹槽,所述第一凹槽的深度等于或大于所述第一接合中间层(201-3)的厚度;在所述第一凹槽的表面制作第一隔离层(201-4);在所述第一凹槽的底面开口;在所述第一绝缘层(201-1)内制作第二凹槽。
- 根据权利要求12至15中任一项所述的方法,其特征在于,所述第一初始装置还包括第三绝缘层(201-6)和第一金属布线层(201-7),所述第一金属布线层(201-7)位于所述第三绝缘层(201-6)的凹槽内,所述第一绝缘层(201-1)覆盖于所述第三绝缘层(201-6)和所述第一金属布线层(201-7)上;其中,在所述第一绝缘层(201-1)内制作的第二凹槽贯穿所述第一绝缘层(201-1),露出所述第一金属布线层(201-7)。
- 根据权利要求16所述的方法,其特征在于,在所述凹槽内部制作所述第一金属层(201-2)之前,所述方法还包括:在所述第一凹槽和所述第二凹槽表面制作第一扩散阻挡层(201-5)。
- 根据权利要求11至17中任意一项所述的方法,其特征在于,所述第一接合 中间层(201-3)或所述第二接合中间层(202-3)的材料包括以下任意一种:硅、碳化硅、锗、氮化铝。
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