WO2022205707A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022205707A1
WO2022205707A1 PCT/CN2021/109155 CN2021109155W WO2022205707A1 WO 2022205707 A1 WO2022205707 A1 WO 2022205707A1 CN 2021109155 W CN2021109155 W CN 2021109155W WO 2022205707 A1 WO2022205707 A1 WO 2022205707A1
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Prior art keywords
layer
conductive
communication
forming
insulating layer
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PCT/CN2021/109155
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English (en)
French (fr)
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王路广
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长鑫存储技术有限公司
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Priority to US17/648,964 priority Critical patent/US12136568B2/en
Publication of WO2022205707A1 publication Critical patent/WO2022205707A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a semiconductor structure and a method for forming the same.
  • TSV Through-Silicon Via
  • the existing TSV structure has major problems in heat dissipation capability and influence on peripheral devices.
  • a semiconductor structure and a method of forming the same are provided.
  • a semiconductor structure comprising:
  • a substrate comprising a substrate and a dielectric layer, the substrate has a front side and a back side arranged oppositely, and the dielectric layer is formed on the front side;
  • a communication structure located in the communication hole and spaced apart from the inner wall of the communication hole;
  • the insulating structure, the inner wall of the communication hole and the communication structure are surrounded to form an air gap.
  • a method of forming a semiconductor structure comprising:
  • a substrate is provided, the substrate includes a substrate and a dielectric layer, the substrate has a front side and a back side arranged oppositely, and the dielectric layer is formed on the front side;
  • a communication structure is formed in the communication hole, and the communication structure and the inner wall of the communication hole are arranged at intervals;
  • the insulating structure, the inner wall of the communication hole and the communication structure are surrounded to form an air gap.
  • a stacked structure is formed based on any one of the above-mentioned semiconductor structures.
  • the above-mentioned semiconductor structure and its forming method due to the air gap between the communication structure and the inner wall of the communication hole, and the poor thermal conductivity of the air, can effectively prevent the heat generated by the communication structure from diffusing to the surrounding semiconductor devices or dielectric layers, thereby effectively improving the performance of the semiconductor device. Thermal performance.
  • the air gap can also effectively isolate the communication structure from the surrounding substrate and/or dielectric layer, thereby effectively preventing the substrate and/or the dielectric layer from being stressed and deformed due to the thermal expansion of the communication structure, thereby effectively preventing the lining
  • the bottom and/or dielectric layers produce interfacial cracking phenomena.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure provided in one embodiment
  • FIG. 2 is a flowchart of a method for forming a semiconductor structure provided in another embodiment
  • FIG. 3 is a flowchart of a method for forming a semiconductor structure provided in yet another embodiment
  • FIGS. 13-16 are schematic diagrams of semiconductor structures in different embodiments.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques.
  • a method for forming a semiconductor structure including:
  • Step S100 providing a substrate 100, the substrate 100 includes a substrate 110 and a dielectric layer 120, the substrate 110 has a front side 110a and a back side 110b arranged oppositely, and the dielectric layer 120 is formed on the front side 110a, please refer to FIG. 4;
  • step S200 a communication hole 100a is formed in the substrate 100, and the communication hole 100a penetrates through the substrate 110 and extends to the dielectric layer 120, please refer to FIG. 5;
  • step S300 a communication structure 200 is formed in the communication hole 100a, and the communication structure 200 and the inner wall of the communication hole 100a are arranged at intervals, please refer to FIG. 10 and FIG. 14;
  • step S400 an insulating structure 300 is formed between the communication structure 200 and the inner wall of the communication hole 100a, please refer to FIG. 11 and FIG. 14 .
  • the insulating structure 300 , the inner wall of the communication hole 100 a and the communication structure 200 are surrounded to form an air gap, please refer to FIG. 14 .
  • the substrate 110 may include, but is not limited to, a silicon substrate.
  • a shallow trench isolation structure 400 may be formed on the side of the substrate 110 close to the dielectric layer 120 .
  • the shallow trench isolation structure 400 isolates the substrate 110 into a plurality of active regions. Active regions are used to form various semiconductor devices.
  • the dielectric layer 120 may include, but is not limited to, an oxide dielectric layer (eg, silicon dioxide, etc.).
  • An interconnect via structure and a metal layer that are electrically connected to the active regions may be formed in the dielectric layer 120, so as to lead out the signals of the semiconductor device, or provide external signals for the semiconductor device.
  • step S200 the communication structure 200 is formed in the communication hole 100a.
  • the corresponding vias 100a of the respective chips are aligned, so that the vias 200 in the respective vias 100a are electrically connected, thereby realizing interconnection between the respective chips.
  • the communication structure 200 is a structure capable of conducting conductive communication, which may include a plurality of film layers.
  • the communication structure 200 may also include only one film layer, which is not limited in this application.
  • the communication structure 200 When the communication structure 200 conducts conductive communication between the chips, it will generate a lot of heat, which may affect the performance of the chips.
  • the communication structure 200 After the communication structure 200 generates heat, expansion and contraction are likely to occur due to thermal stress. If it is in contact with the substrate 110 and/or the dielectric layer 120 through an insulating structure, it may cause stress and deformation of the substrate 110 and/or the dielectric layer 120, thereby causing cracks at the contact interface, and may even affect the Semiconductor device performance in the active region.
  • the insulating structure 300 is located between the communication structure 200 and the inner wall of the communication hole 100 a , thereby achieving electrical isolation between the communication structure 200 and the substrate 110 .
  • the material of the insulating structure 300 may be silicon dioxide or the like.
  • the material of the dielectric layer 120 may be the same or different.
  • the insulating structure 300 , the inner wall of the communication hole 100 a and the communication structure 200 are surrounded to form an air gap 100 b.
  • the air gap 100 b has the same insulating properties as the insulating structure 300 , so that the electrical isolation between the communication structure 200 and the substrate 110 can be effectively achieved together with the insulating structure 300 .
  • the air gap 100b can also effectively isolate the communication structure 200 from the surrounding substrate 110 and/or the dielectric layer 120, thereby effectively preventing the substrate 110 and/or the dielectric layer 120 from being affected by the thermal expansion of the communication structure 200. stress deformation, thereby effectively preventing the occurrence of interface cracks in the substrate 110 and/or the dielectric layer 120 .
  • step S200 includes: etching the substrate 100 from the back surface 110b of the substrate 110 to form the via holes 100a.
  • the substrate 110 and the dielectric layer 120 may be sequentially etched from the back surface 110b of the substrate 110 by a dry etching method, thereby forming the via hole 100a.
  • the depth of the communication hole 100 may be 20 ⁇ m-150 ⁇ m, and the depth extending into the dielectric layer 120 may be 0.5 ⁇ m-1 ⁇ m.
  • the diameter of the communication hole 100 may be 3 ⁇ m-50 ⁇ m.
  • the aspect ratio (ie, the ratio of depth to diameter) of the communication hole 100 may be 0.4-50.
  • the present embodiment can effectively prevent the formation of the semiconductor device and related circuits in the active region when the via hole 100a is formed. damage to the circuit structure.
  • the air gap 100 b formed in step S400 penetrates the interface between the substrate 110 and the dielectric layer 120 .
  • the interface between the substrate 110 and the dielectric layer 120 is easily affected by the thermal expansion of the communication structure 200 and is subject to stress deformation, thereby causing interface cracks.
  • the air gap 100b penetrates the interface between the substrate 110 and the dielectric layer 120, so that the air gap 100b isolates the interface between the substrate 110 and the dielectric layer 120 from the communication structure 200, thereby effectively preventing the interface between the two.
  • the interface produces interface cracks.
  • semiconductor devices are dense around the interface between the substrate 110 and the dielectric layer 120 , and the semiconductor device structure generally penetrates both sides of the interface between the substrate 110 and the dielectric layer 120 .
  • the air gap 100b penetrates the interface between the substrate 110 and the dielectric layer 120, so that the air gap 100b simultaneously isolates the communication structure 200 from the substrate 110 and the dielectric layer 120 on both sides of the interface. Therefore, the present embodiment can also effectively protect the semiconductor devices around the air gap 100b from thermal insulation, and can prevent the semiconductor devices around the air gap 100b from affecting performance due to stress and deformation of the substrate 110 and/or the dielectric layer 120 .
  • the formation of the air gap 100b can effectively prevent the communication structure 200, the insulating structure 300 and the semiconductor substrate 110 from forming parasitic capacitances. Therefore, this embodiment can effectively prevent the related signal distortion or leakage current caused by the signal on the connection structure 200 being coupled to the substrate 110 or surrounding semiconductor devices or other connection structures 200 .
  • the width of the portion of the air gap 100b opposite the dielectric layer 120 is smaller than the width of the portion opposite the substrate 110 .
  • the dielectric layer 120 is a film layer formed on the substrate 110 , and its thickness is much smaller than that of the substrate 110 . Therefore, in this embodiment, the width of the portion of the air gap 100b opposite to the dielectric layer 120 is set to be small, thereby effectively preventing the air gap 100b from causing structural instability of the dielectric layer 120 .
  • the heat generated in the dielectric layer 120 is relatively large.
  • the width of the air gap 100b opposite to the substrate 110 is set to be large, so that heat will flow to the position with the large gap, which is more conducive to heat dissipation, thereby preventing influence on peripheral devices.
  • step S300 includes:
  • a first conductive structure 210 is formed in the communication hole 100a, the first conductive structure 210 is spaced apart from the inner wall of the communication hole 100a, and there is a distance between the first conductive structure 210 and the opening of the communication hole 100a, please refer to FIG. 9;
  • Step S400 includes:
  • a first insulating layer 310 is formed between the inner wall of the via hole 100 a and the first conductive structure 210 , and the distance H1 between the surface of the first insulating layer 310 and the opening of the via hole 100 a is greater than the surface of the first conductive structure 210 and the opening of the via hole 100 a .
  • the distance H2 between the openings of the communication holes 100a please refer to FIG. 10;
  • a second insulating layer 320 is formed on the inner wall of the via hole 100a, the first insulating layer 310 and the second insulating layer 320 constitute the insulating structure 300, the first insulating layer 310, the second insulating layer 320 and the inner wall of the via hole 100a and the connecting structure 200 enclosures form an air gap, see Figure 11.
  • Step S300 further includes:
  • a second conductive structure 220 is formed on the surface of the second insulating layer 320 and the surface of the first conductive structure 210 .
  • the first conductive structure 210 and the second conductive structure 220 form a connection structure 200 , please refer to FIG. 14 .
  • the second insulating layer 320 closes the air gap 100b (refer to FIG. 16 ), or the second insulating layer 320 and the second conductive structure 220 jointly close the air gap 100b (refer to FIG. 14 ).
  • connection structure 200 is divided into the first conductive structure 210 and the second conductive structure 220, and the insulating structure 300 is divided into the first insulating layer 310 and the second insulating layer 320 at the same time, and the first conductive structure is formed first.
  • the structure 210 is formed, and then the first insulating layer 310 , the second insulating layer 320 and the second conductive structure 220 are sequentially formed, so that the gap 100 b is easier to process and form.
  • step S400 further includes:
  • a primary insulating layer 311 is formed on the inner wall of the via hole 100a.
  • the primary insulating layer 311 includes a first sidewall portion 3111 located on the sidewall of the via hole 100a, please refer to FIG. 6 .
  • Step S410 precedes step S310.
  • step S310 includes:
  • Step S312 forming a primary conductive layer 2121 on the surface of the primary barrier layer 2111, please refer to FIG. 8;
  • Step S313 removing part of the primary conductive layer 2121 and the primary barrier layer 2111 to expose part of the first sidewall portion 3111 , the remaining primary barrier layer 2111 constitutes the first barrier layer 211 , and the remaining primary conductive layer 2121 constitutes the first conductive layer 212 , the first barrier layer 211 and the first conductive layer 212 form a first conductive structure 210 , please refer to FIG. 9 .
  • step S420 includes:
  • step S421 part of the primary insulating layer 311 is removed, and the remaining primary insulating layer 311 constitutes the first insulating layer 310 , please refer to FIG. 10 .
  • the distance H1 between the surface of the first insulating layer 310 formed by the remaining primary insulating layer 311 and the opening of the via hole 100 a is greater than the distance H1 between the surface of the first conductive structure 210 and the via hole 100 a Spacing H2 between openings. That is, according to the direction in FIG. 10 , after removing part of the primary insulating layer 311 , the surface of the first insulating layer 310 formed by the remaining primary insulating layer 311 is lower than the surface of the first conductive structure 210 .
  • the material of the primary insulating layer 311 may be silicon dioxide or the like.
  • a silicon dioxide film layer may be deposited on the inner wall of the via hole 100 a to serve as the primary insulating layer 311 by a chemical vapor deposition (CVD) method based on silane (SiH 4 ) or ethyl orthosilicate (TEOS).
  • the thickness of the silicon dioxide film layer may be 0.2 ⁇ m-2 ⁇ m.
  • the primary barrier layer 2111 may be formed by a physical vapor deposition (PVD) method.
  • the material of the primary barrier layer 2111 may be tantalum (Ta), tantalum nitride (TaN), etc., and its thickness may be 0.05 ⁇ m-0.1 ⁇ m.
  • the material of the primary conductive layer 2121 may be metal copper (Cu) or the like.
  • a layer of copper seed crystal layer can be formed on the surface of the primary barrier layer 2111 by PVD method.
  • electroplated copper is grown on the surface of the copper seed crystal layer by electroplating, and the copper seed crystal layer and the electroplated copper together form the primary conductive layer 2121 .
  • the primary conductive layer 2121 grown on the surface of the primary barrier layer 2111 may not fill the communication hole 100a at this time.
  • the filling thickness of the central portion of the primary conductive layer 2121 may be 20%-70% of the depth of the via hole 100a.
  • step S313 part of the primary barrier layer 2111 and part of the primary conductive layer 2121 covered on the first sidewall portion 3111 may be removed by mixing an acid solution, so that the first sidewall portion 3111 of the primary insulating layer 311 is partially exposed, and at the same time A first barrier layer 211 and a first conductive layer 212 are formed.
  • the first barrier layer 211 can effectively prevent the stress caused by the thermal expansion of the first conductive layer 212 .
  • Step S420 is performed after the first sidewall portion 3111 of the primary insulating layer 311 is partially exposed, so that the first insulating layer 310 with a surface lower than the surface of the first conductive structure 210 can be more easily formed, thereby making it easier to realize the air gap 100b.
  • step S420 hydrofluoric acid or dry etching may be used to etch the first sidewall portion 3111 of the primary insulating layer 311 (such as a silicon dioxide film layer) in the via hole 100a, thereby forming a connection first barrier First insulating layer 310 of layer 211 .
  • the primary insulating layer 311 such as a silicon dioxide film layer
  • Step S430 is performed after step S420.
  • a second insulating material layer may be formed on the sidewall of the via hole 100a and the surface of the first conductive structure 210 by a chemical vapor deposition method. Then, the second insulating material layer located outside the via hole 100 a and located on the surface of the first conductive structure 210 is removed to form the second insulating layer 320 .
  • the material of the second insulating layer 320 may be the same as that of the first insulating layer 310 , or may be different from the material of the first insulating layer 310 , which is not limited in the present application.
  • the thickness of the second insulating layer 320 formed in this step may be greater than the thickness of the first insulating layer 310 .
  • the air gap 100b may be closed by the second insulating layer 320 .
  • the thickness of the second insulating layer 320 may also be the same as the thickness of the first insulating layer 310 .
  • the thickness of the second insulating layer 320 may also be the same as that of the first insulating layer 310 .
  • the air gap 100b may be closed by the second insulating layer 320 and the second conductive structure 220 formed subsequently.
  • step S320 includes:
  • Step S321 forming a second barrier base layer 2211 on the surface of the second insulating layer 320, the surface of the first barrier layer 211 and the surface of the first conductive layer 212, please refer to FIG. 12;
  • step S322 a second conductive layer 222 is formed, and the second conductive layer 222 is connected to the second barrier layer 221 , please refer to FIG. 13 or FIG. 14 .
  • the second barrier base layer 2211 may be formed by a chemical vapor deposition method.
  • the material of the second barrier base layer 2211 may be tantalum (Ta), tantalum nitride (TaN), etc., which may be the same as or different from the first barrier layer 211 , which is not limited in this application.
  • the second barrier layer 221 is formed on the surface of the second insulating layer 320 and connected to the second insulating layer 320 , so as to effectively prevent the influence of stress caused by the thermal expansion of the second conductive layer 222 .
  • step S430 after step S430 , the surface of the first barrier layer 211 is exposed and not covered by the second insulating layer 320 . Therefore, the second barrier base layer 2211 formed in this step is connected to the first barrier layer 211 .
  • the material of the second conductive layer 222 may be the same as that of the first conductive layer 212, or of course may be different, which is not limited in this application.
  • the formation process of the first conductive layer 212 may be similar to the formation process of the first conductive layer 212.
  • the copper seed layer is electroplated with copper, and further processed to form the second conductive layer 222 .
  • the second barrier base layer 2211 serves as the second barrier layer 221 .
  • Step S322 includes: forming a second conductive layer 222 on the surface of the second barrier layer 221 .
  • the second conductive layer 222 and the second barrier layer 221 form a second conductive structure 220 , please refer to FIG. 13 .
  • the second conductive layer 222 fills up the via hole 100a. Moreover, the second conductive layer 222 is connected to the second barrier layer 221 and is spaced from the first conductive structure 210 by the second barrier layer 221 .
  • the second barrier layer 221 is provided between the second conductive layer 222 and the first conductive layer 221 . Therefore, the second barrier layer 221 can effectively prevent that the second conductive layer 222 and the first conductive layer 221 formed twice may be inconsistent due to the grain size, etc., and in the subsequent annealing process, the thermal stress may be affected by the interface. crack.
  • the form of the second conductive structure 220 may also be different from this embodiment.
  • step S322 includes:
  • Step S3221 removing at least part of the second barrier base layer 2211 on the surface of the first conductive structure 210;
  • a second conductive layer 222 is formed on the surface of the second barrier layer 221 and the exposed surface of the first conductive structure 210.
  • the second conductive layer 222 and the second barrier layer 221 form the second conductive structure 220, please refer to FIG. 14 or FIG. 15.
  • step S3221 the second barrier layer 221 covering the surface of the first conductive structure 210 may be completely removed, or part of the second barrier layer 221 covering the surface of the first conductive structure 210 may be removed.
  • step S3222 the second conductive layer 222 fills the via holes. Moreover, the second conductive layer 222 is connected to the second barrier layer 221 and the first conductive structure 210 .
  • the second conductive layer 222 is in contact with the first conductive structure 210 (mainly connected to the first conductive layer 212 of the first conductive structure 210 ) to be connected, thereby reducing the reduction of the second conductive structure 220 and the first conductive structure 210 contact resistance.
  • the remaining edge portion can also help prevent the second barrier layer 221 from interacting with the first barrier layer 211
  • the poor contact of the connection affects the inhibition of thermal expansion stress of the conductive layer structure (including the first conductive layer 212 and the second conductive layer 222 ) in the connection.
  • the second barrier layer 221 is connected to the first barrier layer 211 . Therefore, the second barrier layer 221 and the first barrier layer 211 can jointly play a good role in suppressing the thermal expansion stress of the conductive layer structure (including the first conductive layer 212 and the second conductive layer 222 ) in the inner conductive layer.
  • the air gap 100b may be closed by the second barrier layer 221 , so that the second barrier layer 221 is in good contact with the first barrier layer 211 .
  • the thickness of the second barrier layer 221 is set to be greater than the thickness of the first barrier layer 211 . In this case, the contact between the second barrier layer 221 and the first barrier layer 211 can be effectively prevented from affecting the thermal expansion stress of the conductive layer structure (including the first conductive layer 212 and the second conductive layer 222 ) inside due to poor contact. inhibition.
  • the thickness of the second barrier layer 221 may not be greater than the thickness of the first barrier layer 211 , which is not limited in the present application.
  • steps in the flowcharts of FIGS. 1 to 3 are sequentially displayed in accordance with the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 to FIG. 3 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The order of execution is also not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
  • a semiconductor structure is also provided, please refer to FIG. 13 to FIG. 16 , including a substrate 100 , a via hole 100 a , a via structure 200 and an insulating structure 300 .
  • the substrate 100 includes a substrate 110 and a dielectric layer 120.
  • the substrate 110 has a front side 110a and a back side 110b disposed opposite to each other.
  • the dielectric layer 120 is formed on the front surface 110a.
  • the via hole 100 a penetrates through the substrate 110 and extends to the dielectric layer 120 .
  • the communication structure 200 is located in the communication hole 100a and is spaced apart from the inner wall of the communication hole 100a.
  • the insulating structure 300 is located between the communication structure 200 and the inner wall of the communication hole 100a. The insulating structure 300, the inner wall of the communication hole 100a, and the communication structure 200 are surrounded to form an air gap 100a.
  • the insulating structure 300 , the inner wall of the communication hole 100 a and the communication structure 200 are surrounded to form an air gap 100 b.
  • the air gap 100 b has the same insulating properties as the insulating structure 300 , so that the electrical isolation between the communication structure 200 and the substrate 110 can be effectively achieved together with the insulating structure 300 .
  • this structure can effectively prevent the heat generated by the communication structure 200 from diffusing to the surrounding semiconductor devices or dielectric layers, etc., thereby effectively Improve thermal performance.
  • the air gap 100b can also effectively isolate the communication structure 200 from the surrounding substrate 110 and/or the dielectric layer 120, thereby effectively preventing the substrate 110 and/or the dielectric layer 120 from being affected by the thermal expansion of the communication structure 200. stress deformation, thereby effectively preventing the occurrence of interface cracks in the substrate 110 and/or the dielectric layer 120 .
  • the air gap 100 a penetrates the interface between the substrate 110 and the dielectric layer 120 .
  • the width of the portion of the air gap 100b opposite the dielectric layer 120 is smaller than the width of the portion opposite the substrate 110 .
  • the communication structure 200 includes a first conductive structure 210 and a second conductive structure 220 that are connected to each other.
  • the insulating structure 300 includes a first insulating layer 310 and a second insulating layer 320 .
  • the first insulating layer 310 is located between the inner wall of the via hole 100 a and the first conductive structure 210 .
  • the second insulating layer 320 is located between the inner wall of the via hole 100 a and the second conductive structure 220 .
  • the first insulating layer 310, the second insulating layer 320, the inner wall of the communication hole 100a and the communication structure 200 are surrounded to form an air gap.
  • the second insulating layer 320 closes the air gap 100b (refer to FIG. 16 ), or the second insulating layer 320 and the second conductive structure 220 jointly close the air gap 100b (refer to FIGS. 13 to 15 ).
  • the first conductive structure 210 includes a first barrier layer 211 .
  • the first barrier layer 211 is connected to the first insulating layer 310 .
  • the second conductive structure 220 includes a second barrier layer 221 .
  • the second barrier layer 221 is connected to the second insulating layer 320 and the first barrier layer 211 .
  • the thickness of the second barrier layer 221 is greater than the thickness of the first barrier layer 211 .
  • the second conductive structure 220 further includes a second conductive layer 222 filling the via hole 100 a , the second conductive layer 222 is connected to the second barrier layer 221 and is connected to the first conductive structure 210 They are separated by a second barrier layer 221 .
  • the second conductive structure 220 further includes a second conductive layer 222 filling the via hole 100 a , and the second conductive layer 222 is connected to the second barrier layer 221 and the first conductive structure 210 .
  • the edge of the second conductive layer 222 may further include a second barrier layer 221 between the first conductive structures 210 , please refer to FIG. 15 .
  • the semiconductor structure of the present application is not limited to be formed by the method for forming the semiconductor structure in the above-mentioned embodiments.
  • a stack structure is also provided.
  • the stacked structure is formed based on any of the semiconductor structures described above.
  • the above-mentioned semiconductor structure needs to undergo a process such as etching or planarization to expose the communication structure 200 in the dielectric layer 120 (not shown), so that it is connected to the adjacent semiconductor structure.
  • the communication structures 200 in the communication holes 100a can be electrically connected to perform signal transmission.
  • the first conductive layer 212 of the first conductive structure 210 needs to be exposed to perform signal transmission.

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Abstract

本申请涉及一种半导体结构及其形成方法。其中，半导体结构包括：基片，包括衬底以及介质层，衬底具有相对设置的正面与背面，介质层形成于正面；连通孔，贯通衬底，且延伸至介质层；连通结构，位于连通孔内且与连通孔内壁间隔设置；绝缘结构，位于连通结构与连通孔内壁之间；其中，绝缘结构、连通孔内壁以及连通结构围设形成空气间隙。

Description

半导体结构及其形成方法
相关申请的交叉引用
本申请要求于2021年4月1日提交中国专利局、申请号为202110357903.5、发明名称为“半导体结构及其形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体结构及其形成方法。
技术背景
硅通孔(TSV)技术是三维集成电路中堆叠芯片实现互连的一种技术方案。由能够在三维方向有效地实现芯片堆叠，从而制造出结构更复杂、性能更强大、更具成本效率的电子器件，TSV技术成为了目前电子封装技术中最引人注目的一种技术。
然而，现有的TSV结构在散热能力及对周边器件的影响都存在较大的问题。
发明内容
根据本申请的各种实施例，提供一种半导体结构及其形成方法。
一种半导体结构，包括：
基片，包括衬底以及介质层，所述衬底具有相对设置的正面与背面，所述介质层形成于所述正面；
连通孔，贯通所述衬底，且延伸至所述介质层；
连通结构，位于所述连通孔内且与所述连通孔内壁间隔设置；
绝缘结构，位于所述连通结构与连通孔内壁之间；
其中，所述绝缘结构、所述连通孔内壁以及所述连通结构围设形成空气间隙。
一种半导体结构的形成方法，包括：
提供基片，所述基片包括衬底以及介质层，所述衬底具有相对设置的正面与背面，所述介质层形成于所述正面；
于所述基片内形成连通孔，所述连通孔贯通所述衬底，且延伸至所述介质层；
于所述连通孔内形成连通结构，所述连通结构与所述连通孔内壁间隔设置；
于所述连通结构与所述连通孔内壁之间形成绝缘结构；
其中，所述绝缘结构、所述连通孔内壁以及所述连通结构围设形成空气间隙。
一种堆叠结构，基于上述任一项所述的半导体结构加工形成。
上述半导体结构及其形成方法，由于连通结构与连通孔内壁之间具有空气间隙，由于空气导热性差，从而可以有效防止连通结构产生的热量扩散至其周围的半导体器件或者介质层等，从而有效提高散热性能。
并且，此时空气间隙也可以有效隔离连通结构与其周围的衬底和/或介电层，从而有效防止衬底和/或介电层由于受连通结构热膨胀影响而发生应力形变，进而有效防止衬底和/或介电层产生界面裂纹现象。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的半导体结构的形成方法的流程图；
图2为另一实施例中提供的半导体结构的形成方法的流程图；
图3为又一实施例中提供的半导体结构的形成方法的流程图；
图4-图12为半导体结构的形成过程中的结构示意图；
图13-图16为不同实施例中的半导体结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员 通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。
在一个实施例中，请参阅图1，提供一种半导体结构的形成方法，包括：
步骤S100，提供基片100，基片100包括衬底110以及介质层120，衬底110具有相对设 置的正面110a与背面110b，介质层120形成于正面110a，请参阅图4；
步骤S200，于基片100内形成连通孔100a，连通孔100a贯通衬底110，且延伸至介质层120，请参阅图5；
步骤S300，于连通孔100a内形成连通结构200，连通结构200与连通孔100a内壁间隔设置，请参阅图10以及图14；
步骤S400，于连通结构200与连通孔100a内壁之间形成绝缘结构300，请参阅图11以及图14。
其中，绝缘结构300、连通孔100a内壁以及连通结构200围设形成空气间隙，请参阅图14。
在步骤S100中，衬底110可以包括但不限于为硅衬底。衬底110靠近介质层120一侧可以形成有浅沟槽隔离结构400。浅沟槽隔离结构400将衬底110隔离成多个有源区。有源区用于形成各种半导体器件。
介质层120可以包括但不限于为氧化物介质层(如二氧化硅等)。介质层120内可以形成有电连接有源区的互连通孔结构以及金属层，从而将半导体器件的信号向外引出，或者为半导体器件提供外部信号。
在步骤S200中，连通孔100a内用于形成连通结构200。当多个半导体结构形成的芯片堆叠时，各个芯片的相应连通孔100a对准，从而使得各个连通孔100a内的连通结构200电连接，从而在各个芯片之间实现互连。
在步骤S300中，连通结构200为可以进行导电连通的结构，其可以包括多个膜层。当然，连通结构200也可以只包括一个膜层，本申请对此没有限制。
连通结构200在各个芯片之间进行导电连通时，其会产生大量热量，从而可能会影响芯片性能。
同时，连通结构200产生热量后，还容易因热应力而产生膨胀与收缩现象。如果其与衬底110和/介电层120之间通过绝缘结构接触，则可能造成衬底110和/介电层120发生应力形变，进而导致接触界面处产生裂纹的状况,甚至可能会影响到有源区的半导体器件性能。
在步骤S400中，绝缘结构300位于连通结构200与连通孔100a内壁之间，进而实现连通结构200与衬底110之间的电隔离。绝缘结构300的材料可以为二氧化硅等。其与介质层120的材料可以相同，也可以不同。
在本实施中，绝缘结构300、连通孔100a内壁以及连通结构200围设形成空气间隙100b。空气间隙100b与绝缘结构300一样具有绝缘性能，从而可以与绝缘结构300一起有效实现连通结构200与衬底110之间的电隔离。
同时，此时由于连通结构200与连通孔100a内壁之间具有空气间隙100b，空气导热性差，从而可以有效防止连通结构200产生的热量扩散至其周围的半导体器件或者介质层等，从而有效提高散热性能。
并且，此时空气间隙100b也可以有效隔离连通结构200与其周围的衬底110和/或介电层120，从而有效防止衬底110和/或介电层120由于受连通结构200热膨胀影响而发生应力形变，进而有效防止衬底110和/或介电层120产生界面裂纹现象。
在一个实施例中，请参阅图5，步骤S200包括：自衬底110的背面110b刻蚀基片100以形成连通孔100a。
作为示例，可以通过干法刻蚀的方法，自衬底110的背面110b依次刻蚀衬底110以及介质层120，从而形成连通孔100a。连通孔100的深度可以为20μm-150μm，其延伸至介质层120内的深度可以为0.5μm-1μm。连通孔100的直径可以为3μm-50μm。连通孔100的深宽比(即深度与直径之比)可以为0.4-50。
由于衬底110的背面110b距离有源区内形成半导体器件以及连接半导体器件的线路结构距离较远，因此本实施例可以有效防止在形成连通孔100a时，对有源区内形成半导体器件以及相关电路结构造成损伤。
在一个实施例中，请参阅图14，步骤S400中形成的空气间隙100b贯穿衬底110与介质层120的交界面。
衬底110与介质层120的交界面处，容易受连通结构200热膨胀影响而发生应力形变，从而产生界面裂纹。
在本实施例中，空气间隙100b贯穿衬底110与介质层120的交界面，从而使得空气间隙100b将衬底110与介质层120的交界面与连通结构200隔离，进而可以有效防止二者交界面产生界面裂纹。
同时，衬底110与介质层120的交界面周围半导体器件密集，半导体器件结构通常贯穿衬底110与介质层120的交界面两侧。
空气间隙100b贯穿衬底110与介质层120的交界面，使得空气间隙100b同时隔离连通结 构200与位于交界面两侧的衬底110、介质层120。因此，本实施例还可以对空气间隙100b周围的半导体器件进行有效的隔热保护，并可以防止空气间隙100b周围的半导体器件由于衬底110和/或介质层120发生应力形变而影响性能。
并且，由于空气的介电常数较小，因此空气间隙100b的形成可以有效防止连通结构200、绝缘结构300与半导体衬底110形成寄生电容。因此，本实施例可以有效防止连通结构200上的信号耦合到衬底110或者周围的半导体器件或者其他连通结构200上而导致的相关信号失真或者漏电流等现象。
在一个实施例中，空气间隙100b的与介质层120相对的部分的宽度小于与衬底110相对的部分的宽度。
介质层120是形成在衬底110上的膜层，其厚度相对于衬底110的厚度小很多。因此，本实施例设置空气间隙100b的与介质层120相对的部分的宽度较小，从而可以有效防止空气间隙100b导致介质层120结构不稳定。
并且，介质层120中产生的热量较大。此时设置与衬底110相对的空气间隙100b的宽度较大，会使得热量会往间隙大的位置流动，从而更加有利于散热，进而防止对周边器件的影响。
在一个实施例中，请参阅图2，步骤S300包括：
步骤S310，于连通孔100a内形成第一导电结构210，第一导电结构210与连通孔100a内壁间隔设置，且第一导电结构210与连通孔100a的开口之间具有间距，请参阅图9；
步骤S400包括：
步骤S420，于连通孔100a内壁与第一导电结构210之间形成第一绝缘层310，第一绝缘层310的表面与连通孔100a的开口之间的间距H1大于第一导电结构210的表面与连通孔100a的开口之间的间距H2，请参阅图10；
步骤S430，于连通孔100a内壁形成第二绝缘层320，第一绝缘层310与第二绝缘层320构成绝缘结构300，第一绝缘层310、第二绝缘层320与连通孔100a内壁以及连通结构200围设形成空气间隙，请参阅图11。
步骤S300还包括：
步骤S320，于第二绝缘层320表面以及第一导电结构210表面形成第二导电结构220，第一导电结构210与第二导电结构220构成连通结构200，请参阅图14。
其中，第二绝缘层320封闭空气间隙100b(请参阅图16)，或者第二绝缘层320与第二导 电结构220共同封闭空气间隙100b(请参阅图14)。
在本实施例中，通过将连通结构200分为第一导电结构210与第二导电结构220，同时将绝缘结构300分为第一绝缘层310与第二绝缘层320，并且先形成第一导电结构210，然后再依次形成第一绝缘层310、第二绝缘层320以及第二导电结构220，从而使得空隙间隙100b更加容易加工形成。
在一个实施例中，具体地，请参阅图3，步骤S400还包括：
步骤S410，于连通孔100a内壁形成初级绝缘层311，初级绝缘层311包括位于连通孔100a侧壁的第一侧壁部3111，请参阅图6。
步骤S410在步骤S310之前。
此时，步骤S310包括：
步骤S311，于初级绝缘层311表面形成初级阻挡层2111，请参阅图7；
步骤S312，于初级阻挡层2111表面形成初级导电层2121，请参阅图8；
步骤S313，去除部分初级导电层2121以及初级阻挡层2111，以暴露部分第一侧壁部3111，剩余的初级阻挡层2111构成第一阻挡层211，剩余的初级导电层2121构成第一导电层212，第一阻挡层211与第一导电层212构成第一导电结构210，请参阅图9。
之后，步骤S420包括：
步骤S421，去除部分初级绝缘层311，剩余的初级绝缘层311构成第一绝缘层310，请参阅图10。
具体地，去除部分初级绝缘层311后，剩余的初级绝缘层311形成的第一绝缘层310的表面与连通孔100a的开口之间的间距H1大于第一导电结构210的表面与连通孔100a的开口之间的间距H2。即，根据图10中方向，去除部分初级绝缘层311后，剩余的初级绝缘层311形成的第一绝缘层310的表面低于第一导电结构210的表面。
在步骤S410中，初级绝缘层311的材料可以为二氧化硅等。具体地，可以通过基于硅烷(SiH4)或正硅酸乙酯(TEOS)的化学气相沉积(CVD)方法，在连通孔100a内壁沉积形成二氧化硅膜层以作为初级绝缘层311。二氧化硅膜层的厚度可以为0.2μm-2μm。
在步骤S311中，初级阻挡层2111可以通过物理气相沉积(PVD)方法形成。初级阻挡层2111的材料可以为钽(Ta)以及氮化钽(TaN)等，其厚度可以为0.05μm-0.1μm。
在步骤S312中，初级导电层2121的材料可以为金属铜(Cu)等。具体地，可以先通过 PVD方法，在初级阻挡层2111表面形成一层铜籽晶层。然后，再在铜籽晶层表面通过电镀生长电镀铜，铜籽晶层与电镀铜共同构成初级导电层2121。
更具体地，由于后续步骤S313还要去除部分初级导电层2121而形成空气间隙100b，因此，此时初级阻挡层2111表面生长的初级导电层2121可以并不填满连通孔100a。作为示例，初级导电层2121的中央部分的填充厚度可以为连通孔100a深度的20％-70％。
在步骤S313中，可以通过混合酸溶液去掉遮盖在第一侧壁部3111上的部分初级阻挡层2111以及部分初级导电层2121，从而使得初级绝缘层311的第一侧壁部3111部分暴露，同时形成第一阻挡层211以及第一导电层212。
第一阻挡层211可以有效防止第一导电层212热膨胀而引起的应力影响。
初级绝缘层311的第一侧壁部3111部分暴露后，再进行步骤S420，从而可以更加容易形成表面低于第一导电结构210表面的第一绝缘层310，从而使得空气间隙100b更加容易实现。
在步骤S420中，可以利用氢氟酸或干法刻蚀对连通孔100a内的初级绝缘层311(如二氧化硅膜层)的第一侧壁部3111进行刻蚀，从而形成连接第一阻挡层211的第一绝缘层310。
在步骤S420之后进行步骤S430。
在步骤S430中，具体地，可以通过化学气相沉积方法，在连通孔100a侧壁以及第一导电结构210表面形成第二绝缘材料层。然后，去除掉位于连通孔100a外部的以及位于第一导电结构210表面的第二绝缘材料层，从而形成第二绝缘层320。
第二绝缘层320的材料可以与第一绝缘层310相同，也可以与第一绝缘层310不同，本申请对此并没有限制。
作为示例，本步骤形成的第二绝缘层320的厚度可以大于第一绝缘层310的厚度。此时，可以通过第二绝缘层320封闭空气间隙100b。
当然，第二绝缘层320的厚度也可以与第一绝缘层310的厚度相同。或者，第二绝缘层320的厚度也可以小于第一绝缘层310的厚度相同。此时，可以通过第二绝缘层320与后续形成的第二导电结构220共同封闭空气间隙100b。
在一个实施例中，步骤S320包括：
步骤S321，于第二绝缘层320表面、第一阻挡层211表面以及第一导电层212表面形成第二阻挡基层2211，请参阅图12；
步骤S322，形成第二导电层222，第二导电层222连接所述第二阻挡层221，请参阅图13 或图14。
在步骤S321中，可以通过化学气相沉积方法，形成第二阻挡基层2211。第二阻挡基层2211的材料可以为钽(Ta)以及氮化钽(TaN)等，其可以与第一阻挡层211相同，也可以与第一阻挡层211不同，本申请对此也没有限制。
第二阻挡层221形成于第二绝缘层320表面而连接第二绝缘层320，从而可以有效防止第二导电层222热膨胀而引起的应力影响。
同时，本实施例中，在步骤S430之后，第一阻挡层211的表面暴露在外，而未被第二绝缘层320覆盖。因此，本步骤形成的第二阻挡基层2211连接第一阻挡层211。
在步骤S322中，第二导电层222的材料可以与第一导电层212相同，当然也可以不同，本申请对此没有限制。
作为示例，第二导电层222的材料于第一导电层212的材料均为铜时，其形成过程可以与第一导电层212的形成过程类似，可以首先形成铜籽晶层能，然后再在铜籽晶层上电镀铜，并进一步加工形成第二导电层222。
在一个实施例中，第二阻挡基层2211作为第二阻挡层221。
步骤S322包括：于第二阻挡层221表面形成第二导电层222，第二导电层222与第二阻挡层221构成第二导电结构220，请参阅图13。
此时，第二导电层222填满连通孔100a。并且，第二导电层222连接第二阻挡层221，且与第一导电结构210之间由第二阻挡层221间隔。
即，第二导电层222与第一导电层221之间具有第二阻挡层221。因此，第二阻挡层221可以有效预防两次形成的第二导电层222与第一导电层221之间由于晶粒尺寸等可能不一致，而在后续退火工艺中，受热应力影响而在界面处产生裂纹。
当然，第二导电结构220的形式也可以与本实施例不同。
在另一实施例中，步骤S322包括：
步骤S3221，去除第一导电结构210表面的至少部分第二阻挡基层2211；
步骤S3222，于第二阻挡层221表面以及暴露的第一导电结构210表面形成第二导电层222，第二导电层222与第二阻挡层221构成第二导电结构220，请参阅图14或图15。
步骤S3221中，可以将覆盖于第一导电结构210表面的第二阻挡层221全部去除，也可以将覆盖于第一导电结构210表面的第二阻挡层221部分去除。
步骤S3222中，第二导电层222填满连通孔。并且，第二导电层222连接第二阻挡层221以及第一导电结构210。
在本实施例中，第二导电层222与第一导电结构210(主要与第一导电结构210的第一导电层212)接触而连接，从而降低了第二导电结构220与第一导电结构210的接触电阻。
请参阅图15，将覆盖于第一导电结构210表面的第二阻挡层221部分去除时可以兼顾降低接触电阻与预防两次形成的第二导电层222与第一导电层221之间受热应力影响的作用。
同时，如果将覆盖于第一导电结构210表面的第二阻挡层221的中央部分去除，而边缘部分保留，则保留的边缘部分也可以有助于防止第二阻挡层221与第一阻挡层211连接处由于接触不佳而影响对其内部的导电层结构(包括第一导电层212与第二导电层222)的热膨胀应力的抑制作用。
上述实施例中，第二阻挡层221连接第一阻挡层211。因此，第二阻挡层221与第一阻挡层211可以共同对其内部的导电层结构(包括第一导电层212与第二导电层222)的热膨胀应力起到良好的抑制作用。
进一步地，可以通过第二阻挡层221可以封闭空气间隙100b，从而使得第二阻挡层221与第一阻挡层211良好接触。
在一个实施例中，设置第二阻挡层221的厚度大于第一阻挡层211的厚度。此时，可以有效防止第二阻挡层221与第一阻挡层211连接处由于接触不佳而影响对其内部的导电层结构(包括第一导电层212与第二导电层222)的热膨胀应力的抑制作用。
当然，第二阻挡层221的厚度也可以不大于第一阻挡层211的厚度，本申请对此并没有限制。
应该理解的是，虽然图1至图3的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1至图3中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中，还提供一种半导体结构，请参阅图13至图16，包括基片100、连通孔100a、连通结构200以及绝缘结构300。
基片100包括衬底110以及介质层120，衬底110具有相对设置的正面110a与背面110b。介质层120形成于正面110a。连通孔100a贯通衬底110，且延伸至介质层120。连通结构200位于连通孔100a内且与连通孔100a内壁间隔设置。绝缘结构300位于连通结构200与连通孔100a内壁之间。绝缘结构300、连通孔100a内壁以及连通结构200围设形成空气间隙100a。
在本实施中，绝缘结构300、连通孔100a内壁以及连通结构200围设形成空气间隙100b。空气间隙100b与绝缘结构300一样具有绝缘性能，从而可以与绝缘结构300一起有效实现连通结构200与衬底110之间的电隔离。
同时，此时由于连通结构200与连通孔100a内壁之间具有空气间隙100b，由于空气导热性差，此结构可以有效防止连通结构200产生的热量扩散至其周围的半导体器件或者介质层等，从而有效提高散热性能。
并且，此时空气间隙100b也可以有效隔离连通结构200与其周围的衬底110和/或介电层120，从而有效防止衬底110和/或介电层120由于受连通结构200热膨胀影响而发生应力形变，进而有效防止衬底110和/或介电层120产生界面裂纹现象。
在一个实施例中，空气间隙100a贯穿衬底110与介质层120的交界面。
在一个实施例中，空气间隙100b的与介质层120相对的部分的宽度小于与衬底110相对的部分的宽度。
在一个实施例中，连通结构200包括相互连接的第一导电结构210与第二导电结构220。绝缘结构300包括第一绝缘层310与第二绝缘层320。第一绝缘层310位于连通孔100a内壁与第一导电结构210之间。第二绝缘层320位于连通孔100a内壁与第二导电结构220之间。第一绝缘层310、第二绝缘层320与连通孔100a内壁以及连通结构200围设形成空气间隙。
其中，第二绝缘层320封闭空气间隙100b(请参阅图16)，或者第二绝缘层320与第二导电结构220共同封闭空气间隙100b(请参阅图13至图15)。
在一个实施例中，第一导电结构210包括第一阻挡层211。第一阻挡层211连接第一绝缘层310。第二导电结构220包括第二阻挡层221。第二阻挡层221连接第二绝缘层320以及第一阻挡层211。
在一个实施例中，第二阻挡层221的厚度大于第一阻挡层211的厚度。
在一个实施例中，请参阅图13，第二导电结构220还包括填满连通孔100a的第二导电层222，第二导电层222连接第二阻挡层221，且与第一导电结构210之间由第二阻挡层221间 隔。
在一个实施例中，请参阅图14或图15，第二导电结构220还包括填满连通孔100a的第二导电层222，第二导电层222连接第二阻挡层221以及第一导电结构210。
此时，第一导电结构210与第二导电层222之间可以不具有第二阻挡层221，请参阅图14，也可以具有部分第二阻挡层222。例如，第二导电层222边缘处于第一导电结构210之间还可以具有第二阻挡层221，请参阅图15。
关于半导体结构的具体限定以及技术效果可以参见上文中对于半导体结构的形成方法的限定，在此不再赘述。
当然，可以理解的是，本申请的半导体结构并不限于通过上述实施例中的半导体结构的形成方法形成。
在一个实施例中，还提供一种堆叠结构。堆叠结构基于上述任一项的半导体结构加工形成。
具体地，在形成堆叠结构时，上述半导体结构需要经过刻蚀或者平坦化处理等加工工艺而使得介质层120内的连通结构200暴露(未图示)，从而使其在与相邻半导体结构进行堆叠时，连通孔100a内的连通结构200可以进行导电连接，从而进行信号传输。
更具体地，在一些实施例中，当连通结构200包括第一导电结构210以及第二导电结构220时，需要将第第一导电结构210的第一导电层212暴露，从而进行信号传输。
在本说明书的描述中，参考术语“一个实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种半导体结构，包括：
    基片，包括衬底以及介质层，所述衬底具有相对设置的正面与背面，所述介质层形成于所述正面；
    连通孔，贯通所述衬底，且延伸至所述介质层；
    连通结构，位于所述连通孔内且与所述连通孔内壁间隔设置；
    绝缘结构，位于所述连通结构与连通孔内壁之间；
    其中，所述绝缘结构、所述连通孔内壁以及所述连通结构围设形成空气间隙。
  2. 根据权利要求1所述的半导体结构，其中，所述空气间隙贯穿所述衬底与所述介质层的交界面。
  3. 根据权利要求2所述的半导体结构，其中，所述空气间隙的与所述介质层相对的部分的宽度小于与所述衬底相对的部分的宽度。
  4. 根据权利要求1所述的半导体结构，其中，所述连通结构包括相互连接的第一导电结构与第二导电结构，所述绝缘结构包括第一绝缘层与第二绝缘层，所述第一绝缘层位于所述连通孔内壁与所述第一导电结构之间，所述第二绝缘层位于所述连通孔内壁与所述第二导电结构之间，所述第一绝缘层、所述第二绝缘层与所述连通孔内壁以及连通结构围设形成空气间隙；
    其中，所述第二绝缘层封闭所述空气间隙，或者所述第二绝缘层与第二导电结构共同封闭所述空气间隙。
  5. 根据权利要求4所述的半导体结构，其中，所述第一导电结构包括第一阻挡层，所述第一阻挡层连接所述第一绝缘层，所述第二导电结构包括第二阻挡层，所述第二阻挡层连接所述第二绝缘层以及第一阻挡层。
  6. 根据权利要求5所述的半导体结构，其中，所述第二导电结构还包括填满所述连通孔的第二导电层，所述第二导电层连接所述第二阻挡层，且与所述第一导电结构之间由所述第二阻挡层间隔。
  7. 根据权利要求5所述的半导体结构，其中，所述第二导电结构还包括填满所述连通孔的第二导电层，所述第二导电层连接所述第二阻挡层以及所述第一导电结构。
  8. 根据权利要求6或7所述的半导体结构，其中，所述第二阻挡层的厚度大于所述第一阻挡层的厚度。
  9. 一种半导体结构的形成方法，包括：
    提供基片，所述基片包括衬底以及介质层，所述衬底具有相对设置的正面与背面，所述介质层形成于所述正面；
    于所述基片内形成连通孔，所述连通孔贯通所述衬底，且延伸至所述介质层；
    于所述连通孔内形成连通结构，所述连通结构与所述连通孔内壁间隔设置；
    于所述连通结构与所述连通孔内壁之间形成绝缘结构；
    其中，所述绝缘结构、所述连通孔内壁以及所述连通结构围设形成空气间隙。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述于所述基片内形成连通孔包括：
    自所述衬底的背面刻蚀所述基片以形成连通孔。
  11. 根据权利要求9所述的半导体结构的形成方法，其中，所述空气间隙贯穿所述衬底与所述介质层的交界面。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述空气间隙的与所述介质层相对的部分的宽度小于与所述衬底相对的部分的宽度。
  13. 根据权利要求9所述的半导体结构的形成方法，其中，
    所述于所述连通孔内形成连通结构包括：
    于所述连通孔内形成第一导电结构，所述第一导电结构与所述连通孔内壁间隔设置，且所述第一导电结构与所述连通孔的开口之间具有间距；
    所述于所述连通结构与所述连通孔内壁之间形成绝缘结构包括：
    于所述连通孔内壁与所述第一导电结构之间形成第一绝缘层，所述第一绝缘层的表面与所述连通孔的开口之间的间距大于所述第一导电结构的表面与所述连通孔的开口之间的间距；
    于所述连通孔内壁形成第二绝缘层，所述第一绝缘层与所述第二绝缘层构成所述绝缘结构，所述第一绝缘层、所述第二绝缘层与所述连通孔内壁以及连通结构围设形成空气间隙；
    所述于所述连通孔内形成连通结构还包括：
    于所述第二绝缘层表面以及所述第一导电结构表面形成第二导电结构，所述第一导电结构与所述第二导电结构构成所述连通结构；
    其中，所述第二绝缘层封闭所述空气间隙，或者所述第二绝缘层与第二导电结构共同封闭所述空气间隙。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，
    所述于所述连通结构与所述连通孔内壁之间形成绝缘结构还包括：
    于所述连通孔内形成第一导电结构之前，于所述连通孔内壁形成初级绝缘层，所述初级绝缘层包括位于所述连通孔侧壁的第一侧壁部；
    所述于所述连通孔内形成第一导电结构包括：
    于所述初级绝缘层表面形成初级阻挡层；
    于所述初级阻挡层表面形成所述初级导电层；
    去除部分所述初级导电层以及所述初级阻挡层，以暴露部分所述第一侧壁部，剩余的所述初级阻挡层构成第一阻挡层，剩余的所述初级导电层构成所述第一导电层，所述第一阻挡层与所述第一导电层构成第一导电结构；
    所述于所述连通孔内壁与所述第一导电结构之间形成第一绝缘层包括：
    去除部分所述初级绝缘层，剩余的所述初级绝缘层构成第一绝缘层。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，所述于所述第二绝缘层表面以及所述第一导电结构表面形成第二导电结构包括：
    于所述第二绝缘层表面、所述第一阻挡层表面以及所述第一导电层表面形成第二阻挡基层；
    形成所述第二导电层，所述第二导电层连接所述第二阻挡层。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，所述第二阻挡基层作为第二阻挡层，所述形成所述第二导电层包括：
    于所述第二阻挡层表面形成所述第二导电层，所述第二导电层与所述第二阻挡层构成所述第二导电结构。
  17. 根据权利要求15所述的半导体结构的形成方法，其中，所述形成所述第二导电 层包括：
    去除所述第一导电结构表面的至少部分所述第二阻挡基层，剩余的所述第二阻挡基层构成第二阻挡层；
    于所述第二阻挡层表面以及暴露的所述第一导电结构表面形成第二导电层，所述第二导电层与所述第二阻挡层构成所述第二导电结构。
  18. 根据权利要求16或17所述的半导体结构的形成方法，其中，所述第二阻挡层的厚度大于所述第一阻挡层的厚度。
  19. 一种堆叠结构，基于权利要求1-8任一项所述的半导体结构加工形成。
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