WO2022205733A1 - 半导体结构及其制作方法、堆叠结构 - Google Patents

半导体结构及其制作方法、堆叠结构 Download PDF

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WO2022205733A1
WO2022205733A1 PCT/CN2021/112066 CN2021112066W WO2022205733A1 WO 2022205733 A1 WO2022205733 A1 WO 2022205733A1 CN 2021112066 W CN2021112066 W CN 2021112066W WO 2022205733 A1 WO2022205733 A1 WO 2022205733A1
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layer
conductive layer
conductive
substrate
semiconductor structure
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PCT/CN2021/112066
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English (en)
French (fr)
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王路广
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长鑫存储技术有限公司
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Priority to US17/647,458 priority Critical patent/US20220319958A1/en
Publication of WO2022205733A1 publication Critical patent/WO2022205733A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a semiconductor structure, a manufacturing method thereof, and a stacked structure.
  • TSV Through-Silicon Via
  • the TSV structure generally includes a conductive structure formed of a metal material or the like. After the conductive structure is formed, annealing is usually required to make the size of the conductive structure more uniform. When annealing causes thermal expansion of the conductive structure, structures around the conductive structure (such as the semiconductor substrate and the dielectric layer on the substrate) may be thermally stressed to produce interface cracks, which affect the device performance around the conductive structure.
  • a semiconductor structure a method for fabricating the same, and a stacked structure are provided.
  • a semiconductor structure comprising:
  • a substrate includes a substrate and a dielectric layer, the substrate includes a front side and a back side arranged oppositely, the dielectric layer is formed on the front side, and a communication hole is opened on the substrate, and the communication hole extends from the substrate The back of the substrate penetrates through the substrate and extends to the dielectric layer;
  • the conductive structure includes a first conductive layer and a second conductive layer that are connected to each other, the first conductive layer is close to the bottom of the via hole, the second conductive layer is close to the top of the via hole, and The diameter of the first conductive layer is smaller than the diameter of the second conductive layer.
  • a method of fabricating a semiconductor structure comprising:
  • a substrate includes a substrate and a dielectric layer, the substrate includes a front surface and a back surface arranged oppositely, the dielectric layer is formed on the front surface, a communication hole is opened on the substrate, and the communication hole Passing through the substrate from the backside of the substrate and extending to the dielectric layer;
  • a conductive structure is formed on the surface of the insulating layer, the conductive structure includes a first conductive layer and a second conductive layer that are connected to each other, the first conductive layer is close to the bottom of the via hole, and the second conductive layer is close to the the top of the via hole, and the diameter of the first conductive layer is smaller than the diameter of the second conductive layer.
  • a stacked structure is formed based on the above-mentioned semiconductor structure.
  • FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment
  • FIG. 2 is a flowchart of a method for fabricating a semiconductor structure provided in an embodiment
  • 3-11 are schematic diagrams of various steps in the formation process of the semiconductor structure shown in FIG. 1 .
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques.
  • a semiconductor structure includes a substrate 100 , an insulating layer 200 and a conductive structure 320 .
  • the substrate 100 includes a substrate 110 and a dielectric layer 120 .
  • the substrate 110 includes a front side 110a and a back side 110b disposed opposite to each other.
  • the dielectric layer 120 is formed on the front surface 110a.
  • the substrate 100 is provided with a communication hole 100a.
  • the via hole 100 a penetrates through the substrate 110 from the back surface 110 b of the substrate 100 and extends to the dielectric layer 120 .
  • the insulating layer 200 is located on the inner wall surface of the communication hole 100a.
  • the conductive structure 320 includes a first conductive layer 321 and a second conductive layer 322 that are connected to each other.
  • the first conductive layer 321 is close to the bottom of the via hole 100 a
  • the second conductive layer 322 is close to the top of the via hole 100 a
  • the diameter of the first conductive layer 321 is smaller than that of the second conductive layer 322 .
  • the diameter of the first conductive layer 321 corresponding to the semiconductor device formed between the substrate 110 and the dielectric layer 120 is relatively small.
  • the expansion stress of a conductive layer 321 is small, so that the thermal stress of the conductive structure 320 to surrounding devices can be reduced.
  • the semiconductor structure further includes a barrier layer 310 .
  • the barrier layer 310 is located on the surface of the insulating layer 200 , and there is a gap 100 b between the barrier layer 310 and the first conductive layer 321 .
  • the gap 100b can be filled with air or other insulating medium.
  • the barrier layer 310 is a film layer that can effectively inhibit and block the thermal expansion stress of the conductive structure 320 .
  • the material of the barrier layer 310 can be tantalum (Ta), tantalum nitride (TaN), etc., and its thickness can be 0.05 ⁇ m-0.1 ⁇ m.
  • the barrier layer 310 can effectively reduce the thermal expansion coefficient of the conductive structure 320 when the conductive structure 320 thermally expands.
  • the gap 100b isolates the first conductive layer 321 from the barrier layer 310, thereby effectively blocking the effect of thermal expansion stress thereof, thereby better protecting the surrounding devices.
  • the first conductive layer 321 is spaced apart from the barrier layer 310, and the second conductive layer 322 is connected to the barrier layer 310.
  • the material of the first conductive layer 321 may be a metal conductive material such as copper (Cu). Specifically, it may include a first seed layer and a first conductive portion. The first seed layer is formed on the surface of the barrier layer 310 , and the first conductive portion is formed on the surface of the first seed layer.
  • the semiconductor structure further includes an isolation layer 330 .
  • the isolation layer 330 is located at the bottom of the via hole 100 a and between the barrier layer 310 and the first conductive layer 321 .
  • the barrier layer 310 , the isolation layer 330 , the first conductive layer 321 and the second conductive layer 322 together surround the gap 100 b filled with air.
  • the second conductive layer 322 includes a second seed layer 3221 and a second conductive portion 3222 .
  • the second seed layer 3221 surrounds the second conductive portion 3222 .
  • the sidewall of the second seed layer 3221 is in contact with the barrier layer 310 , and the bottom of the second seed layer 3221 is in contact with the first conductive layer 321 .
  • a stack structure is also provided.
  • the stacked structure is formed based on the above-mentioned semiconductor structure processing.
  • the above-mentioned semiconductor structure needs to undergo a process such as etching or planarization to expose the conductive structure 320 in the dielectric layer 120 (not shown), so that the conductive structure 320 in the dielectric layer 120 is exposed to the adjacent semiconductor structure.
  • the conductive structures 320 in the via holes 100a can be conductively connected to perform signal transmission.
  • a method for fabricating a semiconductor structure including:
  • a substrate in step S1, includes a substrate and a dielectric layer, the substrate includes a front and a back that are oppositely arranged, the dielectric layer is formed on the front, a communication hole is opened on the substrate, and the communication hole penetrates through the lining from the back of the substrate. bottom and extend to the dielectric layer.
  • Step S2 forming an insulating layer on the inner wall surface of the via hole.
  • Step S3 forming a conductive structure on the surface of the insulating layer, the conductive structure includes a first conductive layer and a second conductive layer that are connected to each other, the first conductive layer is close to the bottom of the via hole, and the second conductive layer is close to the top of the via hole , and the diameter of the first conductive layer is smaller than the diameter of the second conductive layer.
  • step S100 the substrate 100 is provided.
  • the substrate 100 includes a substrate 110 and a dielectric layer 120 .
  • the substrate 110 has a front surface 110 a and a back surface 110 b disposed opposite to each other, and the dielectric layer 120 is formed on the front surface 110 a.
  • the substrate 110 may include, but is not limited to, a silicon substrate.
  • a shallow trench isolation structure 400 may be formed on the side of the substrate 110 close to the dielectric layer 120 .
  • the shallow trench isolation structure 400 isolates the substrate 110 into a plurality of active regions. Active regions are used to form various semiconductor devices.
  • the dielectric layer 120 may include, but is not limited to, an oxide dielectric layer (eg, silicon dioxide, etc.).
  • An interconnect via structure and a metal layer that are electrically connected to the active regions may be formed in the dielectric layer 120, so as to lead out the signals of the semiconductor device, or provide external signals for the semiconductor device.
  • step S200 a communication hole 100 a is formed in the substrate 100 .
  • the substrate 100 shown in FIG. 3 may be etched from the backside 110b of the substrate 110 by dry etching, thereby forming the substrate 100 having the vias 100a.
  • the via hole 100 a penetrates through the substrate 110 from the back surface 110 b of the substrate 110 and extends to the dielectric layer 120 .
  • the depth of the communication hole 100a may be 20 ⁇ m-150 ⁇ m, and the depth extending into the dielectric layer 120 may be 0.5 ⁇ m-1 ⁇ m.
  • the diameter of the communication hole 100a may be 3 ⁇ m to 50 ⁇ m.
  • the aspect ratio (ie, the ratio of depth to diameter) of the communication hole 100a may be 0.4-50.
  • the via hole 100a is used to form a conductive structure.
  • the corresponding vias 100a of the respective chips are aligned, so that the conductive structures in the respective vias 100a are electrically connected, thereby realizing interconnection between the respective chips.
  • this embodiment can effectively prevent the formation of the semiconductor device and the semiconductor device in the active region when the via hole 100a is formed. Damage to the related circuit structure.
  • step S300 an insulating layer 200 is formed on the inner wall surface of the via hole 100a.
  • the insulating layer 200 is used to achieve electrical isolation between the conductive structure and the substrate 110 .
  • the material of the insulating layer 200 may be silicon dioxide or the like.
  • the materials of the insulating layer 200 and the dielectric layer 120 may be the same or different.
  • silicon dioxide When the material of the insulating layer 200 is silicon dioxide, specifically, silicon dioxide can be deposited on the inner wall of the via hole 100a by a chemical vapor deposition (CVD) method based on silane (SiH 4 ) or ethyl orthosilicate (TEOS) to form dioxide A silicon film layer is used as the insulating layer 200 .
  • the thickness of the silicon dioxide film layer may be 0.2 ⁇ m-2 ⁇ m.
  • step S400 a barrier layer 310 is formed on the surface of the insulating layer 200 .
  • the material of the barrier layer 310 may be tantalum (Ta) or tantalum nitride (TaN), and the thickness thereof may be 0.05 ⁇ m-0.1 ⁇ m.
  • a primary isolation layer 331 is formed on the surface of the barrier layer 310 , and the primary isolation layer 331 includes a sidewall portion 3311 .
  • the material of the primary isolation layer 331 is an insulating material.
  • the material of the primary isolation layer 331 may be silicon dioxide.
  • a silicon dioxide film with a thickness of 0.2 ⁇ m-2 ⁇ m can be deposited on the inner wall of the communication hole 100 a by a chemical vapor deposition (CVD) method based on silane (SiH 4 ) or ethyl orthosilicate (TEOS) as a primary isolation layer 331 .
  • CVD chemical vapor deposition
  • SiH 4 silane
  • TEOS ethyl orthosilicate
  • step S600 a primary conductive layer 3211 is formed on the surface of the primary isolation layer 331 .
  • the first primary seed layer may be formed on the surface of the barrier layer 310 first, and then the first primary conductive layer may be formed on the surface of the first primary seed layer.
  • the first primary conductive layer and the first primary seed layer constitute the primary conductive layer 3211 .
  • the material of the primary conductive layer 3211 may be metal copper (Cu).
  • a layer of copper seed crystal layer can be formed on the surface of the barrier layer 310 as the first primary seed layer by PVD method.
  • electroplated copper is grown on the surface of the first primary seed layer by electroplating to serve as the first primary conductive layer.
  • the primary conductive layer 3211 grown on the surface of the barrier layer 310 may not fill the via 100a at this time.
  • the filling thickness of the central portion of the primary conductive layer 3211 may be 20%-70% of the depth of the via hole 100a.
  • Step S700 removing part of the primary conductive layer 3211 to expose part of the sidewall portion 3311 , and the remaining primary conductive layer 3211 constitutes the first conductive layer 321 .
  • part of the primary conductive layer 3211 covering the sidewall portion 3311 may be removed by a mixed acid solution (eg, a mixed solution of H 2 SO 4 /H 2 O 2 ), so that the sidewall portion 3311 of the primary isolation layer 331 is removed. Partially exposed while forming the first conductive layer 321 .
  • a mixed acid solution eg, a mixed solution of H 2 SO 4 /H 2 O 2
  • the first primary seed layer forms the first seed layer
  • the first primary conductive layer forms the first conductive portion.
  • the first seed layer and the first conductive portion constitute the first conductive layer 321 .
  • step S800 part of the sidewall portion 3311 is removed to form a gap 100 b between the barrier layer 310 and the first conductive layer 321 , and the remaining primary isolation layer 331 constitutes the isolation layer 330 .
  • hydrofluoric acid or dry etching can be used to etch the sidewall portion 3311 of the primary isolation layer 331 (eg, the silicon dioxide film layer), so that the barrier layer 310 and the first conductive layer A gap 100b is formed between 321 .
  • the distance H1 between the surface of the isolation layer 330 formed by the remaining primary isolation layer 331 and the opening of the via hole 100a is greater than the distance between the surface of the first conductive layer 321 and the opening of the via hole 100a H2. That is, after removing part of the primary isolation layer 331 , the upper surface of the isolation layer 330 formed by the remaining primary isolation layer 331 is lower than the upper surface of the first conductive layer 321 .
  • the isolation layer 330 through the formation of the isolation layer 330, the first conductive layer 321 and the barrier layer 310 can be spaced apart easily and effectively.
  • the isolation layer 330 may not be formed, but the first conductive layer 321 and the barrier layer 310 may be spaced apart by other methods. This application does not limit this.
  • a second seed layer 3221 is formed on the surface of the barrier layer 310 and the surface of the first conductive layer 321 , and the second seed layer 3221 closes the gap 100 b to form the gap 100 b on both sides of the first conductive layer 321 .
  • the second seed layer 3221 can be formed by methods such as PVD deposition.
  • the second seed layer 3221 can facilitate the subsequent good formation of the second conductive portion 3222, and on the other hand, can perform a good sealing effect on the gap 100b.
  • a second conductive portion 3222 is formed on the surface of the second seed layer 3221 , and the second conductive portion 3222 and the second seed layer 3221 constitute the second conductive layer 322 .
  • the second conductive portion 3222 may be formed by means of electroplating or the like.
  • the first conductive layer 321 and the second conductive layer 322 of the conductive structure 320 may also be formed simultaneously in one process.
  • the material of the first conductive layer 321 is the same as the material of the second conductive layer 322 .
  • both are made of copper.
  • the first conductive layer 321 and the second conductive layer 322 can be in good contact, thereby reducing the contact resistance between the two, thereby effectively reducing the impedance of the conductive structure 320 .
  • the material of the first conductive layer 321 and the material of the second conductive layer 322 may also be different.
  • the semiconductor structure of the present application is not limited to being formed by the manufacturing method of the semiconductor structure in the above-mentioned embodiments.

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Abstract

一种半导体结构及其制作方法，该半导体结构包括：基片（100），包括衬底（110）以及介质层（120），所述衬底（110）包括相对设置的正面（110a）与背面（110b），所述介质层（120）形成于所述正面（110a），所述基片（100）上开设有连通孔（100a），所述连通孔（100a）从所述衬底（110）的背面（110b）贯通所述衬底（110），且延伸至所述介质层（120）；绝缘层（200），位于所述连通孔（100a）的内壁表面；导电结构（320），所述导电结构（320）包括相互连接的第一导电层（321）与第二导电层（322），所述第一导电层（321）靠近所述连通孔（100a）的底部，所述第二导电层（322）靠近所述连通孔（100a）的顶部，且所述第一导电层（321）的直径小于所述第二导电层（322）的直径。

Description

半导体结构及其制作方法、堆叠结构
相关申请的交叉引用
本申请要求于2021年04月01日提交中国专利局、申请号为202110357894X、发明名称为“半导体结构及其形成方法、堆叠结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体结构及其制作方法、堆叠结构。
背景技术
硅通孔(TSV)技术是三维集成电路中堆叠芯片实现互连的一种技术方案。由能够在三维方向有效地实现芯片堆叠，从而制造出结构更复杂、性能更强大、更具成本效率的电子器件，TSV技术成为了目前电子封装技术中最引人注目的一种技术。
TSV结构通常包括金属材料等形成的导电结构。导电结构形成后通常需要进行退火，以使得导电结构尺寸更加均匀。当退火会导致导电结构发生热膨胀，从而导致导电结构周围的结构(如半导体衬底以及衬底上的介质层)可能会受到热应力作用而产生界面裂纹，从而影响导电结构周围的器件性能。
发明内容
根据一些实施例，提供一种半导体结构及其制作方法、堆叠结构。
一种半导体结构，包括：
基片，包括衬底以及介质层，所述衬底包括相对设置的正面与背面，所述介质层形成于所述正面，所述基片上开设有连通孔，所述连通孔从所述衬底的背面贯通所述衬底，且延伸至所述介质层；
绝缘层，位于所述连通孔的内壁表面；
导电结构，所述导电结构包括相互连接的第一导电层与第二导电层，所述第一导电层靠近所述连通孔的底部，所述第二导电层靠近所述连通孔的顶部，且所述第一导电层的直径小于所述第二导电层的直径。
一种半导体结构的制作方法，包括：
提供基片，所述基片包括衬底以及介质层，所述衬底包括相对设置的正面与背面，所述介质层形成于所述正面，所述基片上开设有连通孔，所述连通孔从所述衬底的背面贯通所述衬底，且延伸至所述介质层；
于所述连通孔内壁表面形成绝缘层；及
于所述绝缘层表面形成导电结构，所述导电结构包括相互连接的第一导电层与第二导电层，所述第一导电层靠近所述连通孔的底部，所述第二导电层靠近所述连通孔的顶部，且所述第一导电层的直径小于所述第二导电层的直径。
一种堆叠结构，基于上述半导体结构加工形成。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例并配合附图详细说明如后。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中的半导体结构的示意图；
图2为一实施例中提供的半导体结构的制作方法的流程图；
图3-图11为图1所示半导体结构的形成过程中各个步骤的示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、 掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。
请参阅图1，在一个实施例中，一种半导体结构包括基片100、绝缘层 200以及导电结构320。
基片100包括衬底110以及介质层120。衬底110包括相对设置的正面110a与背面110b。介质层120形成于正面110a。基片100上开设有连通孔100a。连通孔100a从衬底100的背面110b贯通衬底110，且延伸至介质层120。绝缘层200位于连通孔100a的内壁表面。导电结构320包括相互连接的第一导电层321与第二导电层322。第一导电层321靠近连通孔100a的底部，第二导电层322靠近连通孔100a的顶部，且第一导电层321的直径小于第二导电层322的直径。
在本实施例中，与衬底110与介质层120之间形成的半导体器件相对应的第一导电层321的直径相对较小，因此，该部分对应的衬底110以及介质层120受到的第一导电层321的膨胀应力作用较小，从而可以降低导电结构320对周围器件的热应力作用。
在一个实施例中，半导体结构还包括阻挡层310。阻挡层310位于绝缘层200的表面，且阻挡层310与第一导电层321之间具有间隙100b。间隙100b可以填充空气或是其他隔热介质。阻挡层310为可以对导电结构320的热膨胀应力起到良好的抑制阻挡作用的膜层。阻挡层310材料可以为钽(Ta)以及氮化钽(TaN)等，其厚度可以为0.05μm-0.1μm。阻挡层310可以在导电结构320产生热膨胀时，有效降低导电结构320的热膨胀系数。
由于间隙100b内的空气的导热性差，因此，可以进一步防止导电结构320产生的热量向周围器件扩散。同时，间隙100b将第一导电层321与阻挡层310相隔离，从而有效阻断其热膨胀应力作用，进而对周围器件起到更好的保护作用。
在一个实施例中，第一导电层321与阻挡层310间隔设置，第二导电层 322连接阻挡层310。第一导电层321的材料可以为铜(Cu)等金属导电材料。其具体可以包括第一种子层以及第一导电部。第一种子层形成于阻挡层310表面，第一导电部形成于第一种子层表面。
在一个实施例中，半导体结构还包括隔离层330。隔离层330位于连通孔100a的底部，且位于阻挡层310和第一导电层321之间。阻挡层310、隔离层330、第一导电层321以及第二导电层322共同围设形成填充有空气的间隙100b。
在一个实施例中，第二导电层322包括第二种子层3221与第二导电部3222。第二种子层3221环绕在第二导电部3222周围。第二种子层3221的侧壁与阻挡层310接触，第二种子层3221的底部与第一导电层321接触。
在一个实施例中，还提供一种堆叠结构。该堆叠结构基于上述半导体结构加工形成。
具体地，在形成堆叠结构时，上述半导体结构需要经过刻蚀或者平坦化处理等加工工艺而使得介质层120内的导电结构320暴露(未图示)，从而使其在与相邻半导体结构进行堆叠时，连通孔100a内的导电结构320可以进行导电连接，从而进行信号传输。
请参阅图2，在一个实施例中，提供一种半导体结构的制作方法，包括：
步骤S1，提供基片，基片包括衬底以及介质层，衬底包括相对设置的正面与背面，介质层形成于所述正面，基片上开设有连通孔，连通孔从衬底的背面贯通衬底，且延伸至介质层。
步骤S2，于连通孔内壁表面形成绝缘层。
步骤S3，于绝缘层表面形成导电结构，导电结构包括相互连接的第一导电层与第二导电层，第一导电层靠近所述连通孔的底部，第二导电层靠近所 述连通孔的顶部，且第一导电层的直径小于第二导电层的直径。
下面结合图1、图3-图11对上述半导体结构的制作方法做详细描述。
步骤S100，提供基片100。
如图3所示，基片100包括衬底110以及介质层120，衬底110具有相对设置的正面110a与背面110b，介质层120形成于正面110a。
在步骤S100中，衬底110可以包括但不限于为硅衬底。衬底110靠近介质层120一侧可以形成有浅沟槽隔离结构400。浅沟槽隔离结构400将衬底110隔离成多个有源区。有源区用于形成各种半导体器件。
介质层120可以包括但不限于为氧化物介质层(如二氧化硅等)。介质层120内可以形成有电连接有源区的互连通孔结构以及金属层，从而将半导体器件的信号向外引出，或者为半导体器件提供外部信号。
步骤S200，在基片100内形成连通孔100a。
请参阅图4，具体的，可以通过干法刻蚀的方法，自衬底110的背面110b刻蚀图3所示的基片100，从而形成具有连通孔100a的基片100。连通孔100a从衬底110的背面110b贯通衬底110，且延伸至介质层120。连通孔100a的深度可以为20μm-150μm，其延伸至介质层120内的深度可以为0.5μm-1μm。连通孔100a的直径可以为3μm-50μm。连通孔100a的深宽比(即深度与直径之比)可以为0.4-50。
连通孔100a内用于形成导电结构。当多个半导体结构形成的芯片堆叠时，各个芯片的相应连通孔100a对准，从而使得各个连通孔100a内的导电结构电连接，从而在各个芯片之间实现互连。
由于衬底110的背面110b距离有源区内形成的半导体器件以及连接半导体器件的线路结构距离较远，因此本实施例可以有效防止在形成连通孔100a 时，对有源区内形成半导体器件以及相关电路结构造成损伤。
步骤S300，在连通孔100a的内壁表面形成绝缘层200。
请参阅图5，绝缘层200用于实现导电结构与衬底110之间的电隔离。绝缘层200的材料可以为二氧化硅等。绝缘层200与介质层120的材料可以相同，也可以不同。
当绝缘层200的材料为二氧化硅时，具体地，可以通过基于硅烷(SiH 4)或正硅酸乙酯(TEOS)的化学气相沉积(CVD)方法，在连通孔100a内壁沉积形成二氧化硅膜层以作为绝缘层200。二氧化硅膜层的厚度可以为0.2μm-2μm。
步骤S400，在绝缘层200的表面形成阻挡层310。
请参阅图6，阻挡层310材料可以为钽(Ta)以及氮化钽(TaN)等，其厚度可以为0.05μm-0.1μm。
步骤S500，在阻挡层310的表面形成初级隔离层331，初级隔离层331包括侧壁部3311。
请参阅图7，初级隔离层331的材料为绝缘材料。作为示例，初级隔离层331的材料可以为二氧化硅。具体地，可以通过基于硅烷(SiH 4)或正硅酸乙酯(TEOS)的化学气相沉积(CVD)方法，在连通孔100a内壁沉积形成0.2μm-2μm厚的二氧化硅膜层以作为初级隔离层331。
步骤S600，在初级隔离层331的表面形成初级导电层3211。
请参阅图8，具体地，可以先在阻挡层310表面形成第一初级种子层，然后再在第一初级种子层表面形成第一初级导电层。第一初级导电层与第一初级种子层构成初级导电层3211。
作为示例，初级导电层3211的材料可以为金属铜(Cu)。此时可以先通 过PVD方法，在阻挡层310表面形成一层铜籽晶层作为第一初级种子层。然后，再在第一初级种子层表面通过电镀生长电镀铜，以作为第一初级导电层。
同时，由于后续步骤S700还要去除部分初级导电层3211而形成填充有空气的间隙100b，因此，此时阻挡层310表面生长的初级导电层3211可以并不填满连通孔100a。作为示例，初级导电层3211的中央部分的填充厚度可以为连通孔100a深度的20％-70％。
步骤S700，去除部分初级导电层3211，以暴露部分侧壁部3311，剩余的初级导电层3211构成第一导电层321。
请参阅图9，可以通过混合酸溶液(例如H 2SO 4/H 2O 2混合溶液)去掉覆盖在侧壁部3311上的部分初级导电层3211，从而使得初级隔离层331的侧壁部3311部分暴露，同时形成第一导电层321。
具体地，此时第一初级种子层形成第一种子层，第一初级导电层形成第一导电部。第一种子层与第一导电部构成第一导电层321。
步骤S800，去除部分侧壁部3311，以在阻挡层310和第一导电层321之间形成间隙100b，剩余的初级隔离层331构成隔离层330。
请参阅图10，具体地，可以利用氢氟酸或干法刻蚀对初级隔离层331(如二氧化硅膜层)的侧壁部3311进行刻蚀，从而在阻挡层310和第一导电层321之间形成间隙100b。
去除部分初级隔离层331后，剩余的初级隔离层331形成的隔离层330的表面与连通孔100a的开口之间的间距H1大于第一导电层321的表面与连通孔100a的开口之间的间距H2。即，去除部分初级隔离层331后，剩余的初级隔离层331形成的隔离层330的上表面低于第一导电层321的上表面。
在本实施例中，通过隔离层330的形成，可以简便有效地实现第一导电 层321与阻挡层310间隔设置。当然，在其他实施例中，也可以不形成隔离层330，而是通过其他方式实现第一导电层321与阻挡层310间隔设置。本申请对此并没有限制。
步骤S900，于阻挡层310的表面以及第一导电层321的表面形成第二种子层3221，第二种子层3221封闭间隙100b，从而在第一导电层321的两侧形成间隙100b。
请参阅图11，具体地，可以通过PVD沉积等方法而形成第二种子层3221。在本实施例中，第二种子层3221一方面可以便于后续第二导电部3222的良好形成，另一方面可以对间隙100b进行良好的封闭作用。
步骤S1000，于第二种子层3221的表面形成第二导电部3222，第二导电部3222与第二种子层3221构成第二导电层322。
请参阅图1，具体地，可以通过电镀等方式而形成第二导电部3222。在其他实施例中，导电结构320的第一导电层321与第二导电层322也可以在一次工艺过程中同时形成。第一导电层321的材料与第二导电层322的材料相同。例如，二者的材料均为铜。此时，第一导电层321与第二导电层322可以进行良好的接触，从而降低二者之间的接触电阻，从而有效降低导电结构320的阻抗。当然，在其他实施例中，第一导电层321的材料与第二导电层322的材料也可以不相同。
当然，可以理解的是，本申请的半导体结构并不限于通过上述实施例中的半导体结构的制作方法形成。
在本说明书的描述中，参考术语“一个实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不 一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种半导体结构，包括：
    基片，包括衬底以及介质层，所述衬底包括相对设置的正面与背面，所述介质层形成于所述正面，所述基片上开设有连通孔，所述连通孔从所述衬底的背面贯通所述衬底，且延伸至所述介质层；
    绝缘层，位于所述连通孔的内壁表面；
    导电结构，所述导电结构包括相互连接的第一导电层与第二导电层，所述第一导电层靠近所述连通孔的底部，所述第二导电层靠近所述连通孔的顶部，且所述第一导电层的直径小于所述第二导电层的直径。
  2. 根据权利要求1所述的半导体结构，还包括阻挡层，其中所述阻挡层位于所述绝缘层的表面，且所述阻挡层与所述第一导电层之间具有间隙。
  3. 根据权利要求2所述的半导体结构，其中所述第一导电层与所述阻挡层间隔设置，所述第二导电层连接所述阻挡层。
  4. 根据权利要求3所述的半导体结构，还包括隔离层，其中所述隔离层位于所述连通孔的底部，且位于所述阻挡层和所述第一导电层之间，所述阻挡层、所述隔离层、所述第一导电层以及所述第二导电层共同围设形成所述间隙。
  5. 根据权利要求3所述的半导体结构，其中所述第二导电层包括第二导电部和环绕在所述第二导电部周围的第二种子层，所述第二种子层连接所述阻挡层以及所述第一导电层。
  6. 根据权利要求1所述的半导体结构，其中所述第一导电层与所述第二导电层的材料相同。
  7. 根据权利要求1所述的半导体结构，其中所述连通孔的深宽比为 0.4-50。
  8. 一种半导体结构的制作方法，包括：
    提供基片，所述基片包括衬底以及介质层，所述衬底包括相对设置的正面与背面，所述介质层形成于所述正面，所述基片上开设有连通孔，所述连通孔从所述衬底的背面贯通所述衬底，且延伸至所述介质层；
    于所述连通孔内壁表面形成绝缘层；及
    于所述绝缘层表面形成导电结构，所述导电结构包括相互连接的第一导电层与第二导电层，所述第一导电层靠近所述连通孔的底部，所述第二导电层靠近所述连通孔的顶部，且所述第一导电层的直径小于所述第二导电层的直径。
  9. 根据权利要求8所述的方法，其中所述连通孔自所述背面刻蚀形成。
  10. 根据权利要求8所述的方法，于所述连通孔内壁表面形成绝缘层之后，所述方法还包括：于所述绝缘层的表面形成阻挡层。
  11. 根据权利要求10所述的方法，其中所述于所述绝缘层表面形成导电结构包括：
    在所述阻挡层的表面形成初级隔离层，所述初级隔离层包括侧壁部；
    在所述初级隔离层的表面形成初级导电层；
    去除部分所述初级导电层以暴露部分所述侧壁部，剩余的初级导电层构成第一导电层；
    去除部分所述侧壁部，以在所述阻挡层和所述第一导电层之间形成间隙，剩余的初级隔离层构成隔离层；及
    于所述阻挡层表面以及所述第一导电层表面形成第二导电层，所述第一导电层与所述第二导电层构成所述导电结构。
  12. 根据权利要求11所述的方法，其中所述于所述阻挡层表面以及所述第一导电层表面形成第二导电层，包括：
    于所述阻挡层的表面以及所述第一导电层的表面形成第二种子层，所述第二种子层封闭所述间隙；
    于所述第二种子层的表面形成第二导电部，所述第二导电部与所述第二种子层构成所述第二导电层。
  13. 根据权利要求8所述的方法，其中所述第一导电层的材料与所述第二导电层的材料相同。
  14. 一种堆叠结构，基于权利要求1-7任一项所述的半导体结构加工形成。
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