WO2022214058A1 - 金属凸块结构及制造方法 - Google Patents

金属凸块结构及制造方法 Download PDF

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WO2022214058A1
WO2022214058A1 PCT/CN2022/085732 CN2022085732W WO2022214058A1 WO 2022214058 A1 WO2022214058 A1 WO 2022214058A1 CN 2022085732 W CN2022085732 W CN 2022085732W WO 2022214058 A1 WO2022214058 A1 WO 2022214058A1
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layer
passivation layer
metal bump
metal
metallization
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PCT/CN2022/085732
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English (en)
French (fr)
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陈浩
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颀中科技（苏州）有限公司
合肥颀中科技股份有限公司
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Publication of WO2022214058A1 publication Critical patent/WO2022214058A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Definitions

  • the invention relates to the technical field of chip packaging, in particular to a metal bump structure and a manufacturing method.
  • the process flow of bump forming of flip-chip chips mainly includes the following: introducing a bare chip - covering the bare chip with a PI (polyimide, Polyimide) layer - exposing the PI layer - developing the PI layer And bake—sputter metallization layer on PI layer and pad of bare chip—cover photoresist—expose photoresist—develop photoresist—plating metal bumps—stripping photoresist— Metallization Etch - Reflow solder balls.
  • PI polyimide, Polyimide
  • the passivation A PI layer generally needs to be overlaid on the layer to serve as a stress buffer layer for the metal bumps.
  • this will inevitably lead to an increase in cost.
  • the purpose of the present invention is to provide a metal bump structure to solve the deficiencies in the prior art, which can avoid the metal bumps by increasing the opening degree of the passivation layer so that the metal bumps are directly formed on the pads The effect on the passivation layer in turn saves the use of PI material.
  • the metal bump structure disclosed in the present invention includes a bare chip, and has a substrate, a pad and a passivation layer disposed on the upper surface of the substrate, and the pad is exposed from the passivation layer opening on the passivation layer. ;
  • a metallization layer covering at least the upper surface of the metal pad and completely covering the passivation layer opening
  • Metal bumps are formed on the upper surface of the metallization layer and have bottoms located at the openings of the passivation layer.
  • part of the metallization layer covers the upper surface of the passivation layer, and only part of the upper surface of the metallization layer located in the opening of the passivation layer is formed with metal bumps.
  • the metallization layers outside the metal bumps are exposed to the outside.
  • the size of the cross section of the metal bump is smaller than the size of the opening of the passivation layer.
  • the metal bumps include a first electroplating layer and a second electroplating layer formed on the first electroplating layer; the first electroplating layer adopts one or more of metal copper, nickel, and gold; the The second electroplating layer adopts one or more of metal tin, silver and lead.
  • Another embodiment of the present invention also discloses a method for manufacturing the above-mentioned metal bump, which includes the following steps:
  • a substrate is provided, and a pad and a passivation layer are formed on the upper surface of the substrate, and the pad is exposed outward from the passivation layer opening on the passivation layer;
  • a metallization layer is covered on the upper surface of the passivation layer and the upper surface of the pad;
  • the remaining second photoresist layer is removed after removing the metallization layer outside the predetermined position.
  • the preset position covers at least the opening of the passivation layer outside the metal bump.
  • the size of the pane is smaller than the size of the opening of the passivation layer.
  • pane is arranged in the center of the opening of the passivation layer.
  • the developing solution is used for developing, so that the unexposed photoresist outside the preset position is removed by the developing solution.
  • the present invention avoids the influence of the metal bump on the passivation layer by increasing the opening degree of the passivation layer so that the metal bump is directly formed on the pad, thereby saving the use of PI material.
  • FIG. 1 is a schematic structural diagram of a metal bump disclosed in an embodiment of the present invention.
  • Reference numeral description 10-bare chip, 101-substrate, 102-pad, 103-passivation layer, 104-passivation layer opening, 20-metallization layer, 30-metal bump, 301-first electroplating layer , 302 - the second electroplating layer, 40 - the first photoresist layer, 401 - the pane, 50 - the second photoresist layer.
  • a metal bump structure including: a bare chip 10, a metallization layer 20 and a metal bump 30; the bare chip 10 includes a substrate 101 and a The pads 102 and the passivation layer 103 on the upper surface of the substrate 101 are exposed outward from the passivation layer openings 104 on the passivation layer 103 .
  • the metallization layer 20 covers at least the upper surface of the metal pad 102 and completely covers the passivation layer opening 104 ; the metallization layer 20 is a seed layer for forming the metal bumps 30 .
  • the metallization layer 20 can be a composite layer including a first layer and a second layer disposed on the first layer, wherein the first layer is made of titanium, titanium-tungsten and other titanium metal alloys or compounds, and the first layer is made of titanium alloys or compounds.
  • Two-layer materials include but are not limited to metals such as copper and gold.
  • the metal bumps 30 are formed on the upper surface of the metallization layer 20 and have bottoms located at the passivation layer openings 104 .
  • the size of the bottom of the metal bump 30 is not larger than the size of the passivation layer opening 104 .
  • the size of the cross section of the metal bump 30 is smaller than the size of the passivation layer opening 104 .
  • the metal pads 102 are exposed outward from the passivation layer opening 104 , so the metal bumps 30 can be directly disposed on the metal pads 102 . Enlarging the window on the passivation layer of the protective layer, so that the bump structures of the same size are all grown on the pad 102. When the package is pressed, all the pressing is carried on the pad 102, which will not cause lines and passivation layers. lysis.
  • the metal bumps 30 are directly arranged on the metal pads 102, the influence of the metal bumps 30 on the passivation layer 103 is avoided, and since the metal bumps 30 are not arranged on the passivation layer 103, the metal bumps 30 can be avoided
  • a buffer layer formed of PI material is arranged between 30 and the passivation layer 103, so that the use of PI material can be reduced, and the situation that PI material cannot be supplied due to the limitation of domestic technology can be effectively avoided. Relying on foreign imports has a high cost, and reducing the use of PI materials can effectively reduce the cost in the chip manufacturing process.
  • the size of the metal bumps 30 is smaller than that of the passivation layer openings 104 , in order to avoid oxidation corrosion of the metal pads 102 due to the direct outward exposure of the pads 102 .
  • the metallization layer 20 on the metal pad 102 is set to at least completely cover the passivation layer opening 104.
  • the size of the metallization layer 20 is generally the same as that of the metal bump 30. This embodiment The metallization layer 20 is designed for external expansion.
  • the size of the metallization layer 20 is larger than the size of the bottom of the metal bump 30 and not smaller than the size of the passivation layer opening 104 , thereby forming a protective layer covering the pad 102 The direct exposure of the pad 102 can be effectively avoided.
  • the size of the metallization layer 20 is larger than the size of the passivation layer opening 104 , and part of the metallization layer 20 covers the upper surface of the passivation layer 103 , and only part of the metal in the passivation layer opening 104 is
  • the metal bumps 30 are formed on the upper surface of the chemical layer 20 .
  • the size of the metal bump 30 is set to be smaller than the size of the passivation layer opening 104 .
  • the size of the metal bump 30 can also be set to be consistent with the size of the passivation layer opening 104 .
  • the part of the metallization layer 20 located outside the metal bump 30 is directly exposed to the outside, and the part of the metallization layer 20 exposed to the outside can be Covering the pads 102 outside the metal bumps 30 to protect the pads 102 .
  • Another embodiment of the present invention also discloses a method for manufacturing the above-mentioned metal bump, which includes the following steps:
  • the bare chip includes a substrate 101 , wherein a pad 102 and a passivation layer 103 are formed on the upper surface of the substrate 101 , and the pad 102 is formed on the passivation layer 103 The passivation layer opening 104 is exposed to the outside;
  • S104 removing the first photoresist layer 40 at the target position by exposure and development to form a pane 401 as shown in FIG. 4 ; the target position is opposite to the passivation layer opening 104 , and the target position is the area covered by the passivation layer opening 104 , that is, the projection of the target position on the substrate 101 just falls within the passivation layer opening 104 , and the area on the pad 102 opposite to the target position is used for growing the metal bump 30 .
  • the size of the pane 401 is smaller than the size of the passivation layer opening 104 .
  • the pane 401 is disposed at the center of the passivation layer opening 104 . In this way, after the metal bumps 30 are formed, the metal bumps 30 can be disposed at the center of the passivation layer opening 104 , which can more conveniently implement chip packaging.
  • the first photoresist layer 40 is exposed to high-intensity light (eg, ultraviolet rays) through the photomask, wherein the first photoresist layer 40 at the target position opposite to the position of the partial passivation layer opening 104 is not covered by the photomask. Covered by the light-transmitting area. Then, the entire bare chip is put into a developing solution for development, and the unexposed photoresist on the target position is removed by the developing solution, thereby forming a pane 401 in the target area.
  • high-intensity light eg, ultraviolet rays
  • the metal bumps 30 may be formed by an electroplating process.
  • the metal bumps 30 can be provided with multiple layers as required. In this embodiment, there are two electroplating layers.
  • the specific metallization includes a first electroplating layer 301 and a second electroplating layer formed on the first electroplating layer 301. 302; the first electroplating layer 301 adopts one or more of metal copper, nickel, and gold; and the second electroplating layer 302 adopts one or more metal tin, silver, and lead.
  • S106 remove the remaining first photoresist layer 40 , after the first photoresist layer 40 is removed, the metallization layer 20 other than the metal bumps 30 is exposed to the outside, as shown in FIG. 6 , in the metallization layer 20
  • a second photoresist layer 50 is formed on the upper surface of the metallization layer 20 .
  • the second photoresist layer 50 is a photoresist covering the upper surface of the metallization layer 20 .
  • S107 Remove the second photoresist layer 50 on the metallization layer 20 outside the preset position, so as to expose the metallization layer 20 outside the preset position, as shown in FIG. 8; wherein the preset position is at least To cover the passivation layer openings 104 other than the metal bumps, that is, to retain the second photoresist layer 50 that can at least cover the positions of the passivation layer openings 104 .
  • the second photoresist layer 50 outside the preset position is removed to expose the metallization layer 20 outside the preset position.
  • the second photoresist layer 50 is exposed to high-intensity light through the photomask, wherein the area outside the preset position is covered by the opaque area on the photomask; the developing solution is used to develop, so that the area outside the preset position is covered by the opaque area on the photomask.
  • the unexposed photoresist is removed by the developer.
  • the position of the metallization layer 20 to be removed can be effectively controlled by the arrangement of the second photoresist layer 50.
  • all metallizations outside the area covered by the metal bumps 30 are generally performed.
  • the layers 20 are all removed.
  • only a part of the metallization layer 20 needs to be removed because part of the metallization layer 20 outside the coverage area of the metal bump 30 needs to be preserved to form the protection of the pad 102 .
  • the second photoresist layer 50 is provided to conveniently control the exposure of the metallization layer 20 to be removed, thereby better realizing the selective removal of the metallization layer 20 .

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Abstract

本发明公开了一种金属凸块结构及制造方法，其中金属凸块结构，包括裸芯片、金属化层和金属凸块，裸芯片具有基板、焊盘、钝化层。金属化层至少覆盖在金属焊盘的上表面；金属凸块成型在金属化层的上表面并具有位于钝化层开口的底部。本发明使金属凸块直接成型在焊盘上避免了金属凸块对钝化层的影响节省了PI的使用。

Description

金属凸块结构及制造方法 技术领域
本发明涉及芯片封装技术领域，特别是一种金属凸块结构及制造方法。
背景技术
现有技术中倒装焊芯片的凸块成型的工艺流程主要包括如下：引入裸芯片—在裸芯片上覆盖PI(聚酰亚胺，Polyimide)层—对PI层进行曝光—对PI层进行显影并烘烤—在PI层及裸芯片的焊盘之上溅射金属化层—覆盖光刻胶—对光刻胶进行曝光—对光刻胶进行显影—电镀金属凸块—剥离光刻胶—金属化层蚀刻—回流焊球。现有技术中由于金属凸块在成型后会形成部分覆盖在裸芯片的钝化层之上，为了避免金属凸块在钝化层之上对钝化层造成压裂破损的影响，在钝化层之上一般需要覆盖PI层以作为金属凸块的应力缓冲层。但是受限于PI层材料价格及技术的限制这必然会造成成本的增加。
因此，有必要提出一种能够避免PI层材料使用的金属凸块结构。
发明内容
本发明的目的是提供一种金属凸块结构，以解决现有技术中的不足，它能够通过将钝化层开口程度增大以使金属凸块直接成型在焊盘上从而避免了金属凸块对钝化层的影响进而节省了PI材料的使用。
本发明公开的金属凸块结构，包括裸芯片，具有基板和设置在所述基板上表面的焊盘、钝化层，所述焊盘自所述钝化层上的钝化层开口向外暴露；
金属化层，至少覆盖在所述金属焊盘的上表面并完全覆盖所述钝化层开口；
金属凸块，成型在所述金属化层的上表面并具有位于所述钝化层开口的底部。
进一步的，部分所述金属化层覆盖在所述钝化层的上表面，且仅部分位于钝化层开口内的金属化层的上表面形成有金属凸块。
进一步的，位于所述金属凸块之外的金属化层向外暴露。
进一步的，所述金属凸块横截面的尺寸小于所述钝化层开口的尺寸。
进一步的，所述金属凸块包括第一电镀层和成型在第一电镀层之上的第二电镀层；所述第一电镀层采用金属铜、镍、金的一种或多种；所述第二电镀层采用金属锡、银、铅的一种或多种。
本发明另一实施例还公开了上述的金属凸块的制造方法，包括如下步骤：
提供基板，基板的上表面形成有焊盘和钝化层，所述焊盘自钝化层上的钝化层开口向外暴露；
在钝化层的上表面及焊盘的上表面覆盖金属化层；
在金属化层的上表面成型第一光阻层，去除目标位置的第一光阻层以形成窗格并在窗格内成型金属凸块；
去除剩余第一光阻层后在所述金属化层的上表面形成第二光阻层；
去除预设位置之外的金属化层之上的第二光阻层，以使预设位置之外的金属化层向外暴露；
在去除预设位置之外的金属化层后去除剩余第二光阻层。
进一步的，所述预设位置至少覆盖金属凸块之外的钝化层开口。
进一步的，所述窗格的尺寸小于钝化层开口的尺寸。
进一步的，所述窗格设置在所述钝化层开口的中心位置。
进一步的，“保留预设位置处的金属化层之上的第二光阻层，以使预设位置之外的金属化层向外暴露”包括如下步骤：
透过光罩对第二光阻层进行曝光，其中，预设位置之外的区域被光罩上不透光区域所覆盖；
采用显影液进行显影，使预设位置之外的未经曝光的光刻胶即被显影液去除。
与现有技术相比，本发明通过将钝化层开口程度增大以使金属凸块直接成型在焊盘上从而避免了金属凸块对钝化层的影响进而节省了PI材料的使用。
附图说明
图1是本发明实施例公开的金属凸块的结构示意图；
图2至图10依次示出本发明实施例公开的金属凸块的制造方法的流程示意图；
附图标记说明：10-裸芯片，101-基板，102-焊盘，103-钝化层，104-钝化层开口，20-金属化层，30-金属凸块，301-第一电镀层，302-第二电镀层，40-第一光阻层，401-窗格，50-第二光阻层。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
本发明的实施例：如图1所示，公开了一种金属凸块结构，包括：裸芯片10、金属化层20和金属凸块30；所述裸芯片10包括基板101和设置在所述基板101上表面的焊盘102、钝化层103，所述焊盘102自所述钝化层103上的钝化层开口104向外暴露。
所述金属化层20至少覆盖在所述金属焊盘102的上表面并完全覆盖所述钝化层开口104；金属化层20为种子层，用于所述金属凸块30的成型。金属化层20可以为组合层包括第一层和设置在所述第一层之上的第二层，其中第一层为钛、钛钨等其他钛的金属合金或者化合物制成，所述第二层材质包括但不限于铜、金等金属。
所述金属凸块30成型在所述金属化层20的上表面并具有位于所述钝化层开口104的底部。金属凸块30的底部的尺寸不大于钝化层开口104的尺寸，具体的所述金属凸块30横截面的尺寸小于所述钝化层开口104的尺寸。金属焊盘102自所述钝化层开口104向外暴露，因此金属凸块30可以直接设置在金属焊盘102之上。扩大护层钝化层上的开窗，使同样尺寸的凸块结构全部生长在焊盘102上，在封装压合时，压合全部承接在焊盘102上，不会导致线路及钝化层的裂解。
由于金属凸块30直接设置在金属焊盘102之上避免了金属凸块30对钝化层103的影响，由于金属凸块30不设置在钝化层103之上，因此可以避免在金属凸块30与钝化层103之间设置由PI材料形成的缓冲层，从而能够减少PI材料的使用，进而能够有效的避免因受本国技术限制造成的PI材料供应不上的情况，同时由于PI材料主要依赖国外进口，其成本较大，降低了PI材料的使用能够有效的降低芯片制造过程中的成本。
由于金属凸块30设置在钝化层开口104内，金属凸块30的尺寸小于钝化层开口104的尺寸，为了避免焊盘102的直接向外暴露造成金属焊盘102的氧化腐蚀。本发明实施例中将金属焊盘102之上的金属化层20设置成至少完全覆盖钝化层开口104，现有技术中金属化层20一般与金属凸块30的尺寸相一致，本实施例将金属化层20进行外扩设计，金属化层20的尺寸大于金属凸块30的底部的尺寸并不小于钝化层开口104的尺寸，从而形成覆盖在焊盘102之上的一层保护层能够有效的避免焊盘102直接暴露。
具体的，金属化层20的尺寸大于钝化层开口104的尺寸，并且部分所述金属化层20覆盖在所述钝化层103的上表面，且仅部分位于钝化层开口104内的金属化层20的上表面形成有所述金属凸块30。在本实施例金属凸块30的尺寸设置成小于钝化层开口104的尺寸，当然在另一实施例中金属凸块30的尺寸还可以设置成与钝化层开口104的尺寸相一致。
由于金属凸块30的尺寸小于钝化层开口104的尺寸，因此会造成位于所述金属凸块30之外的部分金属化层20直接向外暴露，该部分向外暴露的金属化层20能够覆盖在金属凸块30之外的焊盘102之上从而起到保护焊盘102的作用。
本发明的另一实施例还公开了上述的金属凸块的制造方法，包括如下步骤：
S101：提供一裸芯片10，如图2所示，该裸芯片包括一基板101，其中基板101的上表面形成有焊盘102和钝化层103，所述焊盘102自钝化层103上的钝化层开口104向外暴露；
S102：在钝化层103的上表面及焊盘102的上表面覆盖金属化层20，如图3所示；金属化层20通过金属溅射工艺成型在裸芯片10之上；
S103：在金属化层20的上表面成型第一光阻层40，第一光阻成40为覆盖在金属化层20之上的光刻胶；
S104：通过曝光显影去除目标位置的第一光阻层40以形成窗格401如图4所示；其中目标位置与钝化层开口104位置相对，目标位置为钝化层开口104所覆盖的区域，也就是目标位置在基板101上的投影正好 落在钝化层开口104内，焊盘102上与目标位置相对设置的区域用于生长金属凸块30。所述窗格401的尺寸小于钝化层开口104的尺寸。所述窗格401设置在所述钝化层开口104的中心位置。这样在金属凸块30成型后金属凸块30能设置在钝化层开口104的中心位置，能够更方便的实现芯片的封装。
具体的，透过光罩对第一光组层40进行高强光线(如，紫外线)曝光，其中，与部分钝化层开口104位置相对的目标位置的第一光阻层40被光罩上不透光区域所覆盖。而后，将整个裸芯片放入显影液中进行显影，则目标位置上的未经曝光的光刻胶即被显影液去除，从而在目标区域形成窗格401。
S105：在窗格401内成型金属凸块30，如图5所示，金属凸块30可以采用电镀工艺成型。所述金属凸块30可以根据需要设置多层，在本实施例中共设置有两层电镀层，具体的金属化包括第一电镀层301和成型在第一电镀层301之上的第二电镀层302；所述第一电镀层301采用金属铜、镍、金的一种或多种；所述第二电镀层302采用金属锡、银、铅的一种或多种。
S106：去除剩余第一光阻层40，在第一光阻层40去除后所述金属凸块30之外的金属化层20向外暴露，如图6所示，在所述金属化层20的上表面形成第二光阻层50，如图7所示，第二光阻层50为覆盖在金属化层20上表面的光刻胶。
S107：去除预设位置之外的金属化层20之上的第二光阻层50，以使预设位置之外的金属化层20向外暴露，如图8所示；其中预设位置至 少要涵盖金属凸块之外的钝化层开口104，也就是保留至少能涵盖钝化层开口104的位置的第二光阻层50。将预设位置之外的第二光阻层50去除以暴露预设位置之外的金属化层20。
具体的透过光罩对第二光阻层50进行高强光线曝光，其中，预设位置之外的区域被光罩上不透光区域所覆盖；采用显影液进行显影，使预设位置之外的未经曝光的光刻胶即被显影液去除。
通过第二光阻层50的设置能够有效的控制需要去除的金属化层20的位置，现有技术中在金属凸块30成型之后一般会将金属凸块30覆盖区域之外的所有的金属化层20都去除掉，在本实施例中由于需要保存部分金属凸块30覆盖区域之外的金属化层20以形成对焊盘102进行保护，因此只需要去除部分金属化层20。在金属凸块30成型后通过设置第二光阻层50以方便的实现控制待去除的金属化层20的显露，从而更好的实现金属化层20的选择性去除。
S108：去除预设位置之外的金属化层20，如图9所示；由于第二光阻层50的设置在对金属化层20进行刻蚀时能够选择性的进行去除，以保留预设位置的金属化层20进而形成对焊盘102的保护。
S109：去除剩余第二光阻层50，如图10所示，最后采用回流工艺将金属凸块30成型为金属球。
以上依据图式所示的实施例详细说明了本发明的构造、特征及作用效果，以上所述仅为本发明的较佳实施例，但本发明不以图面所示限定实施范围，凡是依照本发明的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在本发明的保 护范围内。

Claims (10)

  1. 一种金属凸块结构，其特征在于，包括：
    裸芯片，具有基板和设置在所述基板上表面的焊盘、钝化层，所述焊盘自所述钝化层上的钝化层开口向外暴露；
    金属化层，至少覆盖在所述金属焊盘的上表面并完全覆盖所述钝化层开口；
    金属凸块，成型在所述金属化层的上表面并具有位于所述钝化层开口的底部。
  2. 根据权利要求1所述的金属凸块结构，其特征在于，部分所述金属化层覆盖在所述钝化层的上表面，且仅部分位于钝化层开口内的金属化层的上表面形成有金属凸块。
  3. 根据权利要求1所述的金属凸块结构，其特征在于，位于所述金属凸块之外的金属化层向外暴露。
  4. 根据权利要求1所述的金属凸块结构，其特征在于，所述金属凸块横截面的尺寸小于所述钝化层开口的尺寸。
  5. 根据权利要求1所述的金属凸块结构，其特征在于，所述金属凸块包括第一电镀层和成型在第一电镀层之上的第二电镀层；所述第一电镀层采用金属铜、镍、金的一种或多种；所述第二电镀层采用金属锡、银、铅的一种或多种。
  6. 一种如权利要求1所述的金属凸块结构的制造方法，其特征在于，包括如下步骤：
    提供基板，基板的上表面形成有焊盘和钝化层，所述焊盘自钝化层上的钝化层开口向外暴露；
    在钝化层的上表面及焊盘的上表面覆盖金属化层；
    在金属化层的上表面成型第一光阻层，去除目标位置的第一光阻层以形成窗格并在窗格内成型金属凸块；
    去除剩余第一光阻层后在所述金属化层的上表面形成第二光阻层；
    去除预设位置之外的金属化层之上的第二光阻层，以使预设位置之外的金属化层向外暴露；
    在去除预设位置之外的金属化层后去除剩余第二光阻层。
  7. 根据权利要求6所述的金属凸块结构的制造方法，其特征在于，所述预设位置至少覆盖金属凸块之外的钝化层开口。
  8. 根据权利要求6所述的金属凸块结构的制造方法，其特征在于，所述窗格的尺寸小于钝化层开口的尺寸。
  9. 根据权利要求8所述的金属凸块结构的制造方法，其特征在于，所述窗格设置在所述钝化层开口的中心位置。
  10. 根据权利要求5所述的金属凸块结构的制造方法，其特征在于，“保留预设位置处的金属化层之上的第二光阻层，以使预设位置之外的金属化层向外暴露”包括如下步骤：
    透过光罩对第二光阻层进行曝光，其中，预设位置之外的区域被光罩上不透光区域所覆盖；
    采用显影液进行显影，使预设位置之外的未经曝光的光刻胶即被显影液去除。
PCT/CN2022/085732 2021-04-09 2022-04-08 金属凸块结构及制造方法 WO2022214058A1 (zh)

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