Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
  • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/016—Manufacture or treatment using moulds
  • H10W74/017—Auxiliary layers for moulds, e.g. release layers or layers preventing residue
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
  • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/10—Configurations of laterally-adjacent chips

Definitions

• This invention is directed toward the formation of assemblies of microelectronic components.
• PCBs printed circuit boards
• I/O input/output
• Passive components have relatively large metal-plated terminals which are similarly aligned and placed onto screen-printed solder paste patterns on the PCB.
• the assembly must be heated to a temperature around 250-260 °C to melt the solder (e.g., a solder such as “SAC”, which has a common composition of 96.5% Sn, 3% Ag and 0.5% Cu) and subsequently allow it to flow freely over the pads, with temperature above 220 °C applied for a minute or longer.
• the solder e.g., a solder such as “SAC”, which has a common composition of 96.5% Sn, 3% Ag and 0.5% Cu
• CTE coefficients of thermal expansion
• the CTE of Si is 2.7 ppm/°C
• Cu is 17 ppm/°C
• SAC is about 23 ppm/°C
• FR4 (which is a designation for a range of silica-filled epoxy composites used for PCB construction) is about 14-16 ppm/°C
• underfill polymers and/or varieties of epoxies are between about 15 and over 30 ppm/°C near ambient temperature (above its glass transition temperature it may be substantially higher).
• an assembly used for integrated circuit manufacturing comprises: a substrate; a release layer disposed over the substrate; a plurality of components disposed over the release layer, wherein the plurality of components each comprise an active face in contact with the release layer; and an embedding material layer encapsulating the plurality of components.
• each of the active faces of the components do not substantially contact the embedding material.
• the embedding material layer comprises a plurality of embedding material sublayers.
• the embedding material layer comprises an amalgam.
• the amalgam is a low CTE amalgam with a CTE of about -5 ppm/°C to about 5 ppm/°C.
• the amalgam comprises a matrix metal, an alloying metal and a low CTE material.
• the matrix metal comprises Ga.
• the alloying metal is selected from the group consisting of Cu, Ni, Ag, Ce, and combinations thereof.
• the low CTE material is selected from the group consisting of Zr ⁇ Os, HfWiOx, SC 2 W 3 O 12 , and combinations thereof.
• the amalgam further comprises an element selected from the group consisting of an additional low CTE material, a passivating material, a liquid, a reducing agent, and combinations thereof.
• the release layer comprises an undercut region positioned between the release layer and at least one component of the plurality of components. In some embodiments, the undercut region comprises a deposited material. In some embodiments, the substrate comprises pores.
• a process of fabricating the assembly comprises: depositing a plurality of components onto a release layer, wherein the release layer is disposed over a substrate; and encasing the plurality of components with an embedding material layer.
• encasing the plurality of components with the embedding material layer is performed by a spray process.
• a process of integrating an assembly into an integrated circuit comprises: separating a release layer from a plurality of components encapsulated by an embedding material layer of an assembly to form a laminate; and depositing an interconnect material over each exposed surface of the plurality of components to form a wired laminate.
• the process further comprises placing the wired laminate into a device, and electrically connecting the wired laminate to the device.
• a laminate for integrating into a circuit device comprises: a plurality of components each comprising a plurality of encapsulated surfaces and an exposed surface; and an embedding material encapsulating the plurality of encapsulated surfaces of the plurality of components.
• each of the exposed surfaces comprises a pad. In some embodiments, each of the exposed surfaces are substantially coplanar with each other. In some embodiments, the laminate further comprises interconnect materials disposed over each of the exposed surfaces. In some embodiments, the embedding material comprises an amalgam. In some embodiments, the amalgam comprises a matrix metal, an alloying metal and a low CTE material. In some embodiments, the amalgam is a low CTE amalgam with a CTE of about -5 ppm/°C to about 5 ppm/°C.
• FIG. 1 is a line graph depicting the hardening kinetics for a gallium amalgam at various temperatures.
• FIG. 2 is an illustration of a nebulizer system and method of use for spray deposition of an amalgam.
• FIG. 3 is an illustration of a nebulizer that may be used for spray deposition of an amalgam.
• FIG. 4 is an illustration of an assembly with an embedding material encapsulating components, according to some embodiments.
• FIG. 5 is an illustration of an assembly with multiple embedding materials encapsulating components, according to some embodiments.
• FIG. 6 is an illustration of an assembly with embedding material deposited in undercut regions beneath components, according to some embodiments.
• FIG. 7 is an illustration of an assembly with embedding material deposited on components and a porous substrate with a vacuum applied to the porous substrate, according to some embodiments.
• the assemblies may include closely spaced components held in place by a release layer or by vacuum applied to a porous substrate, and at least one embedding material deposited to encapsulate the components while leaving the side of the components comprising pads uncoated, thereby forming a laminate of the components and embedding material.
• the embedding material may be selected to have favorable CTE, electrical insulating/conductive and/or thermally conductive properties.
• such assemblies may include a deposited material insulating one component from another.
• interconnects may be affected by the patterning technology used.
• the processes used for patterning Cu layers which utilize relatively large aspect ratios where typically the traces are wider than they are high in order to achieve satisfactory geometry with isotropic wet etching, force interconnect traces to be many tens of pm wide (e.g., often at least 2 or 3 thousandths of an inch or more).
• Such interconnect limitations in turn increase the areal density, and the number of interconnect layers required.
• the resulting structure is both thick and rigid (e.g., PCBs are typically about 1 mm thick, and packaged ICs are of the order of 0.5 mm thickness or more). Furthermore, heat dissipation through the IC package material and PCB is relatively poor due to the use of of organic polymers with thermal conductivities of the order of 0.01% of that of Si.
• a desirable architecture would be one in which all of the ICs and other components needed by a circuit, regardless of their sizes, were placed as close together as possible (e.g., preferably with not more than a few pm between them) in bare form and surrounded on all but one surface (e.g., bottom surface) by a thermally conductive embedding medium or material whose CTE was similar to Si and whose surface was coplanar with the ICs.
• the ICs would be thin (e.g., less than 50 pm) which would make the product thin, and in some embodiments flexible.
• Such thinness may facilitate making a contiguous embedding or encapsulating layer as it is difficult to get solidifiable materials to flow uniformly into a space a few pm wide and 250 pm high.
• thinness minimizes the stress in the normal direction to the IC in part due to CTE mismatch of materials, and a thin but highly thermally conductive embedding medium allows for efficient heat removal.
• interconnect traces could advantageously be formed by fabricating them directly on the flat surface of the embedding medium, with approximately the same size as the final layer of interconnect within each IC.
• Two or more such ICs, or an IC with some relatively small passive components, will effectively act as one large IC.
• Such an architecture is difficult or impossible to fabricate utilizing lithography due to diminishing yields and the size limitations of the lithography equipment.
• the width and thickness of traces connecting two I/O pads that are not immediately adjacent may be greater than those that connect adjacent pads.
• such traces of the two I/O pads will likely still be relatively smaller than common PCB traces because of the smaller distance over which current is to be transported.
• top layer interconnect in ICs is of the order of about 2 pm thick and 4- 5 pm wide, these inter-component traces will be an order of magnitude or more smaller than in traditional technologies, which would allow for more compact routing and further savings in circuit area with improved electrical performance due to the shorter traces.
• the laminate may be encapsulated by one or more protective layers to make it ready for use in a product.
• These layers will typically be chosen according to specific requirements, and may be formed using materials well known in the art, such as metals (e.g. aluminum or copper), ceramics (e.g. oxides and nitrides), polyimides, polyester (such as poly(ethylene terephthalate), polyurethane, and others. Connections to other components, if needed, may be provided by metal traces which terminate at the edge of the substrate and are not covered by the final package, or through vias which may be formed through the protective encapsulation. Since complete functional circuits may be fabricated in one unit according to the invention, relatively small numbers of I/O connections are likely to be needed.
• Such a structure can be used for any degree of integration, from circuits conventionally contained within single chips to those which currently occupy large PCBs.
• One application is to what are called “multi-die packages” or “system in package” devices, which may contain a few or even several IC dice in one package, but which is still intended to be placed on a conventional PCB along with others to form the final functional system.
• Another application is for relatively large and complex chips, such as high-end microprocessors, field- programmable gate arrays, and the like. These may be fabricated from “chiplets” that may not function alone as they are subunits of a functional IC and are combined appropriately to form a self-standing circuit.
• such subunits could be the elements of a block diagram of a microprocessor (e.g., the core, the I/O section, the direct memory access (“DMA”) controller, the timing section, etc.).
• a microprocessor e.g., the core, the I/O section, the direct memory access (“DMA”) controller, the timing section, etc.
• Advantages of such an architecture include the ability to easily upgrade a system with improvements in a specific subsystem without having to make completely new masks for the entire chip, the ability to quickly design a new system, and/or the ability to reduce power consumption and signal degradation due to long interconnect traces.
• an embedding material fluid is coated over a set of components disposed over a temporary release layer, wherein the fluid penetrates micron-scale gaps between the components and can be cured at low temperatures to a solid (e.g., flexible solid) embedding material and encapsulates the components.
• the fluid and solid compositions may be selected to have a thermal conductivity and CTE comparable or closely matched to silicon, and may be either electrically conductive or insulating.
• Triggering processes may be used for separating components from the release layer. As described in U.S. Patent No. 6,946,178, the triggering processes include exposing the release layer to heat and light in a single step to degrade the release layer. Irradiation with light (e.g., actinic light) may be used to selectively activate a compound (e.g., polymer) of a release layer under a component which the user wishes to transfer, while leaving other components on the same substrate unactivated.
• light e.g., actinic light
• Heating the compound of the release layer (also referred to as a digital release material (e.g., digital release adhesive (“DRA”))) to an appropriate temperature (e.g., less than about 150°C) may cause the release layer to vaporize and release the component while leaving the unactivated devices still attached to the donor substrate.
• a digital release material e.g., digital release adhesive (“DRA”)
• DRA digital release adhesive
• components may be held in place in close proximity by the release layer while an embedding material encapsulates the components on all sides except for the side facing the release layer, and subsequently the release layer may be decomposed to transfer the assembly and/or expose a non-encapsulated side of the components for application of interconnects.
• transfer processes include Photopolymer Component Assembly (“PCA”) and Light-Induced Forward Transfer (“LIFT”).
• the embedding material comprises an amalgam mixture of gallium and particles of another metal (e.g., copper and/or nickel).
• Such amalgams may be fluid when first mixed, but as the elements interdiffuse a high melting point solid is formed.
• the melting point of an alloy of about 65% Ga, 30% Cu, and 5% Ni melts at over 500°C, yet solidifies from a fluid mixture at ambient temperature (e.g., about 25°C or about 30°C).
• Such amalgams are described, for example, by U.S. Patent #5,053,195 and in “Amalgams for Improved Electronics Interconnection”, IEEE Micro, pp. 46-58, 1993, each of which are incorporated by reference in their entirety for all purposes.
• FIG. 1 depicts the hardening kinetics for a gallium amalgam (5% Ni, 30% Cu).
• gallium amalgams with hardening results similar to those depicted in FIG. 1 have typically utilized powders with average particle diameters in the range of microns to tens of microns.
• the particles may be mixed in an ultrasonic mixer or jetting apparatus.
• ultrasonic spray coaters e.g., coaters made by Sono-tek Corporation, of Milton, NY
• liquid feedstocks are converted into aerosols by an ultrasonic atomizer immediately prior to coating.
• FIG. 2 depicts such a spray coating apparatus (i.e., nebulizer) for spray deposition as discussed in U.S. Patent No. 6,358,567, which is incorporated by reference in its entirety for all purposes.
• the system includes liquid 2 pumped from a liquid pump 4 to an ultrasonic transducer 6 that is used to cause vibrations in the liquid to break up the sprayed liquid into small (e.g., sub-micron sized) droplets of an aerosol that are sprayed onto a substrate 8 disposed over a heater.
• the liquid may comprise the metal particles present in a mixture (e.g., solution). For example, most metals (e.g., Cu and Ni) are not more reactive toward each other than they are toward themselves.
• the metal particles can be combined in a single solution or dispersion, and provided to the desired aerosol particle stream.
• the liquid comprises a passivating material.
• the metal particles comprise a passivating layer.
• FIG. 3 schematically depicts a commercial nebulizer 300 from the Sono-Tek Corporation, in which two input streams are combined.
• the nebulizer 300 includes a liquid A feed channel 302 that comprises a microbore tubing 304, and a liquid B feed channel 306 surrounding the liquid A feed channel 302 and the microbore tubing 304 and encased in a housing 314.
• liquid A 306 and liquid B 310 are combined at an atomizing surface 312 and sprayed out of the nebulizer 300.
• streams of gas may be used to direct streams of aerosol particles from separate liquid streams toward each other in order to mix them.
• Such shaping streams are used, for example by Sono-tek in some spray coating nozzles, and some aspects of shaping steams are disclosed in U.S. Pub. No. 2010/0078496, incorporated by reference in its entirety.
• Other jetting systems such as those made by Optomec (Albuquerque, NM), nScrypt (Orlando, FL) or others may be used to form streams of nanoparticles for mixing and deposition.
• the streams or liquids may include varying amounts of solvent.
• the solvent may be a low-boiling solvent so that it is quickly evaporated once deposited from a surface.
• the solvent may aid in producing a homogeneous, close-packed distribution of particles on the deposited surface.
• the velocity of droplets in such systems is of the order of a few, tens or hundreds of m/s (e.g., 1-900 m/s)
• the distance between dispenser tip and substrate is about a few millimeters and is traversed in at most a few milliseconds, therefore allowing relatively small metal particles to be used without hardening of the formed amalgam before deposition.
• Metal (e.g., gallium) nanoparticles may be synthesized by a variety of methods.
• One example method for synthesizing gallium nanoparticles is described by M.F. Melendrez, et ah, in the Journal of Colloid and Interface Science, vol. 346, pp. 279-287 (2010), which is incorporated by reference in its entirety for all purposes. Since the melting point of Ga is about 29°C, the particles may be kept in solid form or delivered as a liquid.
• Ga may be mixed with nanoparticulate metals by an ultrasonic nebulizer as described herein, which allow for deposition within milliseconds or less after mixing.
• alternating thin layers of Ga and other nanoparticles may be deposited.
• the resulting film of alternating thin layers of Ga and other nanoparticles is heated to melt the Ga and facilitate formation of a homogeneous distribution of particles in the fluid matrix, or with fluid occupying the interstices.
• metal nanoparticles are stabilized against agglomeration, since many bare metal surfaces are reactive and tend to stick to other similar surfaces.
• Examples of thin passivating coatings which can be removed at low temperatures are known and are commercially available.
• a passivating coating for Cu is made by Zerovalent NanoMetals, in Rochester, NY, or the external surface of the metal particle may be oxidized to form a passivating coating.
• reducing agents may be used to remove oxides formed on metal particle surfaces.
• a forming gas (e.g., 4% 3 ⁇ 4 in N2, and/or formic acid) may be used in the gas stream of an application device (e.g., nebulizer) or applied in a separate stream to the deposition surface.
• an application device e.g., nebulizer
• ultrasonic aerosol generators and their associated spray deposition are described, other methods of forming and depositing mixtures of nanoparticles may also be utilized.
• suitable passivation of the particle surfaces may be achieved by oxide formation and/or the attachment of relatively labile organic ligands.
• solutions or suspensions of the relatively unreactive particles may be mixed with a solution or suspension of Ga particles in an apparatus (e.g., a rapid-mixing apparatus), and then deposited by one of a variety of techniques (e.g., spray coating, slot die (i.e., meniscus) coating, and ultrasonic coating, and jetting under pressure (e.g., inkjet printing)).
• the protective passivation may be removed by heat, chemical treatment (e.g. forming gas, formic acid, etc.), and/or photolysis.
• FIG. 1 shows that a high-melting point solid can be formed without heating the object above ambient temperature (i.e., about 25 °C), it may be advantageous to heat the amalgam mixture (e.g., to about 85 °C or 100 °C) to complete the cure more rapidly. Such temperatures are often experienced by electronic products as a result of their normal operation, and so the circuit will likely see excursions to these values in any event.
• the CTE of the amalgam is or is substantially matched to the circuit material (e.g., Si) to mitigate or prevent these excursions from causing damage relative to typical architectures.
• a low CTE amalgam is used.
• the amalgam e.g., low CTE amalgam
• the amalgam includes a matrix metal and an alloying metal.
• the amalgam e.g., low CTE amalgam
• the amalgam (e.g., low CTE amalgam) comprises an amount of the matrix metal of, of about, of at least, or of at least about, 40 wt.%, 45 wt.%, 50 wt.%, 55 wt.%, 60 wt.%, 65 wt.%, 70 wt.%, 75 wt.%, 80 wt.%, 85 wt.%, 90 wt.%, 92 wt.% or 95 wt.%, or any range of values therebetween.
• the matrix metal comprises Ga.
• the alloying metal is selected from Cu, Ni, Ag, Ce, and combinations thereof.
• the low CTE material is selected from ZrWiOs, HfWiOx and/or SC 2 W 3 O 12 .
• the low CTE amalgam further includes an additional low CTE material.
• the additional low CTE material is selected from S1O 2 , S1 3 N 4 , AI 2 O 3 , Si, non- stoichiometric versions thereof, and combinations thereof.
• the amalgam (e.g., low CTE amalgam) further includes a passivating material.
• the amalgam (e.g., low CTE amalgam) further includes a liquid (e.g., solvent). In some embodiments, the liquid is a low viscosity liquid.
• the amalgam (e.g., low CTE amalgam) further includes a reducing agent.
• the CTE of the amalgam is about 15 - 20 ppm/°C, and may vary depending on the specific composition of the amalgam. In some embodiments, lower CTE values may be desirable. There are some materials whose CTE is very close to zero (i.e., smaller than Si), and in some cases even negative. For example, silica (S1O2) has a CTE of about 0.5 ppm/°C. Thus, in some embodiments, a mixture of silica and amalgam in the appropriate proportions can lower the CTE closer to the desired value.
• the CTE of a mixture is not, in general, precisely equal to the mass-weighted average of the components, the relationship between mass fraction and CTE over a wide range of compositions is often close to linear or approximately linear.
• the amalgam has a CTE of, or of about, -25 ppm/°C, -20 ppm/°C, -19 ppm/°C, -18 ppm/°C, -17 ppm/°C, -16 ppm/°C, -15 ppm/°C, -14 ppm/°C, -13 ppm/°C, -12 ppm/°C, -11 ppm/°C, -10 ppm/°C, -9 ppm/°C, -8 ppm/°C, -7 ppm/°C, -6 ppm/°C, -5 ppm/°C, -4 ppm/°C, -3 ppm/°C, -2 ppm/°C, -1 ppm/°
• a negative CTE is provided by ZrWiOs, at about -7.2 ppm/°C.
• the particles of the compounds should be as small as possible (e.g., nanoparticles). Nanoparticles of ZrWiOs have been synthesized (see, for example, H.
• a composite amalgam material should preferably form a uniform solid at temperatures that is tolerated by the circuit components.
• ZrWiOs is sintered at temperatures over 1000°C and therefore may not be practical for use by itself, or in combination with other refractory materials. This problem has in fact prevented low or zero CTE materials from being used in many applications, as described by U.S. Patent No. 6,132,676.
• a uniform solid may be formed at low temperatures and pressures (e.g., atmospheric pressure and temperature less than 150°C or less than 100°C).
• compositional materials can be added in the same way, provided that the amalgam composition includes sufficient initially liquid Ga to fill the empty spaces between solid particles.
• the free volume in a uniform array of equally sized spherical particles is about 33% of the total, depending on the packing. However, by combining multimodal distributions, the free volume can be substantially reduced. For example, with three particle sizes, the remaining free volume may be about 4-5%.
• the thermal conductivity of ZrWiOs which is a ceramic material, is not as high as a typical metal or an elemental crystal such as silicon. According to C.A. Kennedy, et al., in Solid State Communications vol. 134, pp 271-276 (2005), it is about 1 W/m-K, as compared to 149 W/m-K for Si and 401 W/m-K for Cu.
• amalgams e.g., Ga amalgams
• matrix metal e.g., Ga
• the Ga amalgam comprises Ga-M and a negative CTE material (e.g., ZrWiOs), where “M” represents one or more metal atoms.
• M is selected from Cu, Ni, Ag, Ce, and combinations thereof.
• the negative CTE material is selected from ZrWiOs, HfWiOx and/or SC 2 W 3 O 12 .
• the Ga amalgam further comprises a low CTE material.
• the low CTE material is selected from S1O 2 , S1 3 N 4 , AI 2 O 3 , Si, non- stoichiometric versions thereof, and combinations thereof.
• matrix metals e.g., Ga
• the matrix metal may not mix with all other elements.
• the solubility of Si in Ga is about 10 7 atomic %.
• alloys of matrix metals e.g., Ga
• oxides e.g., ZrW 2 0s.
• nanoparticles may be made to be more compatible for forming alloys with each other by coating them using atomic layer deposition, which is a technique that is especially good for forming specific bonds between many metals and oxygen.
• the matrix metal has a D50 average particle size of, of about, of at most, or of at most about, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, or a particle size distribution defined by any range of values therebetween.
• the alloying metal has a D50 average particle size of, of about, of at most, or of at most about, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, or a particle size distribution defined by any range of values therebetween.
• the low CTE material has a D50 average particle size of, of about, of at most, or of at most about, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, or a particle size distribution defined by any range of values therebetween.
• the additional low CTE material has a D50 average particle size of, of about, of at most, or of at most about, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, or a particle size distribution defined by any range of values therebetween.
• the amalgam includes multimodal particle size distributions of particles.
• thin pure metal layers can also be deposited by atomic layer deposition (“ALD”), with strong adhesion to substrates through bonds (e.g., chemical).
• ALD atomic layer deposition
• metals can be bonded to the surface of a given type of nanoparticle which are more compatible with Ga alloys, so that stronger bonds may be subsequently formed.
• Cu is a metal that has high compatibility with an ALD deposited Ga layer, but others are also known, including for example W, Pt, Co, Fe, Ag and Ni.
• fluidized bed technology e.g., as practiced by ALD Nanosolutions in Broomfield, CO
• these coatings can be put onto nanoparticles.
• the amalgam is electrically conducting, for example an amalgam in which a matrix metal (e.g., Ga) comprises the majority of the volume.
• the amalgam is insulating, for example an amalgam in which a ceramic material (e.g., ZrWiOs) is the majority of the volume.
• an advantage of an electrically conducting amalgam is that it can serve as the ground plane for an integrated circuit, eliminating the need for one layer in the interconnect portion of the circuit.
• the components could be electrically isolated from one another by depositing an insulating layer (e.g., of an insulating embedding material) before applying an embedding material comprising an electrically conductive amalgam composition.
• the insulating layer may be a thin (e.g. at most about 1 pm) oxide layer, for example a layer of Si0 2 .
• the insulating layer is formed by plasma-enhanced chemical vapor deposition (PECVD) or any other deposition technique.
• PECVD plasma-enhanced chemical vapor deposition
• the insulating material and/or insulating amalgam material comprises a dielectric material selected from ZrWiOs, S1O2, AI2O3, S13N4, a polymer material (e.g., polyimide, liquid crystal polymers, and benzocyclobutene based polymer), non- stoichiometric ratios thereof, and combinations thereof.
• FIG. 4 illustrates an assembly 400 comprising a plurality of components 406 disposed over and held in place by a release layer 404 disposed over a temporary substrate 402, wherein the components 406 are encapsulated by a single layer of embedding material 408.
• the embedding material 408 is an amalgam described herein.
• the embedding material 408 is deposited to encase the components 406 by a method (e.g., spray deposition or multilayer deposition) described herein.
• FIG. 4 is not drawn to scale, the relative height and width of the assembly 400 is intended to indicate that in some embodiments a large assembly aspect ratio that may be present. As depicted in FIG.
• each component of the plurality of components may be of the same, similar and/or different height, width or shape as the other components.
• the components may have a height of, of about, of at most, or of at most about, 2 pm, 3 pm, 5 pm, 8 pm, 10 pm, 15 pm, 20 pm, 25 pm, 30 pm, 35 pm, 40 pm, 45 pm, 50 pm, 60 pm, 70 pm, 80 pm, 90 pm, 100 pm, 150 pm, 200 pm, 300 pm, 400 pm, 500 pm, 600 pm, 700 pm, 800 pm or 1000 pm, or any range of values therebetween.
• the thinnest components with regard to height may be of the order of 25 pm tall or thinner.
• the spacing between two adjacent components is, is about, is at most, or is at most about, 0.1 pm, 0.5 pm, 1 pm, 2 pm, 3 pm, 4 pm, 5 pm, 6 pm, 7 pm, 8 pm, 9 pm, 10 pm, 12 pm, 15 pm or 20 pm, or any range of values therebetween.
• the spacing between two adjacent components may be 5-10 pm or less.
• the components may have a width of, of about, of at least, or of at least about, 3 pm, 4 pm, 5 pm, 6 pm, 7 pm, 8 pm, 9 pm, 10 pm, 12 pm, 15 pm, 20 pm, 25 pm, 30 pm, 35 pm, 40 pm, 45 pm, 50 pm, 60 pm, 70 pm, 80 pm, 90 pm, 100 pm, 150 pm, 200 pm, 300 pm, 400 pm, 500 pm, 600 pm, 700 pm, 800 pm, 900 pm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm, or any range of values therebetween.
• the width of a component may be between about 25 pm and several mm.
• the components 406 are positioned upside down such that their active faces or sides (e.g., pads) are in contact with the release layer 404, and therefore the active sides are not in contact with the embedding material 408.
• the embedding material 408 is deposited it is hardened.
• hardening is performed by heating and/or allowing the embedding material to cure while resting.
• the laminate subsequent to deposition and/or hardening of the embedding material, the laminate comprising the components 406 and the embedding material is separated from the release layer 404 and substrate 402. In some embodiments, the laminate is peeled away from the release layer.
• a component may be a passive component.
• a passive component is a capacitor or resistor.
• the components are about 150 pm tall (i.e., thick) or more. In some embodiments, the components about twice as wide as they are tall (i.e., thick).
• MEMS microelectromechanical systems
• MEMS microelectromechanical systems
• the embedding material is applied from an amalgam comprising a liquid.
• the liquid is a low viscosity precursor liquid, which may allow complete filling of the narrow cracks between tall components with the embedding material.
• the assembly further comprises a temporary border or dam that may be used to contain the amalgam at the edges of the assembly (e.g., while the material hardens).
• the thickness of the release layer is, or is about, 0.5 pm, 1 pm, 2 pm, 3 pm, 4 pm, 5 pm, 6 pm, 7 pm, 8 pm, 9 pm, 10 pm, 12 pm, 15 pm, 20 pm or 25 pm, or any range of values therebetween.
• the release layer is about 1 -2 pm thick, which may be sufficient to hold the components on a flat surface.
• the substrate surface has an average surface height variation of, of about, of at most, or of at most about, 0.01 pm, 0.05 pm, 0.1 pm, 0.5 pm, 1 pm, 2 pm, 3 pm, 4 pm or 5 pm, or any range of values therebetween.
• FIG. 5 illustrates an assembly 500 comprising a plurality of components 506 disposed over and held in place by a release layer 504 disposed over a temporary substrate 502, wherein the components 506 are encapsulated by a first layer of embedding material 508 and a second layer of an embedding material 510.
• the first layer of embedding material 508 may comprise depressions and/or cracks, where the surface is only partially planarized by flow.
• any number of embedding material layers may be used to encapsulate the components, such as, or at least, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 layers, or any range of values therebetween.
• a layer may comprise two or more sublayers of the same or different composition.
• each of the embedding material layers may have the same, similar or different relative heights (i.e., thicknesses).
• the embedding material of the first and/or second layer may include an insulating material, an amalgam material, or combinations thereof.
• at least one of the embedding materials of the layers comprises an amalgam material.
• encapsulation of the components is performed after formation of the interconnects on the active side of the components. In some embodiments, encapsulation of the components is performed before formation of the interconnects on the active side of the components.
• various compositions of embedding materials can be applied to encapsulate the components.
• the first layer may be applied to the components first and allowed to become at least partially solidified. In some embodiments, the composition of the first layer may be selected to match as closely as possible the CTE of silicon, so that during thermal cycling the stress in and around the silicon ICs is as small as possible. In some embodiments, such a composition may increase the reliability of the contacts between metal interconnect lines and IC I/O pads.
• the second layer with a second composition may subsequently be applied to the components over the first layer.
• the second layer composition is selected for high thermal conductivity.
• a modest mismatch of CTE of the first layer relative to the silicon may be tolerable.
• Such a modest mismatch of CTE may be acceptable, for example, where all the critical components in the first layer rise above and are not completely encapsulated by the first layer, and therefore the critical components will be approximately equally affected by the thermally induced expansions and contractions of the second layer.
• wider or larger components such as passive devices (e.g. resistors and ceramic capacitors) which are in contact with both the first and second layers, may be less affected by CTE mismatch because their larger contact areas provide more total adhered area to the interconnects and so are less susceptible to failure.
• two different embedding material compositions are used in two layers.
• the two different embedding material compositions are configured to simultaneously optimize the thermal expansion match and the thermal conductivity of the device (e.g., circuit).
• the thicknesses of each of the embedding material layers may be selected and configured for flexibility.
• the multiple layers may have the same, similar, or different relative thicknesses.
• the embedding material of the first layer may be an insulator material (e.g., insulating amalgam material), which as an example may eliminate the need for a dielectric layer.
• the embedding material of the second or subsequent layer may a conductor, which as an example may form a ground plane and may in some instances contact some of the passive components, such as bypass capacitors which are all connected to ground.
• laminates and assemblies described herein may be suited for use with ultrathin components, or may be used with components which have not been thinned and may be much thicker.
• components with thicknesses of or of about 250 pm or 500 pm may be utilized, which are examples of silicon wafer thicknesses that may appear in commercial products.
• Any component placement process may be used; for example the conventional pick and place processes disclosed in U.S. Patent Nos. 6,946,178 and 7,141,348, which are incorporated by reference herein in their entirety for all purposes.
• one objective is to provide an embedding layer whose surface is coplanar with the component surfaces, for example as depicted in FIG. 4, so that high-resolution interconnects may be fabricated with minimal further processing of the surface.
• one problem that arises with conventional injection molding embedding is that the components may be pushed into the temporary release layer, and then after application of the molding or embedding compound and release, a discontinuity in height between chip and embedding material, called mold flash, is present.
• mold flash a discontinuity in height between chip and embedding material
• the release layer (e.g., temporary adhesive polymer) has a thickness as described herein (e.g., about 1-2 pm).
• the release layer thickness may be configured such that it is sufficient to temporarily hold the components (e.g., typical surface mount components) as described herein to the substrate.
• the substrate is or is substantially flat (i.e., low average surface height variation) as described herein (e.g., to within less than about ⁇ 1 pm variation).
• the process by which the embedding material is applied does not involve strong lateral forces.
• the components penetrate into the release layer (e.g., polymer film) by, by about, by at most, or by at most about, 1%, 5%, 10%, 20%, 30%, 40%, 50%, 60% or 70%, or any range of values therebetween, of the release layer thickness.
• the resulting discontinuity of the release layer at the deposited component edge is, is about, is at most, or is at most about, 0.01 pm, 0.05 pm, 0.1 pm, 0.2 pm, 0.4 pm, 0.5 pm, 0.6 pm, 0.7 pm, 0.8 pm, 0.9 pm, 1 pm, 1.2 pm, 1.5 pm or 2 pm, or any range of values therebetween.
• discontinuity of the release layer at the deposited component edge is comparable to topographic variations which are normally present on finished ICs.
• assemblies and processes described herein may advantageously reduce the disturbing forces present during molding, and thereby reduce the requirement for thick release layers (e.g., temporary adhesive layers) into which extensive component penetration may occur.
• the release layer (e.g., temporary adhesive polymer) is a photoresist which loses a fraction of its mass as a consequence of light exposure and/or thermal development.
• photoresists are common in the microlithography industry and are based on the loss of t-butyoxycarbonyl moieties, whose loss may result in a loss of about 15% of the film thickness.
• this decomposition results in gaseous products, and reduces (e.g., temporarily or permanently) the adhesion of any surface attached to the film.
• the substrate and laminate comprising the components may be delaminated (e.g., pulled apart) as the decomposition takes place.
• the decomposition of the release layer separates the substrate and laminate comprising the components.
• the release layer material (e.g., photoresist polymer) may be etched (e.g., imaged and developed) to create small depressions between the component and the release layer.
• FIG. 6 illustrates an assembly 600 with a deposited material 612 deposited on the walls of and in undercut regions 606A and 606B of the release layer 604 beneath components 608 and 610, respectively.
• the deposited material is an embedding material as described herein.
• the deposited material is an insulating and/or dielectric material.
• the release layer 604 is disposed over a substrate 602, and the components 608 and 610 are disposed over the release layer 604.
• the substrate 602 (e.g., temporary substrate) is a porous material.
• the undercut regions 606A and 606B may be formed by optical exposure and/or thermal development of the material of the release layer 604 (e.g., polymer).
• the distance the component overhangs the undercut region of the release layer (e.g., polymer) may be a few micrometers.
• the distance the component overhangs the undercut region of the release layer (e.g., polymer) is, is about, is at most, or is at most about, 0.1 pm, 0.2 pm, 0.5 pm, 1 pm, 2 pm, 3 pm, 4 pm, 5 pm, 6 pm, 7 pm, 8 pm, 9 pm, 10 pm, 12 pm, 15 pm or 20 pm, or any range of values therebetween (e.g., about 2-10 pm).
• FIG. 6 depicts where the thickness of undercut region 606A is less than that of undercut region 606B, and where the thickness of the release layer 604 directly beneath component 608 is less that that beneath component 610.
• the thickness of an undercut region and/or release layer region may be reduced relative to another undercut region and/or release layer region beneath two components due to one of the components positioned (e.g., depressed or having been pushed) more deeply into the release layer (e.g., polymer).
• the depth of component depressions into the release layer is, is about, is at most, or is at most about, 25 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm or 1000 nm, or any range of values therebetween (e.g., about 150-300 nm, when the original release layer thickness film is about 1-2 pm; or when the original release layer thickness film is about 2-10 pm relatively deeper depression is formed).
• the release layer is irradiated with light prior to disposing the components over the release layer and undercut regions.
• irradiation of the release layer forms a sensitized release layer.
• the sensitized release layer decomposes when sufficient heat is applied.
• the release layer is deposited on the substrate as a sensitized release layer.
• the release layer is irradiated with light subsequent to disposing the components over the release layer and undercut regions.
• the deposited material e.g., dielectric film
• the deposited material is then deposited on the walls of the components and within the undercut regions.
• deposition of the deposited material is performed by sputtering or PECVD.
• the mean free path of the reactive molecules of the deposited material is sufficiently small that at least some of them diffuse under the overhang before depositing, resulting in a thin layer with tapered thickness further into the undercut regions as shown in FIG. 4.
• the deposited material makes a smooth transition across the edge of the component.
• the deposited material covers the edges of components, whose sharpness might otherwise make it difficult to fabricate interconnects later.
• the deposited material insulates the components (e.g., chips) from later deposited interconnects, and for example may insulate regardless of what metal structures might be part of an IC close to its edge.
• this smooth transition of the deposited material may compensate for any difference in height which might be present due to different amounts of penetration of the components within the release layer (e.g., polymer).
• the assembly 600 may be further processed to encase the components 608 and 610 with embedding materials and/or release the components from the release layer 604 and substrate 602.
• the release layer e.g., photoresist film
• the release material e.g., t-butyoxycarbonyl
• the deposited material is a dielectric
• a thicker graded deposit will be formed that may be useful for covering some edge defects or structures of components.
• the release layer is a thermally decomposable polymer such as disclosed in U.S. Patent Nos. 7,300,824 and 7,863,762, which are incorporated by reference in their entirety for all purposes.
• the release layer e.g., polymer film with or without photosensitizer
• the release layer may be formed on a porous substrate that can serve as a porous vacuum chuck.
• the release layer is heated to a decomposition temperature while a vacuum is applied to the porous vacuum chuck, thereby causing the decomposition products of the release layer to exit through the pores of the porous vacuum chuck while the porous vacuum chuck holds the component laminate in place.
• the embedding material may be applied prior to or subsequent to decomposition of the release layer.
• the release layer may be decomposed before the deposition of the release material (e.g., dielectric).
• the vacuum from the porous vacuum chuck holds the individual components in place, even when there are undercut regions, because this area is a small fraction of the total area, and an adequate pressure differential may be maintained across the components in spite of the open area.
• the deposited material e.g., dielectric film
• an atmospheric pressure process e.g., atmospheric pressure PECVD
• the surfaces of the components are directly in contact with the surface of the substrate (e.g., porous vacuum chuck).
• the porous vacuum chuck defines a, or a substantially, flat, planar surface regardless of any difference in the extent to which components had penetrated into the release layer (e.g., polymer).
• FIG. 7 illustrates the components 704 and 706 disposed over the substrate 702 (e.g., temporary substrate) after removal of a release layer (e.g., temporary adhesive layer) and deposition of a deposited material (e.g., insulating dielectric).
• the insulating material is deposited prior to or subsequent to removal of the release layer (e.g., adhesive).
• the contact (e.g., adhesion) between the deposited material (e.g., dielectric film) and the substrate 702 may be separated (e.g., broken) when the component laminate (e.g., circuit laminate) is peeled away, as it comprises only a small fraction of the total area.
• the substrate may be treated with a low surface energy coating (e.g., thin coating).
• the low surface energy coating is selected from a plasma-deposited fluorocarbon film, self-assembled monolayer of fluorocarbons, or combinations thereof.
• the assembly 700 may be further processed to encase the components 704 and 706 with embedding materials and/or release the components from the substrate 702.
• the separated component laminate may be further processed to add interconnects to the active faces of the components.
• the porous vacuum chuck comprises a plurality of pores.
• the pores are of nanometer-scale diameters and/or micron-scale diameters.
• the pores have an average diameter of, of about, of at most, or of at most about, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 75 nm, 100 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm, 1 mhi, 1.5 mhi, 2 mhi, 3 mhi, 5 mhi or 10 mhi, or any range of values therebetween.
• the substrate e.g., porous vacuum chuck
• the substrate comprises silicon.
• the release layer is deposited on the porous vacuum chuck prior to component deposition.
• a vacuum chuck may not be used to hold the components during the component placement process because, for example, initially all of the area is exposed and the first components placed would not be subject to sufficient holding force.
• vacuum can be applied once the release layer and components are placed on the substrate, and the vacuum is sufficient to hold the components due to the reduction of exposed area on the porous vacuum chuck prior to or subsequent to decomposition of the release layer (e.g., temporary adhesive) (e.g., exposed spaces in between the closely-spaced components).
• Conditional language such as “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to imply that features, elements, and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or steps are included or are to be performed in any particular embodiment.

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