CN112930588A - 半导体装置与烧结纳米粒子的连接 - Google Patents

半导体装置与烧结纳米粒子的连接 Download PDF

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CN112930588A
CN112930588A CN201980067473.4A CN201980067473A CN112930588A CN 112930588 A CN112930588 A CN 112930588A CN 201980067473 A CN201980067473 A CN 201980067473A CN 112930588 A CN112930588 A CN 112930588A
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polymer layer
conductive
substrate
dispensing
semiconductor device
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张荣炜
维卡斯·古普塔
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述的实例中，一种封装装置(100)包含具有装置安装表面的衬底(101)，所述衬底(101)具有在所述装置安装表面上彼此间隔的具有第一厚度的导电凸区(103)。第一聚合物层(105)在所述导电凸区(103)之间安置于所述装置安装表面上，所述第一聚合物层(105)具有等于所述第一厚度的第二厚度。所述导电凸区(103)具有不被所述第一聚合物层(105)覆盖的外表面。第二聚合物层(107)安置在所述第一聚合物层(105)上，所述导电凸区(103)的所述外表面不被所述第二聚合物层(107)覆盖。导电纳米粒子材料(109)安置在所述导电凸区(103)的所述外表面上。第三聚合物层(111)在所述导电凸区(103)上的所述导电纳米粒子材料(109)之间安置于所述第二聚合物层(107)上。至少一个半导体装置裸片(121)安装到所述第三聚合物层(111)，所述至少一个半导体装置裸片(121)具有接合到所述导电纳米粒子材料(109)的电端子(123)。

Description

半导体装置与烧结纳米粒子的连接
本发明大体上涉及半导体装置，且更特定来说涉及安装在衬底上的半导体装置。
背景技术
随着半导体工艺的不断进步，半导体装置越来越小。半导体装置表面上的端子之间的距离(“间距”)不断缩小。进一步来说，针对芯片级封装(其中封装大小为与裸片面积大致相同的面积)的期望及在不需要额外衬底、插入器或载体的情况下将半导体装置裸片安装到芯片载体或电路板的持续需求正在增加。倒装芯片安装用于将半导体装置裸片上的端子安装到载体或衬底。倒装芯片封装要求在半导体装置裸片的端子与衬底上的导电垫或凸区之间进行竖直或“z”连接。为了减少安装裸片所需的表面积，在“x”或“y”方向上延伸的连接(例如接合线、带状接合或重布层)不是所要的，这是因为这些连接增加了板面积。使用焊料凸块、焊球、导电柱(例如铜柱凸块)及铜螺柱在半导体装置裸片的电路侧上的接合垫与衬底(例如芯片载体或电路板)上的导电凸区之间进行竖直连接，这种连接通过从半导体装置裸片上的接合垫在竖直或“z”方向上延伸到凸区而节约总板面积。
为了在装置与板之间进行电连接，已使用各向异性导电膜(ACF)及各向异性导电粘合剂(ACA)。导电球体放置在带、膜或粘合剂中。承载导电球体的膜安置在半导体装置裸片上的裸片接合垫或铜垫与衬底上的凸区之间。通过使用热能与压缩能的组合，在半导体裸片上的接合垫与衬底上的导电凸区之间的竖直方向上通过ACF形成导电路径。然而，因为ACF中的导电球体是随机分布的，所以在垫之间可能会因为导电路径偶尔出现在“x”或“y”方向上而形成不必要的短路。进一步来说，由于导电球体在ACF中的随机分布，形成导电路径的球体的数量也可变化，因此成品装置中不同电连接的导电性或电阻特性可变化。
可将球体固定放置在带或膜中，这增加了膜的成本，并需要与所使用的半导体装置及板的接合垫及凸区对准。金属螺柱可在膜中的已知位置形成并安置，再次增加了成本。
发明内容
在所描述的实例中，一种封装装置包含具有装置安装表面的衬底，所述衬底具有在所述装置安装表面上彼此间隔的具有第一厚度的导电凸区。第一聚合物层在所述导电凸区之间安置于所述装置安装表面上，所述第一聚合物层具有等于所述第一厚度的第二厚度。所述导电凸区具有不被所述第一聚合物层覆盖的外表面。第二聚合物层安置在所述第一聚合物层上，所述导电凸区的所述外表面不被所述第二聚合物层覆盖。导电纳米粒子材料安置在所述导电凸区的所述外表面上。第三聚合物层在所述导电凸区之间安置于所述第二聚合物层上。至少一个半导体装置裸片安装到所述第三聚合物层，所述至少一个半导体装置裸片具有接合到所述导电纳米粒子材料的电端子。
附图说明
图1A到1G是绘示用于形成布置的实例过程的步骤的横截面图。
图2是用于形成布置的方法的流程图。
图3是用于形成布置的替代方法的流程图。
图4以截面方式绘示用于封装装置的布置。
图5是封装装置的投影图。
图6是用于多芯片模块的封装装置布置的横截面。
图7是替代封装装置的投影图及平面图。
具体实施方式
附图中对应的数字及符号通常是指对应的部分，除非另有指示。附图不一定按比例绘制。
在此描述中，术语“半导体装置”是在半导体衬底上形成的装置。半导体装置包含集成电路，其中在半导体衬底上形成数个、数百个或数千个个别装置(例如晶体管)，然后使用在半导体衬底的有源表面上方形成的导电导体彼此耦合以形成完整的电路功能。集成电路可包含处理器、模数转换器、存储器及其它集成装置。术语半导体装置还包含形成在半导体衬底上的离散装置，例如离散晶体管、功率场效应晶体管(FET)、开关功率转换器、继电器、二极管、光耦合器、微波电路，及其它装置，例如无源装置，例如可控硅整流器(SCR)、电阻器，电容器、变压器、电感器及换能器。在此描述中，术语“半导体装置裸片”是最初在半导体晶片上与许多其它半导体装置形成的单个半导体装置，然后通过被称为“单粒化”的切割过程与半导体晶片分离。在此描述中，术语“衬底”包含模制互连衬底(MIS)、层压板、塑料、陶瓷、膜或带基衬底、印刷电路板(PCB)，包含纤维增强玻璃衬底(例如FR4)、BT树脂衬底、导电金属(包含铜、不锈钢、合金42)的金属引线框架，及预模制引线框架(PMLF)，其包含金属引线及在衬底中形成的塑封料。进一步来说，术语“衬底”包含另一半导体装置裸片或半导体晶片的一部分，使得在所述布置中，半导体装置裸片可面对面堆叠以在封装装置中进行额外集成。
在此描述中，术语“喷墨沉积”是用于在表面上沉积材料的额外工艺。在印刷技术中，术语“喷墨印刷”是指用喷嘴将墨滴以图案的形式分配在一个表面上以形成字符及符号，从而使墨滴额外沉积。在工业应用中，喷墨喷嘴可以添加剂沉积的形式沉积材料以在表面形成层。喷墨沉积使用许多耦合到包含电致动器的墨槽的精细喷嘴。储液罐中的压电致动器可响应于电信号迫使少量已知体积的液体材料通过喷嘴。热喷墨喷嘴在储液罐中有一个电阻元件，所述电阻元件加热并膨胀油墨，迫使已知体积的油墨通过喷嘴。在这两种情况下，当墨水下降时，表面张力会导致球形滴形成。由于喷墨喷嘴非常精细，且由于喷嘴包含响应于电信号形成液滴，因此术语“按需液滴”或“DOD”用于描述喷墨沉积工具在喷嘴相对于表面移动(将表面或喷嘴相对于另一个移动)时精确地沉积少量液体。这种精确的液滴放置可常有效地使用材料来精确地放置材料，减少浪费，且不需要清洁或蚀刻步骤来从表面部分移除不需要的材料。与溅射或其它方法相比，喷墨沉积不需要掩模及图案化步骤。当使用喷墨沉积来沉积材料时，多余或不需要的材料的移除也被消除。
在此描述中，术语“电端子”是用于与半导体装置裸片进行电连接的端子。电端子可包含形成接合垫的铝、铜或其它导电金属。焊料凸块、铜凸块、铜柱及铜柱凸块可作为电端子的一部分形成在接合垫上。电端子的凸块可包含额外镀层，例如镍、钯、锡、金、焊料及化学镀镍浸没金(ENIG)与化学镀镍化学镀钯浸没金(ENEPIG)的组合，以促进可焊性、增加附着力、并减少或防止腐蚀或氧化金属(例如铜或铝)。术语“电端子”包含用于与半导体装置裸片进行电连接的所有这些布置。在此描述中，术语“热压缩”是指同时施加高温及机械压力。在实例中，使用热压缩将包含导电纳米粒子的层接合到表面，同时烧结纳米粒子以形成导电路径。在此描述中，术语“纳米粒子”及“纳米球体”是直径在1到100纳米之间的粒子或球体。在此描述中，术语“导电纳米粒子”包含纳米粒子及涂有金属以形成纳米粒子的纳米球体，这些纳米粒子将在通过烧结的热处理下形成导体。包含金属导电纳米粒子的实例可烧结油墨材料是银纳米粒子油墨。在额外替代方案中，导电纳米球体可为金、铜、钯、镍及其组合。在此描述中，衬底上的术语“导电凸区”是用于与衬底中的导体进行电连接的导电区域。通常使用铜凸区，也可使用铝、金及其它导体。铜凸区可镀有镍、金、锡、钯及其组合，以增加可焊性、增加附着力、并减少或防止腐蚀或氧化。在此描述中，被描述为“B级”材料的材料是一种材料，例如液体，其可部分固化以形成稳定的固体层，同时保持可用以在稍后的步骤中完全固化。用于接合装置的B级聚合物可部分固化以形成B级材料的层。在实例布置中，聚合物层可部分固化以形成B级材料，且此层随后可进一步且完全固化以将两个表面接合在一起。
在此描述中，元件被描述为具有“相等厚度”。当每一元件的外表面与另一元件的外表面形成共同表面时，两个元件具有相等厚度。然而，在制造过程中，任一元件的厚度可能发生偏差，且这种偏差可能导致两个元件之间的厚度略有差异，且由于这些制造差异，共同表面的一些部分可升高或相对于共同表面的其它部分而下降。如果两个元件希望具有相等厚度以形成共同表面，如本文所用，那么两个元件被称为具有相等厚度，即使一些制造偏差可以并确实发生。
在所述布置中，通过在衬底上的导电凸区上方分配具有导电纳米粒子的材料来解决在半导体装置裸片与衬底之间提供电连接的问题，同时在衬底上的凸区之间分配聚合物介电层以在衬底上方形成层。半导体装置裸片与衬底对准并放置在所述层上。热压缩可用于通过在所述层中烧结导电纳米粒子将半导体装置裸片的端子与衬底上的凸区接合，从而在装置之间形成导电路径。在实例布置中，烧结的纳米粒子在z方向上提供低电阻导电路径，而不在x及y方向上形成不需要的导电路径，从而防止垫之间不需要的短路。
本文所描述的布置适用于许多“倒装芯片”装置封装及倒装芯片安装装置。在倒装芯片布置中，半导体装置裸片具有电端子，所述电端子可包含布置在电路侧表面上的接合垫及/或接合垫上的导电凸块或柱。半导体装置裸片安装在衬底上，电路侧表面朝向衬底上的装置安装区域，或“倒装”(与电路侧表面朝向远离衬底的布置相比)。倒装芯片封装可包含在经暴露外表面上具有焊球阵列的衬底，以形成球栅阵列(BGA)封装。图7中展示与这些布置一起有用的BGA封装。实例应用包含通过倒装芯片将多个半导体装置裸片安装到衬底来形成多个芯片模块。在实例布置中，所述衬底是印刷电路板(PCB)。印刷电路板可包含层压在一起的多层导体，且可由介电材料形成。用于印制电路板的材料包含用于导体的铜、铝、金及黄铜，及绝缘材料，例如纤维增强玻璃(FR4)、BT树脂、塑料膜、陶瓷、聚酰亚胺、塑料层及带。可形成半导体装置封装，衬底是导电引线框架，且半导体装置在半导体装置裸片安装到引线框架之后被封装在塑封料中。实例包含四方扁平无引线(QFN)封装及有引线封装。图5展示与这些布置一起使用的QFN封装。
虽然所描述的实例中的一些说明在衬底上使用单个半导体装置裸片，但可在布置中将多个装置封装在一起。裸片可以额外布置而堆叠。可将高电压组件(例如FET装置)提供为离散装置，并使用衬底封装，且可与另一装置一起封装，例如，与FET栅极驱动电路一起封装。传感器或模数转换器IC可与数字集成电路一起封装，以形成系统单芯片(SOC或SOIC)封装装置。包含多个半导体装置的封装装置可被称为系统级封装(SIP)。在一些实例布置中，衬底可为半导体晶片的一部分，所述半导体晶片包含用于形成连接的导体。在另一实例中，衬底本身可为另一半导体装置裸片，形成堆叠裸片布置。
为了将倒装芯片安装的半导体装置裸片耦合到衬底，需要竖直或“z”连接。在一些布置中，需要额外模制步骤。
在所述布置中，衬底具有经布置成接收至少一个半导体装置裸片的导电凸区。导电凸区与半导体装置裸片上的电端子相对应地布置。使用喷墨沉积或其它类型的沉积，分配液体材料以形成层，并覆盖导电凸区之间及周围的衬底表面，而导电凸区的上表面保持暴露。所述材料是电介质，且可经提供为聚合物油墨，其经配置为喷墨喷嘴分配，或作为适合于模板印刷的液体。在一个实例中，导电凸区从衬底的表面延伸，且聚合物油墨被分配到足以形成大致相等厚度的层以形成与凸区最外表面大体上连续的表面的厚度。在与所述布置有用的实例中，所述聚合物可为聚酰亚胺、环氧树脂、双马来酰亚胺树脂、丙烯酸酯或其混合物中的一者。聚合物的厚度可在大约10微米到几百微米之间。聚合物可经固化以使其更难更好地实现后续工艺，例如通过热固化或UV固化。在替代实例中，此步骤可省略。
在一个实例中，通过使用横穿衬底表面区域的喷墨沉积喷嘴来同时进行另外两种材料的额外分配。这两种材料包含在导电凸区之间的衬底的部分中的额外聚合物，及包含导电纳米粒子的材料，所述导电纳米粒子经分配以覆盖导电凸区的经暴露表面。这两种材料经分配以形成厚度大体上均匀的层，这两种材料的厚度大致相等，因此这两种材料的最外经暴露表面形成大体上连续的表面。在另一额外实例布置中，两种材料按顺序分配，一个喷嘴按顺序用于两种材料，或使用不同的喷嘴按顺序分配材料，但按顺序执行分配。第二聚合物可为B级材料，其可通过加热或UV部分固化以形成稳定的固体层，使得用于导电凸区的开口不受进一步工艺的干扰。此步骤是任选的，且可省略。导电纳米粒子材料然后可通过相同或另一喷墨喷嘴工具在第二沉积工艺中分配。喷墨沉积喷嘴可非常精确地分配材料的每一者，以形成所要的图案，而无需光致抗蚀剂、掩模或蚀刻步骤，即使在非常精细的几何结构。因此，沉积工艺具有成本效益及时间效益，且不需要酸或化学处理。材料使用非常有效，不需要移除多余的材料。第二聚合物层的厚度可与凸块的厚度大致相等，所述厚度通常在几微米到几百微米之间。
在导电纳米粒子沉积在衬底上的导电凸区上方之后，在导电凸区之间的区域上沉积额外聚合物材料，以在第三聚合物层中形成开口，从而暴露导电纳米粒子材料。这些开口与要安装到衬底的半导体装置裸片上的电端子相对应，且所沉积的聚合物层的厚度与电端子的厚度相对应，无论是铜凸块、柱凸块、球或螺柱形状，如下文进一步描述的，使得能够将具有电端子的半导体装置安装在导电纳米粒子材料上。
在所述布置中，在将金属纳米粒子及第三聚合物分配到所述衬底上之后，将半导体装置裸片倒装芯片安装到所述衬底。在实例工艺中，半导体装置裸片与衬底对准，使得半导体装置裸片的电端子与衬底上的导电凸区上方的开口相对应地对准，然后将半导体装置裸片放置成与金属纳米粒子材料及第三聚合物接触。执行热压缩接合步骤，所述热压缩接合步骤将导电纳米粒子烧结，以在半导体装置裸片的电端子与衬底上的导电凸区之间形成低电阻导电路径。在此过程中，固化第二及第三聚合物层，以硬化材料。在一个实例中，可使用130到250摄氏度的温度，且在大约5兆帕(MPa)的压力下执行热压缩步骤约5到15秒。取决于所选择的纳米粒子油墨及聚合物的特性，在一些布置中，可通过使用热工艺而不使用压力来执行额外固化及额外烧结，以进一步固化聚合物层并增加纳米粒子油墨中的导电性。在额外替代布置中，第一聚合物层可在衬底上进行模板印刷而不是喷墨沉积。
图1A到1G是绘示实例过程的选定步骤的一系列横截面。在图1A中，衬底101经展示为定向成使得装置安装表面104面向上(如图1A到1G所定向)，装置安装表面104具有呈一图案的多个导电凸区103。在一个实例中，导电凸区为铜且可包含如上文所述的额外电镀层。在额外布置中，凸区103由其它导电材料制成。在图1B中，第一聚合物经分配以在导电凸区103之间形成厚度约等于导电凸区103的厚度的层105。聚合物105是绝缘电介质且可使用喷墨沉积进行分配。如图1B所示，聚合物105可由标记为116的喷墨沉积喷嘴分配。在替代布置中，可使用模板沉积工艺来分配聚合物层105。导电凸区103的上表面(如图1B所定向)至少部分地从层105暴露。在实例过程中，聚合物层105可为B级材料，其可部分固化以形成B级层，以在额外处理之前提高稳定性及强度。聚合物层105的部分固化可通过热固化或UV固化工艺来完成。在另一实例过程中，可能不完成此部分固化。聚合物层105形成与导电凸区103的上表面大致同延的表面106，其中导电凸区在表面106处从聚合物层105暴露。
图1C以横截面图绘示实例过程中的接下来的步骤。在图1C中，两个喷墨沉积喷嘴用于同时分配来自喷嘴116的额外聚合物材料及来自喷嘴118的导电纳米粒子材料。因为在喷墨沉积中，喷嘴包含通过向喷嘴发送电信号来形成“按需液滴”的能力，当喷墨喷嘴相对于衬底表面移动时，例如以光栅图案，这两种油墨材料可精确地沉积，使得来自118的导电纳米粒子在仅导电凸区103上方的层中形成区域109，而来自116的额外聚合物材料在仅第一聚合物层105上方且不覆盖凸区103的层中形成区域107。以这种方式，两种材料107、109形成额外层。第二聚合物层107可取决于所选材料进行部分固化，例如热固化或UV固化，以在进一步处理之前硬化此层。聚合物层107具有表面108，其大体上是聚合物层107与导电纳米粒子区域109之间的连续表面，但在制造过程中可能发生一些偏差，使得所述层的厚度可能有轻微偏差。为了形成均匀且所要厚度的层，可多遍次地沉积多个较薄层。或可使用单遍次。尽管在这些实例中展示两个喷嘴116、118以明确绘示，但在喷墨沉积工具中，许多喷嘴，例如几十个或数百个喷嘴，可用于每一墨水的分配工具中。另外，沉积工具可具有同时或以某种顺序图案穿过衬底以更快速地分配材料的多个磁头。
图1D以另一横截面图描绘沉积第三聚合物层的额外步骤。在图1D中，喷墨沉积工具116沉积另一聚合物层111。聚合物层111沉积到厚度112，所述厚度112经选择为与半导体装置裸片(图1D中未展示)上的电端子的高度大体上对应，所述半导体装置裸片将被倒装芯片安装到衬底101，如下文进一步描述。聚合物层111沉积在表面108的聚合物层107上，而导电纳米粒子区域109的表面仍被此聚合物层111覆盖，以使电端子(图1D中未展示，但参见下文所述的图1E)以在半导体装置裸片被倒装芯片安装时满足导电纳米粒子区域。迄今为止描述的用于聚合物层的材料，即层105、层107、层111，可为相同的聚合物材料。在替代布置中，聚合物层可不同。例如，聚合物层中的一些可为UV可固化的，而另一些为热固化材料。用于第一聚合物层105及第二聚合物层107的材料可为B级材料，其可经部分固化以形成B级层，且在下文描述的稍后热处理期间发生额外固化。各种聚合物层类型的组合形成额外替代布置。
图1E以横截面图描绘实例过程中的下一步骤。在图1E中，例如通过拾取及放置工具(未展示)与衬底101相对应并以倒装芯片定向放置半导体装置裸片121。电端子123与覆盖衬底101上导电凸区103的纳米区域109相对应地对准。然后使半导体装置裸片121与第三聚合物层111及纳米粒子区域109物理接触。第三聚合物层的高度112经选择为大体上与电端子123的厚度对应，使得当半导体装置裸片121与聚合物层111的上表面114接触时，电端子123将与导电纳米粒子区域109接触。
在图1F中，展示半导体装置裸片121及衬底101使用热与压力的组合(热压缩)接合在一起以同时固化聚合物层105、107及111，及使区域109中的可烧结纳米粒子烧结并在半导体装置裸片121上的电端子123与衬底101上的导电凸区103之间形成低电阻导电路径。在实例过程中，热压缩步骤之后可进行额外热处理，以进一步固化聚合物层105、107及111，且在不施加机械压力的情况下在区域109中进一步烧结金属纳米粒子。在进一步实例布置中，省略此额外固化。在一个实例中，可使用130到250摄氏度的温度，且在大约5兆帕(MPa)的压力下执行热压缩步骤约5到15秒。其它温度及压力值可用于形成替代布置。
图1G以另一横截面图绘示完成的封装半导体装置布置100。在图1G中，半导体装置裸片121通过区域109及聚合物层105、107及111中的烧结纳米粒子接合到衬底101。塑封料122覆盖装置安装侧上的衬底101的部分，但不覆盖相对侧，且可被描述为“包覆模制”。此塑封料层122保护半导体装置裸片121及聚合物层105、107。或者，可使用金属盖(未展示)来覆盖裸片而不使用塑封料。图1G中的衬底101进一步包含完成封装100的焊球或凸块125的阵列，所述封装100是球栅阵列(BGA)类型封装。这些焊球或凸块可在半导体装置裸片121安装到衬底101之后添加。塑封料122可使用使用树脂或环氧树脂的封装工艺形成。注意，虽然模制工艺被称为“封装”，但是即使当塑封料被模制工艺封装时，衬底101的部分也不被塑封料覆盖，例如图1G中的衬底101的底表面。塑封料122可包含填充料以改进热传递性能。塑封料在室温下可为液体或固体，如果在室温下是固体，那么可使用传送模具或块模具，通过首先在热室中加热塑封料，然后通过流道将其压入含有半导体装置裸片及衬底组合件的模具中。液体树脂可用作替代品。可使用块模具压力机。可同时模制多个安装的装置，然后在模制工艺完成后彼此分离。
图2是绘示用于形成如图1A到1G所示的布置的实例过程的流程图。在图2中，过程200从步骤202开始，执行喷墨沉积以在导电凸区之间的衬底上沉积第一聚合物层，用聚合物层填充凸区之间的间隙，所述聚合物层的厚度大约等于所述凸区的厚度。在步骤204处，执行固化步骤以在进一步处理之前至少部分地固化第一聚合物层，所述固化用于硬化并稳定第一聚合物层。固化可为热固化或UV固化，这取决于用于第一聚合物层的聚合物类型。
在步骤206处，过程200通过同时沉积第二聚合物层及导电纳米粒子区域而继续。例如，在此步骤在图1C中绘示。在一个实例中，使用喷墨沉积工具同时沉积第二聚合物层及纳米粒子区域，使得纳米粒子材料沉积在衬底上的导电凸区的表面上。应注意，如图1B所示，当沉积第一聚合物层时，导电凸区的上表面保持暴露。第二聚合物层沉积在导电凸区之间的第一聚合物层上，使得第二聚合物层不沉积在导电凸区上方，且第二聚合物层与金属纳米粒子区域在两种类型的材料之间形成大体上连续的上表面。
在步骤208处，可部分固化第二聚合物层以使所述层稳定且不太可能被后续工艺损坏。固化也可为UV固化或其它光固化、热固化或两者，具体取决于所用的材料。第二聚合物层可为与第一聚合物层相同的材料，或在替代布置中，可为不同的材料。
在步骤209处，将第三聚合物层沉积在第二聚合物层上方且在导电纳米粒子材料区域之间，如图1D所示。第三聚合物层具有大体上对应于半导体裸片上的电端子的厚度的厚度，所述半导体裸片将被倒装芯片安装到下文所述的衬底上。图1D展示第三聚合物层的沉积。
在步骤210处，拾取及放置工具将半导体装置裸片放置在衬底上方，半导体装置裸片的裸片垫上的电端子与第三聚合物层中的开口相对应，所述开口与衬底上的导电凸区相对应。此步骤在图1E中绘示。所述半导体装置裸片与所述金属纳米粒子区域及所述第二聚合物层物理接触。
在步骤212处，执行热压缩步骤。热及压力经施加以将半导体装置裸片压在第二及第三聚合物层及金属纳米粒子区域上，且热工艺的热固化聚合物层并烧结纳米粒子。由于纳米粒子的烧结，在半导体装置裸片的接合垫上的导电凸块与衬底上的导电凸区之间形成导电路径。此步骤在图1F中绘示。在一个实例中，可使用130到250摄氏度的温度，且在大约5兆帕(MPa)的压力下执行热压缩步骤约5到15秒。其它温度及压力值可用于形成替代布置。
在图2中的步骤213处，展示任选的额外热步骤。在一些实例工艺中，额外热步骤用于进一步固化聚合物层并进一步烧结可烧结纳米粒子。在其它实例过程中，此步骤213可省略。
图2中的步骤214绘示所述过程的最后步骤，衬底及半导体装置裸片进一步受到塑封料的保护，且执行额外工艺以完成如图1G所示的封装半导体装置。
图3以流程图绘示用于形成布置的替代过程300的步骤。从步骤302开始，将第一聚合物层沉积在导电垫之间的装置安装表面上的衬底上，以形成填充垫之间间隙的层。在一个实例过程中，使用喷墨沉积工艺来分配第一聚合物层。在另一替代布置中，可使用模板沉积工艺。
在图3中，在步骤304处，所述过程通过执行第一聚合物层的至少部分固化而继续。第一聚合物层可取决于聚合物进行热固化或UV固化或其它频率光固化。还可取决于为第一聚合物层选择的材料来执行完全固化。如以上图1B所示，第一聚合物填充衬底上导电凸区之间的间隙，但不覆盖导电凸区的上表面，且第一聚合物层与导电凸区的上表面形成大体上连续的表面。
在图3的步骤306处，执行另一沉积。在实例过程中，使用喷墨沉积工具仅在第一聚合物层上沉积第二聚合物层，使导电凸区的上表面保持暴露。在步骤307处，可固化第二聚合物层。取决于聚合物材料的不同，还可使用热固化、光固化或UV聚合物固化。如果第二聚合物层是B级材料，那么可形成B级层，以使所述层稳定且不太可能被后续步骤损坏。
在步骤308处，执行另一沉积，以将导电纳米粒子材料沉积在导电凸区的经暴露表面上，并与第二聚合物层形成大体上连续的表面。此步骤之后的过程的结果与图1C所示相同，所述第二聚合物层的上表面与金属纳米粒子的上表面形成表面层。
在图3中的步骤309处，将第三聚合物层沉积在导电纳米粒子材料区域之间的第二聚合物层上。此步骤在图1D中展示。
在图3中的步骤310处，拾取及放置工具将半导体装置裸片定位在衬底上方，电路侧表面朝向衬底上的导电凸区，并对准，使得半导体装置裸片上的电端子与导电纳米粒子材料对应地放置在衬底上方，且与衬底上的导电凸区对准。此步骤对应于图1E的横截面。
在步骤312处，将半导体装置裸片放置成与第二聚合物层及导电纳米粒子区域接触，并使用压力与热能的组合(即热压缩)将半导体装置裸片接合到衬底。热压缩工艺中的热既固化第一、第二及第三聚合物层(如果先前未固化)，又烧结导电纳米粒子材料以在半导体装置裸片上的导电端子与衬底上的导电凸区之间形成低电阻导电路径，形成z方向连接而不是x或y方向连接。在一个实例中，可使用130到250摄氏度的温度，且在大约5兆帕(MPa)的压力下执行热压缩步骤约5到15秒。其它温度及压力值可用于形成替代布置。
此步骤的结果例如图1F所绘示。另外，可在不使用压力的情况下进行额外热固化及烧结以进一步固化聚合物层并进一步烧结导电纳米粒子材料。在另一替代工艺中，额外热处理可省略，这取决于所使用的材料及层厚度。
在步骤314处，完成半导体装置封装的组装。如图1G中所示，半导体装置裸片可通过封装或包覆模制被塑封料覆盖。或者，可使用金属盖来覆盖裸片而无需模制。另外，球栅阵列封装可包含衬底的相对表面上的多个焊球，用于表面安装到系统印刷电路板，例如，如图1F所示。
图4以横截面图绘示半导体装置裸片421安装在衬底401上的布置，所述衬底401具有使用如上所述的沉积工艺中的一者形成的竖直连接，且形成无引线封装布置。在图4中，为了清楚解释，用于与图1G的元件类似的元件的参考数字是类似的。例如，半导体装置裸片421对应于图1G中的半导体装置裸片121。在图4中，半导体装置裸片421是倒装芯片安装到衬底401。半导体装置裸片421上的电端子423与衬底401上的导电凸区403对准并耦合。第一聚合物层405围绕导电凸区403。第二聚合物层407具有上表面，所述上表面与凸区403上的导电纳米粒子区域409的上表面形成大体上连续的表面。第三聚合物层411在导电纳米粒子区域409之间的第二聚合物层407上形成。通过烧结导电纳米粒子区域409形成的低电阻路径在半导体装置裸片电端子423与衬底401上的导电凸区403之间以z方向进行连接。在此实例中，衬底401是金属引线框架，其经受部分蚀刻工艺(有时被称为“半蚀刻”引线框架)以形成包含引线413及热或电垫412的上层402及下层。引线框架可通过从衬底401的一侧执行部分蚀刻以移除材料，并从相反侧执行第二部分蚀刻以移除材料来形成，在一些区域中，两个部分蚀刻可组合以形成延伸穿过引线框架的厚度的开口，且在另一些情况下，可在引线框架的一层或另一层中形成壁架或角部。塑封料422可安置在开口及移除区域中以完成衬底401。这些蚀刻及模制步骤可在使用衬底以形成用作衬底401的预模制引线框架(PMLF)之前完成。在半导体装置裸片421安装到衬底401且执行上述热压缩步骤以固化聚合物层并烧结导电纳米粒子以形成低电阻电路径之后，可执行包覆模制步骤以形成塑封料422以完成封装装置400。
图5以投影图描绘对应于图4中的横截面的四方扁平无引线(QFN)布置500。在图5中，塑封料522覆盖半导体装置裸片及衬底的至少上部。展示经布置用于封装装置500的表面安装的封装端子513，它们对应于图4中的引线413。因为封装端子不从封装半导体装置的主体延伸，所以封装被描述为“无引线”半导体封装。
图6以横截面绘示包含使用上述实例过程的一者安装到衬底601的多个半导体装置裸片的布置600。在图6中，如上文所描述，半导体装置631与另一半导体装置633经展示为安装到衬底601，并使用烧结导电纳米粒子及聚合物层电耦合到衬底601上的导电凸区。虽然在图6的实例中展示两个半导体装置，但在替代实例中，可将额外半导体装置裸片安装到衬底。在图6中，使用焊球625形成球栅阵列封装，其中模塑化合物635的包覆模制至少覆盖衬底601的上表面及半导体装置裸片。
图7以投影视图及底部平面图描绘用于布置的球栅阵列封装700。在图7中，球栅阵列封装700的塑封料主体735与球栅阵列端子725一起展示。BGA封装700对应于图6中的具有多个半导体装置的布置600或图1G中的BGA封装100。这些布置可经封装为用于半导体装置的其它封装类型。
在所描述的布置中可进行修改，且在权利要求的范围内可进行其它替代布置。

Claims (26)

1.一种封装装置，其包括：
衬底，其具有装置安装表面及相对表面，所述衬底具有在所述装置安装表面上彼此间隔的具有第一厚度的导电凸区；
第一聚合物层，其在所述导电凸区之间并围绕所述导电凸区位于所述衬底的所述装置安装表面上，且具有等于所述导电凸区的所述第一厚度的第二厚度，所述导电凸区具有不被所述第一聚合物层覆盖的外表面，所述第一聚合物层的外表面与所述导电凸区的外表面形成共同表面；
第二聚合物层，其在所述第一聚合物层上，所述第二聚合物层具有第三厚度，所述导电凸区的所述外表面不被所述第二聚合物层覆盖；
导电纳米粒子材料，其在所述导电凸区的所述外表面上且具有等于所述第三厚度的第四厚度，所述第二聚合物层的外表面与所述导电纳米粒子材料的外表面形成共同表面；
第三聚合物层，其在所述导电凸区上的所述导电纳米粒子材料之间位于所述第二聚合物层上，所述导电纳米粒子材料具有从所述第三聚合物层暴露的表面；及
至少一个半导体装置裸片，其安装到所述第三聚合物层且具有接合到所述导电纳米粒子材料的电端子。
2.根据权利要求1所述的封装装置，其中所述第三聚合物层具有与所述半导体装置裸片的所述电端子的厚度相对应的厚度。
3.根据权利要求1所述的封装装置，其中所述第一聚合物层是选自基本上由聚酰亚胺、环氧树脂、双马来酰亚胺树脂、丙烯酸酯及其组合组成的群组中的一者。
4.根据权利要求1所述的封装装置，其中所述第一聚合物层、所述第二聚合物层及所述第三聚合物层是选自基本上由下列各物组成的群组中的一者：聚酰亚胺、环氧树脂、双马来酰亚胺树脂、丙烯酸酯及其组合。
5.根据权利要求1所述的封装装置，其中所述导电纳米粒子材料是可烧结纳米粒子材料。
6.根据权利要求5所述的封装装置，其中所述导电纳米粒子材料包括金属。
7.根据权利要求6所述的封装装置，其中所述导电纳米粒子材料包括银。
8.根据权利要求1所述的封装装置，其中所述导电纳米粒子材料是选自基本上由下列各物组成的群组中的一者：银、锡、镍、铜、金、钯、合金及其组合。
9.根据权利要求1所述的封装装置，且其进一步包括在所述衬底的与所述装置安装表面相对的表面上的封装端子。
10.根据权利要求9所述的封装装置，其中所述封装端子进一步包括焊球阵列以形成球栅阵列封装。
11.根据权利要求9所述的封装装置，其中所述封装端子形成无引线封装。
12.根据权利要求1所述的封装装置，其中所述衬底包括印刷电路板。
13.根据权利要求1所述的封装装置，其中所述衬底包括预模制引线框架。
14.根据权利要求1所述的封装装置，其中所述衬底包括额外半导体装置裸片。
15.一种方法，其包括：
在衬底的装置安装表面上分配围绕彼此间隔的导电凸区的第一聚合物层，所述第一聚合物层具有等于所述导电凸区的第二厚度的第一厚度；
固化所述第一聚合物层，所述导电凸区的外表面从所述第一聚合物层暴露；
在所述第一聚合物层上分配第二聚合物层；
在所述导电凸区的所述经暴露外表面上分配导电纳米粒子材料；
在所述导电凸区之间在所述第二聚合物层上分配第三聚合物层，所述导电纳米粒子材料从所述第三聚合物层暴露；
在所述第三聚合物层上安装半导体装置裸片，所述半导体装置裸片具有与所述导电凸区上方的所述导电纳米粒子材料对准并接触的电端子；及
施加压力及热以将所述半导体装置裸片接合到所述衬底，所述热固化所述第二聚合物层及所述第三聚合物层，并烧结所述导电纳米粒子材料以在所述半导体装置裸片的所述电端子与所述衬底的所述导电凸区之间形成电连接。
16.根据权利要求15所述的方法，其中所述第一聚合物层的所述分配是通过喷墨沉积工艺执行的。
17.根据权利要求15所述的方法，其中所述第一聚合物层的所述分配是通过模板沉积工艺执行的。
18.根据权利要求15所述的方法，其中所述第一聚合物层是UV可固化的。
19.根据权利要求15所述的方法，其中所述第一聚合物层是热可固化的。
20.根据权利要求15所述的方法，其中分配所述第二聚合物层及分配所述导电纳米粒子层是同时执行的。
21.根据权利要求15所述的方法，其中分配所述第二聚合物层是在分配所述导电纳米粒子层之前执行的。
22.根据权利要求15所述的方法，其中分配所述第一聚合物层进一步包括分配选自基本上由聚酰亚胺、环氧树脂、双马来酰亚胺树脂、丙烯酸酯及其组合组成的群组中的一者。
23.根据权利要求15所述的方法，其中分配所述第一聚合物层、所述第二聚合物层及所述第三聚合物层各自进一步包括分配选自基本上由聚酰亚胺、环氧树脂、双马来酰亚胺树脂、丙烯酸酯及其组合组成的群组中的一者。
24.根据权利要求15所述的方法，其中分配所述导电纳米粒子层包括分配选自基本上由下列各物组成的群组中的一者：银、锡、镍、铜、金、钯、合金及其组合。
25.根据权利要求15所述的方法，其中分配所述第二聚合物层及分配所述第三聚合物层进一步包括喷墨沉积。
26.根据权利要求15所述的方法，其中所述第三聚合物层被分配到与所述半导体装置裸片上的所述电端子的高度相对应的厚度。
CN201980067473.4A 2018-12-07 2019-12-09 半导体装置与烧结纳米粒子的连接 Pending CN112930588A (zh)

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