WO2022208603A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2022208603A1 WO2022208603A1 PCT/JP2021/013259 JP2021013259W WO2022208603A1 WO 2022208603 A1 WO2022208603 A1 WO 2022208603A1 JP 2021013259 W JP2021013259 W JP 2021013259W WO 2022208603 A1 WO2022208603 A1 WO 2022208603A1
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- WO
- WIPO (PCT)
- Prior art keywords
- circuit pattern
- electrode
- semiconductor device
- pair
- terminal
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 10
- 230000020169 heat generation Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- -1 or the like Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
Definitions
- the present disclosure relates to semiconductor devices.
- a semiconductor device is provided with a terminal which is an external electrode whose one end is joined to a circuit pattern and whose other end is connected to an external device.
- a terminal which is an external electrode whose one end is joined to a circuit pattern and whose other end is connected to an external device.
- Patent Document 1 in order to increase the bonding area between an electrode and a wiring pattern (corresponding to a circuit pattern), one end of an electrode is provided with a pair of triangular bent portions. A structure is disclosed that is bent so as to stand on the joint surface.
- an object of the present disclosure is to provide a semiconductor device capable of suppressing heat generation at joints between circuit patterns and terminals when a large current is applied.
- a semiconductor device includes a circuit board having a circuit pattern on which a semiconductor element is mounted, and a terminal that is an external electrode whose one end is joined to the circuit pattern and whose other end is connected to an external device.
- the terminal comprises: an electrode joint part having a rectangular shape in top view, the lower surface of which is joined to the circuit pattern by a jointing material; and a pair of sub-wiring portions extending from both ends of the main wiring portion in the width direction along a second side and a third side adjacent to the first side of the electrode junction portion.
- the lower end portions of the pair of sub-wiring portions protrude downward from the lower surface of the electrode joint portion, and the lower end portions of the pair of sub-wiring portions are connected to the circuit pattern by the bonding material together with the lower surface of the electrode joint portion. It is joined.
- the circuit pattern and the electrode joint portion are joined together with the joint material in a state in which the lower ends of the pair of sub-wiring portions protrude downward from the lower surface of the electrode joint portion. Because of the bonding, the bonding area between the circuit pattern and the terminal increases compared to the case where the lower ends of the pair of sub-wiring portions are bonded to the circuit pattern with a bonding material. As a result, heat generation at the junction between the circuit pattern and the terminal can be suppressed when a large current is applied.
- FIG. 3 is a front view showing a state in which terminals included in the semiconductor device according to Embodiment 1 are joined to a circuit pattern;
- FIG. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1;
- FIG. 10 is a front view of a terminal included in a semiconductor device according to a second embodiment;
- 4 is a cross-sectional view taken along the line BB of FIG. 3;
- FIG. FIG. 10 is a front view showing a state in which a terminal included in a semiconductor device according to a second embodiment is joined to a circuit pattern;
- 6 is a cross-sectional view taken along line CC of FIG. 5;
- FIG. 11 is a front view showing a state in which a terminal included in a semiconductor device according to a third embodiment is joined to a circuit pattern
- FIG. 8 is a cross-sectional view taken along line DD of FIG. 7
- FIG. 13 is a front view showing a state in which a terminal included in a semiconductor device according to a fourth embodiment is joined to a circuit pattern
- FIG. 1 is a front view showing a state in which a terminal 3 included in the semiconductor device according to Embodiment 1 is joined to a circuit pattern 2.
- FIG. 2 is a cross-sectional view taken along line AA of FIG.
- the semiconductor device includes a circuit board 1, a semiconductor element (not shown), and terminals 3.
- the semiconductor device further includes a sealing resin (not shown) for sealing the circuit board 1 and the semiconductor element, and a case (not shown) filled with the sealing resin. Therefore, the description of these will be omitted.
- the circuit board 1 is made of ceramic with excellent thermal conductivity, such as aluminum nitride or silicon nitride, or resin with excellent thermal conductivity.
- a circuit pattern 2 is provided on the upper surface of the circuit board 1 .
- the circuit pattern 2 is formed using copper, an aluminum alloy, or the like, and a semiconductor element (not shown) is mounted on the upper surface of the circuit pattern 2 .
- the terminal 3 is an external electrode, and has one end connected to the circuit pattern 2 and the other end connected to an external device (not shown). Specifically, the terminal 3 includes an electrode connection portion 4 , a main wiring portion 5 , a pair of sub-wiring portions 6 , and a device connection portion 7 .
- the electrode connection portion 4, the main wiring portion 5, the pair of sub-wiring portions 6, and the device connection portion 7 are made of, for example, a single metal plate having a certain thickness formed using copper or a copper alloy (hereinafter referred to as "before processing. It is manufactured by processing a metal plate of
- the electrode joint portion 4 has sides 4a and 4d facing each other and sides 4b and 4c adjacent to these sides 4a and 4d, and is formed in a rectangular shape when viewed from above. there is The lower surface of the electrode joint portion 4 is joined to the circuit pattern 2 with a joint material 8 such as solder.
- the main wiring portion 5 is provided upright on the side 4a of the electrode junction portion 4 as the first side. Specifically, the main wiring portion 5 is formed by bending upward along the side 4a the portion that will become the electrode connection portion 4 in the metal plate before processing. there is although not shown, the lower end of the main wiring portion 5 is positioned at the same height as the lower surface of the electrode joint portion 4 and is joined to the circuit pattern 2 together with the lower surface of the electrode joint portion 4 by a joint material 8 .
- the pair of sub-wiring portions 6 are formed from both ends of the main wiring portion 5 in the width direction to a side 4b as a second side adjacent to the side 4a of the electrode joint portion 4 and a third side. It extends along the side 4c as a side.
- the pair of sub-wiring portions 6 are bent in the direction of the sides 4b and 4c with respect to the portion to be the main wiring portions 5 in the metal plate before processing. and arranged in an upright manner along the outer peripheries of the sides 4 b and 4 c of the electrode joint portion 4 .
- the upper ends of the pair of sub-wiring portions 6 are located above the upper ends of the main wiring portions 5 .
- the lower ends of the pair of sub-wiring portions 6 protrude below the lower surface of the electrode joint portion 4 . Therefore, the lower ends of the pair of sub-wiring portions 6 protrude below the lower surface of the electrode-jointing portion 4 and are connected to the circuit pattern 2 together with the lower surface of the electrode-jointing portion 4 and the lower end of the main wiring portion 5 by the joining material 8 . are spliced.
- the device connection portion 7 is formed by bending the portion to be the device connection portion 7 toward the side 4d opposite to the side 4a of the electrode connection portion 4 with respect to the portion to be the main wiring portion 5 in the metal plate before processing. and is connected to an external device (not shown).
- the device connection portion 7 is formed in a rectangular shape when viewed from above, and extends from the upper end portion of the main wiring portion 5 toward the side 4 d of the electrode connection portion 4 .
- the electrode connection portion 4, the main wiring portion 5, and the pair of sub-wiring portions 6 correspond to one end portion of the terminal 3 that is connected to the circuit pattern 2, and the device connection portion 7 is connected to an external device (not shown). It corresponds to the other end of the terminal 3 that is connected.
- the electrode joint portion 4 is formed with a groove 9 penetrating from the upper surface to the lower surface.
- the groove 9 is formed from the central portion of the side 4d of the electrode connection portion 4 to the central portion of the sides 4b and 4c along the direction parallel to the sides 4b and 4c. Further, the groove 9 is branched at this point in a direction parallel to the sides 4a and 4d and formed over the central portions of the sides 4b and 4c. Further, the groove 9 is formed from this point to the side 4a along the sides 4b and 4c.
- the width of the upper surface side and the width of the lower surface side of the groove 9 are constant.
- the terminal 3 and the circuit pattern 2 are heated to a temperature exceeding the melting point of the bonding material 8 in the bonding process. spliced.
- the bonding material 8 melted by heating penetrates into the groove 9 and spreads within the groove 9 , thereby improving the bonding strength between the electrode bonding portion 4 and the circuit pattern 2 .
- the semiconductor device includes a circuit board 1 having a circuit pattern 2 on which a semiconductor element is mounted, one end of which is joined to the circuit pattern 2, and the other end of which is connected to an external device.
- the terminal 3 is provided with a terminal 3 which is an external electrode to be connected.
- the terminal 3 has an electrode joint portion 4 having a rectangular shape in a top view, the lower surface of which is joined to the circuit pattern 2 by a joint material 8, and sides 4a of the electrode joint portion 4. and a pair of sub-wiring portions 6 extending from both ends of the main wiring portion 5 in the width direction along sides 4b and 4c adjacent to the side 4a of the electrode joint portion 4.
- the lower ends of the pair of sub-wiring portions 6 protrude downward from the lower surface of the electrode joint portion 4, and the lower ends of the pair of sub-wiring portions 6 are joined together with the lower surface of the electrode joint portion 4 by the bonding material 8. It is joined with the circuit pattern 2 .
- the circuit is formed with the joint material 8 in a state in which the lower ends of the pair of sub-wiring portions 6 protrude below the lower surface of the electrode joint portion 4 . Since the pattern 2 is bonded, the bonding area between the circuit pattern 2 and the terminal 3 is increased compared to the case where the lower ends of the pair of sub-wiring portions 6 are bonded to the circuit pattern 2 by the bonding material 8 . As a result, heat generation at the junction between the circuit pattern 2 and the terminal 3 can be suppressed when a large current is applied. Therefore, the semiconductor device can be used for a long period of time.
- FIG. 3 is a front view of terminals 3A included in the semiconductor device according to the second embodiment.
- 4 is a cross-sectional view taken along the line BB of FIG. 3.
- FIG. 5 is a front view showing a state where terminal 3A included in the semiconductor device according to the second embodiment is joined to circuit pattern 2.
- FIG. 6 is a cross-sectional view taken along line CC of FIG.
- the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- the shape of the grooves 9 is different from that in the first embodiment.
- the width of the upper surface side and the width of the lower surface side of the groove 9 are constant, but in Embodiment 2, the width of the upper surface side of the groove 9 is formed wider than the width of the lower surface side. .
- the groove 9 has a widened portion 9a on the upper surface side and a constant width portion 9b on the lower surface side.
- the widened portion 9a has a constant width on the upper surface side of the groove 9, which is wider than the constant width portion 9b.
- the uniform width portion 9b is formed on the lower surface side of the groove 9 and communicates with the widened portion 9a.
- the constant width portion 9b has a constant width narrower than that of the widened portion 9a.
- the bonding material 8 melted by heating penetrates into the groove 9 and spreads within the groove 9 , thereby improving the bonding strength between the electrode bonding portion 4 and the circuit pattern 2 .
- the width of the upper surface side is formed wider than the width of the lower surface side in the portion that is branched in the direction and formed over the central portion of the sides 4b and 4c.
- the width of the upper surface side and the width of the lower surface side of the portion formed from the central portion of the sides 4b and 4c to the side 4a are constant.
- the bonding material 8 filled in the groove 9 spreads to cover the periphery of the groove 9 on the upper surface of the electrode bonding portion 4. is desirable.
- the bonding material 8 filled in the groove 9 can have an anchor effect. Therefore, the bonding strength between the electrode bonding portion 4 and the circuit pattern 2 is further improved. This further improves the reliability of the semiconductor device.
- FIG. 7 is a front view showing a state in which terminal 3B included in the semiconductor device according to the third embodiment is joined to circuit pattern 2.
- FIG. 8 is a cross-sectional view taken along line DD of FIG. 7.
- Embodiment 3 the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals, and descriptions thereof are omitted.
- the third embodiment differs from the first embodiment in that a metal plate 20 is provided.
- the metal plate 20 is made of copper, an aluminum alloy, or the like, and is formed to have the same thickness as the electrode joint portion 4, and has a smaller top-view outline than the electrode joint portion 4.
- the metal plate 20 is arranged above the electrode connection portion 4 in a portion surrounded by the main wiring portion 5 and the pair of sub-wiring portions 6, and the main wiring portion 5 and the pair of sub-wiring portions 6 are connected by a bonding material 20a such as solder. It is joined to the sub-wiring portion 6 .
- the lower surface of the metal plate 20 is joined to the upper surface of the electrode joint portion 4 with a joining material 8a such as solder.
- a metal plate 20 is provided above the electrode joint portion 4 in order to increase the current path of the terminal 3B.
- a metal block thicker than the metal plate 20 may be provided instead of the metal plate 20 .
- the metal plate 20 or the metal block is provided above the electrode junction portion 4, and the metal plate 20 or the metal block includes the main wiring portion 5 and the pair of sub-wiring portions. 6 is connected.
- the current path of the terminal 3B is increased, the electrical resistance of the terminal 3B is reduced, and the connection between the circuit pattern 2 and the terminal 3B is reduced when a large current is applied. Heat generation at the location can be further suppressed.
- FIG. 9 is a front view showing a state where terminals 3C included in the semiconductor device according to the fourth embodiment are joined to circuit patterns 2.
- FIG. 9 the same components as those described in Embodiments 1 to 3 are denoted by the same reference numerals, and descriptions thereof are omitted.
- the fourth embodiment differs from the first embodiment in that slits 21 are formed to penetrate from the front surface to the back surface of the main wiring portion 5 .
- the slit 21 is formed so as to extend vertically in the central portion in the width direction of the main wiring portion 5 .
- a current path of the terminal 3C includes a path passing through the main wiring portion 5 and a path passing through the pair of sub-wiring portions 6. Since the device connection portion 7 is directly connected to the main wiring portion 5, the main wiring portion 5 More current flows through the path through the pair of sub-wiring portions 6 than through the path through the pair of sub-wiring portions 6 . As a result, heat is likely to be generated in the main wiring portion 5 when a large current is applied.
- a slit 21 is formed in the main wiring portion 5 in order to reduce the current density of the main wiring portion 5 and make the current density of the main wiring portion 5 and the pair of sub-wiring portions 6 uniform.
- the slit 21 is formed to have a size that allows the current density of the main wiring portion 5 and the pair of sub-wiring portions 6 to be uniform.
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Abstract
Description
<半導体装置の構成>
実施の形態1について、図面を用いて以下に説明する。図1は、実施の形態1に係る半導体装置が備える端子3が回路パターン2と接合された状態を示す正面図である。図2は、図1のA-A線断面図である。
以上のように、実施の形態1では、半導体装置は、上面に半導体素子が搭載される回路パターン2を有する回路基板1と、一端部が回路パターン2と接合され、他端部が外部機器と接続される外部電極である端子3とを備え、端子3は、下面が接合材8により回路パターン2と接合された上面視にて矩形状の電極接合部4と、電極接合部4の辺4aから立設状に設けられた主配線部5と、主配線部5の幅方向の両端から電極接合部4の辺4aに隣接する辺4b,4cに沿って延在する一対の副配線部6とを有し、一対の副配線部6の下端部は、電極接合部4の下面よりも下方に突出し、一対の副配線部6の下端部は、電極接合部4の下面と共に接合材8により回路パターン2と接合されている。
<半導体装置の構成>
次に、実施の形態2に係る半導体装置について説明する。図3は、実施の形態2に係る半導体装置が備える端子3Aの正面図である。図4は、図3のB-B線断面図である。図5は、実施の形態2に係る半導体装置が備える端子3Aが回路パターン2と接合された状態を示す正面図である。図6は、図5のC-C線断面図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
以上のように、実施の形態2に係る半導体装置では、溝9の上面側の幅は下面側の幅よりも広いため、溝9に充填された接合材8にアンカー効果を持たせることができることから、電極接合部4と回路パターン2との接合強度がさらに向上する。これにより、半導体装置の信頼性がさらに向上する。
<半導体装置の構成>
次に、実施の形態3に係る半導体装置について説明する。図7は、実施の形態3に係る半導体装置が備える端子3Bが回路パターン2と接合された状態を示す正面図である。図8は、図7のD-D線断面図である。なお、実施の形態3において、実施の形態1,2で説明したものと同一の構成要素については同一符号を付して説明は省略する。
以上のように、実施の形態3に係る半導体装置では、電極接合部4の上方に金属板20または金属ブロックが設けられ、金属板20または金属ブロックは、主配線部5および一対の副配線部6と接続されている。
<半導体装置の構成>
次に、実施の形態4に係る半導体装置について説明する。図9は、実施の形態4に係る半導体装置が備える端子3Cが回路パターン2と接合された状態を示す正面図である。なお、実施の形態4において、実施の形態1~3で説明したものと同一の構成要素については同一符号を付して説明は省略する。
以上のように、実施の形態4に係る半導体装置では、主配線部5には、上下方向に延びるスリット21が形成されているため、主配線部5の電流密度を低減し、主配線部5と一対の副配線部6との電流密度を均一にすることができる。これにより、大電流通電時における主配線部5の発熱を抑制することできる。
Claims (5)
- 上面に半導体素子が搭載される回路パターンを有する回路基板と、
一端部が前記回路パターンと接合され、他端部が外部機器と接続される外部電極である端子と、を備え、
前記端子は、下面が接合材により前記回路パターンと接合された上面視にて矩形状の電極接合部と、前記電極接合部の第1の辺から立設状に設けられた主配線部と、前記主配線部の幅方向の両端から前記電極接合部の前記第1の辺に隣接する第2の辺および第3の辺に沿って延在する一対の副配線部とを有し、
一対の前記副配線部の下端部は、前記電極接合部の下面よりも下方に突出し、
一対の前記副配線部の下端部は、前記電極接合部の下面と共に前記接合材により前記回路パターンと接合された、半導体装置。 - 前記電極接合部には、上面から下面に向けて貫通する溝が形成された、請求項1に記載の半導体装置。
- 前記溝の上面側の幅は下面側の幅よりも広い、請求項2に記載の半導体装置。
- 前記電極接合部の上方に金属板または金属ブロックが設けられ、
前記金属板または前記金属ブロックは、前記主配線部および一対の前記副配線部と接続された、請求項1から請求項3のいずれか1項に記載の半導体装置。 - 前記主配線部には、上下方向に延びるスリットが形成された、請求項1から請求項4のいずれか1項に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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DE112021007408.3T DE112021007408T5 (de) | 2021-03-29 | 2021-03-29 | Halbleitervorrichtung |
PCT/JP2021/013259 WO2022208603A1 (ja) | 2021-03-29 | 2021-03-29 | 半導体装置 |
JP2023509917A JP7438454B2 (ja) | 2021-03-29 | 2021-03-29 | 半導体装置 |
CN202180096198.6A CN117043939A (zh) | 2021-03-29 | 2021-03-29 | 半导体装置 |
US18/260,592 US20240071868A1 (en) | 2021-03-29 | 2021-03-29 | Semiconductor device |
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PCT/JP2021/013259 WO2022208603A1 (ja) | 2021-03-29 | 2021-03-29 | 半導体装置 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277870U (ja) * | 1988-12-02 | 1990-06-14 | ||
JPH05144986A (ja) * | 1991-11-25 | 1993-06-11 | Fuji Electric Co Ltd | トランジスタモジユール |
JPH09121019A (ja) * | 1995-10-25 | 1997-05-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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2021
- 2021-03-29 WO PCT/JP2021/013259 patent/WO2022208603A1/ja active Application Filing
- 2021-03-29 DE DE112021007408.3T patent/DE112021007408T5/de active Pending
- 2021-03-29 JP JP2023509917A patent/JP7438454B2/ja active Active
- 2021-03-29 US US18/260,592 patent/US20240071868A1/en active Pending
- 2021-03-29 CN CN202180096198.6A patent/CN117043939A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277870U (ja) * | 1988-12-02 | 1990-06-14 | ||
JPH05144986A (ja) * | 1991-11-25 | 1993-06-11 | Fuji Electric Co Ltd | トランジスタモジユール |
JPH09121019A (ja) * | 1995-10-25 | 1997-05-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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DE112021007408T5 (de) | 2024-01-18 |
JP7438454B2 (ja) | 2024-02-26 |
US20240071868A1 (en) | 2024-02-29 |
CN117043939A (zh) | 2023-11-10 |
JPWO2022208603A1 (ja) | 2022-10-06 |
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