WO2021220357A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021220357A1
WO2021220357A1 PCT/JP2020/018004 JP2020018004W WO2021220357A1 WO 2021220357 A1 WO2021220357 A1 WO 2021220357A1 JP 2020018004 W JP2020018004 W JP 2020018004W WO 2021220357 A1 WO2021220357 A1 WO 2021220357A1
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WIPO (PCT)
Prior art keywords
mold resin
semiconductor device
metal block
main terminal
bonding material
Prior art date
Application number
PCT/JP2020/018004
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English (en)
French (fr)
Inventor
慎太郎 荒木
直樹 吉松
一廣 西村
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US17/757,407 priority Critical patent/US20230012134A1/en
Priority to DE112020007132.4T priority patent/DE112020007132T5/de
Priority to CN202080100078.4A priority patent/CN115428142A/zh
Priority to PCT/JP2020/018004 priority patent/WO2021220357A1/ja
Priority to JP2022518454A priority patent/JPWO2021220357A1/ja
Publication of WO2021220357A1 publication Critical patent/WO2021220357A1/ja

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10254—Diamond [C]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance
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    • H01L2924/30107—Inductance
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • This disclosure relates to semiconductor devices.
  • a main terminal for a main circuit that energizes a large current of 100 A or more and a signal terminal used for inputting a control signal or monitoring output of the temperature are provided on the side surface of the resin package.
  • the main terminal was connected to an external bus bar by screwing or welding, and the signal terminal was inserted into a through hole formed in a control board on which an IC or the like was mounted and connected by soldering.
  • Patent Document 1 discloses such a semiconductor device.
  • the back surface of the package is brought into contact with the cooler via thermal paste in order to release the heat generated from the semiconductor element. Then, the package was pressed against the cooler side from the upper surface of the package using a spring to secure a constant surface pressure between the package and the cooler, thereby improving heat dissipation.
  • the current and withstand voltage increased.
  • the improvement of the tracking resistance of the resin may reduce other performances, a significant improvement cannot be expected, and it is difficult to reduce the required creepage distance.
  • the main terminal is usually made of copper, it is technically difficult to increase the current density while suppressing the cost. Due to these circumstances, it was extremely difficult to miniaturize the package.
  • the insulating material When using a ceramic insulating material such as aluminum nitride or silicon carbide or a resin insulating material filled with a filler for insulation with the cooler, the insulating material must have insulation performance as well as heat dissipation performance. Ceramics were more suitable as such insulating materials because of their high current and high withstand voltage, but they were expensive.
  • the bus bar connected to the main terminal requires current in and out to be wired in parallel and close to each other in order to reduce inductance, and insulation is also required. Ingenuity such as providing resin to secure insulation between bus bars was devised. Furthermore, since the bus bar generates heat when energized, it is necessary to secure a large cross-sectional area of the bus bar.
  • the present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device suitable for miniaturization and cost reduction.
  • the semiconductor device includes a metal block, a semiconductor element fixed to the upper surface of the metal block with a first bonding material, and a current flowing in a vertical direction, and fixed to the upper surface of the semiconductor element with a second bonding material.
  • the main terminal, the signal terminal electrically connected to the semiconductor element, the semiconductor element, the first bonding material, the second bonding material, the metal block, the main terminal, and the like.
  • a mold resin that covers a part of the signal terminal is provided, the lower surface of the metal block is exposed from the mold resin, the main terminal and the signal terminal are exposed from the side surface of the mold resin, and the main terminal is exposed.
  • the first portion in the mold resin, the second portion connected to the first portion and bent downward outside the mold resin, and the second portion connected to the second portion and substantially parallel to the lower surface of the mold resin. It is characterized by having the third part of.
  • FIG. It is a perspective view of the semiconductor device. It is a perspective view of the semiconductor device. It is a figure which shows the relationship between the thickness of a metal block and thermal resistance. It is sectional drawing of the semiconductor device which concerns on Embodiment 3.
  • FIG. It is a perspective view of the semiconductor device. It is sectional drawing of the semiconductor device which concerns on Embodiment 4.
  • FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 5.
  • FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 6.
  • FIG. It is a perspective view of the semiconductor device. It is a perspective view of the semiconductor device. It is a perspective view of the semiconductor device. It is a top view of the semiconductor device which concerns on Embodiment 8. It is sectional drawing of the semiconductor device which concerns on Embodiment 9.
  • FIG. It is a perspective view of the semiconductor device. It is a perspective view of the semiconductor device. It is a top view of the semiconductor device which concerns on Em
  • FIG. 1 is a cross-sectional view of the semiconductor device 10 according to the first embodiment.
  • the semiconductor device 10 includes a metal block 12.
  • the metal block 12 is made of, for example, copper or a copper alloy.
  • the semiconductor element 16 is fixed to the upper surface of the metal block 12 with the first bonding material 14a.
  • the semiconductor element 16 is an element that allows a current to flow in the vertical direction.
  • the semiconductor element 16 is an IGBT having a collector on the lower surface and an emitter and a base on the upper surface. The main current enters the collector and exits the emitter.
  • the semiconductor device 16 is a MOSFET, the in of the main current is the drain, and the out is the source. Any element that allows the main current to flow in the vertical direction can be adopted as the semiconductor element 16.
  • the main terminal 18 is fixed to the upper surface of the semiconductor element 16 with the second bonding material 14b.
  • a wire 20 made of aluminum or the like is connected to the upper surface of the semiconductor element 16. By connecting the wire 20 to the signal terminal 22, the signal terminal 22 is electrically connected to the semiconductor element 16.
  • a brazing material such as solder or silver can be used as the first joining material 14a, the second joining material 14b, and the joining material described later.
  • a brazing material such as solder or silver
  • the material of the main terminal 18 and the signal terminal 22 can be copper or a copper alloy.
  • the above configuration is sealed with the mold resin 30 and integrated.
  • the mold resin 30 covers the semiconductor element 16, the first bonding material 14a, and the second bonding material 14b, and covers the metal block 12, the main terminal 18, and a part of the signal terminal 22.
  • the lower surface of the metal block 12 is exposed from the mold resin 30.
  • the metal block 12 is exposed only from the lower surface of the mold resin 30.
  • the exposed metal block 12 serves as an energization path for the collector current.
  • the main terminal 18 and the signal terminal 22 are exposed from the side surface of the mold resin 30.
  • the main terminal 18 is connected to the first portion 18a in the mold resin 30, the second portion 18b that is bent downward outside the mold resin 30 while being connected to the first portion 18a, and the mold resin while being connected to the second portion 18b. It has a third portion 18c that is substantially parallel to the lower surface of the 30.
  • the main terminal 18 is bent downward outside the mold resin 30 and includes a third portion 18c which is a flat portion having substantially the same height as the back surface of the mold resin 30.
  • the main terminal 18 provides an energization path for the emitter current.
  • the signal terminal 22 is bent upward outside the mold resin 30.
  • the signal terminal 22 has a shape bent upward outside the mold resin 30.
  • FIG. 2 is a perspective view of the semiconductor device before forming the mold resin 30.
  • the wire 20 of FIG. 1 is omitted.
  • the main terminal 18 is in contact with the emitters of the two semiconductor elements 16.
  • FIG. 2 shows that the metal block 12 is thicker than the main terminal 18.
  • the material of the metal block 12 is, for example, copper or a copper alloy.
  • the main terminal 18 is a plate-shaped frame.
  • FIG. 3 is a perspective view of the semiconductor device 10 of FIG.
  • the main terminal 18 and all the signal terminals 22 are exposed from the side surface of the mold resin 30.
  • the semiconductor device 10 described with reference to FIG. 1-3 can be used, for example, as an inverter for controlling a motor of an electric vehicle or a train, or a converter for regeneration.
  • both the main terminal 18 and the metal block 12 can be connected to the insulating substrate by solder or the like. Therefore, if the semiconductor device according to the first embodiment is used, a pressing mechanism such as a spring becomes unnecessary, and assembly becomes easy.
  • the metal block 12 through which the collector current flows is exposed only from the back surface of the mold resin 30, and the main terminal 18 through which the emitter current flows and the signal terminal 22 for transmitting and receiving signals are molded resin.
  • the insulation distance can be secured. Therefore, the size can be reduced as compared with the semiconductor element provided with the frame for the collector potential.
  • the inductance can be reduced because unnecessary wiring routing is reduced.
  • the metal block 12 diffuses the heat generated from the semiconductor element 16 and can efficiently dissipate the heat.
  • the die pad DP1 described in Japanese Patent Application Laid-Open No. 2013-0742464 is formed of a frame, a plurality of resin molds are connected by the frame in the manufacturing process thereof, so that the frame needs to be cut. Therefore, as shown in FIG. 10 of JP2013-0742464, the die pad DP1 serving as a collector potential is exposed on the side surface of the resin package. In this case, the package becomes large in order to secure the insulation distance between the main terminal which is the emitter potential and the die pad DP1 which is the collector potential. Further, since the die pad DP1 is a frame, it is difficult to secure a sufficient thickness for improving heat dissipation. These problems are suppressed by exposing the metal block 12 thicker than the main terminal 18 only from the back surface of the mold resin 30 and exposing the main terminal 18 only from the side surface of the mold resin 30 in the semiconductor device 10 of the first embodiment. Will be done.
  • the modified example, modified example or alternative described in the first embodiment can be applied to the semiconductor device according to the following embodiment. Regarding the semiconductor device according to the following embodiment, the difference from the first embodiment will be mainly described.
  • the thickness of the metal block 12 is at least twice the thickness of the main terminal 18.
  • FIG. 4 is a diagram showing the result of calculating the relationship between the thickness of the metal block 12 and the thermal resistance by the finite element method. In the process of increasing the thickness of the metal block 12 to about 2 mm, a sharp decrease in thermal resistance is observed. When the thickness of the metal block 12 is increased to more than 2 mm, the value of thermal resistance gradually saturates. Further, the main terminal 18 can have a thickness of about 1 mm or 1 mm or less in consideration of workability and assembling property. If the current is small, the thickness of the main terminal 18 can be reduced, and the thickness of the metal block 12 can also be reduced.
  • the thickness of the metal block 12 has a correlation with the thermal resistance, and the larger the thickness, the more effective it is, and the effect tends to be gradually saturated. Making the thickness of the metal block 12 more than twice the thickness of the main terminal 18 is effective in reducing the thermal resistance.
  • FIG. 5 is a cross-sectional view of the semiconductor device according to the third embodiment.
  • This semiconductor device includes an insulating substrate 50.
  • the insulating substrate 50 has a metal base 50b, an insulating layer 50a provided on the metal base 50b, and a plurality of circuit patterns 50c provided on the insulating layer 50a.
  • the main terminal 18 is fixed to the circuit pattern 50c on the left side of the plurality of circuit patterns 50c by a third joining member 52.
  • the lower surface of the metal block 12 is fixed to the circuit pattern 50c on the right side of the plurality of circuit patterns 50c by the fourth joining member 54.
  • the electrode 60 is fixed to the circuit pattern 50c on the left side by the bonding material 56.
  • the electrode 62 is fixed to the circuit pattern 50c on the right side by the bonding material 58. A part of the electrodes 60 and 62 rides on the upper surface of the package 64.
  • FIG. 6 is a diagram showing the inside of the semiconductor device of FIG. For ease of understanding, a semiconductor device sealed with the mold resin 30 and a semiconductor device not sealed with the mold resin are shown. Both the metal block 12 and the main terminal 18 are joined to the circuit pattern 50c of the insulating substrate 50.
  • circuit pattern 50c can be easily formed by, for example, etching, circuit formation and assembly are easier than with bus bar wiring.
  • the metal base 50b of the insulating substrate 50 promotes cooling of the wiring portion as compared with the bus bar wiring. If the wiring portion is cooled, the wiring resistance is suppressed, so that the cross-sectional area of the wiring portion can be reduced.
  • the heat generated from the semiconductor element 16 diffuses to the metal block 12 and is conducted to the metal base 50b via the insulating layer 50a.
  • the insulating substrate 50 is a resin insulating substrate
  • the insulating layer 50a has a lower thermal conductivity than ceramics such as aluminum nitride or silicon nitride, but due to the thermal diffusion effect of the metal block 12, the heat equivalent to that when the ceramic substrate is used. It is also possible to obtain resistance.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to the fourth embodiment. Similar to the third embodiment, this semiconductor device has an insulation having a metal base 50b, an insulating layer 50a provided on the metal base 50b, and a plurality of circuit patterns 50c provided on the insulating layer 50a. It includes a substrate 50. An auxiliary insulating layer 80 is provided on a part of the upper surface of the circuit pattern 50c. An auxiliary circuit pattern 82 is provided on the auxiliary insulating layer 80.
  • the main terminal 18 is fixed to the auxiliary circuit pattern 82 with the fifth joining material 55. Further, the lower surface of the metal block 12 is fixed to the circuit pattern 50c by the fourth joining member 54.
  • the third portion 18c including the flat surface of the main terminal 18 is upward from the back surface of the metal block 12.
  • the auxiliary insulating layer 80 and the auxiliary circuit pattern 82 were arranged by laminating on the circuit pattern 50c to which the metal block 12 was joined, and the main terminal 18 was joined to the auxiliary circuit pattern 82.
  • the emitter pattern and the collector pattern can be provided in parallel while being close to each other, and the inductance can be reduced.
  • FIG. 8 is a cross-sectional view of the semiconductor device according to the fifth embodiment.
  • the lower surface of the metal block 12 reaches below the lower surface of the mold resin 30.
  • FIG. 8 shows that the lower surface of the metal block 12 is below the lower surface of the mold resin 30 by a distance L1.
  • the exposed portion of the metal block 12 is more convex than the back surface of the mold resin 30.
  • the semiconductor device according to the fifth embodiment since a joining material such as a solder fillet can be formed on the side surface of the metal block 12, the reliability of the joining portion can be improved.
  • the reliability of the joint is, for example, durability due to temperature stress.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the sixth embodiment.
  • a groove 30a is provided on the lower surface of the mold resin 30 along the outer edge of the metal block 12.
  • the groove 30a surrounds the exposed portion of the metal block 12 and is provided on the back surface of the mold resin 30 in view of the bottom surface.
  • excess bonding material may flow out and short-circuit the circuit patterns.
  • FIG. 10 is a cross-sectional view of the semiconductor device according to the seventh embodiment.
  • the signal terminal 22 is connected to the fourth portion 22a in the mold resin 30, the fifth portion 22b which is bent downward outside the mold resin 30 while being connected to the fourth portion 22a, and the mold resin while being connected to the fifth portion 22b. It has a sixth portion 22c, which is substantially parallel to the lower surface of the thirty.
  • the signal terminal 22 can be connected to the circuit pattern and the circuit pattern can be used as the signal wiring. Therefore, for example, when mounting a plurality of semiconductor devices sealed with a mold resin on the same insulating substrate, a plurality of signal terminals can be externally connected by one connector.
  • both the signal terminal 22 and the main terminal 18 are bent downward outside the mold resin 30, the signal terminal 22 and the main terminal 18 can be connected to the insulating substrate.
  • FIG. 11 is a perspective view of the semiconductor device before forming the mold resin.
  • a main terminal 18 and a plurality of signal terminals 22 are provided.
  • the wire 20 is omitted.
  • FIG. 12 is a perspective view of the semiconductor device of FIG. All the main terminals 18 and the signal terminals 22 are exposed to the outside from the side surface of the mold resin 30.
  • FIG. 13 is a cross-sectional view of the semiconductor device according to the eighth embodiment.
  • the main terminal 18 is exposed from a plurality of side surfaces of the mold resin 30.
  • the main terminal 18 is exposed from the side surface of the mold resin 30 at the three portions of the exposed portions 18A, 18B, and 18C.
  • two exposed portions may be provided to expose the exposed portions from the two side surfaces of the mold resin.
  • four exposed portions may be provided to expose the exposed portions from the four side surfaces of the mold resin.
  • the plurality of exposed portions of the main terminal 18 may include a second portion 18b and a third portion 18c as shown in FIG. 1, respectively.
  • Exposing the main terminal 18 from a plurality of side surfaces of the mold resin 30 improves the degree of freedom in layout of the circuit pattern of the insulating substrate. Increasing the degree of freedom in the layout of the circuit pattern enables the miniaturization of the device.
  • FIG. 14 is a cross-sectional view of the semiconductor device according to the ninth embodiment.
  • a part of the surface of the circuit pattern 50c is covered with the insulating resin 90.
  • a part of the surface of the plurality of circuit patterns 50c is covered with the insulating resin 90.
  • a part of the surface of the auxiliary circuit pattern 82 is also covered with the insulating resin 90.
  • the insulating resin 90 is, for example, a silicone gel. Since the insulating resin 90 improves the insulating property between the circuit pattern and another circuit pattern, the interval between the patterns can be narrowed. Reducing the pattern spacing makes it possible to reduce the size of the device.
  • the semiconductor element 16 in all the embodiments up to this point may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Since the wide bandgap semiconductor has excellent withstand voltage and the like, the semiconductor device can be miniaturized. Wide bandgap semiconductors include, for example, silicon carbide, gallium nitride based materials or diamond. In particular, in the present disclosure, since the heat dissipation is improved by setting the material and thickness of the metal block 12 on which the semiconductor element is mounted as described above, the area of the semiconductor element formed by the wide band gap can be reduced. It is possible. Therefore, it is suitable for cost reduction.

Abstract

金属ブロックと、該金属ブロックの上面に第１接合材で固定された、縦方向に電流を流す半導体素子と、該半導体素子の上面に第２接合材で固定された主端子と、該半導体素子に電気的に接続された信号端子と、該半導体素子と、該第１接合材と、該第２接合材を覆い、該金属ブロックと、該主端子と、該信号端子の一部を覆うモールド樹脂と、を備え、該金属ブロックの下面が該モールド樹脂から露出し、該主端子と該信号端子は、該モールド樹脂の側面から露出し、該主端子は、該モールド樹脂の中の第１部分と、該第１部分につながりつつ該モールド樹脂の外で下方向に曲がった第２部分と、該第２部分とつながりつつ該モールド樹脂の下面と略平行の第３部分と、を有する。

Description

半導体装置
　この開示は半導体装置に関する。
　従来の樹脂モールドされた電力用半導体装置では、例えば１００Ａ以上の大電流を通電する主回路用の主端子と、その制御信号の入力又は温度のモニター出力に用いる信号端子と、を樹脂パッケージの側面から露出させ、主端子は外部のバスバーにねじ締結又は溶接により接続し、信号端子はＩＣなどが実装された制御基板に形成されたスルーホールに挿入してはんだ付けにより接続していた。例えば特許文献１には、そのような半導体装置が開示されている。
　電気自動車などに使用される電力用半導体素子は殆どが６００Ｖ以上の耐圧を有し、パッケージにも同等以上の絶縁耐圧が求められるため、コレクタ端子とエミッタ端子間、またコレクタ端子と信号端子間には絶縁を保つための沿面距離が必要であった。
　パッケージの裏面は、半導体素子から発生する熱を放出するために、放熱グリスを介して冷却器に接触させる。そして、ばねを用いてパッケージの上面からパッケージを冷却器側に押し付けて、パッケージと冷却器との間に一定の面圧を確保することで、放熱性を高めていた。
日本特開２０１０－２８７７３７号公報
　半導体素子の世代が進むごとに大電流化及び高耐圧化が進んできた。しかし、樹脂の耐トラッキングの向上は他の性能を低下させることがあるため、大幅な改善は見込めず、必要な沿面距離を縮小するのも難しい。そして、主端子は通常銅材を使用しているため、コストを抑制しつつ電流密度を上げることは技術的にハードルが高い。これらの事情から、パッケージの小型化が非常に困難であった。
　冷却器との間の絶縁のために、窒化アルミ又は炭化珪素などのセラミックス絶縁材又はフィラーを充填した樹脂絶縁材を使用する場合、絶縁材には絶縁性能と同時に放熱性能が必要である。大電流と高耐圧のために、そのような絶縁材としてはセラミックスの方が適していたが、高価であった。
　パッケージを冷却器にねじ締結する場合、樹脂製のパッケージの面圧の高い部分はクリープして、押し付け力が低下してしまう。そこで、パッケージ上面の押さえにばねを使用することで、長時間高温に曝される樹脂製のパッケージのクリープを抑制できる。しかし、パッケージを冷却器に押し付けるために押さえばねを用いると、ねじ締結の場合と比べて部品点数が増加してコストアップとなることに加え、組み立て性が煩雑になるなどの難点がある。
　主端子に接続されたバスバーは、インダクタンスを低減するために電流のインとアウトを平行且つ近接して配線させるとともに、絶縁も必要となる。バスバー間の絶縁確保のために樹脂を設けるなどの工夫をしていた。さらにはバスバーは通電すると発熱するため、バスバーの断面積を大きく確保する必要があった。
　本開示は上述の問題を解決するためになされたものであり、小型化と低コスト化に好適な半導体装置を提供することを目的とする。
　本願の開示にかかる半導体装置は、金属ブロックと、該金属ブロックの上面に第１接合材で固定された、縦方向に電流を流す半導体素子と、該半導体素子の上面に第２接合材で固定された主端子と、該半導体素子に電気的に接続された信号端子と、該半導体素子と、該第１接合材と、該第２接合材を覆い、該金属ブロックと、該主端子と、該信号端子の一部を覆うモールド樹脂と、を備え、該金属ブロックの下面が該モールド樹脂から露出し、該主端子と該信号端子は、該モールド樹脂の側面から露出し、該主端子は、該モールド樹脂の中の第１部分と、該第１部分につながりつつ該モールド樹脂の外で下方向に曲がった第２部分と、該第２部分とつながりつつ該モールド樹脂の下面と略平行の第３部分と、を有したことを特徴とする。
　本開示のその他の特徴は以下に明らかにする。
　この開示によれば、主電極又は信号端子を直接回路パターンに接合することで、小型化と低コスト化に好適な半導体装置を提供することができる。
実施の形態１に係る半導体装置の断面図である。 半導体装置の斜視図である。 半導体装置の斜視図である。 金属ブロックの厚みと熱抵抗の関係を示す図である。 実施の形態３に係る半導体装置の断面図である。 半導体装置の斜視図である。 実施の形態４に係る半導体装置の断面図である。 実施の形態５に係る半導体装置の断面図である。 実施の形態６に係る半導体装置の断面図である。 実施の形態７に係る半導体装置の断面図である。 半導体装置の斜視図である。 半導体装置の斜視図である。 実施の形態８に係る半導体装置の平面図である。 実施の形態９に係る半導体装置の断面図である。
　本開示の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、実施の形態１に係る半導体装置１０の断面図である。この半導体装置１０は金属ブロック１２を備えている。金属ブロック１２として、熱伝導率が高く、電気抵抗率が低く、低コストな材料を採用し得る。金属ブロック１２は例えば銅または銅合金で形成される。金属ブロック１２の上面には、第１接合材１４ａで半導体素子１６が固定されている。半導体素子１６は、縦方向に電流を流す素子である。一例によれば、半導体素子１６は下面にコレクタを有し、上面にエミッタとベースを備えるＩＧＢＴである。主電流はコレクタに入り、エミッタから出る。別の例によれば、半導体素子１６はＭＯＳＦＥＴであり、主電流のインはドレインであり、アウトはソースである。半導体素子１６として縦方向に主電流を流す任意の素子を採用することができる。
　半導体素子１６の上面には、第２接合材１４ｂで主端子１８が固定されている。半導体素子１６の上面には、アルミ等を材料とするワイヤ２０が接続されている。このワイヤ２０が、信号端子２２に接続されたことで、信号端子２２は、半導体素子１６に電気的に接続される。
　第１接合材１４ａ、第２接合材１４ｂ及び後述の接合材として、はんだ又は銀などのロウ材を用いることができる。例えばろう材をリフロー処理することで、接合材を用いた接合が可能となる。一例によれば、主端子１８と信号端子２２の材料は銅または銅合金とすることができる。
　上記の構成はモールド樹脂３０で封止されて一体化されている。具体的には、モールド樹脂３０は、半導体素子１６と、第１接合材１４ａと、第２接合材１４ｂを覆い、金属ブロック１２と、主端子１８と、信号端子２２の一部を覆う。金属ブロック１２の下面がモールド樹脂３０から露出している。金属ブロック１２はモールド樹脂３０の下面のみから露出している。この露出した金属ブロック１２がコレクタ電流の通電経路となる。
　主端子１８と信号端子２２は、モールド樹脂３０の側面から露出している。主端子１８は、モールド樹脂３０の中の第１部分１８ａと、第１部分１８ａにつながりつつモールド樹脂３０の外で下方向に曲がった第２部分１８ｂと、第２部分１８ｂとつながりつつモールド樹脂３０の下面と略平行の第３部分１８ｃと、を有している。一例によると、主端子１８はモールド樹脂３０の外部で下方に曲げ加工され、モールド樹脂３０の裏面と略同一高さの平坦部である第３部分１８ｃを備える。主端子１８はエミッタ電流の通電経路を提供する。
　一例によれば、信号端子２２はモールド樹脂３０の外部で上方に曲げ加工されている。その結果、信号端子２２はモールド樹脂３０の外部で上方向に曲がった形状を有する。
　図２は、モールド樹脂３０を形成する前の半導体装置の斜視図である。図２において、図１のワイヤ２０は省略されている。主端子１８は２つの半導体素子１６のエミッタに接している。図２には、金属ブロック１２は、主端子１８より厚いことが図示されている。金属ブロック１２の材料は例えば銅又は銅合金である。主端子１８は板状のフレームである。
　図３は、図１の半導体装置１０の斜視図である。主端子１８とすべての信号端子２２はモールド樹脂３０の側面から露出している。図１－３を参照しつつ説明した半導体装置１０は、例えば電気自動車又は電車等のモータを制御するインバータ又は回生用のコンバータに使用することができる。
　ところで、周知の樹脂封止された半導体装置を冷却器に取り付ける場合、パッケージ下面と冷却器の間の微小な隙間を放熱グリスで埋めて放熱性を高め、さらに樹脂パッケージ上面からばね等を用いて樹脂パッケージを冷却器に押さえ付けていた。
　これに対し、実施の形態１に係る半導体装置は、主端子１８を上述の形状とした結果、主端子１８と金属ブロック１２の両方をはんだ等によって絶縁基板に接続し得るものである。そのため、実施の形態１に係る半導体装置を用いれば、ばね等の押さえ機構が不要となり、組み立てが容易となる。
　さらに、実施の形態１に係る半導体装置１０は、コレクタ電流が流れる金属ブロック１２をモールド樹脂３０の裏面のみから露出させ、エミッタ電流が流れる主端子１８と信号を授受する信号端子２２とをモールド樹脂３０の側面のみから露出させることで、絶縁距離を確保できる。よって、コレクタ電位用のフレームが提供される半導体素子と比べ小型化が可能となる。
　さらに、金属ブロック１２の提供によって、無駄な配線引き回しが減るためインダクタンスを低減できる。金属ブロック１２により、半導体素子１６から発生する熱を拡散させ効率よく放熱できる。
　なお、特開２０１３－０７４２６４号公報に記載されたダイパッドＤＰ１をフレームで形成する場合、その製造工程において、複数の樹脂モールドがフレームで接続された状態となるので、フレームの切断が必要となる。そのため、特開２０１３‐０７４２６４号公報の図１０のとおり、樹脂パッケージの側面にコレクタ電位となるダイパッドＤＰ１が露出する。この場合、エミッタ電位となる主端子と、コレクタ電位であるダイパッドＤＰ１との絶縁距離を確保するためにパッケージが大きくなる。さらにダイパッドＤＰ１はフレームなので、放熱性を向上させるための十分な厚みを確保することが困難である。これらの問題は、実施の形態１の半導体装置１０において、主端子１８より厚い金属ブロック１２をモールド樹脂３０の裏面のみから露出させ、主端子１８をモールド樹脂３０の側面のみから露出させることで抑制される。
　実施の形態１に記載した変形例、修正例又は代案については、以下の実施の形態に係る半導体装置に応用し得る。以下の実施の形態に係る半導体装置については、主として実施の形態１との相違点を説明する。
実施の形態２．
　実施の形態２に係る半導体装置は、金属ブロック１２の厚さを主端子１８の厚さの２倍以上としたものである。図４は、金属ブロック１２の厚みと熱抵抗の関係を有限要素法により計算した結果を示す図である。金属ブロック１２の厚さを２ｍｍ程度まで高めていく過程では、熱抵抗に急激な低下が見られる。金属ブロック１２の厚さを２ｍｍより大きくしていくと、徐々に熱抵抗の値は飽和する。また、主端子１８は加工性及び組み立て性を考慮して１ｍｍ程度又は１ｍｍ以下の厚みとすることができる。電流が小さければ主端子１８の厚みを薄くし、金属ブロック１２の厚みも薄くすることが可能である。
　以上のことから、金属ブロック１２の厚みは熱抵抗と相関があり、厚みが大きいほど効果があり徐々に効果が飽和する傾向にある。金属ブロック１２の厚さを主端子１８の厚さの２倍以上とすることは、熱抵抗の低減に効果的である。
　実施の形態３．
　図５は、実施の形態３に係る半導体装置の断面図である。この半導体装置は、絶縁基板５０を備えている。絶縁基板５０は、金属ベース５０ｂと、金属ベース５０ｂの上に設けられた絶縁層５０ａと、絶縁層５０ａの上に設けられた複数の回路パターン５０ｃと、を有する。複数の回路パターン５０ｃのうち左側の回路パターン５０ｃには、第３接合材５２で主端子１８が固定されている。そして、複数の回路パターン５０ｃのうち右側の回路パターン５０ｃには、第４接合材５４で金属ブロック１２の下面が固定されている。
　そして、左側の回路パターン５０ｃには接合材５６によって電極６０が固定されている。右側の回路パターン５０ｃには接合材５８によって電極６２が固定されている。電極６０、６２の一部はパッケージ６４の上面に乗り上げている。
　図６は、図５の半導体装置の内部を示す図である。理解を容易にするために、モールド樹脂３０で封止された半導体装置と、モールド樹脂で封止されていない半導体装置が示されている。金属ブロック１２と主端子１８は両方とも絶縁基板５０の回路パターン５０ｃに接合されている。
　回路パターン５０ｃは例えばエッチングにより容易に形成できるため、バスバー配線に比べて回路形成とアセンブリが容易になる。絶縁基板５０の金属ベース５０ｂは、バスバー配線と比較して、配線部分の冷却を促進する。配線部分が冷却されれば、配線抵抗が抑制されるので、配線部分の断面積を小さくすることができる。
　実施の形態３に係る半導体装置では、半導体素子１６から発生する熱は金属ブロック１２へ拡散し、絶縁層５０ａを介して金属ベース５０ｂへと伝導する。絶縁基板５０を樹脂絶縁基板としたときの絶縁層５０ａは、窒化アルミ又は窒化珪素などのセラミックスに比べて熱伝導率は低いが、金属ブロック１２の熱拡散効果によりセラミックス基板使用時と同等の熱抵抗を得ることも可能となる。また、グリス等で冷却フィンに半導体装置をセットする場合は、ばねなどによる押さえが必要であったが、本開発品の場合、ロウ材などの接合材を用いるため、ばねなどの周辺部品が不要となる。絶縁基板５０の回路パターン５０ｃを使って主回路配線され、薄厚の絶縁層５０ａを挟んで金属ベース５０ｂを配置しているためインダクタンスを小さくすることができる。
　実施の形態４．
　図７は、実施の形態４に係る半導体装置の断面図である。この半導体装置は、実施の形態３と同様、金属ベース５０ｂと、金属ベース５０ｂの上に設けられた絶縁層５０ａと、絶縁層５０ａの上に設けられた複数の回路パターン５０ｃと、を有する絶縁基板５０を備えている。回路パターン５０ｃの一部上面に補助絶縁層８０が設けられている。補助絶縁層８０の上には補助回路パターン８２が設けられている。
　そして、補助回路パターン８２には、第５接合材５５で主端子１８が固定されている。また、回路パターン５０ｃには、第４接合材５４で金属ブロック１２の下面が固定されている。
　図７に図示されているとおり、主端子１８の平坦面を含む第３部分１８ｃは、金属ブロック１２の裏面よりも、上方向にある。そして、金属ブロック１２が接合されている回路パターン５０ｃの上に積層して、補助絶縁層８０と補助回路パターン８２を配置し、主端子１８をその補助回路パターン８２に接合した。このような構成により、エミッタパターンとコレクタパターンを近接させつつ平行に設けることが可能となり、インダクタンスを低減させることができる。
　実施の形態５．
　図８は、実施の形態５に係る半導体装置の断面図である。金属ブロック１２の下面は、モールド樹脂３０の下面より下方に達している。図８には、金属ブロック１２の下面が、モールド樹脂３０の下面より距離Ｌ１だけ下方にあることが図示されている。言いかえると、金属ブロック１２の露出部は、モールド樹脂３０の裏面よりも凸になっている。実施の形態５に係る半導体装置によれば、金属ブロック１２の側面にはんだフィレットなどの接合材を形成することができるため、接合部の信頼性を向上させることができる。接合部の信頼性とは、例えば、温度ストレスによる耐久性である。
　実施の形態６．
　図９は、実施の形態６に係る半導体装置の断面図である。モールド樹脂３０の下面には金属ブロック１２の外縁に沿って溝３０ａが設けられている。この溝３０ａは、底面視で、金属ブロック１２の露出部を囲い、モールド樹脂３０裏面に設けられたものである。例えば、半導体素子１６の熱抵抗を低くするために金属ブロック１２の下の接合材を薄く抑える場合、余剰の接合材が流れ出て回路パターン間を短絡させる可能性がある。そのような余剰の接合材を、溝３０ａで回収することで、余剰の接合材の流出を抑制することができる。
　実施の形態７．
　図１０は、実施の形態７に係る半導体装置の断面図である。信号端子２２は、モールド樹脂３０の中の第４部分２２ａと、第４部分２２ａにつながりつつモールド樹脂３０の外で下方向に曲がった第５部分２２ｂと、第５部分２２ｂとつながりつつモールド樹脂３０の下面と略平行の第６部分２２ｃと、を有している。
　実施の形態７に係る信号端子２２は上述の形状とした結果、信号端子２２を回路パターンに接続し、当該回路パターンを信号配線として用いることができる。そのため、例えば、モールド樹脂で封止された複数の半導体装置を同一の絶縁基板に実装する際に、１個のコネクタによって、複数の信号端子を外部接続することができる。
　実施の形態７の例では、モールド樹脂３０の外で信号端子２２と主端子１８が両方とも下方向に曲げられているので、信号端子２２と主端子１８を絶縁基板に接続できる。
　図１１は、モールド樹脂を形成する前の半導体装置の斜視図である。主端子１８と複数の信号端子２２が設けられている。ワイヤ２０は省略されている。図１２は、図１０の半導体装置の斜視図である。すべての主端子１８と信号端子２２は、モールド樹脂３０の側面から外部に露出している。
　実施の形態８．
　図１３は、実施の形態８に係る半導体装置の断面図である。主端子１８は、モールド樹脂３０の複数の側面から露出している。図１３の例では、主端子１８は露出部１８Ａ、１８Ｂ、１８Ｃの３つの部分においてモールド樹脂３０の側面から露出している。別の例によれば、露出部を２つ設け、モールド樹脂の２つの側面から露出部を露出させてもよい。さらに別の例によれば、露出部を４つ設け、モールド樹脂の４つの側面から露出部を露出させてもよい。主端子１８の複数の露出部は、それぞれ、図１等の第２部分１８ｂと第３部分１８ｃを備え得る。
　主端子１８をモールド樹脂３０の複数の側面から露出させることは、絶縁基板の回路パターンのレイアウト自由度を向上させる。回路パターンのレイアウト自由度を高めることは、装置の小型化を可能とする。
　実施の形態９．
　図１４は、実施の形態９に係る半導体装置の断面図である。回路パターン５０ｃの一部表面は絶縁樹脂９０で覆われている。回路パターン５０ｃが複数ある場合は複数の回路パターン５０ｃの一部表面が絶縁樹脂９０で覆われる。補助回路パターン８２がある場合は補助回路パターン８２の一部表面も絶縁樹脂９０で覆われる。絶縁樹脂９０は例えばシリコーンゲルである。絶縁樹脂９０によって、回路パターンと別の回路パターンとの絶縁性が向上するため、パターンの間隔を狭めることができる。パターンの間隔を小さくすることは、装置の小型化を可能とする。
　ここまでのすべての実施の形態における半導体素子１６を、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成してもよい。ワイドバンドギャップ半導体は耐電圧性などに優れるため、半導体装置を小型化することができる。ワイドバンドギャップ半導体としては、例えば、炭化珪素、窒化ガリウム系材料又はダイヤモンドがある。特に、本開示では半導体素子を実装する金属ブロック１２の材質と厚みを上記のとおりとすることで放熱性を向上させているため、ワイドバンドギャップで形成された半導体素子の面積を小さくすることが可能である。よって、コスト低減に好適である。
　なお、上記の各実施の形態に係る半導体装置の特徴を組み合わせることができる。
　１０　半導体装置、　１２　金属ブロック、　１４ａ　第１接合材、　１４ｂ　第２接合材、　１６　半導体素子、　１８　主端子、　１８ａ　第１部分、　１８ｂ　第２部分、　１８ｃ　第３部分、　２０　ワイヤ、　２２　信号端子、　３０　モールド樹脂

Claims (13)

  1. 　金属ブロックと、
    　前記金属ブロックの上面に第１接合材で固定された、縦方向に電流を流す半導体素子と、
    　前記半導体素子の上面に第２接合材で固定された主端子と、
    　前記半導体素子に電気的に接続された信号端子と、
    　前記半導体素子と、前記第１接合材と、前記第２接合材を覆い、前記金属ブロックと、前記主端子と、前記信号端子の一部を覆うモールド樹脂と、を備え、
    　前記金属ブロックの下面が前記モールド樹脂から露出し、
    　前記主端子と前記信号端子は、前記モールド樹脂の側面から露出し、
    　前記主端子は、前記モールド樹脂の中の第１部分と、前記第１部分につながりつつ前記モールド樹脂の外で下方向に曲がった第２部分と、前記第２部分とつながりつつ前記モールド樹脂の下面と略平行の第３部分と、を有したことを特徴とする半導体装置。
  2. 　前記信号端子は前記モールド樹脂の外部で上方向に曲がった形状を有する請求項１に記載の半導体装置。
  3. 　前記金属ブロックは、前記主端子より厚い銅又は銅合金である請求項１又は２に記載の半導体装置。
  4. 　前記金属ブロックの厚さは前記主端子の厚さの２倍以上である請求項１から３のいずれか１項に記載の半導体装置。
  5. 　金属ベースと、前記金属ベースの上に設けられた絶縁層と、前記絶縁層の上に設けられた複数の回路パターンと、を有する絶縁基板を備え、
    　前記複数の回路パターンのうちある回路パターンには、第３接合材で前記主端子が固定され、
    　前記複数の回路パターンのうち別の回路パターンには、第４接合材で前記金属ブロックの下面が固定された請求項１から４のいずれか１項に記載の半導体装置。
  6. 　金属ベースと、前記金属ベースの上に設けられた絶縁層と、前記絶縁層の上に設けられた複数の回路パターンと、を有する絶縁基板と、
    　前記回路パターンの一部上面に設けられた補助絶縁層と、
    　前記補助絶縁層の上に設けられた補助回路パターンと、を備え、
    　前記補助回路パターンには、第５接合材で前記主端子が固定され、
    　前記回路パターンには、第４接合材で前記金属ブロックの下面が固定された請求項１から４のいずれか１項に記載の半導体装置。
  7. 　前記金属ブロックの下面は、前記モールド樹脂の下面より下方に達する請求項１から６のいずれか１項に記載の半導体装置。
  8. 　前記モールド樹脂の下面には前記金属ブロックの外縁に沿って溝がある請求項１から７のいずれか１項に記載の半導体装置。
  9. 　金属ブロックと、
    　前記金属ブロックの上面に第１接合材で固定された、縦方向に電流を流す半導体素子と、
    　前記半導体素子の上面に第２接合材で固定された主端子と、
    　前記半導体素子に電気的に接続された信号端子と、
    　前記半導体素子と、前記第１接合材と、前記第２接合材を覆い、前記金属ブロックと、前記主端子と、前記信号端子の一部を覆うモールド樹脂と、を備え、
    　前記金属ブロックの下面が前記モールド樹脂から露出し、
    　前記主端子と前記信号端子は、前記モールド樹脂の側面から露出し、
    　前記信号端子は、前記モールド樹脂の中の第４部分と、前記第４部分につながりつつ前記モールド樹脂の外で下方向に曲がった第５部分と、前記第５部分とつながりつつ前記モールド樹脂の下面と略平行の第６部分と、を有したことを特徴とする半導体装置。
  10. 　前記主端子は、前記モールド樹脂の複数の側面から露出したことを特徴とする請求項１から９のいずれか１項に記載の半導体装置。
  11. 　前記複数の回路パターンの一部表面を絶縁樹脂で覆った請求項５又は６に記載の半導体装置。
  12. 　前記半導体素子はワイドバンドギャップ半導体によって形成されている請求項１から１１のいずれか１項に記載の半導体装置。
  13. 　前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料又はダイヤモンドである請求項１２に記載の半導体装置。
PCT/JP2020/018004 2020-04-27 2020-04-27 半導体装置 WO2021220357A1 (ja)

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JP2000223634A (ja) * 1999-01-28 2000-08-11 Hitachi Ltd 半導体装置
JP2003031736A (ja) * 2001-07-13 2003-01-31 Hitachi Ltd 半導体装置およびその製造方法
JP2004266096A (ja) * 2003-02-28 2004-09-24 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
WO2010131679A1 (ja) * 2009-05-14 2010-11-18 ローム株式会社 半導体装置
JP2011082323A (ja) * 2009-10-07 2011-04-21 Renesas Electronics Corp 半導体装置の製造方法
JP2012222000A (ja) * 2011-04-04 2012-11-12 Toyota Motor Corp 半導体モジュール及びその製造方法
JP2020009939A (ja) * 2018-07-10 2020-01-16 三菱電機株式会社 回路基板装置

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JP5481104B2 (ja) 2009-06-11 2014-04-23 ルネサスエレクトロニクス株式会社 半導体装置
JP5823798B2 (ja) 2011-09-29 2015-11-25 ルネサスエレクトロニクス株式会社 半導体装置

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Publication number Priority date Publication date Assignee Title
JPH0766231A (ja) * 1993-08-27 1995-03-10 Sharp Corp 面実装型半導体装置の製造方法
JP2000223634A (ja) * 1999-01-28 2000-08-11 Hitachi Ltd 半導体装置
JP2003031736A (ja) * 2001-07-13 2003-01-31 Hitachi Ltd 半導体装置およびその製造方法
JP2004266096A (ja) * 2003-02-28 2004-09-24 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
WO2010131679A1 (ja) * 2009-05-14 2010-11-18 ローム株式会社 半導体装置
JP2011082323A (ja) * 2009-10-07 2011-04-21 Renesas Electronics Corp 半導体装置の製造方法
JP2012222000A (ja) * 2011-04-04 2012-11-12 Toyota Motor Corp 半導体モジュール及びその製造方法
JP2020009939A (ja) * 2018-07-10 2020-01-16 三菱電機株式会社 回路基板装置

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