WO2022202100A1 - シリコン酸窒化膜の成膜方法及び薄膜トランジスタの製造方法 - Google Patents
シリコン酸窒化膜の成膜方法及び薄膜トランジスタの製造方法 Download PDFInfo
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- WO2022202100A1 WO2022202100A1 PCT/JP2022/007958 JP2022007958W WO2022202100A1 WO 2022202100 A1 WO2022202100 A1 WO 2022202100A1 JP 2022007958 W JP2022007958 W JP 2022007958W WO 2022202100 A1 WO2022202100 A1 WO 2022202100A1
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- silicon oxynitride
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- 238000000034 method Methods 0.000 title claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 239000010408 film Substances 0.000 title claims description 110
- 239000010409 thin film Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000007789 gas Substances 0.000 claims abstract description 53
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 36
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 22
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 230000005684 electric field Effects 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 abstract description 3
- 229910004014 SiF4 Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 73
- 239000011241 protective layer Substances 0.000 description 29
- 229910052731 fluorine Inorganic materials 0.000 description 22
- 239000011737 fluorine Substances 0.000 description 22
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 20
- 239000000758 substrate Substances 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 238000009832 plasma treatment Methods 0.000 description 6
- 229910003902 SiCl 4 Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002221 fluorine Chemical class 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- -1 Al-Nd Chemical class 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910008284 Si—F Inorganic materials 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Definitions
- the present invention relates to a method for forming a silicon oxynitride film and a method for manufacturing a thin film transistor using the film forming method.
- IGZO In--Ga--Zn--O-based oxide semiconductor for a semiconductor layer (channel layer)
- a thin film transistor is known in which a protective layer made of a silicon oxide film containing fluorine and an insulating layer such as a gate insulating layer are formed so as to be adjacent to an oxide semiconductor.
- a protective layer made of a silicon oxide film containing fluorine and an insulating layer such as a gate insulating layer are formed so as to be adjacent to an oxide semiconductor.
- an insulating layer made of a fluorine-containing silicon oxide film is formed on an oxide semiconductor by a plasma CVD method using SiCl 4 gas, SiF 4 gas, and oxygen gas as process gases. Have been described.
- Patent Document 1 has the problem of high manufacturing costs because it uses relatively expensive SiCl 4 gas as the process gas. Therefore, it is conceivable to reduce the manufacturing cost by forming an insulating layer using only SiF 4 gas and oxygen gas without using expensive SiCl 4 as a process gas. There is a problem that the formation of the silicon oxynitride film on the substrate becomes unstable (that is, the film adhesion is poor).
- the present invention has been made to solve the above-described problems at once, and in a film formation method for forming a silicon oxynitride film on an oxide semiconductor, the cost is reduced and the film formation stability is improved.
- the main task is to
- the film forming method of the present invention is a film forming method for forming a silicon oxynitride film on an oxide semiconductor. It is characterized in that the film is formed by a plasma CVD method by supplying a process gas, and in the supplied process gas, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 93% or more.
- a relatively inexpensive gas is used as the process gas in the plasma CVD method without using expensive SiCl 4 , so material costs can be reduced.
- the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is set to 93% or more.
- a film can be stably formed on a semiconductor. As a result, the yield can be improved and the manufacturing cost can be further reduced.
- the inventors of the present invention have I will explain the mechanism considered by them. That is, in the film forming method of the present invention, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is 93% or more, so that oxygen gas (binding energy: 5.16 eV) It is believed that the decomposition of Si—F (bond energy: 5.72 eV), which has a large bond energy and is difficult to decompose, is promoted, and the formation of a silicon oxynitride film starting from silicon atoms is facilitated.
- oxygen gas has a high electronegativity and acts as an additive gas for gas containing fluorine (F), which is thought to facilitate etching of the outermost surface of the substrate.
- F gas containing fluorine
- both surface reactions of film formation and etching progress in parallel, but since etching becomes relatively difficult by increasing the ratio of nitrogen gas, the silicon oxynitride film, which has good insulating properties, is oxidized. Therefore, it is thought that the film can be stably formed on the material semiconductor. Note that the description of this mechanism is not intended to limit the technical scope of the present invention.
- the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 96% or more.
- the leakage current density is 1 ⁇ 10 ⁇ 5 A/cm 2 or less
- the dielectric breakdown electric field strength is 3 MV/cm.
- a specific embodiment of the oxide semiconductor that more remarkably exhibits the effect of the film forming method of the present invention is one composed of In--Ga--Zn--O.
- the film forming method of the present invention can be used to manufacture a thin film transistor using a substrate having a low melting point such as a resin.
- the film forming method of the present invention it is possible to manufacture a thin film transistor having an insulating layer exhibiting good insulating performance even in such a low-temperature treatment.
- a method for manufacturing a thin film transistor according to the present invention is a method for manufacturing a thin film transistor having an oxide semiconductor made of In--Ga--Zn--O as a channel layer, comprising: a semiconductor layer forming step of forming the oxide semiconductor by sputtering; and an insulating layer forming step of forming an insulating layer made of a silicon oxynitride film on the oxide semiconductor by the film forming method described above. According to such a method for manufacturing a thin film transistor, it is possible to obtain the same effect as the film forming method of the present invention described above.
- FIG. 2 is a diagram schematically showing the configuration of a bottom-gate thin film transistor according to this embodiment
- FIG. 4 is a diagram schematically showing a manufacturing process of the thin film transistor of the same embodiment
- FIG. 4 is a diagram schematically showing the configuration of a plasma processing apparatus used in the plasma processing step of the thin film transistor of the same embodiment
- FIG. 10 is a diagram schematically showing the configuration of a top-gate thin film transistor according to another embodiment
- 4 is a graph showing the relationship between the ratio of nitrogen gas flow rate and the stability of film formation in an experimental example.
- 7 is a graph showing the relationship between the ratio of the nitrogen gas flow rate, the film formation rate, and the refractive index in the experimental example.
- 4 is a graph showing the relationship between the ratio of nitrogen gas flow rate and insulating properties in an experimental example.
- a thin film transistor and a method for manufacturing the same according to one embodiment of the present invention will be described below.
- the thin film transistor 1 of this embodiment is a so-called bottom gate type TFT, and uses an oxide semiconductor for the channel. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, a semiconductor layer 5, a source electrode 6 and a drain electrode 7, and a protective layer 8, They are formed in this order from the substrate 2 side.
- the protective layer 8 corresponds to the "insulating layer" in the claims.
- the substrate 2 is made of any material that allows light to pass through. ) or a glass material.
- the gate electrode 3 controls the carrier density in the semiconductor layer 5 by the gate voltage applied to the thin film transistor 1 .
- the gate electrode 3 is made of any material having high conductivity, and is made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, and the like. may be In addition, the conductivity of metal oxides such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), In-Ga-Zn-O (IGZO) It may consist of a membrane.
- the gate electrode 3 may be composed of a single layer structure or a laminated structure of two or more layers of these conductive films.
- the gate insulating layer 4 is made of any insulating material having high insulating properties, and is selected from, for example, SiOx , SiNx , SiON, Al2O3 , Y2O3 , Ta2O5 , Hf2 , and the like. It may be an insulating film that includes one or more oxides that are The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.
- the semiconductor layer (channel layer) 5 passes the current flowing between the source electrode 6 and the drain electrode 7 .
- the semiconductor layer 5 of the present embodiment is made of an oxide semiconductor, and contains, as a main component, an oxide of at least one element selected from, for example, In, Ga, Zn, Sn, Al, Ti, and the like. . Specific examples of materials constituting the semiconductor layer 5 include In--Ga--Zn--O (IGZO), In--Al--Mg--O, In--Al--Zn--O, In--Hf--Zn--O, etc. is mentioned.
- the semiconductor layer 5 is composed of an amorphous oxide semiconductor film.
- the semiconductor layer 5 of the present embodiment has a single-layer structure, but is not limited to this, and may have a laminated structure in which a plurality of layers having different compositions and crystallinities are laminated.
- the source electrode 6 and the drain electrode 7 are formed apart from each other so as to partially cover the surface of the semiconductor layer 5 .
- the source electrode 6 and the drain electrode 7 are made of a highly conductive material so as to function as electrodes.
- the source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are laminated.
- the protective layer (passivation layer) 8 covers and protects the surface (channel region) of the semiconductor layer 5 exposed between the source electrode 6 and the drain electrode 7, and is made of an insulating material. .
- the protective layer 8 is provided in contact with at least the surface of the semiconductor layer 5 .
- the protective layer 8 of this embodiment is provided so as to further cover the surfaces of the source electrode 6 and the drain electrode 7 .
- the protective layer 8 is composed of a fluorine-containing silicon oxynitride film (SiON:F).
- This fluorine-containing silicon oxynitride film preferably has a leakage current density of 1 ⁇ 10 ⁇ 5 A/cm 2 or less and a dielectric breakdown field strength of 3 MV/cm or more. ⁇ 7 A/cm 2 or less, and a dielectric breakdown field strength of 8 MV/cm or more is more preferable.
- a second film made of, for example, a fluorine-containing silicon oxide film (SiN:F), a fluorine-containing silicon oxide film (SiO:F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed on the protective layer 8.
- a protective layer of may be further provided as required.
- the method of manufacturing the thin film transistor 1 of this embodiment includes a gate electrode forming process, a gate insulating layer forming process, a semiconductor layer forming process, a source/drain electrode forming process, a plasma treatment process, and a protective layer forming process.
- the protective layer forming step corresponds to the "insulating layer forming step" in the claims. Each step will be described below.
- the method of forming the gate electrode 3 is not particularly limited, and may be formed by a known method such as a vacuum deposition method.
- the gate insulating layer 4 is formed to cover the surfaces of the substrate 2 and the gate electrode 3 .
- a method for forming the gate insulating layer 4 is not particularly limited, and it may be formed by a known method.
- the semiconductor layer 5 is formed on the gate insulating layer 4 .
- This semiconductor layer 5 may be formed by a known method.
- the semiconductor layer 5 may be formed by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma.
- the semiconductor layer 5 made of an oxide semiconductor may be formed by another method without being limited to this.
- the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5 .
- the source electrode 6 and the drain electrode 7 can be formed by a known method using, for example, RF magnetron sputtering.
- the source electrode 6 and the drain electrode 7 are formed on the surface of the semiconductor layer 5 so as to be spaced apart from each other and partially expose the surface of the semiconductor layer 5 .
- the surface of the semiconductor layer 5 may be subjected to plasma treatment (pre-film formation treatment).
- this plasma processing may be performed using an inductively coupled plasma processing apparatus 100 as illustrated in FIG.
- the plasma processing apparatus 100 includes a vacuum vessel 20 inside which is formed a processing chamber 10 which is evacuated and into which a process gas G is introduced; an antenna 30 provided outside the processing chamber 10; and a high frequency power supply 40 that applies a high frequency (13.56 MHz).
- a high frequency is applied from the high frequency power supply 40 to the antenna 30
- a high frequency magnetic field generated from the antenna 30 is formed in the processing chamber 10 to generate an induced electric field, thereby generating an inductively coupled plasma P.
- the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (N 2 /N 2 +O 2 ) is preferably 70% or more, more preferably 80% or more. More preferably, it is 90% or more.
- N 2 /N 2 +O 2 the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas
- this step is preferably performed at a substrate temperature as low as 150° C. or higher and 300° C. or lower.
- the treatment time for the plasma treatment is not particularly limited, but from the viewpoint of further reducing the fixed charge density in the protective layer 8, it is preferably 15 seconds or more and 45 seconds or less.
- the RF power, the film-forming pressure, the absolute amount of the process gas, and the like may be appropriately set.
- the flow rate of each gas supplied into the processing chamber 10 is controlled by a mass flow controller provided in the gas flow path. That is, the "flow rate" referred to here means a set value in a flow control device such as a mass flow controller (the same applies to other processes).
- a protective layer 8 is formed to cover the surface of the semiconductor layer 5 exposed between the source electrode 6 and the drain electrode 7, as shown in FIG. do.
- the protective layer 8 is formed by plasma CVD (chemical vapor deposition) using the above-described plasma processing apparatus (hereinafter also referred to as plasma CVD apparatus) 100, for example.
- plasma CVD apparatus plasma processing apparatus
- the protective layer forming step is performed while maintaining the plasma generated in the processing chamber 10 of the plasma CVD apparatus 100 in the plasma processing step.
- SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas, and hydrogen gas are supplied as process gases into the processing chamber 10, and a high frequency is applied to the antenna 30 in this state. to generate an inductively coupled plasma.
- the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 93% or more, and 96% or more. is preferred.
- the upper limit of the ratio is not particularly limited, it is preferably 100%.
- the flow rate of the oxygen gas intentionally supplied into the processing chamber 10 is 0 ccm, but even in this case, the process gas inevitably contains oxygen gas. Therefore, a fluorine-containing silicon oxynitride film can be formed. Moreover, this step is preferably performed at a substrate temperature as low as 150° C. or higher and 300° C. or lower. In addition, the RF power, the film-forming pressure, the absolute amount of the process gas, and the like may be appropriately set.
- a fluorine-containing silicon oxide film SiN:F
- a fluorine-containing silicon oxide film SiO:F
- a silicon nitride film SiNx
- a silicon oxide film SiOx
- a second protective layer may be deposited. Film formation of this protective layer can be performed using the plasma CVD apparatus 100 similarly to the protective layer 8 .
- heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure.
- the furnace temperature in the heat treatment is not particularly limited, and is, for example, 150° C. or higher and 300° C. or lower.
- the heat treatment time is not particularly limited, and is, for example, 1 hour or more and 3 hours or less.
- the thin film transistor 1 of the present embodiment can be obtained.
- the plasma CVD method is used to protect the thin film transistor 1 by using a relatively inexpensive gas as a process gas without using expensive SiCl 4 .
- Forming the layer 8 reduces material costs. Further, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is set to 93% or more.
- the protective layer 8 composed of an oxide semiconductor can be stably formed on the semiconductor layer 5 composed of an oxide semiconductor. As a result, the yield can be improved and the manufacturing cost can be further reduced.
- the thin film transistor 1 of the above-described embodiment is a bottom gate type in which the gate electrode 3, the gate insulating layer 4 and the semiconductor layer 5 are stacked in order from the substrate 2 side, but the present invention is not limited to this.
- the thin film transistor 1 may be of a top gate type in which a semiconductor layer 5, a gate insulating layer 4, and a gate electrode 3 are stacked in order from the substrate 2 side.
- the gate insulating layer 4 laminated on the semiconductor layer 5 corresponds to the "insulating layer" in the claims.
- the gate insulating layer 4 is composed of a fluorine-containing silicon oxynitride film (SiON:F), has a leakage current density of 1 ⁇ 10 ⁇ 5 A/cm 2 or less, and has a dielectric breakdown electric field strength of 3 MV/cm 2 . More preferably, it has a leakage current density of 1 ⁇ 10 ⁇ 7 A/cm 2 or less and a dielectric breakdown field strength of 8 MV/cm or more.
- SiON:F fluorine-containing silicon oxynitride film
- the manufacturing method is to perform the semiconductor layer forming step, the source/drain electrode forming step, the plasma processing step, the gate insulating layer forming step, and the gate electrode forming step in this order.
- the gate insulating layer forming step corresponds to the "insulating layer forming step" in the claims. Therefore, in this embodiment, the gate insulating layer forming step is performed by plasma CVD using SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas as process gases.
- SiF 4 silicon tetrafluoride
- the surface of the oxide semiconductor layer 5 is plasma-treated after forming the oxide semiconductor layer 5 and before forming the insulating layer (protective layer 8) thereon, but the present invention is not limited to this. .
- an insulating layer (protective layer 8) may be formed on the surface of the oxide semiconductor layer 5 without performing plasma treatment on the surface.
- the semiconductor layer 5 is made of an oxide semiconductor in the above embodiment, it is not limited to this. In other embodiments, the semiconductor layer 5 may consist of any semiconductor material, for example amorphous Si or polycrystalline Si.
- Example 1 Relationship between nitrogen gas flow rate ratio in process gas and film formation stability The relationship between (also referred to as (N 2 +O 2 )) and the stability of film formation over an oxide semiconductor was evaluated.
- the ratio of N 2 /(N 2 +O 2 ) in the process gas to be supplied is changed (from 0% to 100%), and the silicon substrate and the IGZO film are separated. A fluorine-containing silicon oxynitride film was formed on each surface. Then, the ratio of the film thickness on the IGZO film to the film thickness on the Si substrate (hereinafter also referred to as film thickness ratio) was measured.
- each fluorine-containing silicon oxynitride film was formed by supplying SiF 4 , N 2 , O 2 and H 2 as process gases into the processing chamber of a plasma CVD apparatus, RF power: 20 kW (0.48 W/ cm 2 ), pressure during film formation: 10 Pa, and set temperature: 200°C.
- the flow rates of the supplied gases were set to SiF 4 : 500 sccm, H 2 : 900 sccm, and N 2 +O 2 : 3000 sccm.
- the film thickness of the fluorine-containing silicon oxynitride film after film formation was measured with a spectroscopic ellipsometer (FE-5000S, manufactured by Otsuka Electronics Co., Ltd.). The measurement results are shown in FIG.
- the film thickness ratio is less than 0.9 or more than 1.1. Film formation was unstable.
- N 2 /(N 2 +O 2 ) in the process gas is in the range of 93% or more (93.3%, 96.7%, 100%)
- the film thickness ratio is 0.9 or more. It was 1.1 or less (that is, the film thickness difference was within 10%), and a fluorine-containing silicon oxynitride film could be stably formed on the IGZO film.
- Example 2 Relationship between nitrogen gas flow rate ratio in process gas, film formation rate, and refractive index Next, the ratio of the nitrogen gas flow rate to the total flow rate of nitrogen gas and oxygen gas in the process gas in the plasma CVD method. , the deposition rate and the refractive index of the fluorine-containing silicon oxynitride film over the oxide semiconductor.
- the N 2 /(N 2 +O 2 ) in the process gas was set to 93% or more (specifically, 93.3%, 96.7%, 100%) and on the IGZO film
- the film formation rate and the refractive index were measured for the three samples on which the film was formed.
- the film formation rate of each sample was calculated by dividing the film thickness measured by the spectroscopic ellipsometer by the film formation time.
- the refractive index of each sample was also measured by the above spectroscopic ellipsometer. The results are shown in FIG.
- a fluorine-containing silicon oxynitride film was formed on a Si substrate using the plasma CVD apparatus described above, and an aluminum electrode was formed on this fluorine-containing silicon oxynitride film to prepare a sample.
- three types (93.3%, 96.7%, 100%) in which N 2 /(N 2 +O 2 ) in the process gas supplied when forming the fluorine-containing silicon oxynitride film are changed. created a sample of As for each type of sample, as shown in FIG. 7, a total of six samples were prepared by changing conditions such as RF power, pressure and temperature during film formation, and process gas flow rate.
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Abstract
Description
このような成膜方法であれば、プラズマCVD法におけるプロセスガスとして、高価なSiCl4を用いることなく比較的な安価なガスを用いるので、材料コストを低減できる。さらに、プロセスガスとして供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合を93%以上とし、その割合を非常に高くすることにより、絶縁性の良好な酸窒化シリコン膜を酸化物半導体上に安定して成膜することができる。これにより歩留まりが向上し、製造コストをより一層低減させることができる。
このようにすれば、酸窒化シリコン膜の絶縁性能をより一層向上することができる。
このような低温であれば、本発明の成膜方法を、樹脂等の融点が低い基板を用いた薄膜トランジスタの製造に利用することができる。本発明の成膜方法を用いれば、このような低温処理においても良好な絶縁性能を発揮する絶縁層を備える薄膜トランジスタを製造できる。
このような薄膜トランジスタの製造方法によれば、前記した本発明の成膜方法と同様の作用効果を奏することができる。
本実施形態の薄膜トランジスタ1は所謂ボトムゲート型のTFTであり、酸化物半導体をチャネルに用いたものである。具体的には図1に示すように、基板2と、ゲート電極3と、ゲート絶縁層4と、半導体層5と、ソース電極6及びドレイン電極7と、保護層8とを有しており、基板2側からこの順に形成されている。なおこの実施形態では、保護層8が特許請求の範囲でいう“絶縁層”に相当する。以下、各部について詳述する。
次に、上述した構造の薄膜トランジスタ1の製造方法を、図2を参照して説明する。
本実施形態の薄膜トランジスタ1の製造方法は、ゲート電極形成工程、ゲート絶縁層形成工程、半導体層形成工程、ソース・ドレイン電極形成工程、プラズマ処理工程及び保護層形成工程を含む。なおこの実施形態では、保護層形成工程が特許請求の範囲でいう“絶縁層形成工程”に相当する。以下、各工程について説明する。
まず図2の(a)に示すように、例えばPET等の樹脂材料からなる基板2を準備し、基板2の表面にゲート電極3を形成する。ゲート電極3の形成方法は特に制限されず、例えば真空蒸着法等の既知の方法により形成してよい。
次に、図2の(b)に示すように、基板2及びゲート電極3の表面を覆うようにゲート絶縁層4を形成する。ゲート絶縁層4の形成方法は特に限定されず、既知の方法により形成してよい。
次に、図2の(c)に示すように、ゲート絶縁層4上に半導体層5を形成する。この半導体層5は、既知の方法により形成してよい。例えば、誘導結合型のプラズマを用いて、InGaZnO等の導電性酸化物焼結体をターゲットとしてスパッタリングすることにより半導体層5を形成してよい。なおこれに限らず、他の方法により酸化物半導体からなる半導体層5を形成してもよい。
次に、図2の(d)に示すように、半導体層5上にソース電極6及びドレイン電極7を形成する。ソース電極6およびドレイン電極7の形成は、例えば、RFマグネトロンスパッタリング等を用いた既知の方法により形成することができる。ソース電極6及びドレイン電極7は、半導体層5の表面上で互いに離間し、半導体層5の表面の一部を露出させるように形成される。
ここで、半導体層5の表面に保護層8を形成する前に、半導体層5の表面に対してプラズマ処理(成膜前処理)を行ってもよい。具体的にこのプラズマ処理は、図3に例示するような誘導結合型のプラズマ処理装置100を用いて行ってよい。具体的にプラズマ処理装置100は、真空排気され且つプロセスガスGが導入される処理室10が内側に形成された真空容器20と、処理室10の外部に設けられたアンテナ30と、アンテナ30に高周波(13.56MHz)を印加する高周波電源40とを備えている。高周波電源40からアンテナ30に高周波を印加すると、アンテナ30から発生した高周波磁場が処理室10内に形成されることで誘導電界が発生し、これにより誘導結合型のプラズマPが生成される。
プラズマ処理工程の後、図2の(e)に示すように、ソース電極6及びドレイン電極7の間から露出する半導体層5の表面を覆うように保護層8を形成する。この保護層8の形成は、例えば前記したプラズマ処理装置(以下、プラズマCVD装置ともいう)100を用いてプラズマCVD法(化学気相成長法)を用いて行われる。ここでは、プラズマ処理工程においてプラズマCVD装置100の処理室10内に生成したプラズマを維持した状態で保護層形成工程に移行するようにしている。
必要に応じて酸素を含む大気圧下の雰囲気中で熱処理を行ってもよい。熱処理における炉内温度は特に限定されず、例えば150℃以上300℃以下である。また熱処理時間は特に限定されず、例えば1時間以上3時間以下である。
このように構成した本実施形態の薄膜トランジスタ1の製造方法であれば、保護層形成工程において、プロセスガスとして、高価なSiCl4を用いることなく比較的な安価なガスを用いてプラズマCVD法により保護層8を形成するので、材料コストを低減できる。そしてさらに、プロセスガスとして供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合を93%以上とし、その割合を非常に高くしているので、絶縁性の良好な酸窒化シリコン膜から成る保護層8を酸化物半導体から成る半導体層5上に安定して成膜することができる。これにより歩留まりが向上し、製造コストをより一層低減させることができる。
なお、本発明は前記実施形態に限られるものではない。
そのためこの実施形態では、ゲート絶縁層形成工程は、SiF4(四フッ化ケイ素)ガス、窒素ガス、酸素ガス及び水素ガスをプロセスガスとして用いて、プラズマCVD法により行われる。具体的な方法は、前記した保護層形成工程と同様である。
プラズマCVD法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合(N2/(N2+O2)とも記載する)と、酸化物半導体上への成膜の安定性との関係を評価した。
一方で、プロセスガス中のN2/(N2+O2)を93%以上の範囲で行ったもの(93.3%、96.7%、100%)は、膜厚比が0.9以上1.1以下(すなわち、膜厚の差が10%以内)であり、IGZO膜上に安定してフッ素含有酸窒化シリコン膜を成膜できた。
次に、プラズマCVD法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、酸化物半導体上へのフッ素含有酸窒化シリコン膜の成膜レート及び屈折率との関係を評価した。
次に、プラズマCVD法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、酸化物半導体膜上に成膜したフッ素含有酸窒化シリコン膜の絶縁性との関係を評価した。
2 ・・・基板
3 ・・・ゲート電極
4 ・・・ゲート絶縁層
5 ・・・半導体層
6 ・・・ソース電極
7 ・・・ドレイン電極
8 ・・・保護層
Claims (6)
- 酸化物半導体の上に酸窒化シリコン膜を成膜する成膜方法であって、
前記酸窒化シリコン膜を、SiF4ガス、窒素ガス、酸素ガス及び水素ガスをプロセスガスとして供給して行うプラズマCVD法により成膜し、
前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が93%以上であることを特徴とする成膜方法。 - 前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が96%以上である請求項1に記載の成膜方法。
- 前記酸窒化シリコン膜が、リーク電流密度が1×10-5A/cm2以下であり、絶縁破壊電界強度が3MV/cm以上のものである請求項1又は2に記載の成膜方法。
- 酸化物半導体がIn-Ga-Zn-Oにより構成されている請求項1~3のいずれか一項に記載の成膜方法。
- 前記プラズマCVD法による前記酸窒化シリコン膜の成膜を300℃以下で行う請求項1~4のいずれか一項に記載の成膜方法。
- In-Ga-Zn-Oからなる酸化物半導体をチャネル層とする薄膜トランジスタの製造方法であって、
スパッタリングにより前記酸化物半導体を形成する半導体層形成工程と、
請求項1~5のいずれか一項に記載の成膜方法により、前記酸化物半導体の上に酸窒化シリコン膜から成る絶縁層を成膜する絶縁層形成工程と、を有することを特徴とする薄膜トランジスタの製造方法。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007299913A (ja) * | 2006-04-28 | 2007-11-15 | Toppan Printing Co Ltd | 薄膜トランジスタ及びその製造方法 |
JP2012094757A (ja) * | 2010-10-28 | 2012-05-17 | Fujifilm Corp | 薄膜トランジスタおよびその製造方法 |
JP2014007396A (ja) * | 2012-05-31 | 2014-01-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2014030002A (ja) * | 2012-06-29 | 2014-02-13 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2014039019A (ja) * | 2012-07-20 | 2014-02-27 | Semiconductor Energy Lab Co Ltd | 半導体装置および半導体装置の作製方法 |
JP2014225651A (ja) * | 2013-04-26 | 2014-12-04 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
JP2016213452A (ja) * | 2015-04-28 | 2016-12-15 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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2021
- 2021-03-23 JP JP2021048568A patent/JP2022147359A/ja active Pending
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2022
- 2022-02-25 WO PCT/JP2022/007958 patent/WO2022202100A1/ja active Application Filing
- 2022-02-25 CN CN202280020052.8A patent/CN116982142A/zh active Pending
- 2022-02-25 KR KR1020237031266A patent/KR20230138552A/ko unknown
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007299913A (ja) * | 2006-04-28 | 2007-11-15 | Toppan Printing Co Ltd | 薄膜トランジスタ及びその製造方法 |
JP2012094757A (ja) * | 2010-10-28 | 2012-05-17 | Fujifilm Corp | 薄膜トランジスタおよびその製造方法 |
JP2014007396A (ja) * | 2012-05-31 | 2014-01-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2014030002A (ja) * | 2012-06-29 | 2014-02-13 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2014039019A (ja) * | 2012-07-20 | 2014-02-27 | Semiconductor Energy Lab Co Ltd | 半導体装置および半導体装置の作製方法 |
JP2014225651A (ja) * | 2013-04-26 | 2014-12-04 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
JP2016213452A (ja) * | 2015-04-28 | 2016-12-15 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
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CN116982142A (zh) | 2023-10-31 |
KR20230138552A (ko) | 2023-10-05 |
JP2022147359A (ja) | 2022-10-06 |
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