WO2022193341A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2022193341A1
WO2022193341A1 PCT/CN2021/082380 CN2021082380W WO2022193341A1 WO 2022193341 A1 WO2022193341 A1 WO 2022193341A1 CN 2021082380 W CN2021082380 W CN 2021082380W WO 2022193341 A1 WO2022193341 A1 WO 2022193341A1
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WIPO (PCT)
Prior art keywords
transistor
node
signal
electrically connected
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/082380
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English (en)
French (fr)
Inventor
潘优
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Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US17/290,684 priority Critical patent/US12283214B2/en
Publication of WO2022193341A1 publication Critical patent/WO2022193341A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present application relates to the field of display, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver on Array, integrated gate drive circuit
  • GOA Gate Driver on Array, integrated gate drive circuit
  • the existing GOA circuit works in a high-temperature and high-humidity environment for a long time, the thin-film transistor is prone to leakage current, thereby causing the failure of the GOA circuit.
  • the present application provides a GOA circuit and a display panel, which can solve the technical problem that the GOA circuit is prone to leakage when used for a long time, thereby causing the GOA circuit to fail.
  • the present application provides a GOA circuit, which includes an N-level cascaded GOA unit, and the nth-level GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down maintenance module, and an interrupt control module, 1 ⁇ n ⁇ N-1, both n and N are positive integers;
  • the node control module is connected to the upper-level scan signal, the next-level scan signal, the first scan control signal and the second scan control signal, and is electrically connected to the first node and the second node, and the node control module uses in accordance with the previous-stage scan signal, the next-stage scan signal, the first scan control signal and the second scan control signal, pulling up the potential of the first node and pulling down the second the potential of the node;
  • the pull-up module is connected to the clock signal of the current stage and is electrically connected to the first node, and the pull-up module is used for scanning the signal at the current stage according to the clock signal of the current stage and the potential of the first node
  • the output terminal outputs the scanning signal of this stage
  • the pull-down module is electrically connected to the second node, and the pull-down module is used for pulling down the potential of the scan signal output terminal according to the potential of the second node;
  • the pull-down maintaining module is connected to an upper-level clock signal, a next-level clock signal, the first scan control signal and the second scan control signal, and is electrically connected to the first node and the second node node, the pull-down maintaining module is configured to pull down the first node according to the previous-stage clock signal, the next-stage clock signal, the first scan control signal and the second scan control signal potential and pulling up the potential of the second node;
  • the stoppage control module is connected to the stoppage control signal, and the stoppage control module is configured to pull down the output of the scan signal of the current stage based on the stoppage control signal when the GOA circuit is in the touch stoppage stage
  • the potential of the terminal; the pull-down maintaining module is also used for suppressing the leakage of the first node during the touch pause phase.
  • the node control module includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor;
  • the gate of the first transistor is connected to the previous-stage scan signal, the source of the first transistor is connected to the first scan control signal, and the drain of the first transistor is electrically connected to the first node;
  • the gate of the second transistor is connected to the next-level scan signal, the source of the second transistor is connected to the second scan control signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is connected to a constant voltage low level signal, and the drain of the third transistor is electrically connected to the first node.
  • the first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is connected to the constant voltage low level signal;
  • the first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is connected to the constant voltage low level signal.
  • the pull-up module includes a fourth transistor and a fifth transistor
  • the gate of the fourth transistor is connected to a constant voltage high-level signal, the source of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is connected to the drain of the fifth transistor. grid electrical connection;
  • the source of the fifth transistor is connected to the clock signal of the current stage, and the drain of the fifth transistor is electrically connected to the scan signal output end of the current stage.
  • the pull-down module includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is connected to a constant voltage low level signal, and the drain of the sixth transistor is electrically connected to the current Level scan signal output.
  • the pull-down maintaining module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate of the seventh transistor is connected to the first scan control signal, the source of the seventh transistor is connected to the next-stage clock signal, and the drain of the seventh transistor is electrically connected to the a drain of the eighth transistor and a gate of the ninth transistor;
  • the gate of the eighth transistor is connected to the second scan control signal, and the source of the eighth transistor is connected to the upper-stage clock signal;
  • the source of the ninth transistor is connected to a constant voltage high level signal, and the drain of the ninth transistor is electrically connected to the second node;
  • the gate of the tenth transistor is electrically connected to the drain of the eleventh transistor, the source of the tenth transistor is connected to a constant voltage low level signal, and the drain of the tenth transistor is electrically connected at the first node;
  • the gate of the eleventh transistor is connected to the ground terminal, and the source of the eleventh transistor is electrically connected to the second node.
  • the eleventh transistor when the potential of the second node is the potential of the constant-voltage high-level signal, the eleventh transistor is turned off, and the potential of the drain of the eleventh transistor is The voltage difference between the potential of the ground terminal and the threshold voltage of the eleventh transistor.
  • the voltage difference between the potential of the gate of the tenth transistor and the potential of the drain of the tenth transistor is smaller than the difference between the constant voltage high potential and the constant voltage low potential differential pressure.
  • the stop control module includes a twelfth transistor
  • the gate of the twelfth transistor is connected to the stop control signal, the source of the twelfth transistor is connected to the constant voltage low level signal, and the drain of the twelfth transistor is electrically connected to the Describe the scanning signal output terminal of this stage.
  • the GOA circuit further includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;
  • the gate of the thirteenth transistor, the source of the thirteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor are all connected to a discharge control signal, and the tenth transistor is connected to a discharge control signal.
  • the drains of the three transistors are electrically connected to the scanning signal output end of the current stage;
  • the source of the fourteenth transistor is connected to a constant voltage low level signal, and the drain of the fourteenth transistor is electrically connected to the second node;
  • the source of the fifteenth transistor is connected to the constant voltage low level signal, and the drain of the fifteenth transistor is electrically connected to the pull-down maintaining module.
  • the present application further provides a display panel, which includes a GOA circuit, the GOA circuit includes N-level cascaded GOA units, and the n-th level GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down module, and a pull-down module.
  • Maintenance module and stop control module 1 ⁇ n ⁇ N-1, n and N are positive integers;
  • the node control module is connected to the upper-level scan signal, the next-level scan signal, the first scan control signal and the second scan control signal, and is electrically connected to the first node and the second node, and the node control module uses pulling up the potential of the first node and pulling down the first node according to the previous-stage scan signal, the next-stage scan signal, the first scan control signal and the second scan control signal The potential of the two nodes;
  • the pull-up module is connected to the clock signal of the current stage and is electrically connected to the first node, and the pull-up module is used for scanning the signal at the current stage according to the clock signal of the current stage and the potential of the first node
  • the output terminal outputs the scanning signal of this stage
  • the pull-down module is electrically connected to the second node, and the pull-down module is used for pulling down the potential of the scan signal output terminal according to the potential of the second node;
  • the pull-down maintaining module is connected to an upper-level clock signal, a next-level clock signal, the first scan control signal and the second scan control signal, and is electrically connected to the first node and the second node node, the pull-down maintaining module is configured to pull down the first node according to the previous-stage clock signal, the next-stage clock signal, the first scan control signal and the second scan control signal potential and pulling up the potential of the second node;
  • the stoppage control module is connected to the stoppage control signal, and the stoppage control module is configured to pull down the output of the scan signal of the current stage based on the stoppage control signal when the GOA circuit is in the touch stoppage stage
  • the potential of the terminal; the pull-down maintaining module is also used for suppressing the leakage of the first node during the touch pause phase.
  • the node control module includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor;
  • the gate of the first transistor is connected to the previous-stage scan signal, the source of the first transistor is connected to the first scan control signal, and the drain of the first transistor is electrically connected to the first node;
  • the gate of the second transistor is connected to the next-level scan signal, the source of the second transistor is connected to the second scan control signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is connected to a constant voltage low level signal, and the drain of the third transistor is electrically connected to the first node.
  • the first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is connected to the constant voltage low level signal;
  • the first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is connected to the constant voltage low level signal.
  • the pull-up module includes a fourth transistor and a fifth transistor
  • the gate of the fourth transistor is connected to a constant voltage high-level signal, the source of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is connected to the drain of the fifth transistor. grid electrical connection;
  • the source of the fifth transistor is connected to the clock signal of the current stage, and the drain of the fifth transistor is electrically connected to the scan signal output end of the current stage.
  • the pull-down module includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is connected to a constant voltage low level signal, and the drain of the sixth transistor is electrically connected to the current Level scan signal output.
  • the pull-down maintaining module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate of the seventh transistor is connected to the first scan control signal, the source of the seventh transistor is connected to the next-stage clock signal, and the drain of the seventh transistor is electrically connected to the a drain of the eighth transistor and a gate of the ninth transistor;
  • the gate of the eighth transistor is connected to the second scan control signal, and the source of the eighth transistor is connected to the upper-stage clock signal;
  • the source of the ninth transistor is connected to a constant voltage high level signal, and the drain of the ninth transistor is electrically connected to the second node;
  • the gate of the tenth transistor is electrically connected to the drain of the eleventh transistor, the source of the tenth transistor is connected to a constant voltage low level signal, and the drain of the tenth transistor is electrically connected at the first node;
  • the gate of the eleventh transistor is connected to the ground terminal, and the source of the eleventh transistor is electrically connected to the second node.
  • the eleventh transistor when the potential of the second node is the potential of the constant-voltage high-level signal, the eleventh transistor is turned off, and the potential of the drain of the eleventh transistor is is the voltage difference between the potential of the ground terminal and the threshold voltage of the eleventh transistor.
  • the voltage difference between the potential of the gate of the tenth transistor and the potential of the drain of the tenth transistor is smaller than the constant voltage high potential and the constant voltage low potential pressure difference.
  • the stop control module includes a twelfth transistor
  • the gate of the twelfth transistor is connected to the stop control signal, the source of the twelfth transistor is connected to the constant voltage low level signal, and the drain of the twelfth transistor is electrically connected to the Describe the scanning signal output terminal of this stage.
  • the GOA circuit further includes a thirteenth transistor, a fourteenth transistor and a fifteenth transistor;
  • the gate of the thirteenth transistor, the source of the thirteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor are all connected to a discharge control signal, and the tenth transistor is connected to a discharge control signal.
  • the drains of the three transistors are electrically connected to the scanning signal output end of the current stage;
  • the source of the fourteenth transistor is connected to a constant voltage low level signal, and the drain of the fourteenth transistor is electrically connected to the second node;
  • the source of the fifteenth transistor is connected to the constant voltage low level signal, and the drain of the fifteenth transistor is electrically connected to the pull-down maintaining module.
  • an eleventh transistor is arranged between the gate of the tenth transistor and the second node, and the gate of the eleventh transistor is electrically connected to the ground terminal, Therefore, the negative drift of the tenth transistor and the increasing tendency of the off-state current are weakened, and the leakage of the first node is suppressed when the GOA circuit is in the touch pause stage.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an nth-level GOA unit in a GOA circuit provided by an embodiment of the present application;
  • FIG. 3 is a schematic circuit diagram of an nth-level GOA unit in a GOA circuit provided by an embodiment of the present application;
  • FIG. 4 is a schematic time sequence diagram of an nth-level GOA unit in a GOA circuit provided by an embodiment of the present application;
  • FIG. 5 is another schematic circuit diagram of the nth-level GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode, and the other electrode is called the drain electrode. According to the form in the drawing, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the display panel 100 provided by the embodiment of the present application includes a display area 10 and a GOA circuit area 20 disposed outside the display area 10 .
  • the display area 10 is provided with a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel units defined by the intersection of the plurality of scan lines and the plurality of data lines.
  • the GOA circuit area 20 is provided with a GOA circuit, the GOA circuit includes multi-level GOA cells, and the multi-level GOA cells are connected to a plurality of scan lines in one-to-one correspondence; that is, the number of GOA cells is equal to the number of scan lines.
  • the GOA circuit may include multiple cascaded odd-level GOA units and multiple cascaded even-level GOA units.
  • a plurality of cascaded odd-level GOA units are arranged on one side of the display area 10
  • a plurality of cascaded even-level GOA units are arranged on the other side of the display area 10 .
  • the GOA circuit includes M levels of GOA cells, where M is a positive integer. When M is an even number, the 1st level GOA unit, the 3rd level GOA unit, the 5th level GOA unit, ..., the M-1st level GOA unit are cascaded. Level 2 GOA unit, Level 4 GOA unit, Level 6 GOA unit, ..., Level M GOA unit cascade arrangement.
  • the GOA circuit includes N-level cascaded GOA units.
  • the GOA units arranged in N-level cascade may be odd-level GOA units arranged in multiple cascades, or may be even-level GOA units arranged in multiple cascades.
  • the GOA circuit accesses the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, the fourth clock signal ck4, the fifth clock signal ck5, the sixth clock signal ck6, and the seventh clock
  • the signal ck7, the eighth clock signal ck8 the first start signal STV1 and the second start signal STV2.
  • a plurality of cascaded odd-level GOA units are connected to the first clock signal ck1, the third clock signal ck3, the fifth clock signal ck5, the seventh clock signal ck7 and the first start signal STV1.
  • a plurality of cascaded even-stage GOA units are connected to the second clock signal ck2, the fourth clock signal ck4, the sixth clock signal ck6, the eighth clock signal ck8 and the second start signal STV2.
  • the GOA circuit provided by the embodiment of the present application may adopt a forward scanning mode or a reverse scanning mode.
  • the first start signal is connected to the first-level GOA unit, and the first start signal is used as the upper-level scan signal of the first-level GOA unit;
  • the second start signal is connected to the second-level GOA unit unit, the second start signal is used as the upper-level scan signal of the second-level GOA unit.
  • the GOA circuits are sequentially activated from the first stage GOA cell to the last stage GOA cell.
  • the GOA circuits are sequentially activated from the second-level GOA unit to the last-level GOA unit.
  • the first start signal is connected to the M-1 level GOA unit, and the first start signal is used as the upper level scan signal of the M-1 level GOA unit; the second start signal is connected to For the M-th level GOA unit, the second start signal is used as the upper-level scan signal of the M-th level GOA unit.
  • the GOA circuits are sequentially activated from the last stage GOA cell to the first stage GOA cell.
  • the GOA circuits are sequentially activated from the last-level GOA unit to the second-level GOA unit.
  • the 8k+1 stage clock signal and the first clock signal ck1 are the same signal
  • the 8k+2 stage clock signal and the second clock signal ck2 are the same signal
  • the 8k+3 stage clock signal and the third clock signal are the same signal.
  • the signal ck3 is the same signal
  • the 8k+4th clock signal and the fourth clock signal ck4 are the same signal
  • the 8k+5th clock signal and the fifth clock signal ck5 are the same signal
  • the 8k+6th clock signal and the sixth clock signal are the same signal.
  • the clock signal ck6 is the same signal
  • the 8k+7th clock signal and the seventh clock signal ck7 are the same signal
  • the 8k+8th clock signal and the eighth clock signal ck8 are the same signal, wherein k is greater than or equal to 0, and k is an integer.
  • FIG. 2 is a schematic structural diagram of an nth-level GOA unit in a GOA circuit provided by an embodiment of the present application.
  • the nth level GOA unit may be the remaining GOA units except the first level GOA unit and the last level GOA unit among the odd-numbered level units arranged in multiple cascades.
  • the nth-level GOA unit may also be the remaining GOA units except the second-level GOA unit and the last-level GOA unit among the even-numbered units arranged in multiple cascades.
  • the nth-level GOA unit includes a node control module 101, a pull-up module 102, a pull-down module 103, a pull-down maintenance module 104, and a stop control module 105, 1 ⁇ n ⁇ N-1, n , N are positive integers, N represents the number of cascaded GOA units.
  • the node control module 101 is connected to the previous-level scan signal G(n-2), the next-level scan signal G(n+2), the first scan control signal U2D, the second scan control signal D2U and the constant voltage low voltage
  • the level signal VGL is electrically connected to the first node Q and the second node P, and the node control module 101 is used for the scanning signal G(n-2) of the previous stage, the scanning signal G(n+2) of the next stage,
  • the first scan control signal U2D, the second scan control signal D2U and the constant voltage low level signal VGL pull up the potential of the first node Q and pull down the potential of the second node P.
  • the pull-up module 102 is connected to the clock signal CK(n) of the current stage and the constant-voltage high-level signal VGH, and is electrically connected to the first node Q, and the pull-up module 102 is used for according to the clock signal CK(n) of the current stage. , the constant-voltage high-level signal VGH and the potential of the first node Q output the current-stage scan signal at the current-stage scan signal output terminal G(n).
  • the pull-down module 103 is connected to the constant-voltage low-level signal VGL and is electrically connected to the second node P, and the pull-down module 103 is used for pulling down the potential of the scan signal output terminal according to the potential of the second node P.
  • the pull-down maintaining module 104 is connected to the previous-stage clock signal CK(n-2), the next-stage clock signal CK(n+2), the first scan control signal U2D, the second scan control signal D2U, the constant voltage low voltage The level signal VGL and the constant voltage high level signal VGH are electrically connected to the first node Q and the second node P.
  • the pull-down maintaining module 104 is used for the clock signal CK(n-2) of the previous stage, the clock signal CK(n+2) of the next stage, the first scan control signal U2D, the second scan control signal D2U, the constant voltage low level The signal VGL and the constant-voltage high-level signal VGH pull down the potential of the first node Q and pull up the potential of the second node P.
  • the pause control module 105 is connected to the pause control signal Gas2, and the pause control module 105 is used to pull down the scanning signal output terminal G (n ) of the potential; the pull-down maintaining module 104 is also used for suppressing the leakage of the first node Q during the touch pause period.
  • the pull-down maintaining module 104 suppresses the leakage of the first node Q when the GOA circuit is in the touch pause stage, so that the GOA circuit can easily generate leakage during long-term use, thereby making the GOA circuit ineffective. technical issues.
  • FIG. 3 is a schematic circuit diagram of an nth-level GOA unit in a GOA circuit provided by an embodiment of the present application.
  • the nth-level GOA unit is described in detail with reference to FIG. 1 , FIG. 2 , and FIG. 3 .
  • the node control module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2.
  • the gate of the first transistor T1 is connected to the previous-level scan signal G(n-2), the source of the first transistor T1 is connected to the first scan control signal U2D, and the drain of the first transistor T1 is electrically connected to the first scan control signal U2D.
  • the gate of the second transistor T2 is connected to the next-level scan signal G(n+2), the source of the second transistor T2 is connected to the second scan control signal D2U, and the drain of the second transistor T2 is electrically connected to the first Node Q.
  • the gate of the third transistor T3 is electrically connected to the first node Q, the source of the third transistor T3 is connected to the constant voltage low level signal VGL, and the drain of the third transistor T3 is electrically connected to the second node P.
  • the first terminal of the first capacitor C1 is electrically connected to the first node Q, and the second terminal of the first capacitor C1 is connected to the constant voltage low level signal VGL.
  • the first terminal of the second capacitor C2 is electrically connected to the second node P, and the second terminal of the second capacitor C2 is connected to the constant voltage low level signal VGL.
  • the pull-up module 102 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is connected to the constant voltage high level signal VGH
  • the source of the fourth transistor T4 is electrically connected to the first node Q
  • the drain of the fourth transistor T4 is electrically connected to the gate of the fifth transistor T5 connect.
  • the source of the fifth transistor T5 is connected to the clock signal CK(n) of the current stage
  • the drain of the fifth transistor T5 is electrically connected to the scan signal output terminal G(n) of the current stage.
  • the pull-down module 103 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is electrically connected to the second node P, the source of the sixth transistor T6 is connected to the constant voltage low-level signal VGL, and the drain of the sixth transistor T6 is electrically connected to the scanning signal output terminal of the current stage G(n).
  • the pull-down sustain module 104 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11.
  • the gate of the seventh transistor T7 is connected to the first scan control signal U2D
  • the source of the seventh transistor T7 is connected to the next-level clock signal CK(n+2)
  • the drain of the seventh transistor T7 is electrically connected to the eighth The drain of the transistor T8 and the gate of the ninth transistor T9.
  • the gate of the eighth transistor T8 is connected to the second scan control signal D2U
  • the source of the eighth transistor T8 is connected to the upper-stage clock signal CK(n-2).
  • the source of the ninth transistor T9 is connected to the constant voltage high level signal VGH, and the drain of the ninth transistor T9 is electrically connected to the second node P.
  • the gate of the tenth transistor T10 is electrically connected to the drain of the eleventh transistor T11, the source of the tenth transistor T10 is connected to the constant voltage low level signal VGL, and the drain of the tenth transistor T10 is electrically connected to the first transistor T10. Node Q.
  • the gate of the eleventh transistor T11 is connected to the ground terminal GND, and the source of the eleventh transistor T11 is electrically connected to the second node P.
  • the potential of the source of the eleventh transistor T11 is the potential of the constant-voltage high-level signal VGH
  • the gate of the eleventh transistor T11 The potential of the pole is the potential of the ground terminal GND.
  • the eleventh transistor T11 is in a saturated state, and the eleventh transistor T11 is turned off.
  • the potential of the drain of the eleventh transistor T11 is the difference between the potential of the ground terminal GND and the threshold voltage of the eleventh transistor T11 pressure difference between.
  • the potential of the gate of the tenth transistor T10 is the voltage difference between the potential of the ground terminal GND and the threshold voltage of the eleventh transistor T11. Therefore, the voltage difference between the potential of the gate of the tenth transistor T10 and the potential of the drain of the tenth transistor T10 is smaller than the voltage difference between the constant voltage high potential and the constant voltage low potential.
  • the embodiment of the present application provides an eleventh transistor T11 between the gate of the tenth transistor T10 and the second node P, and the eleventh transistor T11 has a The gate is electrically connected to the ground terminal GND, thereby reducing the negative drift of the tenth transistor T10 and the increasing tendency of off-state current, thereby suppressing the leakage of the first node Q when the GOA circuit is in the touch pause phase.
  • the shutdown control module includes a twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to the stop control signal Gas2, the source of the twelfth transistor T12 is connected to the constant voltage low level signal VGL, and the drain of the twelfth transistor T12 is electrically connected to the scanning signal of the current stage Output G(n).
  • the GOA circuit when the GOA circuit is in the touch pause stage, the potential of the pause control signal Gas2 is high, the twelfth transistor T12 is turned on under the control of the pause control signal Gas2, and the constant-voltage low-level signal VGL passes through the The twelve transistors T12 are output to the scanning signal output terminal G(n) of this stage, so that the GOA circuit realizes the function of suspending scanning during the display period.
  • the third transistor T3 is turned on under the control of the potential of the first node Q, and the constant-voltage low-level signal VGL is output to the second node P through the third transistor T3, so that The potential of the second node P is at a low potential, so that the eleventh transistor T11 is turned on and the tenth transistor T10 is turned off. Since the negative drift of the tenth transistor T10 and the increasing tendency of the off-state current are weakened, the leakage of the first node Q can be suppressed when the GOA circuit is in the touch pause phase.
  • FIG. 4 is a schematic time sequence diagram of the nth-level GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the first scan control signal U2D is a constant voltage high level signal VGH
  • the second scan control signal D2U is a constant voltage low level signal VGL.
  • the first scan control signal U2D is a constant voltage low level signal VGL
  • the second scan control signal D2U is a constant voltage high level signal VGH.
  • the first transistor T1 is turned on under the control of the previous-stage scan signal G(n-2), and the first scan control signal U2D passes through the first transistor T1 charges the first capacitor C1 so that the potential of the first node Q is a high potential. Since the potential of the first node Q is at a high potential, the third transistor T3 is turned on under the control of the potential of the first node Q, and the constant-voltage low-level signal VGL charges the second node P through the third transistor T3, so that the second node P is charged. The potential of the node P is a low potential. Since the potential of the second node P is at a low potential, the sixth transistor T6 is turned off under the control of the potential of the second node P.
  • the potential of the clock signal CK(n+2) of the next stage is a low potential
  • the potential of the clock signal CK(n) of the present stage is a low potential
  • the seventh transistor T7 is turned on under the control of the first scan control signal U2D, and the potential of the next-stage clock signal CK(n+2) is output to the gate of the ninth transistor T9 through the seventh transistor T7, so that the ninth transistor T9 is turned off .
  • the fourth transistor T4 is turned on under the control of the constant voltage high level signal VGH, and the potential of the first node Q is output to the gate of the fifth transistor T5 through the fourth transistor T4, so that the fifth transistor T5 is turned on.
  • the clock signal CK(n) of the current stage is output to the scanning signal output terminal G(n) of the current stage through the fifth transistor T5, so that the potential of the scanning signal output terminal G(n) of the current stage is a low potential.
  • the potential of the previous stage scan signal G(n-2) changes from high potential to low potential
  • the current stage clock signal CK(n) changes from low potential to high potential.
  • the first transistor T1 is turned off under the control of the previous-stage scan signal G(n-2).
  • the potential of the first node Q is a high potential
  • the potential of the second node P is a low potential.
  • the fourth transistor T4 is turned on under the control of the constant voltage high level signal VGH, and the potential of the first node Q is output to the gate of the fifth transistor T5 through the fourth transistor T4, so that the fifth transistor T5 is turned on.
  • the clock signal CK(n) of the current stage is output to the scanning signal output terminal G(n) of the current stage through the fifth transistor T5, thereby outputting the scanning signal of the current stage. Since the potential of the second node P is at a low potential, the sixth transistor T6 is turned off under the control of the potential of the second node P.
  • the potential of the next-stage clock signal CK(n+2) is still at a low potential
  • the seventh transistor T7 is turned on under the control of the first scan control signal U2D
  • the next-stage clock signal CK(n+2) has a low potential.
  • the potential is output to the gate of the ninth transistor T9 through the seventh transistor T7, so that the ninth transistor T9 is turned off.
  • the potential of the next stage clock signal CK(n+2) changes from low potential to high potential
  • the seventh transistor T7 is turned on under the control of the first scan control signal U2D
  • the next stage clock signal CK(n+2) The potential of t is output to the gate of the ninth transistor T9 through the seventh transistor T7, so that the ninth transistor T9 is turned on.
  • the constant-voltage high-level signal VGH is output to the second node P through the ninth transistor T9, so that the potential of the second node P is at a high potential.
  • the sixth transistor T6 is turned on under the control of the potential of the second node P, and the constant voltage low level signal VGL is output to the scanning signal output terminal G(n) of the current stage through the sixth transistor T6, thereby pulling down the potential of the scanning signal of the current stage.
  • the potential of the source of the eleventh transistor T11 is a high potential
  • the potential of the gate terminal of the eleventh transistor T11 is the potential of the ground terminal GND, so that the eleventh transistor T11 is turned off.
  • the potential of the drain of the eleventh transistor T11 is the voltage difference between the potential of the ground terminal GND and the threshold voltage of the eleventh transistor T11.
  • the tenth transistor T10 is turned on under the control of the potential of the drain of the eleventh transistor T11, and the constant-voltage low-level signal VGL is output to the first node Q through the tenth transistor T10, thereby pulling down the potential of the first node Q.
  • the eleventh transistor T11 is arranged between the gate of the tenth transistor T10 and the second node P, and the first The gate of the eleventh transistor T11 is electrically connected to the ground terminal GND, thereby reducing the negative drift and increasing off-state current of the tenth transistor T10 , thereby suppressing the leakage of the first node Q when the GOA circuit is in the touch pause phase.
  • the GOA circuit When the GOA circuit is in the touch stop stage, the potential of the stop control signal Gas2 is high, the twelfth transistor T12 is turned on under the control of the stop control signal Gas2, and the constant voltage low level signal VGL is passed through the twelfth transistor. T12 is output to the scanning signal output terminal G(n) of this stage, so that the GOA circuit can realize the pause scanning function during the display period.
  • the third transistor T3 is turned on under the control of the potential of the first node Q, and the constant-voltage low-level signal VGL is output to the second node P through the third transistor T3, so that The potential of the second node P is at a low potential, so that the eleventh transistor T11 is turned on and the tenth transistor T10 is turned off. Since the negative drift of the tenth transistor T10 and the increasing tendency of the off-state current are weakened, the leakage of the first node Q can be suppressed when the GOA circuit is in the touch pause phase.
  • FIG. 5 is another schematic circuit diagram of the nth-level GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the difference between the nth level GOA unit shown in FIG. 5 and the nth level GOA unit shown in FIG. 3 is that the nth level GOA unit shown in FIG. 5 further includes a thirteenth transistor T13 and a fourteenth transistor T14 and the fifteenth transistor T15.
  • the gate of the thirteenth transistor T13, the source of the thirteenth transistor T13, the gate of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 are all connected to the discharge control signal Gas1, and the drain of the thirteenth transistor T13 The pole is electrically connected to the scanning signal output terminal G(n) of this stage.
  • the source of the fourteenth transistor T14 is connected to the constant voltage low level signal VGL, and the drain of the fourteenth transistor T14 is electrically connected to the second node P.
  • the source of the fifteenth transistor T15 is connected to the constant voltage low level signal VGL, and the drain of the fifteenth transistor T15 is electrically connected to the pull-down maintaining module 104 . Specifically, the drain of the fifteenth transistor T15, the drain of the seventh transistor, and the drain of the eighth transistor are electrically connected.
  • the thirteenth transistor T13 , the fourteenth transistor T14 and the fifteenth transistor T15 are turned on under the control of the discharge control signal Gas1 , and the discharge control signal Gas1 is output to the present through the thirteenth transistor T13
  • the stage scan signal output terminal G(n) the constant voltage low level signal VGL is output to the first node Q through the fourteenth transistor T14, and the constant voltage low level signal VGL is output to the ninth transistor T9 through the fifteenth transistor T15. gate, so that the scanning signal output terminal G(n) of this stage is at a high potential.
  • the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 can be set in each GOA unit, so that the scan lines on the display panel can be connected to each other through the discharge control signal Gas1.
  • the scan signal is input, and then the display panel can be discharged.

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Abstract

一种GOA电路，包括N级级联设置的GOA单元，第n级GOA单元包括节点控制模块（101）、上拉模块（102）、下拉模块（103）、下拉维持模块（104）以及中停控制模块（105），1＜n＜N-1，n、N均为正整数。

Description

GOA电路及显示面板 技术领域
本申请涉及显示领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA(Gate Driver on Array，集成栅极驱动电路)技术是利用现有薄膜晶体管阵列制程将栅极驱动电路制作在阵列基板上，实现对扫描线逐行扫描的一项技术。然而，现有的GOA电路长期在高温高湿环境下工作时，薄膜晶体管极易产生漏电，进而导致GOA电路失效。
 技术问题
本申请提供一种GOA电路及显示面板，可以解决GOA电路长期使用时极易产生漏电，进而使得GOA电路失效的技术问题。
 技术解决方案
第一方面，本申请提供一种GOA电路，其包括N级级联设置的GOA单元，第n级GOA单元包括节点控制模块、上拉模块、下拉模块、下拉维持模块以及中停控制模块，1<n<N-1，n、N均为正整数；
所述节点控制模块接入上一级扫描信号、下一级扫描信号、第一扫描控制信号以及第二扫描控制信号，并电性连接于第一节点以及第二节点，所述节点控制模块用于根据所述上一级扫描信号、所述下一级扫描信号、所述第一扫描控制信号以及所述第二扫描控制信号，拉高所述第一节点的电位以及拉低所述第二节点的电位；
所述上拉模块接入本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于根据所述本级时钟信号以及所述第一节点的电位在本级扫描信号输出端输出本级扫描信号；
所述下拉模块电性连接于所述第二节点，所述下拉模块用于根据所述第二节点的电位下拉所述扫描信号输出端的电位；
所述下拉维持模块接入上一级时钟信号、下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，并电性连接于所述第一节点以及所述第二节点，所述下拉维持模块用于根据所述上一级时钟信号、所述下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，拉低所述第一节点的电位以及拉高所述第二节点的电位；
所述中停控制模块接入中停控制信号，所述中停控制模块用于在所述GOA电路处于触控中停阶段时，基于所述中停控制信号拉低所述本级扫描信号输出端的电位；所述下拉维持模块还用于在所述触控中停阶段抑制所述第一节点漏电。
在本申请提供的GOA电路中，所述节点控制模块包括第一晶体管、第二晶体管、第三晶体管、第一电容以及第二电容；
所述第一晶体管的栅极接入所述上一级扫描信号，所述第一晶体管的源极接入第一扫描控制信号，所述第一晶体管的漏极电性连接于所述第一节点；
所述第二晶体管的栅极接入所述下一级扫描信号，所述第二晶体管的源极接入第二扫描控制信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极接入恒压低电平信号，所述第三晶体管的漏极电性连接于所述第二节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端接入所述恒压低电平信号；
所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端接入所述恒压低电平信号。
在本申请提供的GOA电路中，所述上拉模块包括第四晶体管以及第五晶体管；
所述第四晶体管的栅极接入恒压高电平信号，所述第四晶体管的源极电性连接于所述第一节点，所述第四晶体管的漏极与所述第五晶体管的栅极电性连接；
所述第五晶体管的源极接入所述本级时钟信号，所述第五晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供的GOA电路中，所述下拉模块包括第六晶体管；
所述第六晶体管的栅极电性连接于所述第二节点，所述第六晶体管的源极接入恒压低电平信号，所述第六晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供的GOA电路中，所述下拉维持模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
所述第七晶体管的栅极接入所述第一扫描控制信号，所述第七晶体管的源极接入所述下一级时钟信号，所述第七晶体管的漏极电性连接于所述第八晶体管的漏极以及所述第九晶体管的栅极；
所述第八晶体管的栅极接入所述第二扫描控制信号，所述第八晶体管的源极接入所述上一级时钟信号；
所述第九晶体管的源极接入恒压高电平信号，所述第九晶体管的漏极电性连接于所述第二节点；
所述第十晶体管的栅极电性连接于所述第十一晶体管的漏极，所述第十晶体管的源极接入恒压低电平信号，所述第十晶体管的漏极电性连接于所述第一节点；
所述第十一晶体管的栅极连接于接地端，所述第十一晶体管的源极电性连接于所述第二节点。
在本申请提供的GOA电路中，当所述第二节点的电位为所述恒压高电平信号的电位时，所述第十一晶体管关闭，所述第十一晶体管的漏极的电位为所述接地端的电位与所述第十一晶体管的阈值电压之间的压差。
在本申请提供的GOA电路中，所述第十晶体管的栅极的电位与所述第十晶体管的漏极的电位之间的压差小于所述恒压高电位与所述恒压低电位的压差。
在本申请提供的GOA电路中，所述中停控制模块包括第十二晶体管；
所述第十二晶体管的栅极接入所述中停控制信号，所述第十二晶体管的源极接入恒压低电平信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供的GOA电路中，所述GOA电路还包括第十三晶体管、第十四晶体管以及第十五晶体管；
所述第十三晶体管的栅极、所述第十三晶体管的源极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极均接入放电控制信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号输出端；
所述第十四晶体管的源极接入恒压低电平信号，所述第十四晶体管的漏极电性连接于所述第二节点；
所述第十五晶体管的源极接入所述恒压低电平信号，所述第十五晶体管的漏极电性连接于所述下拉维持模块。
第二方面，本申请还提供一种显示面板，其包括GOA电路，所述GOA电路包括N级级联设置的GOA单元，第n级GOA单元包括节点控制模块、上拉模块、下拉模块、下拉维持模块以及中停控制模块，1<n<N-1，n、N均为正整数；
所述节点控制模块接入上一级扫描信号、下一级扫描信号、第一扫描控制信号以及第二扫描控制信号，并电性连接于第一节点以及第二节点，所述节点控制模块用于根据所述上一级扫描信号、所述下一级扫描信号、所述第一扫描控制信号以及、所述第二扫描控制信号，拉高所述第一节点的电位以及拉低所述第二节点的电位；
所述上拉模块接入本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于根据所述本级时钟信号以及所述第一节点的电位在本级扫描信号输出端输出本级扫描信号；
所述下拉模块电性连接于所述第二节点，所述下拉模块用于根据所述第二节点的电位下拉所述扫描信号输出端的电位；
所述下拉维持模块接入上一级时钟信号、下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，并电性连接于所述第一节点以及所述第二节点，所述下拉维持模块用于根据所述上一级时钟信号、所述下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，拉低所述第一节点的电位以及拉高所述第二节点的电位；
所述中停控制模块接入中停控制信号，所述中停控制模块用于在所述GOA电路处于触控中停阶段时，基于所述中停控制信号拉低所述本级扫描信号输出端的电位；所述下拉维持模块还用于在所述触控中停阶段抑制所述第一节点漏电。
在本申请提供述的显示面板中，所述节点控制模块包括第一晶体管、第二晶体管、第三晶体管、第一电容以及第二电容；
所述第一晶体管的栅极接入所述上一级扫描信号，所述第一晶体管的源极接入第一扫描控制信号，所述第一晶体管的漏极电性连接于所述第一节点；
所述第二晶体管的栅极接入所述下一级扫描信号，所述第二晶体管的源极接入第二扫描控制信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极接入恒压低电平信号，所述第三晶体管的漏极电性连接于所述第二节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端接入所述恒压低电平信号；
所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端接入所述恒压低电平信号。
在本申请提供述的显示面板中，所述上拉模块包括第四晶体管以及第五晶体管；
所述第四晶体管的栅极接入恒压高电平信号，所述第四晶体管的源极电性连接于所述第一节点，所述第四晶体管的漏极与所述第五晶体管的栅极电性连接；
所述第五晶体管的源极接入所述本级时钟信号，所述第五晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供述的显示面板中，所述下拉模块包括第六晶体管；
所述第六晶体管的栅极电性连接于所述第二节点，所述第六晶体管的源极接入恒压低电平信号，所述第六晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供述的显示面板中，所述下拉维持模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
所述第七晶体管的栅极接入所述第一扫描控制信号，所述第七晶体管的源极接入所述下一级时钟信号，所述第七晶体管的漏极电性连接于所述第八晶体管的漏极以及所述第九晶体管的栅极；
所述第八晶体管的栅极接入所述第二扫描控制信号，所述第八晶体管的源极接入所述上一级时钟信号；
所述第九晶体管的源极接入恒压高电平信号，所述第九晶体管的漏极电性连接于所述第二节点；
所述第十晶体管的栅极电性连接于所述第十一晶体管的漏极，所述第十晶体管的源极接入恒压低电平信号，所述第十晶体管的漏极电性连接于所述第一节点；
所述第十一晶体管的栅极连接于接地端，所述第十一晶体管的源极电性连接于所述第二节点。
在本申请提供述的显示面板中，当所述第二节点的电位为所述恒压高电平信号的电位时，所述第十一晶体管关闭，所述第十一晶体管的漏极的电位为所述接地端的电位与所述第十一晶体管的阈值电压之间的压差。
在本申请提供述的显示面板中，所述第十晶体管的栅极的电位与所述第十晶体管的漏极的电位之间的压差小于所述恒压高电位与所述恒压低电位的压差。
在本申请提供述的显示面板中，所述中停控制模块包括第十二晶体管；
所述第十二晶体管的栅极接入所述中停控制信号，所述第十二晶体管的源极接入恒压低电平信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请提供述的显示面板中，所述GOA电路还包括第十三晶体管、第十四晶体管以及第十五晶体管；
所述第十三晶体管的栅极、所述第十三晶体管的源极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极均接入放电控制信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号输出端；
所述第十四晶体管的源极接入恒压低电平信号，所述第十四晶体管的漏极电性连接于所述第二节点；
所述第十五晶体管的源极接入所述恒压低电平信号，所述第十五晶体管的漏极电性连接于所述下拉维持模块。
 有益效果
本申请提供的GOA电路及显示面板，在GOA电路中，通过在第十晶体管的栅极和第二节点之间设置第十一晶体管，且第十一晶体管的栅极电性连接于接地端，从而减弱第十晶体管负漂以及关态电流增加的趋势，进而在GOA电路处于触控中停阶段时，抑制第一节点漏电。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的结构示意图；
图2为本申请实施例提供的GOA电路中的第n级GOA单元的结构示意图；
图3为本申请实施例提供的GOA电路中的第n级GOA单元的电路示意图；
图4为本申请实施例提供的GOA电路中的第n级GOA单元的时序示意图；
图5为本申请实施例提供的GOA电路中的第n级GOA单元的另一电路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。
请参阅图1，图1为本申请实施例提供的显示面板的结构示意图。如图1所示，本申请实施例提供的显示面板100包括显示区域10以及设置在显示区域10外的GOA电路区域20。显示区域10上设置有多条扫描线、多条数据线以及多条扫描线与多条数据线交叉限定的多个子像素单元。GOA电路区域20上设置有GOA电路，GOA电路包括多级GOA单元，多级GOA单元与多条扫描线一一对应连接；即，GOA单元的数量与扫描线的数量相等。
其中，GOA电路可以包括多个级联设置的奇数级GOA单元以及多个级联设置的偶数级GOA单元。多个级联设置的奇数级GOA单元设置在显示区域10的一侧，多个级联设置的偶数级GOA单元设置在显示区域10的另一侧。比如，GOA电路包括M级GOA单元，M为正整数。当M为偶数时，第1级GOA单元、第3级GOA单元、第5级GOA单元、……、第M-1级GOA单元级联设置。第2级GOA单元、第4级GOA单元、第6级GOA单元、……、第M级GOA单元级联设置。
在本申请实施例中，GOA电路包括N级级联设置的GOA单元。在一些实施方式中，N级级联设置的GOA单元可以为多个级联设置的奇数级GOA单元，也可以为多个级联设置的偶数级GOA单元。
在本申请实施例中，GOA电路接入第一时钟信号ck1、第二时钟信号ck2、第三时钟信号ck3、第四时钟信号ck4、第五时钟信号ck5、第六时钟信号ck6、第七时钟信号ck7、第八时钟信号ck8、第一起始信号STV1以及第二起始信号STV2。具体的，多个级联设置的奇数级GOA单元接入第一时钟信号ck1、第三时钟信号ck3、第五时钟信号ck5、第七时钟信号ck7以及第一起始信号STV1。多个级联设置的偶数级GOA单元接入第二时钟信号ck2、第四时钟信号ck4、第六时钟信号ck6、第八时钟信号ck8以及第二起始信号STV2。
需要说明的是，本申请实施例提供的GOA电路可以采用正向扫描模式或者反向扫描模式。当GOA电路采用正向扫描模式时，第一起始信号接入第一级GOA单元，第一起始信号作为第一级GOA单元的上一级扫描信号；第二起始信号接入第二级GOA单元，第二起始信号作为第二级GOA单元的上一级扫描信号。在多个级联设置的奇数级GOA单元中，GOA电路从第1级GOA单元至最后一级GOA单元依次启动。在多个级联设置的偶数级GOA单元中，GOA电路从第2级GOA单元至最后一级GOA单元依次启动。
当GOA电路采用反向扫描模式时，第一起始信号接入第M-1级GOA单元，第一起始信号作为第M-1级GOA单元的上一级扫描信号；第二起始信号接入第M级GOA单元，第二起始信号作为第M级GOA单元的上一级扫描信号。在多个级联设置的奇数级GOA单元中，GOA电路从最后一级GOA单元至第1级GOA单元依次启动。在多个级联设置的偶数级GOA单元中，GOA电路从最后一级GOA单元至第2级GOA单元依次启动。
需要说明的是，第8k+1级时钟信号与第一时钟信号ck1为同一信号，第8k+2级时钟信号与第二时钟信号ck2为同一信号，第8k+3级时钟信号与第三时钟信号ck3为同一信号，第8k+4级时钟信号与第四时钟信号ck4为同一信号，第8k+5级时钟信号与第五时钟信号ck5为同一信号，第8k+6级时钟信号与第六时钟信号ck6为同一信号，第8k+7级时钟信号与第七时钟信号ck7为同一信号，第8k+8级时钟信号与第八时钟信号ck8为同一信号，其中，k大于等于0，且k为整数。
请参阅图1、图2，图2为本申请实施例提供的GOA电路中的第n级GOA单元的结构示意图。结合图1、图2所示，第n级GOA单元可以为多个级联设置的奇数级单元中除第1级GOA单元以及最后一级GOA单元之外的其余GOA单元。第n级GOA单元也可以为多个级联设置的偶数级单元中除第2级GOA单元以及最后一级GOA单元之外的其余GOA单元。
具体的，在本申请实施例中，第n级GOA单元包括节点控制模块101、上拉模块102、下拉模块103、下拉维持模块104以及中停控制模块105，1<n<N-1，n、N均为正整数，N表示GOA单元的级联数量。
其中，节点控制模块101接入上一级扫描信号G（n-2）、下一级扫描信号G（n+2）、第一扫描控制信号U2D、第二扫描控制信号D2U以及恒压低电平信号VGL，并电性连接于第一节点Q以及第二节点P，节点控制模块101用于根据上一级扫描信号G（n-2）、下一级扫描信号G（n+2）、第一扫描控制信号U2D、第二扫描控制信号D2U以及恒压低电平信号VGL，拉高第一节点Q的电位以及拉低第二节点P的电位。
其中，上拉模块102接入本级时钟信号CK（n）以及恒压高电平信号VGH，并电性连接于第一节点Q，上拉模块102用于根据本级时钟信号CK（n）、恒压高电平信号VGH以及第一节点Q的电位在本级扫描信号输出端G（n）输出本级扫描信号。
其中，下拉模块103接入恒压低电平信号VGL，并电性连接于第二节点P，下拉模块103用于根据第二节点P的电位下拉扫描信号输出端的电位。
其中，下拉维持模块104接入上一级时钟信号CK（n-2）、下一级时钟信号CK（n+2）、第一扫描控制信号U2D、第二扫描控制信号D2U、恒压低电平信号VGL以及恒压高电平信号VGH，并电性连接于第一节点Q以及第二节点P。下拉维持模块104用于根据上一级时钟信号CK（n-2）、下一级时钟信号CK（n+2）、第一扫描控制信号U2D、第二扫描控制信号D2U、恒压低电平信号VGL以及恒压高电平信号VGH，拉低第一节点Q的电位以及拉高第二节点P的电位。
其中，中停控制模块105接入中停控制信号Gas2，中停控制模块105用于在GOA电路处于触控中停阶段时，基于中停控制信号Gas2拉低本级扫描信号输出端G（n）的电位；下拉维持模块104还用于在触控中停期间抑制第一节点Q漏电。
本申请实施例提供的GOA电路，通过下拉维持模块104在GOA电路处于触控中停阶段时，抑制第一节点Q漏电，从而可以解决GOA电路长期使用时极易产生漏电，进而使得GOA电路失效的技术问题。
请参阅图1、图2、图3，图3为本申请实施例提供的GOA电路中的第n级GOA单元的电路示意图。结合图1、图2、图3所示对第n级GOA单元进行详细介绍。
在一些实施例中，节点控制模块101包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1以及第二电容C2。第一晶体管T1的栅极接入上一级扫描信号G（n-2），第一晶体管T1的源极接入第一扫描控制信号U2D，第一晶体管T1的漏极电性连接于第一节点Q。第二晶体管T2的栅极接入下一级扫描信号G（n+2），第二晶体管T2的源极接入第二扫描控制信号D2U，第二晶体管T2的漏极电性连接于第一节点Q。第三晶体管T3的栅极电性连接于第一节点Q，第三晶体管T3的源极接入恒压低电平信号VGL，第三晶体管T3的漏极电性连接于第二节点P。第一电容C1的第一端电性连接于第一节点Q，第一电容C1的第二端接入恒压低电平信号VGL。第二电容C2的第一端电性连接于第二节点P，第二电容C2的第二端接入恒压低电平信号VGL。
在一些实施例中，上拉模块102包括第四晶体管T4以及第五晶体管T5。第四晶体管T4的栅极接入恒压高电平信号VGH，第四晶体管T4的源极电性连接于第一节点Q，第四晶体管T4的漏极与第五晶体管T5的栅极电性连接。第五晶体管T5的源极接入本级时钟信号CK（n），第五晶体管T5的漏极电性连接于本级扫描信号输出端G（n）。
在一些实施例中，下拉模块103包括第六晶体管T6。第六晶体管T6的栅极电性连接于第二节点P，第六晶体管T6的源极接入恒压低电平信号VGL，第六晶体管T6的漏极电性连接于本级扫描信号输出端G（n）。
在一些实施例中，下拉维持模块104包括第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10以及第十一晶体管T11。第七晶体管T7的栅极接入第一扫描控制信号U2D，第七晶体管T7的源极接入下一级时钟信号CK（n+2），第七晶体管T7的漏极电性连接于第八晶体管T8的漏极以及第九晶体管T9的栅极。第八晶体管T8的栅极接入第二扫描控制信号D2U，第八晶体管T8的源极接入上一级时钟信号CK（n-2）。第九晶体管T9的源极接入恒压高电平信号VGH，第九晶体管T9的漏极电性连接于第二节点P。第十晶体管T10的栅极电性连接于第十一晶体管T11的漏极，第十晶体管T10的源极接入恒压低电平信号VGL，第十晶体管T10的漏极电性连接于第一节点Q。第十一晶体管T11的栅极连接于接地端GND，第十一晶体管T11的源极电性连接于第二节点P。
特别的，当第二节点P的电位为恒压高电平信号VGH的电位时，第十一晶体管T11的源极的电位为恒压高电平信号VGH的电位，第十一晶体管T11的栅极的电位为接地端GND的电位。此时，第十一晶体管T11处于饱和状态，第十一晶体管T11关闭，根据晶体管的特性，第十一晶体管T11的漏极的电位为接地端GND的电位与第十一晶体管T11的阈值电压之间的压差。也即，第十晶体管T10的栅极的电位为接地端GND的电位与第十一晶体管T11的阈值电压之间的压差。从而，第十晶体管T10的栅极的电位与第十晶体管T10的漏极的电位之间的压差小于恒压高电位与恒压低电位的压差。
相较于现有技术将晶体管的栅极和节点直接连接，本申请实施例通过在第十晶体管T10的栅极和第二节点P之间设置第十一晶体管T11，且第十一晶体管T11的栅极电性连接于接地端GND，从而减弱第十晶体管T10负漂以及关态电流增加的趋势，进而在GOA电路处于触控中停阶段时，抑制第一节点Q漏电。
在一些实施例中，中停控制模块包括第十二晶体管T12。第十二晶体管T12的栅极接入中停控制信号Gas2，第十二晶体管T12的源极接入恒压低电平信号VGL，第十二晶体管T12的漏极电性连接于本级扫描信号输出端G（n）。
特别的，当GOA电路处于触控中停阶段时，中停控制信号Gas2的电位为高电位，第十二晶体管T12在中停控制信号Gas2的控制下打开，恒压低电平信号VGL经第十二晶体管T12输出至本级扫描信号输出端G（n），从而使得GOA电路在显示期间实现暂停扫描功能。与此同时，由于第一节点Q的电位为高电位，第三晶体管T3在第一节点Q的电位控制下打开，恒压低电平信号VGL经第三晶体管T3输出至第二节点P，使得第二节点P的电位为低电位，进而使得第十一晶体管T11打开，第十晶体管T10关闭。由于第十晶体管T10负漂以及关态电流增加的趋势减弱，从而可以在GOA电路处于触控中停阶段时，抑制第一节点Q漏电。
下面以GOA电路处于正向扫描模式为例进行说明。请参阅图3、图4，图4为本申请实施例提供的GOA电路中的第n级GOA单元的时序示意图。
结合图3、图4所示，当GOA电路处于正向扫描模式时，第一扫描控制信号U2D为恒压高电平信号VGH，第二扫描控制信号D2U为恒压低电平信号VGL。当GOA电路处于反向扫描模式时，第一扫描控制信号U2D为恒压低电平信号VGL，第二扫描控制信号D2U为恒压高电平信号VGH。
首先，当上一级扫描信号G（n-2）为高电位时，第一晶体管T1在上一级扫描信号G（n-2）的控制下打开，第一扫描控制信号U2D经第一晶体管T1对第一电容C1进行充电，使得第一节点Q的电位为高电位。由于第一节点Q的电位为高电位，第三晶体管T3在第一节点Q的电位的控制下打开，恒压低电平信号VGL经第三晶体管T3对第二节点P进行充电，使得第二节点P的电位为低电位。由于第二节点P的电位为低电位，第六晶体管T6在第二节点P的电位控制下关闭。
与此同时，下一级时钟信号CK（n+2）的电位为低电位，本级时钟信号CK（n）的电位为低电位。第七晶体管T7在第一扫描控制信号U2D的控制下打开，下一级时钟信号CK（n+2）的电位经第七晶体管T7输出至第九晶体管T9的栅极，使得第九晶体管T9关闭。第四晶体管T4在恒压高电平信号VGH的控制下打开，第一节点Q的电位经第四晶体管T4输出至第五晶体管T5的栅极，使得第五晶体管T5打开。本级时钟信号CK（n）经第五晶体管T5输出至本级扫描信号输出端G（n），使得本级扫描信号输出端G（n）的电位为低电位。
随后，上一级扫描信号G（n-2）的电位由高电位转为低电位，本级时钟信号CK（n）由低电位转为高电位。第一晶体管T1在上一级扫描信号G（n-2）的控制下关闭。此时，由于第一电容C1、第二电容C2的存储作用，使得第一节点Q的电位为高电位，第二节点P的电位为低电位。第四晶体管T4在恒压高电平信号VGH的控制下打开，第一节点Q的电位经第四晶体管T4输出至第五晶体管T5的栅极，使得第五晶体管T5打开。本级时钟信号CK（n）经第五晶体管T5输出至本级扫描信号输出端G（n），进而输出本级扫描信号。由于第二节点P的电位为低电位，第六晶体管T6在第二节点P的电位控制下关闭。
与此同时，下一级时钟信号CK（n+2）的电位仍为低电位，第七晶体管T7在第一扫描控制信号U2D的控制下打开，下一级时钟信号CK（n+2）的电位经第七晶体管T7输出至第九晶体管T9的栅极，使得第九晶体管T9关闭。
最后，下一级时钟信号CK（n+2）的电位由低电位转为高电位，第七晶体管T7在第一扫描控制信号U2D的控制下打开，下一级时钟信号CK（n+2）的电位经第七晶体管T7输出至第九晶体管T9的栅极，使得第九晶体管T9打开。恒压高电平信号VGH经第九晶体管T9输出至第二节点P，使得第二节点P的电位为高电位。第六晶体管T6在第二节点P的电位控制下打开，恒压低电平信号VGL经第六晶体管T6输出至本级扫描信号输出端G（n），进而拉低本级扫描信号的电位。
与此同时，由于第十一晶体管T11的源极的电位为高电位，第十一晶体管T11的栅极端的电位为接地端GND的电位，使得第十一晶体管T11关闭，根据晶体管的特性，此时第十一晶体管T11的漏极的电位为接地端GND的电位与第十一晶体管T11的阈值电压之间的压差。第十晶体管T10在第十一晶体管T11的漏极的电位控制下打开，恒压低电平信号VGL经第十晶体管T10输出至第一节点Q，进而拉低第一节点Q的电位。
需要说明的是，相较于现有技术将晶体管的栅极和节点直接连接，本申请实施例通过在第十晶体管T10的栅极和第二节点P之间设置第十一晶体管T11，且第十一晶体管T11的栅极电性连接于接地端GND，从而减弱第十晶体管T10负漂以及关态电流增加的趋势，进而在GOA电路处于触控中停阶段时，抑制第一节点Q漏电。当GOA电路处于触控中停阶段时，中停控制信号Gas2的电位为高电位，第十二晶体管T12在中停控制信号Gas2的控制下打开，恒压低电平信号VGL经第十二晶体管T12输出至本级扫描信号输出端G（n），从而使得GOA电路在显示期间实现暂停扫描功能。与此同时，由于第一节点Q的电位为高电位，第三晶体管T3在第一节点Q的电位控制下打开，恒压低电平信号VGL经第三晶体管T3输出至第二节点P，使得第二节点P的电位为低电位，进而使得第十一晶体管T11打开，第十晶体管T10关闭。由于第十晶体管T10负漂以及关态电流增加的趋势减弱，从而可以在GOA电路处于触控中停阶段时，抑制第一节点Q漏电。
请参阅图5，图5为本申请实施例提供的GOA电路中的第n级GOA单元的另一电路示意图。其中，图5所示的第n级GOA单元相较于图3的第n级GOA单元的区别在于，图5所示的第n级GOA单元还包括第十三晶体管T13、第十四晶体管T14以及第十五晶体管T15。
第十三晶体管T13的栅极、第十三晶体管T13的源极、第十四晶体管T14的栅极以及第十五晶体管T15的栅极均接入放电控制信号Gas1，第十三晶体管T13的漏极电性连接于本级扫描信号输出端G（n）。第十四晶体管T14的源极接入恒压低电平信号VGL，第十四晶体管T14的漏极电性连接于第二节点P。第十五晶体管T15的源极接入恒压低电平信号VGL，第十五晶体管T15的漏极电性连接于下拉维持模块104。具体的，第十五晶体管T15的漏极、第七晶体管的漏极以及第八晶体管的漏极电性连接。
当放电控制信号Gas1为高电位时，第十三晶体管T13、第十四晶体管T14以及第十五晶体管T15在放电控制信号Gas1的控制下打开，放电控制信号Gas1经第十三晶体管T13输出至本级扫描信号输出端G（n），恒压低电平信号VGL经第十四晶体管T14输出至第一节点Q，恒压低电平信号VGL经第十五晶体管T15输出至第九晶体管T9的栅极，进而使得本级扫描信号输出端G（n）为高电位。
也即，本申请实施例可以在每个GOA单元中均设置第十三晶体管T13、第十四晶体管T14以及第十五晶体管T15，从而可以通过放电控制信号Gas1使得显示面板上的扫描线均接入扫描信号，进而可以对显示面板进行放电。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种GOA电路，其包括N级级联设置的GOA单元，第n级GOA单元包括节点控制模块、上拉模块、下拉模块、下拉维持模块以及中停控制模块，1<n<N-1，n、N均为正整数；
    所述节点控制模块接入上一级扫描信号、下一级扫描信号、第一扫描控制信号以及第二扫描控制信号，并电性连接于第一节点以及第二节点，所述节点控制模块用于根据所述上一级扫描信号、所述下一级扫描信号、所述第一扫描控制信号以及、所述第二扫描控制信号，拉高所述第一节点的电位以及拉低所述第二节点的电位；
    所述上拉模块接入本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于根据所述本级时钟信号以及所述第一节点的电位在本级扫描信号输出端输出本级扫描信号；
    所述下拉模块电性连接于所述第二节点，所述下拉模块用于根据所述第二节点的电位下拉所述扫描信号输出端的电位；
    所述下拉维持模块接入上一级时钟信号、下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，并电性连接于所述第一节点以及所述第二节点，所述下拉维持模块用于根据所述上一级时钟信号、所述下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，拉低所述第一节点的电位以及拉高所述第二节点的电位；
    所述中停控制模块接入中停控制信号，所述中停控制模块用于在所述GOA电路处于触控中停阶段时，基于所述中停控制信号拉低所述本级扫描信号输出端的电位；所述下拉维持模块还用于在所述触控中停阶段抑制所述第一节点漏电。
  2. 根据权利要求1所述的GOA电路，其中，所述节点控制模块包括第一晶体管、第二晶体管、第三晶体管、第一电容以及第二电容；
    所述第一晶体管的栅极接入所述上一级扫描信号，所述第一晶体管的源极接入第一扫描控制信号，所述第一晶体管的漏极电性连接于所述第一节点；
    所述第二晶体管的栅极接入所述下一级扫描信号，所述第二晶体管的源极接入第二扫描控制信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极接入恒压低电平信号，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端接入所述恒压低电平信号；
    所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端接入所述恒压低电平信号。
  3. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极接入恒压高电平信号，所述第四晶体管的源极电性连接于所述第一节点，所述第四晶体管的漏极与所述第五晶体管的栅极电性连接；
    所述第五晶体管的源极接入所述本级时钟信号，所述第五晶体管的漏极电性连接于所述本级扫描信号输出端。
  4. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第六晶体管；
    所述第六晶体管的栅极电性连接于所述第二节点，所述第六晶体管的源极接入恒压低电平信号，所述第六晶体管的漏极电性连接于所述本级扫描信号输出端。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
    所述第七晶体管的栅极接入所述第一扫描控制信号，所述第七晶体管的源极接入所述下一级时钟信号，所述第七晶体管的漏极电性连接于所述第八晶体管的漏极以及所述第九晶体管的栅极；
    所述第八晶体管的栅极接入所述第二扫描控制信号，所述第八晶体管的源极接入所述上一级时钟信号；
    所述第九晶体管的源极接入恒压高电平信号，所述第九晶体管的漏极电性连接于所述第二节点；
    所述第十晶体管的栅极电性连接于所述第十一晶体管的漏极，所述第十晶体管的源极接入恒压低电平信号，所述第十晶体管的漏极电性连接于所述第一节点；
    所述第十一晶体管的栅极连接于接地端，所述第十一晶体管的源极电性连接于所述第二节点。
  6. 根据权利要求5所述的GOA电路，其中，当所述第二节点的电位为所述恒压高电平信号的电位时，所述第十一晶体管关闭，所述第十一晶体管的漏极的电位为所述接地端的电位与所述第十一晶体管的阈值电压之间的压差。
  7. 根据权利要求6所述的GOA电路，其中，所述第十晶体管的栅极的电位与所述第十晶体管的漏极的电位之间的压差小于所述恒压高电位与所述恒压低电位的压差。
  8. 根据权利要求1所述的GOA电路，其中，所述中停控制模块包括第十二晶体管；
    所述第十二晶体管的栅极接入所述中停控制信号，所述第十二晶体管的源极接入恒压低电平信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端。
  9. 根据权利要求1所述的GOA电路，其中，所述GOA电路还包括第十三晶体管、第十四晶体管以及第十五晶体管；
    所述第十三晶体管的栅极、所述第十三晶体管的源极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极均接入放电控制信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号输出端；
    所述第十四晶体管的源极接入恒压低电平信号，所述第十四晶体管的漏极电性连接于所述第二节点；
    所述第十五晶体管的源极接入所述恒压低电平信号，所述第十五晶体管的漏极电性连接于所述下拉维持模块。
  10. 一种显示面板，其包括GOA电路，所述GOA电路包括N级级联设置的GOA单元，第n级GOA单元包括节点控制模块、上拉模块、下拉模块、下拉维持模块以及中停控制模块，1<n<N-1，n、N均为正整数；
    所述节点控制模块接入上一级扫描信号、下一级扫描信号、第一扫描控制信号以及第二扫描控制信号，并电性连接于第一节点以及第二节点，所述节点控制模块用于根据所述上一级扫描信号、所述下一级扫描信号、所述第一扫描控制信号以及、所述第二扫描控制信号，拉高所述第一节点的电位以及拉低所述第二节点的电位；
    所述上拉模块接入本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于根据所述本级时钟信号以及所述第一节点的电位在本级扫描信号输出端输出本级扫描信号；
    所述下拉模块电性连接于所述第二节点，所述下拉模块用于根据所述第二节点的电位下拉所述扫描信号输出端的电位；
    所述下拉维持模块接入上一级时钟信号、下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，并电性连接于所述第一节点以及所述第二节点，所述下拉维持模块用于根据所述上一级时钟信号、所述下一级时钟信号、所述第一扫描控制信号以及所述第二扫描控制信号，拉低所述第一节点的电位以及拉高所述第二节点的电位；
    所述中停控制模块接入中停控制信号，所述中停控制模块用于在所述GOA电路处于触控中停阶段时，基于所述中停控制信号拉低所述本级扫描信号输出端的电位；所述下拉维持模块还用于在所述触控中停阶段抑制所述第一节点漏电。
  11. 根据权利要求10所述的显示面板，其中，所述节点控制模块包括第一晶体管、第二晶体管、第三晶体管、第一电容以及第二电容；
    所述第一晶体管的栅极接入所述上一级扫描信号，所述第一晶体管的源极接入第一扫描控制信号，所述第一晶体管的漏极电性连接于所述第一节点；
    所述第二晶体管的栅极接入所述下一级扫描信号，所述第二晶体管的源极接入第二扫描控制信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极接入恒压低电平信号，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端接入所述恒压低电平信号；
    所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端接入所述恒压低电平信号。
  12. 根据权利要求10所述的显示面板，其中，所述上拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极接入恒压高电平信号，所述第四晶体管的源极电性连接于所述第一节点，所述第四晶体管的漏极与所述第五晶体管的栅极电性连接；
    所述第五晶体管的源极接入所述本级时钟信号，所述第五晶体管的漏极电性连接于所述本级扫描信号输出端。
  13. 根据权利要求10所述的显示面板，其中，所述下拉模块包括第六晶体管；
    所述第六晶体管的栅极电性连接于所述第二节点，所述第六晶体管的源极接入恒压低电平信号，所述第六晶体管的漏极电性连接于所述本级扫描信号输出端。
  14. 根据权利要求10所述的显示面板，其中，所述下拉维持模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
    所述第七晶体管的栅极接入所述第一扫描控制信号，所述第七晶体管的源极接入所述下一级时钟信号，所述第七晶体管的漏极电性连接于所述第八晶体管的漏极以及所述第九晶体管的栅极；
    所述第八晶体管的栅极接入所述第二扫描控制信号，所述第八晶体管的源极接入所述上一级时钟信号；
    所述第九晶体管的源极接入恒压高电平信号，所述第九晶体管的漏极电性连接于所述第二节点；
    所述第十晶体管的栅极电性连接于所述第十一晶体管的漏极，所述第十晶体管的源极接入恒压低电平信号，所述第十晶体管的漏极电性连接于所述第一节点；
    所述第十一晶体管的栅极连接于接地端，所述第十一晶体管的源极电性连接于所述第二节点。
  15. 根据权利要求14所述的显示面板，其中，当所述第二节点的电位为所述恒压高电平信号的电位时，所述第十一晶体管关闭，所述第十一晶体管的漏极的电位为所述接地端的电位与所述第十一晶体管的阈值电压之间的压差。
  16. 根据权利要求15所述的GOA电路，其中，所述第十晶体管的栅极的电位与所述第十晶体管的漏极的电位之间的压差小于所述恒压高电位与所述恒压低电位的压差。
  17. 根据权利要求10所述的显示面板，其中，所述中停控制模块包括第十二晶体管；
    所述第十二晶体管的栅极接入所述中停控制信号，所述第十二晶体管的源极接入恒压低电平信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端。
  18. 根据权利要求10所述的显示面板，其中，所述GOA电路还包括第十三晶体管、第十四晶体管以及第十五晶体管；
    所述第十三晶体管的栅极、所述第十三晶体管的源极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极均接入放电控制信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号输出端；
    所述第十四晶体管的源极接入恒压低电平信号，所述第十四晶体管的漏极电性连接于所述第二节点；
    所述第十五晶体管的源极接入所述恒压低电平信号，所述第十五晶体管的漏极电性连接于所述下拉维持模块。
PCT/CN2021/082380 2021-03-16 2021-03-23 Goa 电路及显示面板 Ceased WO2022193341A1 (zh)

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