WO2022186192A1 - 半導体素子、電力変換装置および半導体素子の製造方法 - Google Patents

半導体素子、電力変換装置および半導体素子の製造方法 Download PDF

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WO2022186192A1
WO2022186192A1 PCT/JP2022/008577 JP2022008577W WO2022186192A1 WO 2022186192 A1 WO2022186192 A1 WO 2022186192A1 JP 2022008577 W JP2022008577 W JP 2022008577W WO 2022186192 A1 WO2022186192 A1 WO 2022186192A1
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electrode
bonding electrode
bonding
manufacturing
nickel
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French (fr)
Japanese (ja)
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雅司 小田原
昌利 砂本
隆二 上野
祥太郎 中村
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023503858A priority Critical patent/JP7584620B2/ja
Priority to CN202280016917.3A priority patent/CN116888708A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/01—Manufacture or treatment
    • H10D48/021—Manufacture or treatment of two-electrode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting

Definitions

  • the present disclosure relates to a semiconductor device, a power converter, and a method of manufacturing a semiconductor device.
  • the back side of the semiconductor element is joined to the semiconductor substrate by soldering, and the front side of the semiconductor element is made of aluminum alloy.
  • An electrode (surface electrode) made of, for example, is joined to a wiring circuit or the like by wire bonding of aluminum or the like.
  • a mounting method that directly solders electrodes made of aluminum alloy, copper, etc. to the front side of the semiconductor element, or a copper wire bonding method is adopted.
  • a bonding electrode layer of nickel, gold, copper, or the like can be formed to a thickness of about 1 ⁇ m or more on an electrode (front electrode) of an aluminum alloy or the like on the surface of a semiconductor element. ing.
  • the thickness of the film formed by the vacuum film forming method is usually about 1.0 ⁇ m or less, and if an attempt is made to increase the thickness of the bonding electrode layer, the film forming takes an order of magnitude longer than the plating method, resulting in increased manufacturing costs. It gets bulky.
  • an electroless plating method is attracting attention, which can selectively form a bonding electrode layer on an electrode made of an aluminum alloy or the like, and can form a bonding electrode layer thicker than about 1.0 ⁇ m at a low cost and at a high speed.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2005-19829
  • a contact hole is intentionally provided by an interlayer insulating film between a semiconductor substrate and an electrode, and the shape of the contact hole is used to form the same shape as the contact hole on the surface of the electrode. are uniformly formed.
  • the present disclosure has been made to solve the above problems, and aims to improve the long-term reliability of semiconductor devices.
  • a semiconductor chip an electrode provided on at least one main surface of the semiconductor chip; a first bonding electrode provided on the electrode; and a second bonding electrode provided on the first bonding electrode,
  • the electrode has a convex portion on the surface on the side of the first bonding electrode, In the first bonding electrode, the surface on the second bonding electrode side is smooth,
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to Embodiments 1 and 2.
  • FIG. FIG. 2 is a flowchart of the method for manufacturing a semiconductor device according to the first and second embodiments.
  • FIG. 3 is a schematic cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first and second embodiments.
  • FIG. 4 is a schematic cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first and second embodiments.
  • FIG. 5 is a schematic cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first and second embodiments.
  • FIG. 6 is a flowchart of electroless plating in Embodiments 1 and 3.
  • FIG. 7 is a schematic cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 8 is a schematic cross-sectional view of a conventional semiconductor device relating to first and second embodiments.
  • FIG. 9 is a flowchart of electroless plating in Embodiments 2 and 4.
  • FIG. 10 is a schematic cross-sectional view for explaining the method of manufacturing a semiconductor device according to the second embodiment.
  • FIG. 11 is a schematic cross-sectional view of a semiconductor device in Embodiments 3 and 4.
  • FIG. FIG. 12 is a flowchart of a method for manufacturing a semiconductor device according to Embodiments 3 and 4.
  • FIG. FIG. 13 is a schematic cross-sectional view of a conventional semiconductor device relating to third and fourth embodiments.
  • FIG. 14 is a schematic cross-sectional view of a semiconductor device according to Embodiment 5.
  • FIG. FIG. 15 is a flowchart of electroless plating according to Embodiment 5.
  • FIG. 16 is a schematic cross-sectional view of a conventional semiconductor device according to the fifth embodiment.
  • FIG. 17 is a block diagram showing the configuration of the power conversion system according to the sixth embodiment.
  • the semiconductor device of this embodiment includes: a semiconductor chip 1; an electrode 4 (electrode layer) provided as a wiring layer on the front side (one main surface) of the semiconductor chip 1; a first bonding electrode 6 provided on the electrode 4 (the surface opposite to the semiconductor chip 1); and a second bonding electrode 7 provided on the first bonding electrode 6 (the surface opposite to the semiconductor chip 1).
  • the electrode 4 has a convex portion on the surface on the side of the first bonding electrode 6, In the first bonding electrode 6, the surface on the second bonding electrode 7 side is smooth, The surface of the second bonding electrode 7 opposite to the first bonding electrode 6 is smooth.
  • a back electrode 5 (back electrode layer) is provided on the back side of the semiconductor chip 1 (the surface opposite to the electrode 4).
  • the height of the projections of the electrode 4 is preferably 1.0 ⁇ m or more.
  • the height of the projections of the electrode 4 can be calculated by the following method. That is, an arbitrary cross section obtained by irradiating a gallium ion beam with a focused ion beam device (FIB device) is observed with a scanning electron microscope (SEM) at a magnification of 5000 times. It is possible to measure the heights of arbitrary 10 points among the observed protrusions and regard the average value as the height of the protrusions of the electrode 4 .
  • the surface of the first bonding electrode 6 on the side of the second bonding electrode 7 and the surface of the second bonding electrode 7 on the side opposite to the first bonding electrode 6 are substantially smooth, and may not be completely smooth. , may have some height difference. In this case, the height difference is preferably 0.5 ⁇ m or less.
  • the above height difference can be calculated by the following method. That is, an arbitrary cross section obtained by irradiating a gallium ion beam with a focused ion beam device (FIB device) is observed with a scanning electron microscope (SEM) at a magnification of 5000 times. Within a range of 20 ⁇ m in the horizontal direction of the surface to be observed, an arbitrarily determined measurement point is used as a reference point, the difference between the highest point and the lowest point is measured, and the average value is taken as the first bonding electrode 6. It can be regarded as the height difference between the surface on the second bonding electrode 7 side and the surface of the second bonding electrode 7 on the side opposite to the first bonding electrode 6 .
  • a gate oxide film 2 may be provided between the semiconductor chip 1 and the electrode 4 , and a gate electrode 3 may be provided within the gate oxide film 2 . In this case, the projection of the electrode 4 is positioned above the gate oxide film 2 .
  • the semiconductor chip 1 is made of silicon carbide, for example.
  • the constituent material of the semiconductor chip 1 is not limited to silicon carbide, and may be silicon, gallium arsenide, gallium nitride, or the like, or a front-back conduction type semiconductor element such as an IGBT or a diode. Even in such a case, similar effects are expected.
  • the size of the semiconductor chip 1 is, for example, about 7 mm ⁇ 14 mm.
  • the electrode 4 preferably contains aluminum or an aluminum alloy.
  • Aluminum alloys include, for example, aluminum alloys containing aluminum and silicon, silicon, copper, or the like.
  • the first bonding electrode 6 preferably contains nickel, nickel phosphorous, or nickel boron.
  • Examples of the first bonding electrode 6 include an electroless nickel plating layer.
  • the second joining electrode 7 preferably contains gold or palladium.
  • Examples of the second bonding electrode 7 include an electroless gold plating layer and an electroless palladium plating layer.
  • the first bonding electrode 6 and the second bonding electrode 7 are not limited to the nickel plating layer, the gold plating layer and the palladium plating layer, and the electrode 4, the first bonding electrode 6 and the second bonding electrode 7 Any plating layer that enables bonding may be used. Even if an electrolytic copper plating layer or the like is used as such a plating layer, it is expected that the same effect can be obtained.
  • the first joining electrode 6 and the second joining electrode 7 are preferably formed by electroless plating.
  • the gate oxide film 2 is made of an insulating material such as silicon oxide.
  • the gate electrode 3 is made of, for example, a conductive material such as polysilicon.
  • the back electrode 5 is composed of a plurality of metal layers. Since the back electrode 5 may be used for bonding, the back electrode 5 is an electrode made of nickel or a nickel alloy containing silicon, copper, or the like, and is plated with nickel or gold, which has excellent bonding properties. It is preferable to use an electrode consisting of
  • the semiconductor element shown in FIG. 1 is a front-back conduction type semiconductor element having a front electrode (electrode 4 ) and a back electrode 5 . That is, the electrode 4 is a front electrode of a front-back conduction type semiconductor element.
  • the electrode 4 has a convex portion on the surface on the first bonding electrode 6 side, and the first bonding electrode 6 has a smooth surface on the second bonding electrode 7 side.
  • the surface of the second bonding electrode 7 opposite to the first bonding electrode 6 is smooth. This suppresses the generation of voids during bonding of the first bonding electrode 6 and the second bonding electrode 7, thereby improving the adhesion of the bonding portion. Therefore, long-term reliability of the semiconductor device can be improved.
  • the method for manufacturing a semiconductor device includes: a first step (electrode forming step) of forming an electrode on at least one main surface of a semiconductor chip; A second step of forming a first bonding electrode on the electrode (first bonding electrode forming step); and a third step of forming a second bonding electrode on the first bonding electrode (second bonding electrode forming step).
  • a convex portion is formed on the surface of the electrode on the side of the first bonding electrode.
  • the surface of the first bonding electrode on the side of the second bonding electrode is formed smooth.
  • the surface of the second bonding electrode opposite to the first bonding electrode is formed smooth.
  • the formation of the electrode 4 on the semiconductor chip 1 (first step), the formation of the back electrode 5, the masking of the back electrode 5, the electroless plating treatment (second step). step and third step), and masking stripping are performed in this order.
  • FIG. 3 to 5 are schematic cross-sectional views showing the manufacturing process flow of the semiconductor device shown in FIG.
  • FIG. 3 shows a cross-sectional structure of the semiconductor element before forming the electrode 4, the back electrode 5, the first bonding electrode 6, and the second bonding electrode 7 in the first embodiment.
  • FIG. 1 A specific method for manufacturing the semiconductor device shown in FIG. 1 will be described below with reference to FIGS. From the viewpoint of manufacturing efficiency, it is preferable that all the steps in the first embodiment are performed in a wafer state.
  • gate oxide film 2 including gate electrode 3 is first formed of an insulating material as gate oxide film 2.
  • a deposition method such as thermal oxidation or chemical vapor deposition, for example, it is patterned by photolithography or etching to form a lower portion of the gate oxide film 2 (in FIG. chip 1 side).
  • the gate electrode 3 is formed by patterning by the above-described method.
  • patterning is performed by the above-described method to form the gate oxide film 2.
  • the thickness of the gate oxide film 2 including the gate electrode 3 is preferably, for example, 1.0 ⁇ m or more and 3.0 ⁇ m or less.
  • First step electrode forming step
  • an aluminum alloy with low electric resistance is used by sputtering, which is easy to control the process.
  • the semiconductor element of the present embodiment includes gate oxide film 2 and gate electrode 3
  • electrode 4 is formed while maintaining the irregularities caused by gate oxide film 2 and gate electrode 3.
  • a convex portion is formed.
  • a titanium compound such as titanium or titanium nitride may be formed as a barrier metal between the semiconductor chip 1 and the aluminum alloy and between the gate oxide film 2 and the aluminum alloy. .
  • the thickness of the electrode 4 is, for example, preferably 0.5 ⁇ m or more and 5.0 ⁇ m or less, and the height of the projection of the electrode 4 is preferably 1.0 ⁇ m or more.
  • the electrodes 4 may contain, in addition to aluminum, silicon of about 1% by mass, silicon of about 1% by mass, and zero About 0.5% by mass of copper or the like may be added, and its concentration is preferably constant in the electrode.
  • nickel for example, is used to form the back electrode 5 composed of a plurality of metal layers on the semiconductor chip 1 opposite to the surface on which the electrode 4 is formed. is patterned by sputtering with easy process control, and then gold is patterned by sputtering with easy process control.
  • a barrier metal such as a titanium alloy or a nickel alloy may be formed between the semiconductor chip 1 and nickel depending on the application.
  • the thickness of the back electrode 5 is, for example, preferably 0.3 ⁇ m or more and 5.0 ⁇ m or less for the nickel layer, and preferably 0.01 ⁇ m or more and 0.2 ⁇ m or less for the gold layer.
  • the back electrode masking is performed to prevent the back electrode 5 from being damaged during the subsequent film forming process of the first bonding electrode 6 and the second bonding electrode 7 . This is done by attaching a film coated with an adhesive that can be peeled off by irradiating it with ultraviolet light.
  • the masking tape attached to the back electrode surface of the wafer is peeled off. Specifically, for example, using a masking tape that is peeled off when irradiated with ultraviolet light, the masking tape is peeled off by irradiating the back surface of the wafer that has undergone electroless plating with ultraviolet light.
  • degreasing is performed.
  • Degreasing is performed to remove light organic matter contamination, oils and fats, oxide films, etc. remaining on the surface of the electrode 4 and to impart wettability to the surface of the electrode 4 . It is preferable to saponify the residue by using an alkaline chemical solution that has a strong etching power for aluminum alloys and the like.
  • the purpose of the pickling is to neutralize the surface of the electrode 4, etch the surface of the electrode 4, increase the reactivity with the zincate solution described later, and improve the adhesion of the plating.
  • the zincate treatment is a treatment in which an oxide film (eg, aluminum oxide film) is removed while etching the surface of an electrode (eg, aluminum alloy electrode) to form a film of zinc or the like on the electrode surface.
  • an oxide film eg, aluminum oxide film
  • an electrode eg, aluminum alloy electrode
  • Zinc ions receive electrons on the surface of the aluminum alloy, forming a zinc film on the surface of the aluminum.
  • the zinc-coated aluminum alloy is immersed in nitric acid to dissolve the zinc once. Then, by immersing the aluminum alloy in the zincate solution again, the oxide film of aluminum is removed and zinc is uniformly coated. This operation smoothes the surface of the aluminum.
  • the zincate treatment is performed at least twice, preferably three times, because the more the number of zincate treatments, the more uniform the aluminum surface and the better the finish of the plating layer. When a uniform zinc film is formed on the surface of the electrode 4 by this zincate treatment, a sound plating layer can be adhered in the subsequent electroless plating treatment.
  • the components of the reducing agent are incorporated into the plating layer, so the electroless nickel plating layer becomes an alloy.
  • Hypophosphorous acid is generally used as a reducing agent, and this phosphorus is taken into the plating layer, so the electroless nickel plating layer contains phosphorus.
  • the initial nickel deposition rate is intentionally reduced in order to improve the degree of unevenness formation (filling property) of the aluminum alloy.
  • the reactivity decreases in the convex portions of the electrode 4 due to the action of the stabilizer and complexing agent contained in the plating solution, but the reactivity increases in the concave portions of the electrode 4. Since the agent concentrates and has higher reactivity than the convex portions, the electroless nickel plating layer is formed smoothly. To reduce the nickel deposition rate, it is effective to lower the temperature of the nickel plating bath or to suppress the supply of the nickel source and reducing agent to the reaction surface.
  • the nickel deposition rate is preferably 4.0 ⁇ m/hr or more and 10 ⁇ m/hr or less, more preferably 6.0 ⁇ m/hr or more and 8.0 ⁇ m/hr or less. As will be described later, the speed is maintained until the electroless nickel plating layer becomes smooth.
  • the nickel deposition rate is increased by increasing the temperature of the nickel plating bath or promoting the diffusion of the nickel source and reducing agent to the reaction surface.
  • a smooth electroless nickel plating layer is deposited on the aluminum alloy having uneven portions.
  • the nickel deposition rate is preferably 10 ⁇ m/hr or more and 15 ⁇ m/hr or less, more preferably 11 ⁇ m/hr or more and 13 ⁇ m/hr or less.
  • the thickness of the electroless nickel plating layer is preferably, for example, 1.0 ⁇ m or more and 7.0 ⁇ m or less. Moreover, when there is a height difference on the surface of the electroless nickel plating layer, it is preferably 0.5 ⁇ m or less.
  • the third step (second bonding electrode forming step) is performed. Electroless gold plating will be described as an example of the third step.
  • the electroless gold plating used here is generally a substitution type, and gold plating is deposited by replacing nickel with gold.
  • Substitution-type electroless gold plating is performed on an electroless nickel plating layer, and utilizes the action of nickel and gold being substituted by the action of a complexing agent contained in the plating solution. Since it is a substitution type, the reaction stops when the surface of nickel is covered with gold. Therefore, it is difficult to increase the thickness of the plating layer, which is generally about 0.05 ⁇ m in many cases.
  • the underlying electroless nickel plating layer is preferably smooth.
  • a smooth first bonding electrode 6 (nickel plating layer) and a second bonding electrode 7 (gold plating layer) are deposited on the surface of the electrode 4 having a convex portion by electroless plating.
  • a semiconductor device can be obtained by
  • the resulting semiconductor element is less susceptible to local corrosion than when the surfaces of the electroless nickel plating layer and the electroless gold plating layer have irregularities as shown in FIG.
  • the resulting semiconductor element suppresses the occurrence of voids in the recesses during soldering, compared to the case where the surfaces of the electroless nickel plating layer and the electroless gold plating layer have unevenness as shown in FIG. be done. Therefore, the semiconductor device of this embodiment is expected to have an effect of extending the operating life even in a power cycle test when it is incorporated in a power module.
  • the present embodiment even if the electrode 4 has unevenness, by forming the surfaces of the first bonding electrode 6 and the second bonding electrode 7 smooth, local nickel corrosion and Since the generation of voids is suppressed, the solderability is improved, and the long-term reliability of the semiconductor element can be secured.
  • Embodiment 2 CMP (Chemical Mechanical Polishing) is additionally performed in the electroless plating step of the manufacturing method shown in the first embodiment. Since the constituent elements of the semiconductor device of this embodiment have been described in the first embodiment, redundant description will be omitted.
  • CMP Chemical Mechanical Polishing
  • Electroless nickel plating and CMP will be described below, but since the other steps are the same as in Embodiment 1, redundant description will be omitted.
  • FIG. 9 is a flowchart of the first joining electrode forming step (second step) in Embodiment 2.
  • the procedure up to the second zincate treatment is the same as in Embodiment 1, but after that, electroless nickel plating and CMP are performed in this order. First, electroless nickel plating will be explained.
  • the components of the reducing agent are incorporated into the plating layer, so the electroless nickel plating layer becomes an alloy.
  • Hypophosphorous acid is generally used as a reducing agent, and this phosphorus is taken into the plating layer, so the electroless nickel plating layer contains phosphorus.
  • the nickel plating layer is affected by the uneven surface of the aluminum alloy, so the upper surface of the electroless nickel plating layer becomes uneven.
  • the thickness of the electroless nickel plating layer is reduced by 1.0 ⁇ m due to the subsequent CMP, it is preferable to form the electroless nickel plating layer thicker than the final desired thickness.
  • CMP means a process for flattening irregularities by improving mechanical polishing performance by surface chemical action of slurry.
  • the electroless nickel plating layer is subjected to CMP, the slurry collides with the steps of the uneven surface to generate heat energy, which promotes a chemical reaction at the steps. Therefore, the convex portion is selectively etched so as to eliminate the step, and the electroless nickel plating layer is flattened.
  • a smooth surface shape can be obtained by polishing the electroless nickel plated layer of the convex portion by 1.0 ⁇ m by CMP.
  • a smooth electroless gold plating layer is formed by electroless gold plating.
  • the fact that the second bonding electrode is an electroless gold plating layer is an example, and the second bonding electrode may be an electroless palladium plating layer, for example.
  • a semiconductor element can be obtained by depositing a smooth first bonding electrode (nickel plating layer) and a second bonding electrode (gold plating layer) by an electroless plating method.
  • the resulting semiconductor element is less susceptible to local corrosion than when the surfaces of the electroless nickel plating layer and the electroless gold plating layer have irregularities as shown in FIG.
  • the resulting semiconductor element suppresses the occurrence of voids in the recesses during soldering, compared to the case where the surfaces of the electroless nickel plating layer and the electroless gold plating layer have unevenness as shown in FIG. be done. Therefore, the semiconductor device of this embodiment is expected to have an effect of extending the operating life even in a power cycle test when it is incorporated in a power module.
  • the present embodiment even if the electrodes have unevenness, by forming the surfaces of the first bonding electrode 6 and the second bonding electrode 7 to be smooth, local nickel corrosion and voids are eliminated. is suppressed, solderability is improved, and long-term reliability of the semiconductor element can be ensured.
  • Embodiment 3 in the semiconductor element of the present embodiment, a first bonding electrode is also provided on the back electrode 5 (on the opposite side of the semiconductor chip 1), similarly to the electrode 4 (front electrode) in the first embodiment.
  • An electrode 61 and a second bonding electrode 71 are formed. Since other components have been described in the first embodiment, overlapping descriptions will be omitted.
  • the back electrode 5 is made of, for example, aluminum (the same material as the electrode 4) or an aluminum alloy containing silicon, silicon, copper, or the like, so that it can be plated by electroless plating. be done.
  • a smooth electroless nickel plating layer is simultaneously deposited on the electrode 4 having uneven portions and the smooth back electrode 5. .
  • electroless gold plating a smooth electroless gold plating layer is simultaneously deposited on the electroless nickel plating layer on the electrode 4 and the electroless nickel plating layer on the back electrode 5 .
  • the fact that the second bonding electrode is an electroless gold plating layer is an example, and the second bonding electrode may be an electroless palladium plating layer, for example.
  • the resulting semiconductor element is less susceptible to local corrosion than when the surfaces of the electroless nickel plating layer and the electroless gold plating layer have irregularities as shown in FIG.
  • the resulting semiconductor element suppresses the occurrence of voids in the recesses during soldering, compared to the case where the surfaces of the electroless nickel plating layer and the electroless gold plating layer have unevenness as shown in FIG. be done. Therefore, the semiconductor device of this embodiment is expected to have an effect of extending the operating life even in a power cycle test when it is incorporated in a power module.
  • the present embodiment even if the electrodes have unevenness, by forming the surfaces of the first bonding electrode and the second bonding electrode to be smooth, local nickel corrosion and voids occur. is suppressed, the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
  • Embodiment 4 the semiconductor element having the configuration shown in Embodiment 3 is formed, but the first bonding electrode 6 is formed on the electrode 4 by the manufacturing method shown in Embodiment 2, and the back electrode is formed. 5 is formed by the manufacturing method shown in Embodiment 2, except that CMP is not performed. Other components have been described in Embodiments 1 and 3, so overlapping descriptions will be omitted.
  • the back electrode 5 is made of, for example, aluminum (the same material as the electrode 4) or an aluminum alloy containing silicon, silicon, copper, or the like, so that it can be plated by electroless plating. be done.
  • a smooth electroless nickel plating layer is deposited on the electrode 4 having uneven portions.
  • a smooth electroless nickel plating layer is deposited on the smooth back electrode 5 .
  • electroless gold plating a smooth electroless gold plating layer is simultaneously deposited on the electroless nickel plating layer on the electrode 4 and the electroless nickel plating layer on the back electrode 5 .
  • the fact that the second bonding electrode is an electroless gold plating layer is an example, and the second bonding electrode may be an electroless palladium plating layer, for example.
  • the resulting semiconductor element is less susceptible to local corrosion than when the surfaces of the electroless nickel plating layer and the electroless gold plating layer have irregularities as shown in FIG.
  • the resulting semiconductor element suppresses the occurrence of voids in the recesses during soldering, compared to the case where the surfaces of the electroless nickel plating layer and the electroless gold plating layer have unevenness as shown in FIG. be done. Therefore, the semiconductor device of this embodiment is expected to have an effect of extending the operating life even in a power cycle test when it is incorporated in a power module.
  • the present embodiment even if the electrodes have unevenness, by forming the surfaces of the first bonding electrode and the second bonding electrode to be smooth, local nickel corrosion and voids occur. is suppressed, the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
  • Embodiment 5 in any one of the semiconductor elements according to Embodiments 1 to 4, the second bonding electrode 7 is composed of multiple layers. Since the other components have been described in the first to fourth embodiments, redundant description will be omitted.
  • the second bonding electrode has a two-layer structure consisting of first layer 7a and second layer 7b.
  • the first layer 7a preferably contains palladium, palladium phosphorus or a palladium alloy. Examples of the first layer 7a include an electroless palladium plated layer.
  • the second layer 7b preferably contains gold. As the second layer 7b, for example, an electroless gold plating layer can be used.
  • the first layer 7a and the second layer 7b are not limited to the palladium plated layer and the gold plated layer, and are plated layers that enable the bonding of the first bonding electrode 6, the first layer 7a and the second layer 7b. I wish I had. Even if an electrolytic copper plating layer or the like is used as such a plating layer, it is expected that the same effect can be obtained.
  • the first layer 7a and the second layer 7b are preferably formed by electroless plating.
  • FIG. 15 is a flow diagram of electroless plating in this embodiment.
  • the procedure up to electroless nickel plating is the same as in the first embodiment, and then electroless palladium plating and electroless gold plating are performed in this order. Electroless palladium plating and electroless gold plating will be described below, but since the other steps have been described in the first to fourth embodiments, redundant description will be omitted.
  • the electroless palladium plating used here is generally a substitution type, and palladium plating is deposited by replacing nickel with palladium.
  • Formic acid and hypophosphorous acid are used as reducing agents.
  • the thickness of the first layer 7a is preferably, for example, 0.1 ⁇ m or more and 1.0 ⁇ m or less.
  • Electroless gold plating is generally of the substitution type, as described above, but may be of the substitution-reduction type, or the substitution type and the reduction type may be carried out successively.
  • the electroless gold plating layer locally corrodes the electroless nickel plating layer through the electroless palladium plating layer. If the surface of the electroless nickel plated layer has unevenness, the presence of the electroless palladium plated layer promotes local corrosion of the concave portions due to the galvanic action. Therefore, when there is an electroless palladium plating layer, the underlying electroless nickel plating layer is preferably smooth.
  • a smooth first bonding electrode 6 (nickel plating layer) and a smooth second bonding electrode 7 on the surface of the electrode 4 having protrusions are formed by an electroless plating method.
  • a semiconductor element can be obtained by depositing the layer 7a (palladium plating layer) and the second layer 7b (gold plating layer).
  • the configuration of the second bonding electrode 7 is not limited to two layers, and may be three or more layers.
  • the layer in contact with the first bonding electrode 6 that is, the bottom layer preferably contains palladium, palladium phosphorus, or a palladium alloy, and is the farthest from the first bonding electrode 6 .
  • the layer, ie the top layer preferably comprises gold.
  • the bottom layer is an electroless palladium plating layer
  • the top layer is a reduction type electroless gold plating layer
  • the layer between the top layer and the bottom layer i.e., the intermediate layer.
  • the layer may be configured to be a substitutional electroless gold plating layer.
  • the resulting semiconductor element is less susceptible to local corrosion than when the surfaces of the electroless nickel plating layer, the electroless palladium plating layer, and the electroless gold plating layer have irregularities as shown in FIG. be.
  • the electroless palladium plating layer is smooth, diffusion of nickel to the surface of the electroless gold plating layer is prevented, and the bonding strength with solder is improved.
  • the resulting semiconductor element has a recessed portion during soldering, compared to the case where the surfaces of the electroless nickel plated layer, the electroless palladium plated layer, and the electroless gold plated layer have uneven portions as shown in FIG. void generation is suppressed. Therefore, the semiconductor device of this embodiment is expected to have an effect of extending the operating life even in a power cycle test when it is incorporated in a power module.
  • the surfaces of the first bonding electrode and the first and second layers, which are the second bonding electrode are formed to be smooth. This suppresses the local corrosion of nickel and the generation of voids, thereby improving the solderability and ensuring the long-term reliability of the semiconductor element.
  • Embodiment 6 applies any one of the semiconductor devices according to the first to fifth embodiments described above to a power converter. Although the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a sixth embodiment.
  • FIG. 17 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
  • the power conversion system shown in FIG. 17 is composed of a power supply 100, a power conversion device 200 and a load 300.
  • the power supply 100 is a DC power supply and supplies DC power to the power converter 200 .
  • the power supply 100 can be configured with various devices, for example, it can be configured with a DC system, a solar battery, or a storage battery, or it can be configured with a rectifier circuit or an AC/DC converter connected to an AC system. good too.
  • the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300 , converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300 .
  • the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. 203.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 .
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices, such as a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an electric motor for an air conditioner.
  • the main conversion circuit 201 includes a switching element (not shown) and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power, and the load is 300 supplies.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel. At least one of each switching element and each freewheeling diode of main conversion circuit 201 is a switching element or freewheeling diode of semiconductor device 202 corresponding to the semiconductor element of any one of the first to fifth embodiments described above.
  • each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
  • Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .
  • the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. may be provided.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201 .
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) to the drive circuit provided in the main conversion circuit 201 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. to output The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
  • any one of the semiconductor elements of Embodiments 1 to 5 is applied as the semiconductor device 202 constituting the main conversion circuit 201. Therefore, the power conversion device according to the present embodiment 200 can achieve improved long-term reliability.
  • the present disclosure is not limited to this, and can be applied to various power converters.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it.
  • the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, an electricity storage system, or the like.

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WO2024004683A1 (ja) * 2022-07-01 2024-01-04 株式会社デンソー 半導体装置
JP2024134749A (ja) * 2023-03-22 2024-10-04 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
WO2025004877A1 (ja) * 2023-06-27 2025-01-02 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法

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JP2001177096A (ja) * 1999-12-14 2001-06-29 Fuji Electric Co Ltd 縦型半導体装置の製造方法および縦型半導体装置
JP2010251719A (ja) * 2009-03-23 2010-11-04 Fuji Electric Systems Co Ltd 半導体装置の製造方法
JP2011219828A (ja) * 2010-04-12 2011-11-04 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2017059636A (ja) * 2015-09-15 2017-03-23 三菱電機株式会社 半導体装置の製造方法

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JP2001177096A (ja) * 1999-12-14 2001-06-29 Fuji Electric Co Ltd 縦型半導体装置の製造方法および縦型半導体装置
JP2010251719A (ja) * 2009-03-23 2010-11-04 Fuji Electric Systems Co Ltd 半導体装置の製造方法
JP2011219828A (ja) * 2010-04-12 2011-11-04 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2017059636A (ja) * 2015-09-15 2017-03-23 三菱電機株式会社 半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
WO2024004683A1 (ja) * 2022-07-01 2024-01-04 株式会社デンソー 半導体装置
JP2024134749A (ja) * 2023-03-22 2024-10-04 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
WO2025004877A1 (ja) * 2023-06-27 2025-01-02 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法

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