Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/435—Cross-sectional shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
  • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
  • H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/014—Manufacture or treatment using batch processing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
  • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Definitions

• the present disclosure relates to an electronic assembly and a method for fabricating the same.
• electromagnetic waves which refer to waves in which an electric field and a magnetic field are combined typically occur. Since such electromagnetic waves are generated from the electronic product and propagate toward an external space of the electronic product, the electromagnetic waves are easy to expose to a human body or a device. In particular, when electromagnetic waves are exposed to a user, they are harmful to the human body, and, when electromagnetic waves are exposed to an industrial device and a home appliance, malfunction of the device may be caused.
• An electric field forming electromagnetic waves may be easily blocked by using a conductor.
• the electric field may be easily blocked by grounding a roof, a wall or a floor of a building and the like, or using a grounded shielding material.
• the magnetic field forming electromagnetic waves is not easily blocked even by using geographic features unlike the electric field, a special material having high magnetic permeability should be used or a special method should be used.
• the special material and the special method may require an excessive cost and a long processing time.
• an embodiment of the present disclosure has been invented based on the above- described background, and provides an electronic assembly which can maximize blocking performance of electromagnetic waves while minimizing a cost required to fabricate.
• an electronic assembly including: a circuit board including a plurality of electric conductive connectors; a plurality of spaced semiconductor integrated circuits coupled to a first main surface of the circuit board; a cover layer disposed on the semiconductor integrated circuit to substantially enclose and to cover the semiconductor integrated circuit; a plurality of solder bumps disposed on a second main surface facing the first main surface of the circuit board in order to provide an electric connection to the electronic assembly; a first metal foil layer including a cut portion to expose the solder bump, and bonded to the second main surface of the circuit board; and a metal coating layer which is conformally coated over an upper surface of the electronic assembly on the first main surface of the circuit board, and is extended toward the second main surface of the circuit board across edges of the electronic assembly in order to physically, electrically contact the metal foil layer, and to coat side surfaces of the electronic assembly, wherein the semiconductor integrated circuit is electrically connected with the electric conductive connector and the solder bump, wherein the first metal foil layer and the cover layer have a
• an electronic assembly including: a circuit board including a plurality of electric conductive connectors, and at least one electric conductive ground connector extended toward a side surface of the electronic assembly; first and second semiconductor integrated circuits coupled to a first main surface and a second main surface of the circuit board that face each other, respectively; first and second cover layers which substantially enclose and planarize the first and second semiconductor integrated circuits, respectively, and are disposed on the first and second semiconductor integrated circuits, respectively; a plurality of solder bumps disposed on the second main surface of the circuit board in order to provide an electric connection to the electronic assembly; a first metal foil layer bonded to the second cover layer; and a metal coating layer which is conformally coated over an upper surface of the electronic assembly on the first main surface of the circuit board, and is extended toward the second main surface of the circuit board across edges of the electronic assembly in order to physically, electrically contact the metal foil layer and the ground connector, and to coat the side surfaces of the electronic assembly, wherein the semiconductor integrated circuit is electrically connected with the electric conductive
• FIG. 1 is a longitudinal cross-sectional view of an electronic assembly according to a first embodiment of the present disclosure
• FIG. 2 is a top view of FIG. 1 ;
• FIG. 3 is a longitudinal cross-sectional view of an electronic assembly according to a second embodiment of the present disclosure;
• FIG. 4 is a longitudinal cross-sectional view of an electronic assembly according to a third embodiment of the present disclosure.
• FIG. 5 is a longitudinal cross-sectional view of an electronic assembly according to a fourth embodiment of the present disclosure.
• FIG. 6 is a view illustrating a circuit board at a step of providing a circuit board of the present disclosure
• FIG. 7 is a view illustrating a cover layer disposed on a circuit board at a step of disposing a cover layer of the present disclosure
• FIG. 8 is a view illustrating a first metal foil layer bonded onto a circuit board at a step of bonding a first metal foil layer of the present disclosure
• FIG. 9 is atop view of FIG. 8;
• FIG. 10 is a view illustrating a plurality of articles divided at a step of dividing an article of the present disclosure
• FIG. 11 is a view illustrating an electronic assembly fabricated by an electronic assembly fabrication method of the present disclosure.
• FIG. 12 is a sequence diagram illustrating a method for fabricating an electronic assembly sequentially according to embodiments of the present disclosure.
• a direction such as “upper side” or the like, are described with reference to illustrations in the drawings, and it is to be noted that these may be expressed differently when the orientation of a corresponding object is changed.
• a longitudinal direction may refer to an x-axis direction of FIGS.
• a widthwise direction may refer to a y-axis direction of FIGS. 1 to 5.
• a thickness direction may refer to a z-axis direction of FIGS. 1 to 5.
• the electronic assembly 1 may protect an electronic component such as a semiconductor element from the outside, and may be electrically connected with an external configuration.
• the electronic assembly 1 may have at least part thereof shielded to prevent electromagnetic waves from being discharged to the outside.
• the electronic assembly 1 may include an upper surface 11, an edge 12, and a side surface 13.
• the upper surface 11 refers to one surface of an upper side of the electronic assembly 1.
• the upper surface 11 may be extended in the longitudinal direction and the widthwise direction.
• the edge 12 refers to an edge portion between the upper surface 11 and the side surface 13 of the electronic assembly 1.
• the edge 12 may be plural in number, and the plurality of edges 12 may be provided on both sides of the electronic assembly 1 in the longitudinal direction.
• the side surface 13 refers to both side surfaces of the electronic assembly 1 in the longitudinal direction.
• the side surface 13 may be extended in the thickness direction.
• the side surface 13 may be plural in number.
• the electronic assembly 1 may have a predetermined length L, a width W, and a thickness T.
• the electronic assembly 1 may include a circuit board 100, a semiconductor integrated circuit 200, a cover layer 300, a solder bump 400, a metal foil layer 500, an adhesive layer 600, a metal coating layer 700, and an electric conductive ground connector 800.
• the circuit board 100 may be provided to have various kinds of electronic components mounted thereon.
• the circuit board 100 may be a printed circuit board (PCB).
• the circuit board 100 may have a first main surface 101 and a second main surface 102.
• the first main surface 101 refers to an upper surface of the circuit board 100
• the second main surface 102 refers to a bottom surface of the circuit board 100
• the circuit board 100 may include an electric conductive connector 110.
• the electric conductive connector 110 may include a material having electric conductivity to allow a current to flow therethrough.
• the electric conductive connector 110 may be connected with one or more of the first main surface 101 and the second main surface 102, and may be inserted into the circuit board 100.
• electronic components disposed on or in the circuit board 100 may exchange electric signals with the electric conductive connector 110.
• the electric conductive connector 110 may be plural in number, and some of the plurality of electric conductive connectors 110 may be disconnected from each other. In addition, some of the plurality of electric conductive connectors 110 may be electrically connected with each other. At least two electric conductive connectors 110 of the plurality of electric conductive connectors 110 may be electrically connected to the same semiconductor integrated circuit 200.
• the semiconductor integrated circuit 200 may perform various functions as an electronic element.
• the semiconductor integrated circuit 200 may be coupled to the first main surface 101 on the first main surface 101 of the circuit board 100.
• the semiconductor integrated circuit 200 may be plural in number, and the plurality of semiconductor integrated circuits 200 may be spaced apart from one another along the longitudinal direction.
• the plurality of semiconductor integrated circuits 200 may be electrically connected to the different electric conductive connectors 110, respectively.
• the semiconductor integrated circuit 200 may be electrically connected with the solder bump 400 via the electric conductive connector 110.
• the semiconductor integrated circuit 200 may have at least part thereof enclosed by the cover layer 300.
• one of the other surfaces of the semiconductor integrated circuit 200 except for the bottom surface contacting the first main surface 101 may be enclosed by the cover layer 300.
• the semiconductor integrated circuit 200 may be referred to as a semiconductor IC.
• the cover layer 300 may cover the plurality of semiconductor integrated circuits 200.
• the cover layer 300 may substantially planarize the semiconductor integrated circuit 200 by enclosing the plurality of semiconductor integrated circuits 200, respectively.
• planarizing the semiconductor integrated circuit 200 may refer to the plurality of semiconductor integrated circuits 200 having different sizes being enclosed by the cover layer 300 which has a planar upper surface. Accordingly, other configurations may be disposed on the planar upper surface of the cover layer 300.
• the cover layer 300 may substantially encapsulate the plurality of semiconductor integrated circuits 200, respectively.
• encapsulating the semiconductor integrated circuit 200 may refer to the cover layer 300 covering and substantially enclosing the other surfaces except for the bottom surface of the semiconductor integrated circuit 200.
• the cover layer 300 described above may be in contact with the circuit board 100, and may be disposed on the circuit board 100.
• the cover layer 300 may include an epoxy molding compound (EMC).
• EMC epoxy molding compound
• the cover layer 300 may have a length L and a width W which are substantially coextensive with the circuit board 100.
• the solder bump 400 may provide an electric connection to the electronic assembly 1.
• the solder bump 400 may be disposed on the second main surface 102 of the circuit board 100.
• solder bump 400 may be disposed inside a cut portion 511, which will be described below, and may be exposed to the outside through the cut portion 511.
• solder bump 400 may be plural in number, and the plurality of solder bumps 400 may be electrically connected with the electric conductive connectors 110.
• the metal foil layer 500 may block electromagnetic waves emitted from the semiconductor integrated circuit 200.
• the metal foil layer 500 may include one or more of copper (Cu) and stainless steel (SUS).
• the metal foil layer 500 may include a first metal foil layer 510 and a second metal foil layer 520.
• the first metal foil layer 510 may be bonded to the second main surface 102 of the circuit board 100.
• the first metal foil layer 510 being bonded to the second main surface 102 may be a concept including not only being bonded in direct contact with the second main surface 102 but also being bonded to the second main surface 102 through a first adhesive layer 610.
• the first metal foil layer 510 may be exposed to the outside.
• the first metal foil layer 510 may include the cut portion 511 to expose the solder bump 400.
• the cut portion 511 may be formed by penetrating through the first metal foil layer 510 in the thickness direction.
• the second metal foil layer 520 may be bonded to the cover layer 300.
• the second metal foil layer 520 being bonded to the cover layer 300 may be a concept including not only being bonded in direct contact with the cover layer 300 but also being bonded to the cover layer 300 through a second adhesive layer 620.
• the second metal foil layer 520 may be in contact with the metal coating layer 700, and may be disposed between the metal coating layer 700 and the cover layer 300.
• the first metal foil layer 510 and the second metal foil layer 520 may have a length L and a width W which are substantially coextensive with the circuit board 100.
• the adhesive layer 600 may perform a function of an adhesive.
• the adhesive layer 600 may include an epoxy resin.
• the adhesive layer 600 may include the first adhesive layer 610 and the second adhesive layer 620.
• the first adhesive layer 610 may be disposed between the first metal foil layer 510 and the circuit board 100, and may be bonded to the first metal foil layer 510 and the second main surface 102 of the circuit board 100.
• the second adhesive layer 620 may be disposed between the second metal foil layer 520 and the cover layer 300, and may be bonded to the second metal foil layer 520 and the cover layer 300.
• the metal coating layer 700 may block an electric field emitted from the semiconductor integrated circuit 200 or moving toward the semiconductor integrated circuit 200 from the outside.
• the metal coating layer 700 may be conformally coated over the second metal foil layer 520. In other words, the metal coating layer 700 may be coated over an upper surface of the second metal foil layer 520.
• the metal coating layer 700 may be extended toward the second main surface 102 across the edges 12 to coat both side surfaces 13 of the electronic assembly 1. That is, the metal coating layer 700 may be extended in the widthwise direction to cover side surfaces of the circuit board 100, the cover layer 300, the metal foil layer 500, and the adhesive layer 600 in the longitudinal direction. In addition, the metal coating layer 700 may be extended in the widthwise direction to physically, electrically contact the first metal foil layer 510.
• the metal coating layer 700 may have a length L and a width W which are substantially coextensive with the circuit board 100.
• the metal coating layer 700 may have a predetermined thickness.
• the thickness of the metal coating layer 700 may vary according to a region of the metal coating layer 700, and the thickness of the metal coating layer 700 may refer to a thickness at a predetermined point, not an average thickness.
• the metal coating layer 700 may have different from each other thicknesses on the upper surface 11 and on the side surface 13.
• the thickness of the metal coating layer 700 may be smaller than about 30 micron, and may be larger than about 0.5 micron. More preferably, the thickness of the metal coating layer 700 may be smaller than about 20 micron, and may be larger than about 1 micron.
• the metal coating layer 700 may have different from each other an upper average thickness tl on the upper surface 11, and a side average thickness t2 on the side surface 13.
• an average thickness ratio tl/t2 of the upper average thickness tl to the side average thickness t2 of the metal coating layer 700 may exceed 0.2 and may be less than or equal to 0.5.
• the electric conductive ground connector 800 may be embedded in the circuit board 100.
• the electric conductive ground connector 800 may be extended from the inside of the circuit board 100 toward the metal coating layer 700 to physically, electrically contact the metal coating layer 700.
• the electric conductive ground connector 800 may be extended in the longitudinal direction to have one end thereof contact the metal coating layer 700.
• the electric conductive ground connector 800 may be plural in number, and the plurality of electric conductive ground connectors 800 may be disconnected from each other.
• the second metal foil layer 520 and the second adhesive layer 620 may be omitted in addition to the above-described configuration.
• the second embodiment of the present disclosure will be described with further reference to FIG. 3.
• differences from the above-described embodiment are mainly described, and the same description and reference numerals as in the above-described embodiment are referred to.
• the metal coating layer 700 may be disposed on the cover layer 300, and may be directly bonded to the cover layer 300.
• the metal coating layer 700 may be conformally coated over the cover layer 300.
• the metal coating layer 700 may be extended toward the first metal foil layer 510 from the upper surface of the cover layer 300 across the edges 12.
• the metal coating layer 700 may include a center portion 710, a side portion 720, and a taper portion 730, in addition to the above- described configuration.
• the third embodiment of the present disclosure will be described with further reference to FIG. 4.
• the center portion 710 may be a portion of the metal coating layer 700 that corresponds to at least part of the upper surface 11 of the electronic assembly 1.
• the center portion 710 may be enclosed by the taper portion 730, and may refer to a portion of the metal coating layer 700 that is adjacent to a center of the second metal foil layer 520.
• the center portion 710 described above may be extended in the longitudinal direction and the widthwise direction.
• the center portion 710 may be a substantially planar surface.
• the side portion 720 may be portions of the metal coating layer 700 that correspond to both side surfaces of the electronic assembly 1.
• the side portion 720 may be extended in the thickness direction.
• the taper portion 730 may be a portion of the metal coating layer 700 that is between the center portion 710 and the side portion 720. One end of the taper portion 730 may be connected with the metal coating layer 700, and the other end may be connected with the side portion 720.
• the taper portion 730 may have a predetermined slope to have a tapering shape.
• the taper portion 730 may taper toward the edge 12 of the electronic assembly 1 from the center portion, thereby having its thickness reduced. In other words, a thickness of one side of the taper portion 730 that is connected with the center portion 710 may be larger than a thickness of one side that is connected with the side portion 720.
• the semiconductor integrated circuit 200 may include a first semiconductor integrated circuit 210 and a second semiconductor integrated circuit 220, in addition to the above-described configuration.
• the fourth embodiment of the present disclosure will be described by referring to FIG. 5 more.
• the first semiconductor integrated circuit 210 may be coupled with the circuit board 100 on the first main surface 101 of the circuit board 100.
• the first semiconductor integrated circuit 210 may be plural in number, and the plurality of first semiconductor integrated circuits 210 may be spaced apart from each other along the longitudinal direction.
• the second semiconductor integrated circuit 220 may be coupled with the circuit board 100 on the second main surface 102 of the circuit board 100.
• the second semiconductor integrated circuit 220 may be plural in number, and the plurality of second semiconductor integrated circuits 220 may be spaced apart from each other along the longitudinal direction.
• the cover layer 300 may include a first cover layer 310 and a second cover layer 320 which have a length L and a width W substantially coextensive with the circuit board 100.
• the first cover layer 310 may be disposed on an upper side of the circuit board 100, and may cover the plurality of first semiconductor integrated circuits 210. In addition, the first cover layer 310 may planarize the plurality of first semiconductor integrated circuits 210 by enclosing the plurality of first semiconductor integrated circuits 210, respectively.
• the second cover layer 320 may be disposed on a lower side of the circuit board 100, and may cover the plurality of second semiconductor integrated circuits 220. In addition, the second cover layer 320 may planarize the plurality of second semiconductor integrated circuits 220 by enclosing the plurality of second semiconductor integrated circuits 220, respectively.
• the second cover layer 320 may include a cover cut portion 321, and the first metal foil layer 510 may include a foil cut portion 512.
• the first adhesive layer 610 may include an adhesive cut portion 611.
• the cover cut portion 321 may be formed by penetrating through the second cover layer 320, and the foil cut portion 512 may be formed by penetrating through the first metal foil layer 510.
• the adhesive cut portion 611 may be formed by penetrating through the first adhesive layer 610.
• the cover cut portion 321, the foil cut portion 512, and the adhesive cut portion 611 may have the same size and shape.
• the second cover layer 320, the first metal foil layer 510, and the first adhesive layer 610 may be aligned such that the cover cut portion 321, the foil cut portion 512, and the adhesive cut portion 611 are placed on positions corresponding to one another.
• the cover cut portion 321, the foil cut portion 512, and the adhesive cut portion 611 may be referred to as a cut portion, and the cut portion may be a concept that includes the cover cut portion 321, the foil cut portion 512, and the adhesive cut portion 611.
• the solder bump 400 may be plural in number, and may be disposed inside the cut portion. Accordingly, the plurality of solder bumps 400 may be exposed to the outside through the cut portion.
• the first adhesive layer 610 may be disposed between the first metal foil layer 510 and the second cover layer 320, and may be bonded to the first metal foil layer 510 and the second cover layer 320.
• the electronic assembly fabrication method S10 may fabricate a plurality of electronic assemblies 1.
• the electronic assembly fabrication method S10 may include a step of forming an article S100, a step of dividing the article S200, and a step of forming an electric conductive layer S300.
• the article 2 may be formed.
• the article 2 may be divided into a plurality of divided articles 20 by the step of dividing the article S200.
• the step of forming the article S 100 may include a step of providing a circuit board S 110, a step of disposing a cover layer S 120, and a step of bonding a first metal foil layer S130.
• the circuit board 100 including a plurality of segments 120 may be provided.
• the circuit board 100 may have a first main surface 101 and a second main surface 102 which face each other.
• the first main surface 101 may refer to an upper surface of the circuit board 100
• the second main surface 102 may refer to a lower surface of the circuit board 100.
• the segment 120 may include a first side portion 121 and a second side portion 122.
• first side portion 121 of the segment 120 may refer to a part of the first main surface 101 of the circuit board 100
• second side portion 122 may refer to a part of the second main surface 102 of the circuit board 100.
• each of the plurality of segments 120 may include a semiconductor integrated circuit 200, a solder bump 400, and an electric conductive ground connector 800.
• the semiconductor integrated circuit 200 may be coupled to the first side portion 121 of the segment 120.
• the semiconductor integrated circuit 200 may be plural in number, and the plurality of semiconductor integrated circuits 200 may be spaced apart from each other.
• the solder bump 400 may be disposed on the second side portion 122 of the segment 120.
• the solder bump 400 may be plural in number.
• the electric conductive ground connector 800 may be embedded in the segment 120.
• the electric conductive ground connector 800 of at least one divided article 20 may physically, electrically contact an electric conductive layer 900 which is coated over side surfaces 13 of the divided article 20, which will be described below.
• the electric conductive ground connector 800 of the at least one divided article 20 may be extended toward one or more of the side surfaces 13 of the divided article 20.
• a cover layer 300 may be disposed on the circuit board 100 to cover the semiconductor integrated circuit 200 in each segment 120.
• a first metal foil layer 510 including a plurality of penetrating holes 513 may be bonded to the circuit board 100.
• the first metal foil layer 510 may be bonded to the second side portion 122 of each segment 120, and may cover the second side portion 122.
• the plurality of solder bumps 400 may be exposed to the outside through the plurality of penetrating holes 513.
• the article 2 may be divided into the plurality of respective divided articles 20.
• the divided article 20 may include at least one segment 120.
• the step of dividing the article S200 may include one or more processes of saw cutting, laser cutting, water jet cutting, die cutting, scoring, and breaking.
• the saw cutting may cut the article by using a rotating disc, and the laser cutting may cut the article by irradiating lasers of high energy.
• the water jet cutting may cut the article by spraying water of high pressure through a nozzle, and the die cutting may cut the article in a shape of a mold by using a mold having a predetermined shape.
• the scoring may cut the article by using a scoring blade, and the breaking may cut the article by breaking. Referring to FIG. 11, at the step of forming the electric conductive layer S300, the electric conductive layer 900 including metal may be formed on an upper surface of the divided article 20. At the step of forming the electric conductive layer S300, the electric conductive layer 900 may physically, electrically contact the first metal foil layer 510.
• the electric conductive layer 900 may be electrically extended, continuously going over the side surfaces 13 of the at least divided article 20 and upper edges 12 of the divided article 20.
• the electric conductive layer 900 may be disposed on an upper surface 11 of the at least one divided article 20.
• the upper surface 11 of the divided article 20 may be the opposite surface of the first metal foil layer 510.
• the divided article 20 having the electric conductive layer 900 disposed on the upper surface thereof may be referred to as the electronic assembly 1.
• the electronic assembly 1 includes the metal foil layer 500 and the metal coating layer 700, thereby having an effect of blocking electromagnetic waves.
• masking for exposing the solder bump 400 to the outside may be performed by using the step of bonding the first metal foil layer S130, without using a sputtering process requiring use of a tape, so that there is an effect of noticeably reducing a manufacturing process and a cost.

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• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
• Physics & Mathematics (AREA)
• Health & Medical Sciences (AREA)
• Electromagnetism (AREA)
• Toxicology (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Superconductors And Manufacturing Methods Therefor (AREA)
• Non-Silver Salt Photosensitive Materials And Non-Silver Salt Photography (AREA)
• Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)

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• 2021
  • 2021-02-26 KR KR1020210026758A patent/KR20220122296A/ko active Pending
• 2022
  • 2022-01-28 US US18/278,681 patent/US12604737B2/en active Active
  • 2022-01-28 JP JP2023551976A patent/JP2024508822A/ja active Pending
  • 2022-01-28 WO PCT/IB2022/050766 patent/WO2022180461A1/en not_active Ceased

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