WO2022179028A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022179028A1
WO2022179028A1 PCT/CN2021/103881 CN2021103881W WO2022179028A1 WO 2022179028 A1 WO2022179028 A1 WO 2022179028A1 CN 2021103881 W CN2021103881 W CN 2021103881W WO 2022179028 A1 WO2022179028 A1 WO 2022179028A1
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Prior art keywords
barrier layer
opening
forming
semiconductor structure
substrate
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French (fr)
Inventor
穆天蕾
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/612,546 priority Critical patent/US12205893B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Definitions

  • the present disclosure relates to, but is not limited to, a method of forming a semiconductor structure and a semiconductor structure.
  • DRAM dynamic random access memory
  • Embodiments of the present disclosure provide a method for forming a semiconductor structure and a semiconductor structure, which reduce the contact resistance of the bit line contact structure by increasing the contact area of the bottom of the bit line contact opening.
  • a first aspect of the embodiments of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate, and forming a dielectric layer on the surface of the substrate; forming a mask layer on the surface of the dielectric layer, the mask layer having a thickness through the mask layer forming a first barrier layer on the sidewall of the first opening, the first barrier layer enclosing the second opening; forming a second barrier layer filling the second opening; using a first etching process to remove the first barrier layer and the second barrier layer, until the first barrier layer or the second barrier layer is completely removed, the rate at which the first barrier layer is removed by the first etching process is different from the rate at which the second barrier layer is removed;
  • the dielectric layer and part of the substrate form a bit line contact opening, the bottom of the bit line contact opening has a raised area and a recessed area, and the raised area and the recessed area have a height difference.
  • a second aspect of the present disclosure provides a semiconductor structure, comprising: a substrate having an active region therein, and a first contact opening exposing the active region; the bottom of the first contact opening includes a first region and a second region, The first area and the second area have a height difference; the dielectric layer is located on the surface of the substrate, the dielectric layer has a second contact opening penetrating the dielectric layer, the second contact opening exposes the first contact opening, and the second contact opening is in contact with the first contact
  • the openings constitute bit line contact openings.
  • the bottom area of the bit line contact opening is increased by using the bit line contact opening having a recessed area and a raised area, so that the contact area of the bit line contact structure formed by filling the bit line contact opening subsequently increases, thereby reducing the The contact resistance of the subsequently formed bit line contact structure is small.
  • FIG. 1 is a schematic top-view structural diagram of a substrate provided by an embodiment of the present disclosure
  • DRAM Dynamic Random Access Memory
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate, forming a dielectric layer on the surface of the substrate; forming a mask layer on the surface of the dielectric layer, the mask layer having a first opening penetrating the thickness of the mask layer ; Form a first barrier layer on the sidewall of the first opening, and the first barrier layer surrounds the second opening; form a second barrier layer filling the second opening; adopt a first etching process to remove the first barrier layer and the second barrier layer barrier layer, until the first barrier layer or the second barrier layer is completely removed, the rate of removing the first barrier layer and the rate of removing the second barrier layer by the first etching process are different; the dielectric layer and part exposed by the first opening are removed
  • the base is formed with a bit line contact opening, the bottom of the bit line contact opening has a raised area and a recessed area, and the raised area and the recessed area have a height difference.
  • FIG. 1 is a schematic top view of the structure of the substrate provided in this embodiment
  • FIGS. 2 , 4 , 6 , 8 , 10 , 12 , 14 , 16 , 18 , 20 , 22 and 24 are In the method for forming a semiconductor structure provided in this embodiment, cross-sectional structural diagrams corresponding to each step along the AA1 direction are shown in FIGS.
  • a substrate 100 is provided, and the substrate 100 includes a shallow trench isolation structure 110 , an active region 120 and a word line structure 130 therein.
  • the material of the substrate 100 may include silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and the silicon material is used as the substrate 100 in this embodiment for the convenience of those skilled in the art
  • the understanding of the subsequent formation method does not constitute a limitation, and in the actual application process, a suitable substrate material can be selected according to requirements.
  • a plurality of active regions 120 in the substrate 100 are arranged parallel to each other and spaced apart.
  • the substrate 100 also includes other memory structures except the shallow trench isolation structure 110 , the active region 120 and the word line structure 130 . Since the other memory structures do not involve the core technology of the present disclosure, the More details will be given; those skilled in the art can understand that the substrate 100 further includes other memory structures except the shallow trench isolation structure 110, the active region 120 and the word line structure 130 for normal operation of the memory.
  • the method for forming the semiconductor structure provided in this embodiment is described in detail with the cross-sectional structure of AA1 and the cross-sectional structure of BB1, wherein the cross-section AA1 is the cross-section in the extension direction of the bit line structure, and the cross-section BB1 is the extension direction of the word line structure. section above.
  • the word line structure 130 is a buried word line structure located in the substrate 100.
  • the word line structure 103 passes through the active region 120 and the shallow trench isolation structure 110 at intervals.
  • the word The line structure 130 is located in the shallow trench isolation structure 110 ; it should be noted that in other schematic cross-sectional views of the substrate 100 , the word line structure 130 may be located in the active region 120 .
  • a dielectric layer 101 is formed on the surface of the substrate 100; wherein, referring to FIG.
  • a mask layer 102 is formed on the surface of the dielectric layer 101, and the mask layer 102 has a first opening 112 through the thickness of the mask layer 102; the mask layer 102 and the first opening 112 are used to define bit lines The location of the contact opening.
  • forming the first opening 112 having a thickness through the mask layer 102 includes: forming a patterned photoresist on the top of the mask layer 102 , and forming an opening 112 through the thickness of the mask layer 102 based on the patterned photoresist The first opening 112 .
  • the mask layer 102 is a single-layer structure; in other embodiments, the mask layer may also be a multi-layer mask structure.
  • a first barrier layer 103 is formed on the sidewall of the first opening 112 , and the first barrier layer 103 surrounds the second opening 122 .
  • forming the first barrier layer 103 on the sidewall of the first opening 112 includes the following steps: forming a cover mask layer 102 on the top surface and covering the sidewall and bottom of the first opening 112
  • the first barrier film (not shown), the first barrier film (not shown) surrounds the second opening 122, and in the direction parallel to the surface of the substrate, the width of the second opening 122 is smaller than the width of the first opening 112; remove A first barrier film (not shown) located on the top surface of the mask layer 102 and the bottom of the first opening 112 forms the first barrier layer 103 .
  • the first barrier layer 103 is also located at the bottom of the first opening 112 .
  • forming the first barrier layer 103 on the sidewall of the first opening 112 includes the following steps: forming a cover mask The top surface of the film layer 102 and a first barrier film (not shown) covering the sidewall and bottom of the first opening 112, the first barrier film (not shown) encloses the second opening 122, in a direction parallel to the surface of the substrate , the width of the second opening 122 is smaller than the width of the first opening 112 ; the first barrier film (not shown) on the top surface of the mask layer 102 is removed to form the first barrier layer 103 .
  • the width B of the first barrier layer 103 is 5 nm ⁇ 20 nm, such as 8 nm, 11 nm, 14 nm or 17 nm. If the width of the first barrier layer 103 is less than 5 nm, the size of the recessed area of the bit line contact opening formed by the subsequent etching of the first barrier layer 103 may be too small.
  • bit line contact structure In the process of filling the bit line contact opening to form the bit line contact structure, The bit line contact structure cannot completely fill the recessed area, resulting in filling defects in the bit line contact structure; if the width of the first barrier layer 103 is greater than 20 nm, the size of the second barrier layer formed by filling the gap between the first barrier layer 103 and the subsequent filling of the first barrier layer 103 is too small. , which in turn causes the size of the recessed area of the bitline contact opening formed by etching the second barrier layer to be too small. During the process of filling the bitline contact opening to form the bitline contact structure, the bitline contact structure cannot completely fill the recessed area, resulting in Semiconductor structural defects.
  • a second barrier layer 104 filling the second opening 122 (refer to FIG. 6 ) is formed.
  • forming the second barrier layer 104 filling the second opening 122 includes the following steps: forming a second barrier film filling the second opening 122 (refer to FIG. 6 ) and covering the first barrier layer 103 (not shown), the material of the second barrier film (not shown) and the material of the first barrier layer 103 have an etching selectivity ratio, and the second barrier film (not shown) higher than the first barrier layer 103 is removed, The remaining second barrier film (not shown) serves as the second barrier layer 104 .
  • the etching selectivity ratio of the first barrier layer 103 and the second barrier layer 104 ranges from 1:1.1 to 1:3; in another example, the etch selectivity of the first barrier layer 103 and the second barrier layer 104 The etch selectivity ratio ranges from 1.1:1 to 3:1. That is, the first barrier layer 103 and the second barrier layer 104 have an etching selectivity ratio, including the etching rate of the first barrier layer 103 being greater than the etching rate of the second barrier layer 104 , or the etching rate of the first barrier layer 103 The etching rate is lower than the etching rate of the second barrier layer 104 .
  • a first etching process is used to remove the first barrier layer 103 and the second barrier layer 104 until the first barrier layer 103 or the second barrier layer 104 is completely removed, and the first etching process removes the first barrier layer 103 or the second barrier layer 104
  • the rate of a barrier layer 103 is different from the rate of removing the second barrier layer 104; the dielectric layer 101 and part of the substrate 100 exposed by the first opening 112 are removed to form a bit line contact opening 105 with a raised area at the bottom of the bit line contact opening 105 115 and the recessed area 125, the raised area 115 and the recessed area 125 have a height difference.
  • the depth of the bit line contact opening 105 is 20 nm ⁇ 40 nm, such as 25 nm, 30 nm or 35 nm.
  • the height difference between the protruding region 115 and the recessed region 125 is 1 nm ⁇ 15 nm, for example, 3 nm, 5 nm, 7 nm, 9 nm, 11 nm or 13 nm.
  • the controllability of changing the bottom area of the bit line contact opening 105 is achieved.
  • the height difference between the raised region 115 and the recessed region 125 is less than 1 nm, the increased area at the bottom of the bit line contact opening 105 is negligible. At this time, the contact resistance of the bit line contact structure formed by filling the bit line contact opening 105 can be improved.
  • the contact resistance of the bit line contact structure is still very large, which affects the electrical properties of the semiconductor structure; if the height difference between the convex region 115 and the concave region 125 is greater than 15 nm, the gap between the concave region 125 and the convex region 115 is at this time.
  • the depth-to-width ratio is large, and the bit line contact structure formed by the subsequent filling of the bit line contact opening 105 is difficult to be completely filled, thereby causing structural defects and affecting the yield of the semiconductor structure.
  • Using the first etching process to remove the first barrier layer 103 and the second barrier layer 104 until the first barrier layer 103 or the second barrier layer 104 is completely removed including: using the first etching process to remove the first barrier layer 103 and the second barrier layer 104 until the first barrier layer 103 or the second barrier layer, whichever has the fastest etching rate, is completely removed; or use the first etching process to remove the first barrier layer 103 and the second barrier layer layer 104 until the first barrier layer 103 or the second barrier layer 104, whichever is slower, is completely removed.
  • this example is described in detail by taking the etch rate of the second barrier layer 104 greater than the etch rate of the first barrier layer 103 as an example.
  • the first etching process is adopted. , remove the first barrier layer 103 and the second barrier layer 104 until the first barrier layer 103 and the second barrier layer 104 are completely removed by the one with the faster etching rate.
  • the first barrier layer 103 and the second barrier layer 104 are simultaneously etched by the first etching process.
  • the first etching process is stopped. Since the etching rate of the first barrier layer 103 is lower than that of the second barrier layer 104 , the first barrier layer 103 remains.
  • the etching gas used in the first etching process at least includes a mixed gas of oxygen and fluorocarbon gas, and the etching time of the first etching process is 20-60s, such as 30s, 40s or 50s.
  • the remaining first barrier layer 103 or the second barrier layer 104 is etched by a second etching process, and the dielectric layer exposed by the first opening 112 is etched until the substrate 100 is exposed.
  • the height of the middle region at the bottom of the first opening 112 is always lower than that of the first etching process.
  • the height of the bottom edge region of the opening 112 until the middle region at the bottom of the first opening 112 exposes the substrate 100 , at which time the dielectric layer 101 remains in the bottom edge region of the first opening 112 .
  • a third etching process is used to etch the substrate 100 with a predetermined thickness exposed by the first opening 112 to form the bit line contact opening 105 .
  • the height of the middle region at the bottom of the first opening 112 is always lower than the bottom edge of the first opening 112
  • the height of the region is increased until the bit line contact opening 105 is formed. At this time, the region with a higher bottom height forms the raised region 115 , and the region with a lower bottom height forms the recessed region 125 .
  • the mask layer 102 is removed.
  • etching rate of the second barrier layer 104 is greater than that of the first barrier layer 103 .
  • the above-mentioned etching examples are also applicable to the second barrier layer 104 .
  • the etching rate of the barrier layer 104 is lower than that of the first barrier layer 103 .
  • this example is described in detail by taking an example that the etching rate of the second barrier layer 104 is lower than that of the first barrier layer 103 . Referring to FIGS. 20 to 25 , the first etching process, the first barrier layer 103 and the second barrier layer 104 are removed, until the first barrier layer 103 or the second barrier layer 104 is completely removed by whichever has a slower etching rate.
  • the first barrier layer 103 and the second barrier layer 104 are simultaneously etched by the first etching process.
  • the first etching process is stopped. Because the etching rate of a barrier layer 103 is higher than that of the second barrier layer 104, the dielectric layer 101 at the bottom of the first barrier layer 103 is over-etched; that is, removing the first barrier layer 103 and the second barrier layer 104 During the process, part of the dielectric layer 101 is removed, and the etched dielectric layer 101 is located at the bottom of the first barrier layer 103 or the second barrier layer 104 , whichever is etched faster.
  • the etching gas used in the first etching process at least includes a mixed gas of oxygen and fluorocarbon gas, and the etching time of the first etching process is 20-60s, such as 30s, 40s or 50s.
  • the remaining dielectric layer 101 exposed by the first opening 112 is etched by a second etching process until the substrate 100 is exposed.
  • the second etching process continues to etch the dielectric layer 101, so that during the etching process of the dielectric layer 101, the height of the bottom edge region of the first opening 112 is always lower than the height of the middle region at the bottom of the first opening 112, After the dielectric layer 101 in the bottom edge region of the first opening 112 is etched, the dielectric layer 101 in the middle region at the bottom of the first opening 112 remains; The substrate 100 in the bottom edge region of the first opening 112 is over-etched.
  • a third etching process is used to etch the substrate 100 with a predetermined thickness exposed by the first opening 112 to form the bit line contact opening 105 .
  • the etching of the first opening 112 by the second etching process may lead to an over-etching phenomenon of the substrate 100 in the bottom edge region of the first opening 112
  • the height of the middle region at the bottom of the first opening 112 is always higher than the height of the bottom edge region of the first opening 112 until the bit line contacts the opening 105 .
  • the region with a higher bottom height forms a raised region 115
  • the region with a lower bottom height forms a raised region 115 .
  • a recessed region 125 is formed.
  • the mask layer 102 is removed.
  • the above-mentioned etching example is described in detail with the etching rate of the second barrier layer 104 being lower than that of the first barrier layer 103 . In other implementations, the above-mentioned etching example is also applicable to the second barrier layer 104 .
  • the etching rate of the barrier layer 104 is higher than that of the first barrier layer 103 .
  • a concave-convex-shaped bit line structure opening 105 is formed between the two word line structures 130 to increase the contact area of the subsequently formed bit line contact structure, and does not occupy the formation of the word line structure 130 area, and will not affect the performance of the word line structure 130 .
  • the bottom area of the bit line contact opening is increased by forming a bit line contact opening with a recessed area and a raised area at the bottom, so that the contact area of the bit line contact structure formed by filling the bit line contact opening subsequently increase, thereby reducing the contact resistance of the subsequently formed bit line contact structure.
  • a semiconductor structure including: a substrate having an active region therein, and a first contact opening exposing the active region; the bottom of the first contact opening includes a first region and a second region, and the first contact opening includes a first region and a second region.
  • the first area and the second area have a height difference; the dielectric layer is located on the surface of the substrate, the dielectric layer has a second contact opening penetrating the dielectric layer, the second contact opening exposes the first contact opening, and the second contact opening and the first contact opening A bit line contact opening is formed.
  • a semiconductor structure including:
  • the substrate 100 has an active region 120 therein, and a first contact opening (not shown) exposing the active region 120 .
  • the material of the substrate 100 may include silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and the silicon material is used as the substrate 100 in this embodiment for the convenience of those skilled in the art
  • the understanding of the subsequent formation method does not constitute a limitation, and in the actual application process, a suitable substrate material can be selected according to requirements.
  • a plurality of active regions 120 in the substrate 100 are arranged parallel to each other and spaced apart.
  • the substrate 100 also includes other memory structures except the shallow trench isolation structure 110 , the active region 120 and the word line structure 130 . Since the other memory structures do not involve the core technology of the present disclosure, the More details will be given; those skilled in the art can understand that the substrate 100 further includes other memory structures except the shallow trench isolation structure 110, the active region 120 and the word line structure 130 for normal operation of the memory.
  • the dielectric layer 101 is located on the surface of the substrate 100.
  • the dielectric layer 101 has a second contact opening (not shown) passing through the dielectric layer 101, and the second contact opening (not shown) exposes the first contact opening (not shown).
  • the second contact opening (not shown) and the first contact opening (not shown) constitute the bit line contact opening 105 .
  • the bottom of the first contact opening (not shown) includes a first area and a second area, and the first area and the second area have a height difference, that is, the bottom of the bit line contact opening 105 includes a first area and a second area, and the first area and the second area has a height difference.
  • the first area is the raised area 115
  • the second area is the recessed area 125
  • the first area is arranged around the second area; it should be noted that this embodiment mainly reflects that the bottom of the bit line contact opening 105 includes The first area and the second area with different heights, in other embodiments, the first area may be a concave area, and the second area may be a convex area; in addition, in other embodiments, the first area and the second area may be It is spliced and arranged at the bottom of the bit line contact opening.
  • the width of the first region is 5 nm ⁇ 20 nm, for example, 8 nm, 11 nm, 14 nm or 17 nm. If the width of the first region is less than 5 nm, the size of the recessed region of the bit line contact opening formed by subsequent etching of the first region may be too small.
  • the bit line contact structure In the process of filling the bit line contact opening to form the bit line contact structure, the bit line contact structure The recessed area cannot be completely filled, resulting in filling defects in the contact structure of the bit line; if the width of the first area is greater than 20 nm, the size of the second barrier layer formed by filling the gap between the first area will be too small, which will lead to the etching of the second barrier The size of the recessed area of the bit line contact opening formed by the layer is too small, and in the process of filling the bit line contact opening to form the bit line contact structure, the bit line contact structure cannot completely fill the recessed area, thereby causing semiconductor structure defects.
  • the depth of the bit line contact opening 105 is 20 nm ⁇ 40 nm, such as 25 nm, 30 nm or 35 nm; the height difference between the first area and the second area is 1 nm ⁇ 15 nm , for example, 3 nm, 5 nm, 7 nm, 9 nm, 11 nm or 13 nm.
  • the height difference between the raised region 115 and the recessed region 125 is less than 1 nm, the increased area at the bottom of the bit line contact opening 105 is negligible. At this time, the contact resistance of the bit line contact structure formed by filling the bit line contact opening 105 can be improved. Negligible, that is, the contact resistance of the bit line contact structure is still very large, which affects the electrical properties of the semiconductor structure; if the height difference between the convex region 115 and the concave region 125 is greater than 15 nm, the gap between the concave region 125 and the convex region 115 is at this time. The depth-to-width ratio is large, and the bit line contact structure formed by the subsequent filling of the bit line contact opening 105 is difficult to be completely filled, thereby causing structural defects and affecting the yield of the semiconductor structure.
  • a concave-convex-shaped bit line structure opening 105 is formed between the two word line structures 130 to increase the contact area of the subsequently formed bit line contact structure, and does not occupy the formation of the word line structure 130 area, and will not affect the performance of the word line structure 130 .
  • the present disclosure increases the bottom area of the bit line contact opening by using the bit line contact opening with the recessed area and the raised area, so as to increase the contact area of the bit line contact structure formed by filling the bit line contact opening subsequently, thereby reducing the subsequent size of the bit line contact opening. Contact resistance of the formed bit line contact structure.
  • the bottom area of the bit line contact opening is increased by forming a bit line contact opening with a recessed area and a raised area at the bottom, so that the subsequent filling of the bit line contact
  • the contact area of the bit line contact structure formed by the opening is increased, thereby reducing the contact resistance of the subsequently formed bit line contact structure.

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Abstract

本公开实施例提供一种半导体结构的形成方法及半导体结构，其中，半导体结构的形成方法，包括：提供基底，在基底表面形成介质层；在介质层表面形成掩膜层，掩膜层内具有贯穿掩膜层厚度的第一开口；在第一开口的侧壁形成第一阻挡层，第一阻挡层围成第二开口；形成填充第二开口的第二阻挡层；采用第一刻蚀工艺，去除第一阻挡层和第二阻挡层，直至第一阻挡层或第二阻挡层被完全去除；去除第一开口暴露出的介质层和部分基底，形成位线接触开口，位线接触开口的底部具有凸起区域和凹陷区域，凸起区域和凹陷区域具有高度差。

Description

半导体结构的形成方法及半导体结构
本申请基于申请号为202110214102.3、申请日为2021年02月25日、申请名称为“半导体结构的形成方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，其全部内容在此引入本申请作为参考。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)的线宽逐渐减小，所需形成的位线结构的尺寸减小，导致所需形成的位线接触结构的尺寸减小，而位线接触结构的尺寸减小导致位线接触结构的接触电阻增大，从而影响后续形成的半导体结构的电性能，进而导致半导体结构的良率降低。
在位线接触结构尺寸减小的前提下，如何减小位线接触结构的接触电阻，是当前亟待解决的问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构的形成方法及半导体结构，通过增大位线接触开口底部接触面积的方式减小位线接触结构的接触电阻。
本公开的实施例的第一方面提供了一种半导体结构的形成方法，包括：提供基底，在基底表面形成介质层；在介质层表面形成掩膜层，掩膜层内具有贯穿掩膜层厚度的第一开口；在第一开口的侧壁形成第一阻挡层，第一阻挡层围成第二开口；形成填充第二开口的第二阻挡层；采用第一刻蚀工艺，去除第一阻挡层和第二阻挡层，直至第一阻挡层或第二阻挡层被完全去除，第一刻蚀工艺去除第一阻挡层的速率和去除第二 阻挡层的速率不同；去除第一开口暴露出的介质层和部分基底，形成位线接触开口，位线接触开口的底部具有凸起区域和凹陷区域，凸起区域和凹陷区域具有高度差。
本公开的第二方面提供了一种半导体结构，包括：基底，基底中具有有源区，以及暴露出有源区的第一接触开口；第一接触开口底部包括第一区域和第二区域，第一区域和第二区域具有高度差；介质层，位于基底表面，介质层中具有贯穿介质层的第二接触开口，第二接触开口暴露出第一接触开口，第二接触开口与第一接触开口构成位线接触开口。
本公开实施例通过具有凹陷区域和凸起区域的位线接触开口，以增大位线接触开口的底部面积，使后续填充位线接触开口形成的位线接触结构的接触面积增大，从而减小后续形成的位线接触结构的接触电阻。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的基底的俯视结构示意图；
图2、图4、图6、图8、图10、图12、图14、图16、图18、图20、图22和图24为本公开一实施例提供的半导体结构的形成方法中，各步骤对应的沿AA1方向的剖面结构示意图；
图3、图5、图7、图9、图11、图13、图15、图17、图19、图21、图23和图25为本公开一实施例提供的半导体结构的形成方法中，各步骤对应的沿BB1方向的剖面结构示意图。
附图标记：
100、基底；110、浅沟槽隔离结构；120、有源区；130、字线结构；
101、介质层；102、掩膜层；103、第一阻挡层；104、第二阻挡层；105、位线接触开口；112、第一开口；122、第二开口；115、凸起区域； 125、凹陷区域。
具体实施方式
随着动态随机存取存储器(DynamicRandomAccessMemory，DRAM)的线宽逐渐减小，所需形成的位线结构的尺寸减小，导致所需形成的位线接触结构的尺寸减小，而位线接触结构的尺寸减小导致位线接触结构的接触电阻增大，从而影响后续形成的半导体结构的电性能，进而导致半导体结构的良率降低。
本公开一实施例提供了一种半导体结构的形成方法，包括：提供基底，在基底表面形成介质层；在介质层表面形成掩膜层，掩膜层内具有贯穿掩膜层厚度的第一开口；在第一开口的侧壁形成第一阻挡层，第一阻挡层围成第二开口；形成填充第二开口的第二阻挡层；采用第一刻蚀工艺，去除第一阻挡层和第二阻挡层，直至第一阻挡层或第二阻挡层被完全去除，第一刻蚀工艺去除第一阻挡层的速率和去除第二阻挡层的速率不同；去除第一开口暴露出的介质层和部分基底，形成位线接触开口，位线接触开口的底部具有凸起区域和凹陷区域，凸起区域和凹陷区域具有高度差。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的基底的俯视结构示意图，图2、图4、图6、图8、图10、图12、图14、图16、图18、图20、图22和图24为本实施例提供的半导体结构的形成方法中，各步骤对应的沿AA1方向的剖面结构示意图，图3、图5、图7、图9、图11、图13、图15、图17、图19、图21、图23和图25为本实施例提供的半导体结构的形成方法中，各步骤对应的沿BB1方向的剖面结构示意图，以下结合附图对本实施例提供的一种半导体结构的形成方法作进一步详细说明，具体如下：
参考图1，提供基底100，基底100内包括浅沟槽隔离结构110、有源区120和字线结构130。
基底100的材料可以包括硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
基底100内多个有源区120相互平行间隔排布。需要说明的是，基底100中还包括除浅沟槽隔离结构110、有源区120和字线结构130外的其他存储器结构，由于其他存储器结构并不涉及到本公开的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除浅沟槽隔离结构110、有源区120和字线结构130外的其他存储器结构，用于存储器的正常运行。
本实施例以AA1截面的剖面结构和BB1截面的剖面结构，对本实施例提供的半导体结构的形成方法进行详细说明，其中AA1截面即位线结构延伸方向上的截面，BB1截面即字线结构延伸方向上的截面。字线结构130为埋入式字线结构，位于基底100中，字线结构103间隔穿过有源区120和浅沟槽隔离结构110，在AA1截面(参考图2)的剖面示意图中，字线结构130位于浅沟槽隔离结构110中；需要说明的是，在基底100的其他剖面示意图中，字线结构130可以位于有源区120中。
参考图2和图3，在基底100表面形成介质层101；其中，参考图2，部分介质层101还覆盖字线结构130，用于字线结构130与基底100顶部导电结构的电隔离。
参考图4和图5，在介质层101表面形成掩膜层102，掩膜层102内具有贯穿掩膜层102厚度的第一开口112；掩膜层102和第一开口112用于定义位线接触开口的位置。
在一个例子中，形成具有贯穿掩膜层102厚度的第一开口112，包括：在掩膜层102顶部形成图形化的光刻胶，基于图形化的光刻胶形成贯穿掩膜层102厚度的第一开口112。另外，需要说明的是，在本实施例中，掩膜层102为单层结构；在其他实施例中，掩膜层也可以为多层掩膜结构。
参考图6～图9，在第一开口112的侧壁形成第一阻挡层103，第一阻挡 层103围成第二开口122。
在一个例子中，参考图6和图7，在第一开口112的侧壁形成第一阻挡层103，包括以下步骤：形成覆盖掩膜层102顶部表面，且覆盖第一开口112侧壁和底部的第一阻挡膜(未图示)，第一阻挡膜(未图示)围成第二开口122，在平行于基底表面方向上，第二开口122的宽度小于第一开口112的宽度；去除位于掩膜层102顶部表面和第一开口112底部的第一阻挡膜(未图示)，形成第一阻挡层103。
在另一例子中，参考图8和图9，第一阻挡层103还位于第一开口112底部，此时在第一开口112的侧壁形成第一阻挡层103，包括以下步骤：形成覆盖掩膜层102顶部表面，且覆盖第一开口112侧壁和底部的第一阻挡膜(未图示)，第一阻挡膜(未图示)围成第二开口122，在平行于基底表面方向上，第二开口122的宽度小于第一开口112的宽度；去除位于掩膜层102顶部表面的第一阻挡膜(未图示)，形成第一阻挡层103。
在本实施例中，在平行于基底100表面方向上，第一阻挡层103的宽度B为5nm～20nm，例如8nm、11nm、14nm或17nm。第一阻挡层103的宽度若小于5nm，可能导致后续刻蚀第一阻挡层103形成的位线接触开口的凹陷区域的尺寸过小，在填充位线接触开口形成位线接触结构的过程中，位线接触结构无法完全填充凹陷区域，从而导致位线接触结构出现填充缺陷；第一阻挡层103的宽度若大于20nm，导致后续填充第一阻挡层103间隙形成的第二阻挡层的尺寸过小，进而导致刻蚀第二阻挡层形成的位线接触开口的凹陷区域的尺寸过小，在填充位线接触开口形成位线接触结构的过程中，位线接触结构无法完全填充凹陷区域，从而出现半导体结构缺陷。
参考图10和图11，形成填充第二开口122(参考图6)的第二阻挡层104。
在一个例子中，形成填充第二开口122(参考图6)的第二阻挡层104，包括以下步骤：形成填充第二开口122(参考图6)且覆盖第一阻挡层103的第二阻挡膜(未图示)，第二阻挡膜(未图示)的材料与第一阻挡层103的材料具有刻蚀选择比，去除高于第一阻挡层103的第二阻挡膜(未图示)，剩余的第二阻挡膜(未图示)作为第二阻挡层104。
在一个例子中，第一阻挡层103和第二阻挡层104的刻蚀选择比的范围 为1：1.1至1：3；在另一个例子中，第一阻挡层103和第二阻挡层104的刻蚀选择比的范围为1.1：1至3：1。即第一阻挡层103和第二阻挡层104存在刻蚀选择比，包括第一阻挡层103的被刻蚀速率大于第二阻挡层104的被刻蚀速率，或第一阻挡层103的被刻蚀速率小于第二阻挡层104的被刻蚀速率。
参考图12～图25，采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103或第二阻挡层104被完全去除，第一刻蚀工艺去除第一阻挡层103的速率和去除第二阻挡层104的速率不同；去除第一开口112暴露出的介质层101和部分基底100，形成位线接触开口105，位线接触开口105底部具有凸起区域115和凹陷区域125，凸起区域115和凹陷区域125具有高度差。
在一个例子中，在垂直于基底表面的方向上，位线接触开口105的深度为20nm～40nm，例如25nm、30nm或35nm。
在本实施例中，凸起区域115和凹陷区域125的高度差为1nm～15nm，例如，3nm、5nm、7nm、9nm、11nm或13nm。通过凸起区域115和凹陷区域125的高度差控制，实现位线接触开口105底部面积变化的可控性。另外，若凸起区域115和凹陷区域125的高度差小于1nm，位线接触开口105底部增加的面积可忽略不计，此时对填充位线接触开口105形成位线接触结构的接触电阻的改善可忽略不计，即位线接触结构的接触电阻依然很大，影响半导体结构的电性能；若凸起区域115和凹陷区域125的高度差大于15nm，此时凹陷区域125与凸起区域115之间的间隙的深宽比较大，后续填充位线接触开口105形成的位线接触结构难以完全填充，从而导致结构缺陷，影响半导体结构的良率。
采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103或第二阻挡层104被完全去除，包括：采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103或第二阻挡层中被刻蚀速率快的一者被完全去除；或采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103或第二阻挡层104被刻蚀速率慢的一者被完全去除。
在一个具体的例子中，本示例以第二阻挡层104的被刻蚀速率大于第一 阻挡层103的被刻蚀速率为例进行详细说明，参考图12～图19，采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103和第二阻挡层104中被刻蚀速率快的一者完全去除。
参考图12和图13，采用第一刻蚀工艺同时对第一阻挡层103和第二阻挡层104进行刻蚀，当第二阻挡层104被完全去除，停止第一刻蚀工艺，此时第一阻挡层103由于刻蚀速率小于第二阻挡层104的刻蚀速率，第一阻挡层103存在残留。
在本实施例中，第一刻蚀工艺采用的刻蚀气体至少包括氧气和碳氟气体的混合气体，且第一刻蚀工艺的刻蚀时间为20～60s，例如30s、40s或50s。
参考图14和图15，采用第二刻蚀工艺刻蚀剩余的第一阻挡层103或第二阻挡层104，并刻蚀第一开口112暴露出的介质层，直至暴露出基底100。
在本示例中，由于第一刻蚀工艺对第一阻挡层103的刻蚀存在刻蚀残留，导致第二刻蚀工艺在执行过程中，第一开口112底部中间区域的高度始终低于第一开口112底部边缘区域的高度，直至第一开口112底部中间区域暴露出基底100，此时第一开口112底部边缘区域的介质层101存在残留。
参考图16和图17，采用第三刻蚀工艺刻蚀第一开口112暴露出的预设厚度的基底100，形成位线接触开口105。
由于第二刻蚀工艺对第一开口112底部边缘区域的刻蚀存在刻蚀残留，导致第三刻蚀工艺执行过程中，第一开口112底部中间区域的高度始终低于第一开口112底部边缘区域的高度，直至形成位线接触开口105，此时底部高度较高的区域形成凸起区域115，底部高度较低的区域形成凹陷区域125。
参考图18和图19，去除掩膜层102。
需要说明的是，上述刻蚀示例以第二阻挡层104的被刻蚀速率大于第一阻挡层103的被刻蚀速率进行具体介绍，在其他实施里中，上述刻蚀示例同样适用于第二阻挡层104的被刻蚀速率小于第一阻挡层103的被刻蚀速率的情况。
在另一个具体的例子中，本示例以第二阻挡层104的被刻蚀速率小于第一阻挡层103的被刻蚀速率为例进行详细说明，参考图20～图25，采用第一刻蚀工艺，去除第一阻挡层103和第二阻挡层104，直至第一阻挡层103或 第二阻挡层104中被刻蚀速率慢的一者完全去除。
参考图20和图21，采用第一刻蚀工艺同时对第一阻挡层103和第二阻挡层104进行刻蚀，当第二阻挡层104被完全去除，停止第一刻蚀工艺，此时第一阻挡层103由于刻蚀速率大于第二阻挡层104的刻蚀速率，第一阻挡层103底部的介质层101存在过刻蚀的现象；即去除第一阻挡层103和第二阻挡层104的过程中，部分介质层101被去除，被刻蚀的介质层101位于第一阻挡层103或第二阻挡层104中被刻蚀速率较快的一者底部。
在本实施例中，第一刻蚀工艺采用的刻蚀气体至少包括氧气和碳氟气体的混合气体，且第一刻蚀工艺的刻蚀时间为20～60s，例如30s、40s或50s。
参考图22和图23，采用第二刻蚀工艺刻蚀第一开口112暴露出的剩余的介质层101，直至暴露出基底100。
此时，第二刻蚀工艺持续对介质层101进行刻蚀，导致对介质层101的刻蚀过程中，第一开口112底部边缘区域的高度始终低于第一开口112底部中间区域的高度，当第一开口112底部边缘区域的介质层101被刻蚀完后，第一开口112底部中间区域的介质层101存在残留；当第一开口112底部中间区域的介质层101被刻蚀完后，第一开口112底部边缘区域的基底100存在过刻蚀的现象。
采用第三刻蚀工艺刻蚀第一开口112暴露出的预设厚度的基底100，形成位线接触开口105。
由于第二刻蚀工艺对第一开口112的刻蚀会导致第一开口112底部边缘区域的基底100存在过刻蚀现象，在第三刻蚀工艺刻蚀预设厚度的基底100的过程中，第一开口112底部中间区域的高度始终高于第一开口112底部边缘区域的高度，直至形成位线接触开口105，此时底部高度较高的区域形成凸起区域115，底部高度较低的区域形成凹陷区域125。
参考图24和图25，去除掩膜层102。
需要说明的是，上述刻蚀示例以第二阻挡层104的被刻蚀速率小于第一阻挡层103的被刻蚀速率进行具体介绍，在其他实施里中，上述刻蚀示例同样适用于第二阻挡层104的被刻蚀速率大于第一阻挡层103的被刻蚀速率的情况。
需要说明的是，本实施例通过两个字线结构130之间形成凹凸状的位线 结构开口105，以增大后续形成的位线接触结构的接触面积，并没有占用字线结构130的形成区域，不会对字线结构130的性能产生影响。
相对于相关技术而言，通过形成底部具有凹陷区域和凸起区域的位线接触开口，以增大位线接触开口的底部面积，使后续填充位线接触开口形成的位线接触结构的接触面积增大，从而减小后续形成的位线接触结构的接触电阻。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本公开另一实施例涉及一种半导体结构，包括：基底，基底中具有有源区，以及暴露出有源区的第一接触开口；第一接触开口底部包括第一区域和第二区域，第一区域和第二区域具有高度差；介质层，位于基底表面，介质层中具有贯穿介质层的第二接触开口，第二接触开口暴露出第一接触开口，第二接触开口与第一接触开口构成位线接触开口。
图18和图19为本实施例提供的半导体结构的结构示意图，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图1、图18和图19，半导体结构，包括：
基底100，基底100中具有有源区120，以及暴露出有源区120的第一接触开口(未图示)。
基底100的材料可以包括硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
基底100内多个有源区120相互平行间隔排布。需要说明的是，基底100中还包括除浅沟槽隔离结构110、有源区120和字线结构130外的其他存储器结构，由于其他存储器结构并不涉及到本公开的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除浅沟槽隔离结构110、有源区120和字线结构130外的其他存储器结构，用于存储器的正常运 行。
介质层101，位于基底100表面，介质层101中具有贯穿介质层101的第二接触开口(未图示)，第二接触开口(未图示)暴露出第一接触开口(未图示)，第二接触开口(未图示)与第一接触开口(未图示)构成位线接触开口105。
其中，第一接触开口(未图示)底部包括第一区域和第二区域，第一区域和第二区域具有高度差，即位线接触开口105底部包括第一区域和第二区域，第一区域和第二区域具有高度差。
在本实施例中，第一区域为凸起区域115，第二区域为凹陷区域125，第一区域环绕第二区域设置；需要说明的是，本实施例主要在于体现位线接触开口105底部包括高度不同的第一区域和第二区域，在其他实施例中，可以是第一区域为凹陷区域，第二区域为凸起区域；另外，在其他实施例中，第一区域和第二区域可以是拼接设置在位线接触开口底部。
在本实施例中，在平行于基底100表面方向上，第一区域的宽度为5nm～20nm，例如8nm、11nm、14nm或17nm。第一区域的宽度若小于5nm，可能导致后续刻蚀第一区域形成的位线接触开口的凹陷区域的尺寸过小，在填充位线接触开口形成位线接触结构的过程中，位线接触结构无法完全填充凹陷区域，从而导致位线接触结构出现填充缺陷；第一区域的宽度若大于20nm，导致后续填充第一区域间隙形成的第二阻挡层的尺寸过小，进而导致刻蚀第二阻挡层形成的位线接触开口的凹陷区域的尺寸过小，在填充位线接触开口形成位线接触结构的过程中，位线接触结构无法完全填充凹陷区域，从而出现半导体结构缺陷。
另外，在本实施例中，在垂直于基底表面的方向上，位线接触开口105的深度为20nm～40nm，例如25nm、30nm或35nm；第一区域和第二区域的高度差为1nm～15nm，例如，3nm、5nm、7nm、9nm、11nm或13nm。通过凸起区域115和凹陷区域125的高度差控制，实现位线接触开口105底部面积变化的可控性。另外，若凸起区域115和凹陷区域125的高度差小于1nm，位线接触开口105底部增加的面积可忽略不计，此时对填充位线接触开口105形成位线接触结构的接触电阻的改善可忽略不计，即位线接触结构的接触电阻依然很大，影响半导体结构的电性能；若凸起区域115和凹陷区 域125的高度差大于15nm，此时凹陷区域125与凸起区域115之间的间隙的深宽比较大，后续填充位线接触开口105形成的位线接触结构难以完全填充，从而导致结构缺陷，影响半导体结构的良率。
需要说明的是，本实施例通过两个字线结构130之间形成凹凸状的位线结构开口105，以增大后续形成的位线接触结构的接触面积，并没有占用字线结构130的形成区域，不会对字线结构130的性能产生影响。
本公开通过具有凹陷区域和凸起区域的位线接触开口，以增大位线接触开口的底部面积，使后续填充位线接触开口形成的位线接触结构的接触面积增大，从而减小后续形成的位线接触结构的接触电阻。
由于一实施例与本实施例相互对应，因此本实施例可与一实施例互相配合实施。一实施例中提到的相关技术细节在本实施例中依然有效，在一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在一实施例中。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开 中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的形成方法及半导体结构中，通过形成底部具有凹陷区域和凸起区域的位线接触开口，以增大位线接触开口的底部面积，使后续填充位线接触开口形成的位线接触结构的接触面积增大，从而减小后续形成的位线接触结构的接触电阻。

Claims (15)

  1. 一种半导体结构的形成方法，所述半导体结构的形成方法包括：
    提供基底，在所述基底表面形成介质层；
    在所述介质层表面形成掩膜层，所述掩膜层内具有贯穿所述掩膜层厚度的第一开口；
    在所述第一开口的侧壁形成第一阻挡层，所述第一阻挡层围成第二开口；
    形成填充所述第二开口的第二阻挡层；
    采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层被完全去除，所述第一刻蚀工艺去除所述第一阻挡层的速率和去除所述第二阻挡层的速率不同；
    去除所述第一开口暴露出的介质层和部分所述基底，形成位线接触开口，所述位线接触开口的底部具有凸起区域和凹陷区域，所述凸起区域和所述凹陷区域具有高度差。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，所述高度差为1nm～15nm。
  3. 根据权利要求1所述的半导体结构的形成方法，其中，所述第一刻蚀工艺采用的刻蚀气体为至少包括氧气和碳氟气体的混合气体。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述第一刻蚀工艺的刻蚀时间为20s～60s。
  5. 根据权利要求1所述的半导体结构的形成方法，还包括：
    所述第一阻挡层还位于所述第一开口底部；
    在所述第一开口的侧壁形成第一阻挡层，包括以下步骤：
    形成覆盖所述掩膜层顶部表面，且覆盖所述第一开口侧壁和底部的第一阻挡膜，所述第一阻挡膜围成所述第二开口，在平行于所述基底表面方向上，所述第二开口的宽度小于所述第一开口的宽度；
    去除位于所述掩膜层顶部表面的所述第一阻挡膜，形成所述第一阻挡层。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，在平行于所述基底表面方向上，所述第一阻挡层的宽度为5nm～20nm。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，形成填充所述第二开口的第二阻挡层，包括以下步骤：
    形成填充所述第二开口且覆盖所述第一阻挡层的第二阻挡膜，所述第二阻挡膜的材料与所述第一阻挡层的材料具有刻蚀选择比；
    去除高于所述第一阻挡层的所述第二阻挡膜，剩余所述第二阻挡膜作为所述第二阻挡层。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，所述第一阻挡层和所述第二阻挡层的刻蚀选择比的范围为1：1.1至1：3，或者1.1：1至3：1。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层被完全去除，包括：
    采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层中被刻蚀速率快的一者完全去除；
    或采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层被刻蚀速率慢的一者完全去除。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，若采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层中被刻蚀速率快的一者完全去除，包括：
    去除所述第一开口暴露出的介质层和部分所述基底，形成位线接触开口，包括以下步骤：
    采用第二刻蚀工艺刻蚀剩余的所述第一阻挡层或所述第二阻挡层，并刻蚀所述第一开口暴露出的所述介质层，直至暴露出所述基底；
    采用第三刻蚀工艺刻蚀所述第一开口暴露出的预设厚度的所述基底，形成所述位线接触开口。
  11. 根据权利要求9所述的半导体结构的形成方法，其中，若采用第一刻蚀工艺，去除所述第一阻挡层和所述第二阻挡层，直至所述第一阻挡层或所述第二阻挡层中被刻蚀速率慢的一者完全去除，包括：
    其中，去除所述第一阻挡层和所述第二阻挡层的过程中，部分所述介质层被去除，被刻蚀的所述介质层位于所述第一阻挡层或所述第二阻挡层中被刻蚀速率较快的一者底部；
    去除所述第一开口暴露出的介质层和部分所述基底，形成位线接触开口，包括以下步骤：
    采用第二刻蚀工艺刻蚀所述第一开口暴露出的剩余的所述介质层，直至暴露出所述基底；
    采用第三刻蚀工艺刻蚀所述第一开口暴露出的预设厚度的所述基底，形成所述位线接触开口。
  12. 一种半导体结构，其所述半导体结构包括：
    基底，所述基底中具有有源区，以及暴露出所述有源区的第一接触开口；
    所述第一接触开口底部包括第一区域和第二区域，所述第一区域和所述第二区域具有高度差；
    介质层，位于所述基底表面，所述介质层中具有贯穿所述介质层的第二接触开口，第二接触开口暴露出所述第一接触开口，所述第二接触开口与所述第一接触开口构成位线接触开口。
  13. 根据权利要求12所述的半导体结构，其中，所述第一区域环绕所述第二区域设置。
  14. 根据权利要求13所述的半导体结构，其中，在平行于所述基底表面的方向上，所述第一区域的宽度为5nm～20nm。
  15. 根据权利要求12所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述位线接触开口的深度为20nm～40nm，所述高度差为1nm～15nm。
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