WO2023137835A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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WO2023137835A1
WO2023137835A1 PCT/CN2022/078996 CN2022078996W WO2023137835A1 WO 2023137835 A1 WO2023137835 A1 WO 2023137835A1 CN 2022078996 W CN2022078996 W CN 2022078996W WO 2023137835 A1 WO2023137835 A1 WO 2023137835A1
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conductive
layer
bit line
structures
groove
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PCT/CN2022/078996
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English (en)
French (fr)
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李广济
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长鑫存储技术有限公司
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Priority to EP22776854.6A priority Critical patent/EP4239667A4/en
Priority to US17/804,937 priority patent/US20230232615A1/en
Publication of WO2023137835A1 publication Critical patent/WO2023137835A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to but not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • Dynamic random access memory (Dynamic random access memory, referred to as DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices. Wherein, the DRAM includes a plurality of storage units repeatedly arranged.
  • the disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a method for fabricating a semiconductor structure, including:
  • a substrate is provided, and a plurality of active regions are arranged in the substrate, and the plurality of active regions are arranged at intervals along the first direction;
  • bit line structures are arranged at intervals along the first direction;
  • a plurality of barrier structures arranged at intervals along the first direction are formed on the contact structure, the barrier structures are correspondingly arranged and connected to the bit line structure, and a first groove is formed between any two adjacent barrier structures;
  • a conductive structure is formed in the first groove, wherein the conductive structure includes a protective layer and a conductive part, and the protective layer covers sidewalls and bottom walls of the conductive part.
  • the forming a conductive structure in the first groove includes:
  • the protective layer in the first groove, covers the bottom surface and the sidewall of the first groove, and the protective layer in the first groove forms a second groove;
  • the cross-sectional shape of the conductive part includes a Z-shape, an L-shape or an inverted L-shape.
  • forming the protective layer in the first groove includes:
  • the protection layer is formed in the first groove by atomic layer deposition process.
  • filling the second groove with a conductive material to form the conductive part includes:
  • the formation of a plurality of barrier structures arranged at intervals along the first direction on the contact structure includes:
  • the top surface of the dielectric layer is higher than the top surface of the bit line structure
  • the dielectric layer is removed to form the first groove, and the first groove exposes the top surface of the contact structure.
  • a projection of the contact structure on the substrate partially coincides with a projection of the active region on the substrate.
  • the providing substrate wherein a plurality of active regions are arranged in the substrate, and the plurality of active regions are arranged at intervals along the first direction, includes:
  • An isolation structure is formed in the isolation trench, and the active region is formed on the substrate between adjacent isolation structures.
  • the forming a plurality of bit line structures on the substrate includes:
  • a spacer layer is formed on the sidewall of the first conductive layer, the sidewall of the second conductive layer, and the sidewall and top surface of the isolation layer.
  • the bit line structure and the contact structure before forming the first dielectric layer on the bit line structure and the contact structure, further comprising:
  • the forming a contact structure between adjacent bit line structures includes:
  • the contact structure is formed by removing part of the initial contact structure, and the top surface of the contact structure is lower than the top surface of the bit line structure.
  • the manufacturing method of the semiconductor structure further includes:
  • An insulating layer is formed on the conductive structure, and the insulating layer covers the top surface of the conductive structure.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • the substrate is provided with a plurality of active regions, and the plurality of active regions are arranged at intervals along the first direction;
  • a plurality of bit line structures are arranged on the substrate and connected to the active region, and the plurality of bit line structures are arranged at intervals along the first direction;
  • the plurality of contact structures are disposed on the substrate and located between adjacent bit line structures;
  • barrier structures located above the contact structure, the barrier structures are correspondingly arranged and connected to the bit line structure;
  • a plurality of conductive structures are arranged on the contact structure and are electrically connected to the contact structure, each of the conductive structures is spaced apart from each of the barrier structures, wherein the conductive structure includes a protective layer and a conductive part, and the protective layer covers the side wall and the bottom wall of the conductive part.
  • a projection of the contact structure on the substrate partially coincides with a projection of the active region on the substrate.
  • the longitudinal cross-sectional shape of the conductive portion includes a Z-shape, an L-shape or an inverted L-shape.
  • the semiconductor structure further includes an insulating layer disposed on top surfaces of the conductive structure and the bit line structure.
  • Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram of forming an initial contact structure and a sidewall layer of a single-layer structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram of forming an initial contact structure and a sidewall layer of a multilayer structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram of forming a contact structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of removing part of the spacer layer in the method of manufacturing the semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a schematic diagram of forming a dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 7 is a schematic diagram of forming a third groove in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 8 is a schematic diagram of forming a barrier structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a schematic diagram of forming a first groove in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of forming a protective layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram of forming an initial conductive portion in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 12 is a schematic diagram of forming a conductive portion and a conductive structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 13 is a schematic diagram of forming an insulating layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Conductive structure 111.
  • Protective layer 111.
  • Insulation layer 511. First conductive layer;
  • Dynamic random access memory (Dynamic random access memory, referred to as DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices. Wherein, the DRAM includes a plurality of storage units repeatedly arranged.
  • metal elements in adjacent metal layers such as tungsten are not provided with a protective layer, or only part of the protective layer is provided to etch the above-mentioned metal elements, and the tungsten element is relatively active and easily penetrates into the dielectric under the condition of voltage difference or high temperature, forming tungsten whiskers, resulting in leakage, resulting in charge leakage.
  • the intensity of etching metal is increased, the metal that needs to be kept next to the metal residue will be etched away due to the fine pattern layer, resulting in pattern breakage, which reduces the performance and yield of the semiconductor structure.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure will be described below with reference to FIGS. 1-13 .
  • This embodiment does not limit the semiconductor structure.
  • the following will introduce the semiconductor structure as a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment may also be other structures.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S100 providing a substrate, in which a plurality of active regions are arranged, and the plurality of active regions are arranged at intervals along a first direction.
  • Step S200 forming a plurality of bit line structures on the substrate, the plurality of bit line structures are arranged at intervals along a first direction.
  • Step S300 Form a contact structure between adjacent bit line structures.
  • Step S400 Form a plurality of barrier structures arranged at intervals along the first direction on the contact structure, the barrier structures are correspondingly arranged and connected to the bit line structures, and a first groove is formed between any two adjacent barrier structures.
  • Step S500 forming a conductive structure in the first groove, the conductive structure includes a protective layer and a conductive part, and the protective layer covers sidewalls and bottom walls of the conductive part.
  • the conductive structure is formed through the above steps, and there is no specific limitation on the specific implementation method and structure of the conductive structure, as long as the protective layer of the conductive structure can be ensured to cover the sidewall and bottom wall of the conductive structure.
  • the conductive part is protected by the protective layer, thereby improving the etching parameters in the etching process, preventing metal residues, thereby avoiding leakage or short circuit in the semiconductor structure, thereby improving the performance and yield of the semiconductor structure.
  • this embodiment is a further description of step S100 above, and the following structure-related drawings describe the implementation method of step S100 in this embodiment in detail.
  • a substrate 10 is provided.
  • the substrate 10 is used as a supporting component of the DRAM for supporting other components disposed thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • silicon material is used for the substrate 10
  • the silicon material is used as the substrate 10 in this embodiment to facilitate the understanding of subsequent forming methods by those skilled in the art, and does not constitute a limitation.
  • a suitable material for the substrate 10 can be selected according to requirements.
  • a plurality of active regions 20 are disposed in the substrate 10 , and the plurality of active regions 20 are arranged at intervals along the first direction X.
  • the first direction X is an extension direction parallel to the front side of the substrate 10 .
  • the formation of the active region 20 can adopt the following methods:
  • a layered photoresist layer and a mask layer are deposited on the top surface of the substrate 10 by an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process, and a mask pattern is formed on the photoresist layer by exposure or development etching, and a part of the photoresist layer and a part of the mask layer are removed by etching with the photoresist layer having the mask pattern as a mask plate, thereby forming a plurality of isolation trenches 30 arranged at intervals along the first direction X on the substrate 10. Then, the remaining photoresist layer and mask layer are removed through an etching process.
  • the isolation structure 40 is deposited in the isolation trench 30 by an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process. Active regions 20 are formed on the substrate 10 between adjacent isolation structures 40 .
  • the isolation structure 40 may use insulating materials, such as silicon dioxide, silicon oxynitride, and the like.
  • the isolation structure 40 can be used as a barrier isolation layer, which can isolate multiple active regions 20 insulatively, and at the same time, can also avoid the occurrence of sidewall layer leakage current in the subsequent semiconductor structure, thereby ensuring the performance and yield of the semiconductor structure.
  • this embodiment is a further description of step S200 above, and the following structure-related drawings describe the implementation method of step S200 in this embodiment in detail.
  • a plurality of bit line structures 50 are formed on the substrate 10 , and the plurality of bit line structures 50 are arranged at intervals along the first direction X. As shown in FIG. 2 , in some embodiments, a plurality of bit line structures 50 are formed on the substrate 10 , and the plurality of bit line structures 50 are arranged at intervals along the first direction X. As shown in FIG. 2 , in some embodiments, a plurality of bit line structures 50 are formed on the substrate 10 , and the plurality of bit line structures 50 are arranged at intervals along the first direction X. As shown in FIG.
  • bit line contact 53 may be formed by forming a via hole through an etching process, and then depositing a contact material in the via hole.
  • the formation of the bit line structure 50 may adopt the following method:
  • a first initial conductive layer, a second initial conductive layer and an initial isolation layer are sequentially deposited on the substrate 10 by atomic layer deposition, physical vapor deposition or chemical vapor deposition.
  • patterning is performed on the first initial conductive layer, the second initial conductive layer and the initial isolation layer, so as to form a plurality of first trenches (not shown) arranged at intervals along the first direction X on the first initial conductive layer, the second initial conductive layer and the initial isolation layer.
  • a spacer layer 52 is formed on the sidewall of the first trench by an atomic layer deposition process, the retained first initial conductive layer forms a first conductive layer 511 , the retained second initial conductive layer forms a second conductive layer 512 , and the retained initial isolation layer forms an isolation layer 513 .
  • the first conductive layer 511 , the second conductive layer 512 and the isolation layer 513 are stacked to form the bit line 51 .
  • the sidewall layer 52 is disposed on the sidewalls of the first conductive layer 511 , the sidewalls of the second conductive layer 512 , and the sidewalls and top surfaces of the isolation layer 513 .
  • the bit line 51 and the spacer layer 52 form the bit line structure 50 , that is, the spacer layer 52 is a part of the bit line structure 50 .
  • the material of the first conductive layer 511 may include but not limited to tungsten, polysilicon, etc.
  • the material of the second conductive layer 512 may include but not limited to polysilicon, titanium nitride, tungsten, and the like.
  • the side wall layer 52 is formed by an atomic layer deposition process.
  • the atomic layer deposition process has the characteristics of slow deposition rate, high density of deposited film and good step coverage.
  • the sidewall layer 52 formed by the atomic layer deposition process can isolate and protect the bit line structure 50 under the condition that the thickness of the sidewall layer 52 is relatively thin, avoiding occupying a large space, and is beneficial to subsequent filling or formation of other structural layers.
  • the side wall layer 52 may be a single-layer structure or a multi-layer structure.
  • the material of the sidewall layer 52 may include but not limited to isolation materials such as silicon dioxide, borophosphosilicate glass, silicon nitride, or silicon oxynitride.
  • the side wall layer 52 may include a first side wall layer 521, a second side wall layer 522 and a third side wall layer 523, and the materials of the first side wall layer 521, the second side wall layer 522 and the third side wall layer 523 may be the same or different.
  • the materials of the first spacer layer 521 , the second sidewall layer 522 and the third sidewall layer 523 may include isolation materials such as silicon dioxide, borophosphosilicate glass, etc., so as to isolate the bit line structure 50 from subsequent structures such as contact structures.
  • the first spacer layer 521, the second sidewall layer 522, and the third sidewall layer 523 may include silicon nitride or silicon oxide, thereby forming a "NON" structure, such as a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer, wherein "O" represents silicon oxide, and "N" represents silicon nitride.
  • this embodiment is a further description of step S300 above, and the following structure-related drawings describe the implementation method of step S300 in this embodiment in detail.
  • an initial contact structure 61 may be formed between and on the adjacent bit line structures 50 .
  • the contact structure 60 may be a capacitive contact structure.
  • contact holes are formed between adjacent bit line structures 50 .
  • an initial contact structure 61 is deposited in the contact hole by using an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the initial contact structure 61 fills the entire contact hole, extends out of the contact hole, and covers the top surface of the bit line structure 50 .
  • the top surface of the contact structure 60 is lower than the top surface of the bit line structure 50 . It should be noted that, in an example, the top surface of the contact structure 60 may be flush with the top surface of the first conductive layer 511 or the second conductive layer 512 in the bit line structure 50, or, taking the direction from the bottom surface of the substrate 10 to the top surface of the substrate 10 as the extending direction, along the extending direction, the top surface of the contact structure 60 may be flush with any position in the first conductive layer 511 or the second conductive layer 512.
  • the top surface of the contact structure 60 is flush with the top surface of the isolation layer 513 in the bit line structure 50.
  • the spacer layer 52 is used to perform insulation isolation between the contact structure 60 and the bit line 51, so as to ensure the distance between the contact structure 60 and the adjacent bit line 51, and reduce the influence on the parasitic capacitance of the bit line 51.
  • the material of the contact structure 60 may include but not limited to polysilicon, titanium nitride or tungsten, etc., so as to ensure the electrical conductivity between the active region 20 and the subsequently formed semiconductor structure.
  • the projection of the contact structure 60 on the substrate 10 partially coincides with the projection of the active region 20 on the substrate 10 , thereby facilitating the alignment between the contact structure 60 and the active region 20 .
  • the lateral width of the contact structure 60 is greater than that of the bit line structure 50 , thereby reducing the difficulty of alignment between the contact structure 60 and the active region 20 .
  • the sidewall layer 52 covering the top surface of the isolation layer 513 and part of the sidewall of the isolation layer 513 is removed by etching, so as to facilitate subsequent formation of a barrier layer on the sidewall and part of the top surface of the isolation layer 513, and provide a good adhesion basis for the subsequent formation of a conductive structure.
  • this embodiment is a further description of step S400 above, and the following structure-related drawings describe the implementation method of step S400 in this embodiment in detail.
  • a plurality of barrier structures 70 arranged at intervals along the first direction X are formed on the contact structure 60 .
  • the plurality of barrier structures 70 are set in one-to-one correspondence with the plurality of bit line structures 50, and any barrier structure 70 is connected to the corresponding bit line structure 50.
  • the barrier structure 70 may be formed using the following methods:
  • the dielectric layer 80 is formed on the bit line structure 50 and the contact structure 60 by atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process. Wherein, the top surface of the dielectric layer 80 is higher than the top surface of the bit line structure 50 .
  • the material of the dielectric layer 80 may include, but is not limited to, silicon nitride, silicon dioxide, silicon oxynitride, or borophosphosilicate glass.
  • the dielectric layer 80 is patterned to form a plurality of third grooves 90 arranged at intervals on the dielectric layer 80 .
  • the third groove 90 is located between two adjacent bit line structures 50 , and the third groove 90 exposes part of the sidewall and part of the top surface of one side of the bit line structure 50 .
  • the barrier structure 70 is deposited in the third groove 90 by atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process.
  • the remaining dielectric layer 80 is removed by etching, that is, the dielectric layer 80 between any two adjacent barrier structures 70 is removed, so that the first groove 100 is formed between the adjacent barrier structures 70 .
  • the first groove 100 exposes the top surface of the contact structure 60 , so as to facilitate the subsequent formation of the conductive structure 110 in the first groove 100 .
  • the material of the dielectric layer 80 can be deposited from borophosphosilicate glass, and the dielectric layer 80 formed by this material is easy to be removed in the subsequent process steps. Therefore, the remaining dielectric layer 80 can be removed by wet etching. Utilizing the wet etching process with a high selectivity ratio, the etching time can be appropriately increased, so that the remaining dielectric layer 80 is completely removed, ensuring that the barrier structure 70 and the bit line structure 50 are not damaged while the dielectric layer 80 is completely removed, and the disconnection phenomenon is prevented.
  • the barrier structure 70 is deposited and formed in the third groove 90 .
  • an initial barrier structure (not shown) is deposited and formed in the third groove 90, on the bit line structure 50, and on the dielectric layer 80, part of the initial barrier structure is removed, and the remaining initial barrier structure forms the barrier structure 70.
  • the top surface of the barrier structure 70 is flush with the top surface of the dielectric layer 80.
  • the material of the initial barrier structure may include, but is not limited to, silicon nitride.
  • the initial barrier structure is partially removed to ensure the height dimension of the barrier structure 70 and to facilitate subsequent formation of other semiconductor structures on the barrier structure 70, thereby ensuring the performance and yield of the semiconductor structure.
  • this embodiment is a further description of step S500 above, and the following structure-related drawings describe the implementation method of step S500 in this embodiment in detail.
  • a conductive structure 110 is formed in the first groove 100 .
  • the conductive structure 110 includes a protective layer 111 and a conductive portion 112 , and the protective layer 111 covers sidewalls and bottom walls of the conductive portion 112 .
  • the formation of the conductive structure 110 may adopt the following methods:
  • a protective layer 111 is formed in the first groove 100 by a deposition process, and the protective layer 111 covers the bottom surface and the sidewall of the first groove 100 .
  • the protective layer 111 in the first groove 100 forms the second groove 120 .
  • the material of the protective layer 111 may include but not limited to titanium nitride, tantalum nitride, titanium, tantalum and the like.
  • a conductive material is filled in the second groove 120 by a deposition process to form the conductive portion 112 .
  • the conductive material may include but not limited to tungsten, polysilicon and the like.
  • the protective layer 111 is first formed on the sidewall and the bottom surface of the first groove 100, and then the conductive part 112 is formed on the protective layer 111, and the conductive part 112 is effectively isolated and protected by the protective layer 111, so as to avoid the leakage or short circuit caused by the conductive material in the conductive part 112, such as tungsten whiskers; on the other hand, the above-mentioned forming method of the conductive structure 110 is easy to control. , thereby improving the performance and yield of semiconductor structures.
  • the deposition of the protective layer 111 can be accomplished by atomic layer deposition.
  • the atomic layer deposition process has the characteristics of slow deposition rate, high density of deposited film and good step coverage. Forming the protective layer 111 by atomic layer deposition can effectively isolate and protect the conductive part 112 under the condition of thinner thickness, and at the same time, avoid occupying a large space, which is beneficial to the subsequent filling or formation of other structural layers.
  • the formation of the conductive part 112 may adopt the following methods:
  • the conductive material is filled in the second groove 120 by atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process, and the conductive material covers the surface of the protection layer 111 and fills the second groove 120 . That is to say, the above-mentioned conductive material is equivalent to forming the initial conductive part 1120 , and the initial conductive part 1120 fills the entire second groove 120 and covers the top surface of the protective layer 111 on the top surface of the barrier structure 70 .
  • part of the initial conductive part 1120 and part of the protection layer 111 are removed by chemical mechanical polishing, exposing the top surface of the barrier structure 70 . That is, the top surface of the retained initial conductive portion 1120 is flush with the top surface of the barrier structure 70 to form the conductive portion 112 , and the top surface of the retained protective layer 111 is flush with the top surface of the barrier structure 70 .
  • the initial conductive part 1120 is formed on the surface of the protective layer 111, and then part of the initial conductive part 1120 and part of the protective layer 111 are removed by chemical mechanical polishing, so that the top surface of the conductive part 112 and the remaining protective layer 111 are flush with the top surface of the barrier structure 70, thereby effectively controlling the formation quality and shape of the conductive part 112, thereby improving the performance and yield of the semiconductor structure.
  • the cross-sectional shapes of the conductive portion 112 include Z-shape, L-shape and inverted L-shape.
  • the above-mentioned Z-shaped, L-shaped, and inverted L-shaped conductive portion 112 facilitates the dislocation arrangement of other semiconductor structural components formed later, thereby improving the formation size or formation volume of the semiconductor structure.
  • an insulating layer 130 is formed on the conductive structure 110 by an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process, so as to facilitate subsequent formation of other structures of semiconductor structures on the conductive structure 110 or the insulating layer 130.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate 10 , a bit line structure 50 , a contact structure 60 , a barrier structure 70 and a conductive structure 110 .
  • a plurality of active regions 20 are arranged in the substrate 10 , and the plurality of active regions 20 are arranged at intervals along the first direction X. In this embodiment, insulation is implemented between any two adjacent active regions 20 through the isolation structure 40 .
  • bit line structures 50 There are multiple bit line structures 50 , and the multiple bit line structures 50 are disposed on the substrate 10 at intervals along the first direction X.
  • a plurality of bit line structures 50 are provided in one-to-one correspondence with a plurality of active regions 20, and the extending direction is from the bottom surface of the substrate 10 to the top surface of the substrate 10, and along the extending direction, the active regions 20 in the same extending direction are connected to the bit line structures 50 located above the active region 20.
  • the active region 20 may be connected to the bit line structure 50 through the bit line contact 53 .
  • the contact structure 60 is disposed on the substrate 10 , and there are multiple contact structures 60 . Wherein, a contact structure 60 is provided between any two adjacent bit line structures 50 .
  • barrier structures 70 located above the contact structure 60 , wherein the barrier structures 70 are correspondingly arranged and connected to the bit line structures 50 .
  • the conductive structure 110 is disposed on the contact structure 60 , and the plurality of conductive structures 110 are arranged in one-to-one correspondence with the plurality of contact structures 60 .
  • the conductive structure 110 is disposed on the contact structure 60 and is electrically connected to the contact structure 60 .
  • Each conductive structure 110 is spaced apart from each barrier structure 70 .
  • the conductive structure 110 includes a protective layer 111 and a conductive portion 112 , and the protective layer 111 covers sidewalls and bottom walls of the conductive portion 112 .
  • a protective layer is provided on the side wall and the bottom wall of the conductive part, and the conductive part is protected by the protective layer, so that the etching parameters in the etching process can be improved to prevent metal residues, thereby avoiding leakage or short circuit in the semiconductor structure, thereby improving the performance and yield of the semiconductor structure.
  • the projection of the contact structure 60 on the substrate 10 partially coincides with the projection of the active region 20 on the substrate 10 , thereby facilitating the alignment between the contact structure 60 and the active region 20 .
  • the lateral width of the contact structure 60 is greater than the lateral width of the bit line structure 50 , thereby reducing the difficulty of alignment between the contact structure 60 and the active region 20 .
  • the longitudinal cross-sectional shape of the conductive part 112 includes Z-shape, L-shape or inverted L-shape, which facilitates the dislocation arrangement of other semiconductor structural components formed later, thereby improving the formation size or formation volume of the semiconductor structure.
  • the semiconductor structure further includes an insulating layer 130 .
  • the insulating layer 130 is disposed on the top surfaces of the conductive structure 110 and the bit line structure 50 , so as to facilitate subsequent formation of other semiconductor structures on the conductive structure 110 or the bit line structure 50 or the insulating layer 130 .
  • orientations or positional relationships indicated by the terms “center”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “inner”, “outer”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present disclosure.
  • the protective layer is used to protect the conductive part, avoiding leakage or short circuit problems caused by metal residues in the etching process, thereby improving the performance and yield of the semiconductor structure.

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Abstract

本公开公布了一种半导体结构的制作方法及半导体结构，涉及半导体技术领域。该方法包括：提供基底，基底内设有沿第一方向间隔设置的有源区；于基底上形成间隔设置的位线结构；于相邻的位线结构之间形成接触结构；在接触结构上形成阻挡结构，阻挡结构与位线结构对应设置并相连，任意相邻的阻挡结构之间形成第一凹槽；于第一凹槽内形成导电结构，导电结构包括保护层和导电部，保护层包覆导电部的侧壁和底壁。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202210052781.3，申请日为2022年01月18日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。其中，动态随机存储器包括重复设置的多个存储单元。
随着电子产品日益朝向轻、薄、短、小发展，动态随机存取存储器组件的设计也朝着符合高集成度、高密度、小型化的趋势发展，半导体结构要求更加精细，重复图形多而密集，为了刻蚀后的存储单元尺寸的一致性，需要刻蚀质量要求很高的刻蚀工艺。而在小尺寸大数量的阵列图形刻蚀制程工艺中，存在有电荷泄露和图形断裂等问题，降低了半导体结构的性能和良率。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，包括：
提供基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置；
于所述基底上形成多个位线结构，多个所述位线结构沿所述第一方向间隔设置；
于相邻的所述位线结构之间形成接触结构；
在所述接触结构上形成沿所述第一方向间隔设置的多个阻挡结构，所述阻挡结构与所述位线结构对应设置并相连，任意相邻的两个所述阻挡结构之间形成第一凹槽；
于所述第一凹槽内形成导电结构，其中，所述导电结构包括保护层和导电部，所述保护层包覆所述导电部的侧壁和底壁。
根据本公开的一些实施例，所述于所述第一凹槽内形成导电结构，包括：
于所述第一凹槽内形成所述保护层，所述保护层覆盖所述第一凹槽的底面和侧壁，所述第一凹槽内的所述保护层形成第二凹槽；
于所述第二凹槽内填充导电材料，形成所述导电部。
根据本公开的一些实施例，以平行于所述第一方向的平面为截面，所述导电部的截 面形状包括Z型、L型或倒L型。
根据本公开的一些实施例，所述于所述第一凹槽内形成所述保护层，包括：
利用原子层沉积工艺于所述第一凹槽内形成所述保护层。
根据本公开的一些实施例，所述于所述第二凹槽内填充导电材料，形成所述导电部，包括：
于所述第二凹槽内填充导电材料，所述导电材料覆盖所述保护层的表面并填充满所述第二凹槽；
去除部分所述保护层和部分所述导电材料形成所述导电部，暴露所述阻挡结构的顶面，所述导电部的顶面、所述保护层的顶面与所述阻挡结构的顶面平齐。
根据本公开的一些实施例，所述在所述接触结构上形成沿所述第一方向间隔设置的多个阻挡结构，包括：
于所述位线结构上和所述接触结构上形成介质层，所述质层的顶面高于所述位线结构的顶面；
图形化所述介质层，于相邻的两个所述位线结构之间形成第三凹槽，所述第三凹槽暴露出所述位线结构的部分侧壁和部分顶面；
于所述第三凹槽内形成所述阻挡结构；
去除所述介质层，形成所述第一凹槽，所述第一凹槽暴露出所述接触结构的顶面。
根据本公开的一些实施例，所述接触结构在所述基底上的投影与所述有源区在所述基底上的投影部分重合。
根据本公开的一些实施例，所述提供基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置，包括：
于所述基底内形成多个间隔设置的隔离沟槽；
于所述隔离沟槽内形成隔离结构，相邻所述隔离结构之间的所述基底形成所述有源区。
根据本公开的一些实施例，所述于所述基底上形成多个位线结构，包括：
于所述基底上依次沉积形成第一导电层、第二导电层和隔离层；
图形化所述第一导电层、所述第二导电层和所述隔离层；
于所述第一导电层的侧壁、所述第二导电层的侧壁及所述隔离层的侧壁和顶面形成侧墙层。
根据本公开的一些实施例，所述于所述位线结构上和所述接触结构上形成第一介质层之前，还包括：
去除覆盖所述隔离层顶面和部分所述隔离层侧壁的所述侧墙层。
根据本公开的一些实施例，所述于相邻的所述位线结构之间形成接触结构，包括：
于相邻的所述位线结构之间和所述位线结构上形成初始接触结构；
去除部分所述初始接触结构形成所述接触结构，所述接触结构的顶面低于所述位线结构的顶面。
根据本公开的一些实施例，所述半导体结构的制作方法还包括：
于所述导电结构上形成绝缘层，所述绝缘层覆盖所述导电结构的顶面。
本公开的第二方面提供了一种半导体结构，包括：
基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置；
多个位线结构，多个所述位线结构设在所述基底上，并与所述有源区连接，多个所述位线结构沿第一方向间隔设置；
多个接触结构，多个所述接触结构设在所述基底上，并位于相邻的所述位线结构之间；
多个阻挡结构，位于所述接触结构上方，所述阻挡结构与所述位线结构对应设置并相连；
多个导电结构，设置在所述接触结构上，且与所述接触结构电连接，每个所述导电结构与每个所述阻挡结构间隔设置，其中，所述导电结构包括保护层和导电部，所述保护层包覆所述导电部的侧壁和底壁。
根据本公开的一些实施例，所述接触结构在所述基底上的投影与所述有源区在所述基底上的投影部分重合。
根据本公开的一些实施例，以平行于所述第一方向的平面为截面，所述导电部的纵截面形状包括Z型、L型或倒L型。
根据本公开的一些实施例，所述半导体结构还包括绝缘层，所述绝缘层设在所述导电结构和所述位线结构的顶面上。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的半导体结构的制作方法中形成初始接触结构以及单层结构的侧墙层的示意图。
图3是根据一示例性实施例示出的半导体结构的制作方法中形成初始接触结构以 及多层结构的侧墙层的示意图。
图4是根据一示例性实施例示出的半导体结构的制作方法中形成接触结构的示意图。
图5是根据一示例性实施例示出的半导体结构的制作方法中去除部分侧墙层的示意图。
图6是根据一示例性实施例示出的半导体结构的制作方法中形成介质层的示意图。
图7是根据一示例性实施例示出的半导体结构的制作方法中形成第三凹槽的示意图。
图8是根据一示例性实施例示出的半导体结构的制作方法中形成阻挡结构的示意图。
图9是根据一示例性实施例示出的半导体结构的制作方法中形成第一凹槽的示意图。
图10是根据一示例性实施例示出的半导体结构的制作方法中形成保护层的示意图。
图11是根据一示例性实施例示出的半导体结构的制作方法中形成初始导电部的示意图。
图12是根据一示例性实施例示出的半导体结构的制作方法中形成导电部以及导电结构的示意图。
图13是根据一示例性实施例示出的半导体结构的制作方法中形成绝缘层的示意图。
附图标记：
10、基底；20、有源区；
30、隔离沟槽；40、隔离结构；
50、位线结构；51、位线；
52、侧墙层；53、位线接触；
60、接触结构；61、初始接触结构；
70、阻挡结构；80、介质层；
90、第三凹槽；100、第一凹槽；
110、导电结构；111、保护层；
112、导电部；120、第二凹槽；
130、绝缘层；511、第一导电层；
512、第二导电层；513、隔离层；
521、第一侧墙层；522、第二侧墙层；
523、第三侧墙层；1120、初始导电部。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。其中，动态随机存储器包括重复设置的多个存储单元。
随着电子产品日益朝向轻、薄、短、小发展，动态随机存取存储器组件的设计也朝着符合高集成度、高密度、小型化的趋势发展，半导体结构要求更加精细，重复图形多而密集，为了刻蚀后的存储单元尺寸的一致性，需要刻蚀质量要求很高的刻蚀工艺。而在小尺寸大数量的阵列图形刻蚀制程工艺中，阵列中间图形的刻蚀金属层会有金属残留。
半导体结构中，相邻的金属层中的金属元素比如钨之间并未设置保护层，或者仅仅设置有部分保护层对上述金属元素进行刻蚀保护，而钨元素较为活泼容易在有电压差或高温情况下，渗入介电质，形成钨晶须，从而产生漏电，导致电荷泄漏，当漏电情况较为严重时，会导致钨烧毁，使得半导体结构直接短路。另一方面，若增加刻蚀金属强度，因图形层精细，会导致金属残留旁侧需要保留的金属被刻蚀掉，导致图形断裂，降低了半导体结构的性能和良率。
为了解决上述技术问题之一，本公开示例性的实施例中提供了一种半导体结构的制作方法，下面结合图1-图13对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S100：提供基底，基底内设有多个有源区，多个有源区沿第一方向间隔设置。
步骤S200：于基底上形成多个位线结构，多个位线结构沿第一方向间隔设置。
步骤S300：于相邻的位线结构之间形成接触结构。
步骤S400：在接触结构上形成沿第一方向间隔设置的多个阻挡结构，阻挡结构与位 线结构对应设置并相连，任意相邻的两个阻挡结构之间形成第一凹槽。
步骤S500：于第一凹槽内形成导电结构，导电结构包括保护层和导电部，保护层包覆导电部的侧壁和底壁。
本实施例中通过上述各个步骤形成导电结构，对于形成导电结构的具体实现方法和结构没有具体限定，只要能够确保导电结构的保护层包覆在导电结构的侧壁和底壁即可。
本实施例中，通过在导电部的侧壁和底壁上形成保护层，利用保护层对导电部进行保护，由此可以提高刻蚀工艺中的刻蚀参数，防止产生金属残留，从而避免半导体结构中的漏电或短路的情况产生，进而提高半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S100的进一步说明，下面结构相关的附图，对本实施例中的步骤S100的实现方法进行详细说明。
如图2所示，提供基底10，基底10作为动态随机存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。在本实施例中基底10采用硅材料，而本实施例采用硅材料作为基底10是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底10的材料。
参照图2所示，基底10内设有多个有源区20，多个有源区20沿第一方向X间隔设置。参照图2所示，以图中示出的方位为例，第一方向X为平行于基底10的前侧面的延伸方向。
其中，在一些实施例中，有源区20的形成可以采用以下方法：
参照图2所示，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10的顶面上沉积层叠设置的光刻胶层和掩膜层，通过曝光或显影刻蚀的方式在光刻胶层上形成掩膜图案，以具有掩膜图案的光刻胶层为掩膜版，刻蚀去除部分光刻胶层和部分掩膜层，从而在基底10上形成多个沿第一方向X间隔设置的隔离沟槽30。而后，通过刻蚀工艺去除剩余的光刻胶层和掩膜层。然后，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在隔离沟槽30内沉积形成隔离结构40。相邻的隔离结构40之间的基底10形成有源区20。其中，隔离结构40可以采用绝缘材料，比如二氧化硅、氮氧化硅等。
在本实施例中，隔离结构40可以作为阻挡隔离层，可以绝缘性地分隔开多个有源区20，同时，也可以避免后续半导体结构中的侧墙层泄露电流等情况的发生，从而保证半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S200的进一步说明，下面结构相关的附图，对本实施例中的步骤S200的实现方法进行详细说明。
如图2所示，在一些实施例中，于基底10上形成多个位线结构50，多个位线结构50沿第一方向X间隔设置。
需要说明的是，在位线结构50形成之前，可以先在基底10上形成多个沿第一方向X间隔设置的位线接触53。在一个示例中，位线接触53可以通过刻蚀工艺形成通孔，而后在通孔中沉积接触材料的方式形成。
在另一个示例中，位线结构50的形成可以采用以下方法：
利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10上依次沉积形成第一初始导电层、第二初始导电层和初始隔离层(图中未示出)。
而后，对第一初始导电层、第二初始导电层和初始隔离层进行图形化处理，从而在第一初始导电层、第二初始导电层和初始隔离层上形成多个沿第一方向X间隔设置的第一沟槽(图中未示出)。
然后，利用原子层沉积工艺在第一沟槽的侧壁上形成侧墙层52，被保留下来的第一初始导电层形成第一导电层511，被保留下来的第二初始导电层形成第二导电层512，被保留下来的初始隔离层形成隔离层513。其中，沿第一方向X，层叠设置的第一导电层511、第二导电层512和隔离层513形成位线51。在本实施例中，侧墙层52设置在第一导电层511的侧壁、第二导电层512的侧壁和隔离层513的侧壁上和顶面上。位线51和侧墙层52形成位线结构50，也即侧墙层52是位线结构50的一部分。
其中，第一导电层511的材料可以包括但不限于钨、多晶硅等，第二导电层512的材料可以包括但不限于多晶硅、氮化钛和钨等。
本实施例中，侧墙层52通过原子层沉积工艺形成，原子层沉积工艺具有沉积速率慢，沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成的侧墙层52，能够在侧墙层52的厚度较薄的条件下对位线结构50进行隔离保护，避免占据较大的空间，有利于后续实现其他结构层的填充或形成。
需要说明的是，参照图2和图3所示，在一些实施例中，侧墙层52可以是单层结构，也可以是多层结构。其中，当侧墙层52为单层结构时，侧墙层52的材料可以包括但不限于二氧化硅、硼磷硅玻璃、氮化硅或氮氧化硅等隔离材料。而当侧墙层52为多层结构时，侧墙层52可以包括第一侧墙层521、第二侧墙层522和第三侧墙层523，第一侧墙层521、第二侧墙层522和第三侧墙层523的材料可以相同，也可以不相同。在一个示例中，第一侧墙层521、第二侧墙层522和第三侧墙层523的材料均可以包括二氧化硅、硼磷硅玻璃等隔离材料，以对位线结构50和后续所形成的接触结构等结构进行隔离。在另一个示例中，第一侧墙层521、第二侧墙层522和第三侧墙层523可以包括氮化硅或氧化硅，从而形成一种“NON”结构，比如氮化硅层、氧化硅层以及氮化硅层，其中，“O”代表氧化硅，“N”代表氮化硅。由于氧化硅层与氮化硅层产生的应力方向不同，采用 “NON”结构有助于降低应力，提高侧墙层52的隔离性能，且有利于在后续结构中进行选择性刻蚀，从而保证并改善半导体结构的性能。
根据一个示例性实施例，本实施例是对上文中步骤S300的进一步说明，下面结构相关的附图，对本实施例中的步骤S300的实现方法进行详细说明。
如图2和图4所示，在相邻的位线结构50之间形成接触结构60，可以先在相邻的位线结构50之间和位线结构50上形成初始接触结构61。
而后，去除部分初始接触结构61，被保留下来的初始接触结构61形成接触结构60，其中，接触结构60的顶面低于位线结构50的顶面。接触结构60可以是电容接触结构。
待位线结构50形成之后，相邻的位线结构50之间形成接触孔(图中未示出)。而后，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在接触孔内沉积形成初始接触结构61。初始接触结构61填充满整个接触孔，并延伸至接触孔外，覆盖在位线结构50的顶面上。
然后，通过刻蚀工艺去除部分初始接触结构61。被保留下来的初始接触结构61形成接触结构60。即，接触结构60的顶面低于位线结构50的顶面。需要说明的是，在一个示例中，接触结构60的顶面可以与位线结构50中的第一导电层511或第二导电层512的顶面平齐，或者，以基底10的底面至基底10的顶面的方向为延伸方向，沿着延伸方向，接触结构60的顶面可以与第一导电层511或第二导电层512中的任意位置处平齐。
本实施例中，接触结构60的顶面与位线结构50中的隔离层513的顶面平齐，同时，在接触结构60和位线51之间通过侧墙层52进行绝缘隔离，从而保证接触结构60和相邻位线51之间的间距，降低对位线51的寄生电容的影响。其中，接触结构60的材料可以包括但不限于多晶硅、氮化钛或钨等，以保证有源区20与后续所形成的半导体结构之间的导电性。
如图2所示，在一些实施例中，接触结构60在基底10上的投影与有源区20在基底10上的投影部分重合，从而有利于接触结构60与有源区20之间的对准。
需要说明的是，在一个示例中，沿第一方向X，接触结构60的横向宽度大于位线结构50的横向宽度，从而降低接触结构60与有源区20之间的对准难度。
如图5所示，在一些实施例中，待接触结构60形成之后，通过刻蚀去除覆盖隔离层513顶面以及部分隔离层513侧壁的侧墙层52，以便于后续在隔离层513的侧壁和部分顶面上形成阻挡层，为后续形成导电结构提供良好的附着基础。
根据一个示例性实施例，本实施例是对上文中步骤S400的进一步说明，下面结构相关的附图，对本实施例中的步骤S400的实现方法进行详细说明。
如图6至图8所示，在一些实施例中，在接触结构60上形成沿第一方向X间隔设置的多个阻挡结构70。其中，多个阻挡结构70与多个位线结构50一一对应设置，并且任意 一个阻挡结构70和与其相对应的那个位线结构50连接。
参照图6至图8所示，在一些实施例中，阻挡结构70的形成可以采用以下方法：
利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在位线结构50和接触结构60上形成介质层80。其中，介质层80的顶面高于位线结构50的顶面。介质层80的材料可以包括但不限于包括氮化硅、二氧化硅、氮氧化硅或硼磷硅玻璃等。
待介质层80形成之后，图形化介质层80，以在介质层80上形成间隔设置的多个第三凹槽90。其中，第三凹槽90位于相邻的两个位线结构50之间，并且，第三凹槽90暴露出其中一侧的位线结构50的部分侧壁和部分顶面。
而后，利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在第三凹槽90内沉积形成阻挡结构70。
然后，通过刻蚀去除剩余的介质层80，即去除任意相邻的两个阻挡结构70之间的介质层80，从而在相邻的阻挡结构70之间形成第一凹槽100。其中，第一凹槽100暴露出接触结构60的顶面，以便于后续在第一凹槽100内形成导电结构110。
其中，在一个示例中，介质层80的材料可以选用硼磷硅玻璃沉积而成，该种材料所形成的介质层80易于在后续制程工序中被清除，因此，可以通过湿法刻蚀去除剩余的介质层80。利用高选择比的湿法刻蚀工艺，可以适当增加刻蚀时间，从而使得剩余的介质层80完全被去除，确保在完全清除介质层80的同时不会对阻挡结构70和位线结构50造成损害，防止断线现象产生。
需要说明的是，参照图8所示，在第三凹槽90中沉积形成阻挡结构70。在一个示例中，在第三凹槽90中、位线结构50上和介质层80上沉积形成初始阻挡结构(图中未示出)，去除部分初始阻挡结构，保留的初始阻挡结构形成阻挡结构70，阻挡结构70的顶面与介质层80的顶面平齐。初始阻挡结构的材料可以包括但不限于氮化硅。其中，促使阻挡结构沉积形成之后，对初始阻挡结构进行部分去除，以保证阻挡结构70的高度尺寸，并且便于后续在阻挡结构70上形成其他半导体结构，从而保证半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S500的进一步说明，下面结构相关的附图，对本实施例中的步骤S500的实现方法进行详细说明。
如图9至图12所示，待阻挡结构70形成之后，于第一凹槽100内形成导电结构110。其中，导电结构110包括保护层111和导电部112，保护层111包覆导电部112的侧壁和底壁。
参照图9至图12所示，在一些实施例中，导电结构110的形成可以采用以下方法：
利用沉积工艺在第一凹槽100内形成保护层111，保护层111覆盖第一凹槽100的底面和侧壁上。其中，第一凹槽100内的保护层111形成第二凹槽120。其中，保护层111 的材料可以包括但不限于氮化钛、氮化钽、钛、钽等。
而后，利用沉积工艺在第二凹槽120内填充导电材料，形成导电部112。其中，导电材料可以包括但不限于钨、多晶硅等。
本实施例中，先在第一凹槽100的侧壁和底面上形成保护层111，而后，在保护层111上形成导电部112，通过保护层111对导电部112进行有效的隔离保护，避免因导电部112中的导电材料比如金属钨产生钨晶须而导致的漏电或短路等情况；另一方面，导电结构110的上述形成方法便于控制，在形成方法中，也能有效控制导电部112的成型形状和形成尺寸，从而提高半导体结构的性能和良率。
如图10所示，在一些实施例中，保护层111的沉积形成可以采用原子层沉积工艺完成，原子层沉积工艺具有沉积速率慢，沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成保护层111能够在厚度较薄的条件下对导电部112进行有效的隔离保护，同时，避免占据较大的空间，有利于后续实现其他结构层的填充或形成。
如图11和图12所示，在一些实施例中，导电部112的形成可以采用以下方法：
利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在第二凹槽120内填充导电材料，该导电材料覆盖保护层111的表面，并填充满第二凹槽120。也就是说，上述导电材料相当于是形成初始导电部1120，初始导电部1120填充满整个第二凹槽120后，并覆盖在阻挡结构70顶面的保护层111的顶面上。
而后通过化学机械研磨去除部分初始导电部1120和部分保护层111，暴露阻挡结构70的顶面。即，被保留下来的初始导电部1120的顶面与阻挡结构70的顶面平齐，并形成导电部112，被保留下来的保护层111的顶面与阻挡结构70的顶面平齐。
本实施例中，通过在保护层111表面形成初始导电部1120，而后通过化学机械研磨去除部分初始导电部1120和部分保护层111，使得导电部112、保留下来的保护层111的顶面与阻挡结构70的顶面平齐，从而有效控制导电部112的形成质量和形成形状，进而提高半导体结构的性能和良率。
如图12所示，在一些实施例中，以平行于第一方向X的平面为截面，导电部112的截面形状包括Z型、L型和倒L型。其中，通过上述Z型、L型和倒L型等截面形状的导电部112，便于后续所形成的其他半导体结构部件的错位布置，从而改善半导体结构的形成尺寸或形成体积。
如图13所示，在一些实施例中，待导电结构110形成之后，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在导电结构110上形成绝缘层130，以便于后续在导电结构110或绝缘层130上形成半导体结构的其他结构。
如图13所示，本公开一示例性的实施例提供的一种半导体结构，该半导体结构包括：基底10、位线结构50、接触结构60、阻挡结构70和导电结构110。
其中，在基底10内设有多个有源区20，多个有源区20沿第一方向X间隔设置。在本实施例中，任意相邻的两个有源区20之间通过隔离结构40来实现绝缘的。
位线结构50为多个，多个位线结构50沿第一方向X间隔设置于基底10上。其中，多个位线结构50与多个有源区20一一对应设置，以自基底10的底面至基底10的顶面为延伸方向，沿着延伸方向，处于同一延伸方向上的有源区20和与位于该有源区20上方的位线结构50连接。其中，在一个示例中，有源区20可以通过位线接触53与位线结构50连接。
接触结构60设置在基底10上，接触结构60为多个。其中，任意相邻的两个位线结构50之间均设置有一个接触结构60。
阻挡结构70为多个，并位于接触结构60的上方，其中，阻挡结构70与位线结构50对应设置并相连。
导电结构110设置在接触结构60上，多个导电结构110与多个接触结构60一一对应设置。导电结构110设置在接触结构60上，并与接触结构60电连接。每个导电结构110与每个阻挡结构70间隔设置。其中，导电结构110包括保护层111和导电部112，保护层111包覆导电部112的侧壁和底壁。
本实施例中，通过在导电部的侧壁和底壁上设置一层保护层，利用保护层对导电部进行保护，由此可以提高刻蚀工艺中的刻蚀参数，防止产生金属残留，从而避免半导体结构中的漏电或短路的情况产生，进而提高半导体结构的性能和良率。
如图13所示，在一些实施例中，接触结构60在基底10上的投影与有源区20在基底10上的投影部分重合，从而有利于接触结构60与有源区20之间的对准。
需要说明的是，参照图13所示，在一个示例中，沿第一方向X，接触结构60的横向宽度大于位线结构50的横向宽度，从而降低接触结构60与有源区20之间的对准难度。
如图13所示，在一些实施例中，以平行于第一方向X的平面为截面，导电部112的纵截面形状包括Z型、L型或倒L型，便于后续所形成的其他半导体结构部件的错位布置，从而改善半导体结构的形成尺寸或形成体积
如图13所示，在一些实施例中，该半导体结构还包括绝缘层130。其中，绝缘层130设在导电结构110和位线结构50的顶面上，以便于后续在导电结构110或者位线结构50或者绝缘层130上形成半导体结构的其他结构。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例的半导体结构的制作方法及半导体结构中，通过在导电部的侧壁和底壁上形成保护层，利用保护层对导电部进行保护，避免出现因刻蚀工艺中的金属残留而导致的漏电或短路的问题，从而提高半导体结构的性能和良率。

Claims (16)

  1. 一种半导体结构的制作方法，包括：
    提供基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置；
    于所述基底上形成多个位线结构，多个所述位线结构沿所述第一方向间隔设置；
    于相邻的所述位线结构之间形成接触结构；
    在所述接触结构上形成沿所述第一方向间隔设置的多个阻挡结构，所述阻挡结构与所述位线结构对应设置并相连，任意相邻的两个所述阻挡结构之间形成第一凹槽；
    于所述第一凹槽内形成导电结构，其中，所述导电结构包括保护层和导电部，所述保护层包覆所述导电部的侧壁和底壁。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述于所述第一凹槽内形成导电结构，包括：
    于所述第一凹槽内形成所述保护层，所述保护层覆盖所述第一凹槽的底面和侧壁，所述第一凹槽内的所述保护层形成第二凹槽；
    于所述第二凹槽内填充导电材料，形成所述导电部。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，以平行于所述第一方向的平面为截面，所述导电部的截面形状包括Z型、L型或倒L型。
  4. 根据权利要求2所述的半导体结构的制作方法，其中，所述于所述第一凹槽内形成所述保护层，包括：
    利用原子层沉积工艺于所述第一凹槽内形成所述保护层。
  5. 根据权利要求2所述的半导体结构的制作方法，其中，所述于所述第二凹槽内填充导电材料，形成所述导电部，包括：
    于所述第二凹槽内填充导电材料，所述导电材料覆盖所述保护层的表面并填充满所述第二凹槽；
    去除部分所述保护层和部分所述导电材料形成所述导电部，暴露所述阻挡结构的顶面，所述导电部的顶面、所述保护层的顶面与所述阻挡结构的顶面平齐。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，所述在所述接触结构上形成沿所述第一方向间隔设置的多个阻挡结构，包括：
    于所述位线结构上和所述接触结构上形成介质层，所述质层的顶面高于所述位线结构的顶面；
    图形化所述介质层，于相邻的两个所述位线结构之间形成第三凹槽，所述第三凹槽暴露出所述位线结构的部分侧壁和部分顶面；
    于所述第三凹槽内形成所述阻挡结构；
    去除所述介质层，形成所述第一凹槽，所述第一凹槽暴露出所述接触结构的顶面。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，所述接触结构在所述基底上的投影与所述有源区在所述基底上的投影部分重合。
  8. 根据权利要求1所述的半导体结构的制作方法，其中，所述提供基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置，包括：
    于所述基底内形成多个间隔设置的隔离沟槽；
    于所述隔离沟槽内形成隔离结构，相邻所述隔离结构之间的所述基底形成所述有源区。
  9. 根据权利要求6所述的半导体结构的制作方法，其中，所述于所述基底上形成多个位线结构，包括：
    于所述基底上依次沉积形成第一导电层、第二导电层和隔离层；
    图形化所述第一导电层、所述第二导电层和所述隔离层；
    于所述第一导电层的侧壁、所述第二导电层的侧壁及所述隔离层的侧壁和顶面形成侧墙层。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述于所述位线结构上和所述接触结构上形成第一介质层之前，还包括：
    去除覆盖所述隔离层顶面和部分所述隔离层侧壁的所述侧墙层。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，所述于相邻的所述位线结构之间形成接触结构，包括：
    于相邻的所述位线结构之间和所述位线结构上形成初始接触结构；
    去除部分所述初始接触结构形成所述接触结构，所述接触结构的顶面低于所述位线结构的顶面。
  12. 根据权利要求1-11任一项所述的半导体结构的制作方法，其中，所述半导体结构的制作方法还包括：
    于所述导电结构上形成绝缘层，所述绝缘层覆盖所述导电结构的顶面。
  13. 一种半导体结构，包括：
    基底，所述基底内设有多个有源区，多个所述有源区沿第一方向间隔设置；
    多个位线结构，多个所述位线结构设在所述基底上，并与所述有源区连接，多个所述位线结构沿第一方向间隔设置；
    多个接触结构，多个所述接触结构设在所述基底上，并位于相邻的所述位线结构之间；
    多个阻挡结构，位于所述接触结构上方，所述阻挡结构与所述位线结构对应设置并相连；
    多个导电结构，设置在所述接触结构上，且与所述接触结构电连接，每个所述导电结构与每个所述阻挡结构间隔设置，其中，所述导电结构包括保护层和导电部，所述保护层包覆所述导电部的侧壁和底壁。
  14. 根据权利要求13所述的半导体结构，其中，所述接触结构在所述基底上的投影与所述有源区在所述基底上的投影部分重合。
  15. 根据权利要求13所述的半导体结构，其中，以平行于所述第一方向的平面为截面，所述导电部的纵截面形状包括Z型、L型或倒L型。
  16. 根据权利要求13-15任一项所述的半导体结构，其中，所述半导体结构还包括绝缘层，所述绝缘层设在所述导电结构和所述位线结构的顶面上。
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