WO2022170788A1 - 电子元件封装体、电子元件组装结构及电子设备 - Google Patents

电子元件封装体、电子元件组装结构及电子设备 Download PDF

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Publication number
WO2022170788A1
WO2022170788A1 PCT/CN2021/126445 CN2021126445W WO2022170788A1 WO 2022170788 A1 WO2022170788 A1 WO 2022170788A1 CN 2021126445 W CN2021126445 W CN 2021126445W WO 2022170788 A1 WO2022170788 A1 WO 2022170788A1
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electronic component
pins
substrate
circuit board
component package
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PCT/CN2021/126445
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English (en)
French (fr)
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向志强
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华为数字能源技术有限公司
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Publication of WO2022170788A1 publication Critical patent/WO2022170788A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10719—Land grid array [LGA]

Definitions

  • the present application relates to the field of packaging technology, and in particular, to an electronic component package, an electronic component assembly structure, and an electronic device.
  • the existing chip-embedded packaging substrate generally adopts a land grid array (LGA) to realize the fixation between the packaging component and the circuit board.
  • LGA land grid array
  • the contact array package is a surface mount package, the package component and the circuit board are soldered through surface contact, and the reliability of the soldering is poor, and it is easy to cause breakage at the solder joint, which affects the reliability of the package component.
  • the present application provides an electronic component package, an electronic component assembly structure, and an electronic device.
  • the pins of the electronic component package provided by the present application have welding areas of different dimensions, which improves the reliability of welding between the electronic component package and the circuit board in the electronic component assembly structure.
  • the present application provides an electronic component assembly structure.
  • the electronic component assembly structure includes an electronic component package body, a circuit board, and a solder joint welded between the circuit board and the electronic component package body.
  • the electronic component package includes a substrate, electronic components, and leads. Electronic components are packaged inside the substrate.
  • the pins are electrically connected with the electronic components, and part of the structures of the pins are exposed relative to the substrate for welding with the circuit board.
  • the electronic components may be active devices such as chips, or passive devices such as capacitors, inductors, and resistors. Exemplarily, the number of electronic components is plural.
  • the electronic components are packaged in the package body, and the substrate is the carrier of the packaged electronic components, providing electrical connection, protection, support, heat dissipation, assembly and other functions for the packaged electronic components.
  • the substrate includes an encapsulation layer and a first circuit layer.
  • Electronic components are encapsulated inside the encapsulation layer.
  • the first circuit layer and the packaging layer are stacked and arranged.
  • the first circuit layer is provided with a first surface and a second surface arranged opposite to each other.
  • the first side is located between the substrate and the second side.
  • Each pin includes a first part and a second part connected to the first part.
  • the first part is embedded in the first circuit layer.
  • the second portion protrudes relative to the second face. It can be understood that the second surface is the bottom surface of the electronic component package, and the electronic component package has pins from the bottom surface.
  • the second portion includes a bottom surface and a side surface.
  • the bottom surface is the outer surface of the lead away from the encapsulation layer, and the side surface is located between the bottom surface and the second surface. It can be understood that both the bottom surface and the side surface are exposed relative to the second surface.
  • the solder joint surrounds the second portion of the lead protruding from the second side. That is, the solder joint surrounds the bottom and side surfaces of the second portion. As shown in Figure 3, the solder joints are not only on the bottom surface of the lead, but also on the side of the second part to surround the second part.
  • the pins protrude from the substrate, so that the part of the pins welded to the circuit board is a three-dimensional pin, the pins have welding areas of different dimensions, and the solder joints can not only connect to the bottom surface of the pins, but also connect the pins
  • the side of the pin not only increases the soldering area of the pin, but also enhances the soldering strength of the pin in different dimensions, and improves the reliability of the soldering between the electronic component package and the circuit board.
  • the bottom wall of the lead and the side wall of the protruding lead can be climbed with tin, so that the solder joints surround the bottom and side surfaces of the lead.
  • the number of pins is multiple, and the multiple pins are arranged at intervals. It can be understood that the pins are made of conductive material, and the insulating material is spaced between the plurality of pins.
  • the part of the pin embedded in the first circuit layer and the part of the pin protruding from the first circuit layer may be integrally formed, or may be formed in steps. The present application is not limited, and the process of forming the pins in the electronic component package may be an etching process or a laser welding process, and those skilled in the art can design according to actual needs.
  • the material used in the first part is the same as the main material used in the second part.
  • the body material used in the first part and the second part may be, but not limited to, copper, aluminum or gold. It can be understood that the material used in the first part of the pin embedded in the first circuit layer will not be remelted during the soldering process, so as to ensure the reliability of the electronic component package circuit.
  • the material used in the first part is the same as the main body material used in the second part, that is, neither the first part nor the second part of the pin will be remelted.
  • the main body material used for the first part and the second part of the pin is different from the material used for the solder joint, and the first part and the second part of the pin will not be heavy during the process of soldering the electronic component package and the circuit board.
  • the shape of the first part and the second part is substantially unchanged, so as to improve the reliability of electronic equipment soldering.
  • BGA ball grid array
  • a side surface of at least one pin includes an inclined surface.
  • the second portion of the pin may be a trapezoid or a pyramid.
  • the side surface of the second part includes an inclined surface, and the cross-sectional shape of the second part can be a trapezoid.
  • the surface area of the side surface of the second part is enlarged to further increase the number of pins The welding area is large, which improves the reliability of the welding between the electronic component package and the circuit board.
  • a side surface of at least one pin includes a stepped surface.
  • the second portion of the pin may have a stepped structure.
  • the cross-sectional shape of the second part of the lead can be a stepped shape, and the surface area of the side surface of the second part is enlarged, so as to further increase the welding area of the lead, and improve the welding ability between the electronic component package and the circuit board. reliability.
  • the embodiments of the present application do not limit the specific shape of the second part of the pin, and those skilled in the art can design this according to actual requirements.
  • the second portion of the at least one pin includes a curved surface.
  • the second portion of the pin is a circular frustum.
  • the sides of the pins are curved.
  • the second part is in the form of a circular truncated cone.
  • the surface area of the side surface of the second part is enlarged to further increase the soldering area of the pins and improve the electronic component package body and the circuit board. Soldering reliability.
  • the area of the bottom surface is larger than the area of the cross-section of the pin along the surface of the substrate. That is, the area of the bottom surface is larger than the area of the cross-section of the lead along the second surface.
  • the area of the bottom surface of the pin is larger than the area of the cross-section of the pin along the second surface, so that after the electronic component package and the circuit board are welded, the solder joint and the pin can form an interlocking force in the vertical direction, The strength of the solder joint in the thickness direction of the electronic component package is further improved, and the failure of the solder joint due to the long-term vibration of the electronic component is avoided, thereby improving the reliability of the electronic device.
  • the solder joint includes a first segment and a second segment connected to the first segment.
  • the first segment is located between the bottom surface of the pin and the circuit board, and the second segment is arranged around the side of the pin.
  • the projection of the second segment on the board overlaps the projection of the bottom surface of the pin on the board.
  • the area of the bottom surface of the pin is larger than the area of the cross-section of the pin along the second surface, so that the solder joint and the pin can form an interlocking force in the vertical direction, which further improves the solder joint in the electronic component package body.
  • the strength in the thickness direction can avoid the failure of solder joints due to long-term vibration of electronic components, thereby improving the reliability of electronic equipment.
  • the material used for the solder joint includes tin, and the material used for the body of the second part is different from the material used for the solder joint. It can be understood that the material used for the solder joints includes tin, and the solder joints will be remelted during the process of soldering the electronic component package and the circuit board to wrap the second part and effectively weld the electronic component package and the circuit board.
  • the material used for the solder joints includes tin, and the material used for the solder joints is different from the main body material used in the second part. That is, the general shape of the second part does not change during the soldering process, so that the solder joint can effectively surround the second part, thereby improving the reliability of soldering the electronic component package and the circuit board.
  • the side of at least one pin facing away from the substrate is provided with a groove. That is, the side of the pins facing the circuit board is provided with grooves.
  • the groove is recessed from the bottom surface of the lead toward the side of the substrate. Part of the structure of the solder joint is embedded in the groove. It can be understood that the grooves do not penetrate the pins. Exemplarily, the number of grooves is plural.
  • the second portion of the at least one pin includes a plurality of sub-pins. A plurality of sub-pins are arranged with gaps, and the plurality of sub-pins are all connected with the first part. The second portion of the portion of the plurality of pins includes a plurality of spaced sub-pins.
  • the grooves divide the second portion into a plurality of spaced sub-pins.
  • the plurality of sub-pins are arranged symmetrically.
  • a plurality of sub-pins are arranged in a matrix. Wherein, the gap between any two adjacent sub-pins is smaller than the gap between any two adjacent pins.
  • a groove is provided on the side of a single lead away from the substrate, which increases the exposed surface area of a single lead, and part of the structure of the solder joint is embedded in the groove, which further increases the welding area of a single lead.
  • Solder can fill the grooves when the electronic component package is soldered, which further improves the reliability of soldering the electronic component package and the circuit board.
  • the present application does not limit the width, depth or number of any trenches.
  • the second part of the single lead may be divided into a plurality of sub-leads arranged at intervals.
  • the dicing method can be, but is not limited to, etching or laser.
  • the electronic component package is provided with a first side surface and a second side surface that are arranged opposite to each other.
  • the second side is connected between the first side and the second side, and the plurality of pins includes a first pin and a second pin.
  • the first pin is closest to the first side surface
  • the second pin is closest to the second side surface
  • grooves are provided on the sides of the first pin and the second pin away from the substrate.
  • the possibility of fatigue failure of the pins on the edge of the electronic component package due to the vibration of the electronic equipment is relatively high. Therefore, the pins on the edge of the electronic component package are cut to form a plurality of sub-leads arranged at intervals. It not only increases the reliability of edge pin welding, but also avoids cutting all the pins and increasing the cost.
  • the second part of each pin may also be provided with a plurality of sub-pins arranged at intervals, which is not limited in the present application.
  • the side of the substrate facing away from the circuit board is provided with pads.
  • the substrate further includes a second circuit layer stacked with the encapsulation layer. The pad is embedded in the second circuit layer. It can be understood that the second circuit layer is disposed on the top surface of the electronic component package, and the first circuit layer is disposed on the bottom surface of the electronic component package.
  • the electronic component package is provided with a first circuit layer and a second circuit layer opposite to each other, so that both sides (top and bottom) of the electronic component package have circuits that can be electrically connected It can provide a good foundation for the double-sided interconnection of electronic components encapsulated in the electronic component package, which is beneficial to realize the shortest interconnection path and realize the thin packaging of the substrate in the limited space layout, with strong practicability and reliability. good sex.
  • the electronic component package further includes bonding wires.
  • the pads include a first pad and a second pad.
  • the first pad and the second pad are spaced apart and electrically connected by bonding wires.
  • the bonding wire may be a metal wire or a metal strip. That is, the second wiring layer is bonded by wire bonding and/or clip bonding. This application does not limit the number, position and shape of the pads in the second circuit layer, which can be designed by those skilled in the art according to actual needs.
  • the second circuit layer is formed on the upper surface of the substrate, and the first pad and the second pad in the second circuit layer are electrically connected by bonding wires, so as to avoid the first pad and the second pad When soldering by solder reflow, remelting is performed during the solder reflow process, thereby improving the reliability of the electronic component package.
  • the electronic component package further includes a package.
  • the package body is located on the side of the substrate away from the circuit board.
  • the bonding wire is encapsulated inside the package body, and the package body adopts magnetic material.
  • the magnetic material is a liquid magnetic material, and the bonding wires are encapsulated by the liquid magnetic material to form a package body using the magnetic material.
  • the application does not limit the types of magnetic materials, which can be designed by those skilled in the art according to actual needs.
  • the pads in the second circuit layer are connected by bonding wires, and the surface of the second circuit layer is a package body using a magnetic material, and the package body and the bonding wires form a complete magnetic component (such as a transformer). , inductance) winding, which can prevent the current inside the electronic component package from being too large, which is conducive to improving the reliability of electronic equipment.
  • the package body is seamlessly connected with the first circuit layer, which is beneficial to the heat dissipation of the electronic components in the substrate, thereby improving the heat dissipation performance of the electronic component package body.
  • the present application also provides an electronic component assembly structure.
  • the electronic component assembly structure includes an electronic component package body, a circuit board, and a solder joint welded between the electronic component package body and the circuit board.
  • the electronic component package includes a substrate, electronic components, and leads.
  • the electronic components are packaged inside the substrate, and the pins are electrically connected with the electronic components.
  • the side of the pin facing away from the electronic component is provided with a groove.
  • the groove is recessed from the bottom surface of the lead toward the side of the electronic component.
  • the solder joints are embedded in the grooves. The grooves do not penetrate the pins.
  • the pins are arranged with a gap relative to the exposed surface of the first circuit layer, and are connected to each other as a whole on the side close to the substrate.
  • a plurality of sub-pins separated by trenches use the same electrical network.
  • a single pin is provided with a groove on the side away from the substrate, and the solder joint is embedded in the groove, which not only increases the exposed surface area of the single pin, but also enhances the welding strength of the pin in the three-dimensional direction.
  • the reliability of soldering the electronic component package body and the circuit board is improved, thereby improving the reliability of the electronic component assembly structure.
  • the present application does not limit the width, depth or number of any trenches.
  • the present application further provides an electronic device.
  • An electronic device includes a housing and the electronic component assembly structure provided in the first aspect or the second aspect.
  • the electronic component assembly structure is mounted on the casing.
  • the electronic device includes the electronic component assembly structure provided in the first aspect and the second aspect.
  • the electronic component assembly structure the electronic component package body and the circuit board have welding areas of different dimensions, which improves the secondary component of the electronic component assembly structure. Soldering reliability, thereby improving the reliability of electronic equipment.
  • the present application further provides an electronic component package.
  • the electronic component package includes a substrate, electronic components, and leads. Electronic components are packaged inside the substrate.
  • the pins are electrically connected with the electronic components, and part of the structures of the pins are exposed relative to the substrate for welding with the circuit board.
  • the substrate includes an encapsulation layer and a first circuit layer. Electronic components are encapsulated inside the encapsulation layer.
  • the first circuit layer and the packaging layer are stacked and arranged.
  • the first circuit layer is provided with a first surface and a second surface arranged opposite to each other.
  • the first side is located between the substrate and the second side.
  • the first circuit layer includes a plurality of pins arranged at intervals. The plurality of pins are electrically connected with the electronic components.
  • Each pin includes a first part and a second part connected to the first part.
  • the first part is embedded in the first circuit layer.
  • the second portion protrudes relative to the second face.
  • the second surface is the bottom surface of the electronic component package, and the electronic component package has pins from the bottom surface.
  • the second part includes a bottom surface and a side surface.
  • the bottom surface is the outer surface of the lead away from the encapsulation layer, and the side surface is located between the bottom surface and the second surface. It can be understood that both the bottom surface and the side surface are exposed relative to the second surface. Both the bottom and sides are intended for soldering with solder.
  • the pins protrude from the substrate, so that the part of the pins welded to the circuit board is a three-dimensional pin, the pins have welding areas of different dimensions, and the solder joints can not only connect to the bottom surface of the pins, but also connect the pins
  • the side of the pin not only increases the soldering area of the pin, but also enhances the soldering strength of the pin in different dimensions, and improves the reliability of the soldering between the electronic component package and the circuit board.
  • the number of pins is multiple, and the multiple pins are arranged at intervals.
  • the sides of at least one of the pins include sloped surfaces.
  • the second portion of the pin may have a stepped structure.
  • the sides of at least one of the pins include stepped surfaces.
  • the second portion of the pin may have a stepped structure.
  • the second portion of the at least one pin includes a curved surface.
  • the second portion of the pin is a circular frustum.
  • the side surface of the second part includes an inclined surface, a stepped surface or a curved surface.
  • the surface area of the side surface of the second part is enlarged to further increase the welding area of the pins and improve the The reliability of the soldering between the electronic component package and the circuit board is improved.
  • the area of the bottom surface is larger than the area of the cross-section of the pin along the surface of the substrate. That is, the area of the bottom surface is larger than the area of the cross-section of the lead along the second surface.
  • the area of the bottom surface of the pin is larger than the area of the cross-section of the pin along the second surface, so that after the electronic component package and the circuit board are welded, the solder joint and the pin can form an interlocking force in the vertical direction, The strength of the solder joint in the thickness direction of the electronic component package is further improved, and the failure of the solder joint due to the long-term vibration of the electronic component is avoided, thereby improving the reliability of the electronic device.
  • the material used in the first part is the same as the main body material used in the second part.
  • the body material used in the first part and the second part may be, but not limited to, copper, aluminum or gold. It can be understood that the material used in the first part of the pin embedded in the first circuit layer will not be remelted during the soldering process, so as to ensure the reliability of the electronic component package circuit.
  • the material used in the first part is the same as the main body material used in the second part, that is, neither the first part nor the second part of the pin will be remelted.
  • the body material used for the first part and the second part of the lead is different from the material used for the solder joint, and the first part and the second part of the lead will not be in the process of welding the electronic component package and the circuit board. Remelting, the shape of the first part and the second part is roughly unchanged, so as to improve the reliability of electronic equipment soldering.
  • the side of at least one pin facing away from the substrate is provided with a groove. That is, the side of the pins facing the circuit board is provided with grooves. The groove is recessed from the bottom surface of the lead toward the side of the substrate.
  • a groove is provided on the side of a single lead away from the substrate, which increases the exposed surface area of the single lead, and further increases the welding area of the single lead. Solder can fill the groove when the electronic component package is welded. , which further improves the reliability of the soldering between the electronic component package and the circuit board.
  • the present application does not limit the width, depth or number of any trenches.
  • a side of the substrate facing away from the pin includes a first pad and a second pad.
  • the first pad and the second pad are spaced apart.
  • the electronic component assembly structure also includes bonding wires and a package body.
  • the bonding wire is electrically connected between the first pad and the second pad.
  • the package body is located on the side of the substrate away from the circuit board, the bonding wire is packaged inside the package body, and the package body adopts magnetic material.
  • the pads on the side of the substrate away from the pins are connected by bonding wires, and are embedded in a package body using magnetic materials, and the package body and bonding wires form a complete magnetic component (such as transformers, inductors, etc.) ) winding can prevent the current inside the electronic component package from being too large, which is beneficial to improve the reliability of the electronic device.
  • the package body is seamlessly connected with the first circuit layer, which is beneficial to the heat dissipation of the electronic components in the substrate, thereby improving the heat dissipation performance of the electronic component package body.
  • the present application further provides an electronic component package.
  • the electronic component package includes a substrate, electronic components and pins.
  • the electronic components are packaged inside the substrate, and the pins are electrically connected with the electronic components.
  • the side of the pin facing away from the electronic component is provided with a groove.
  • the groove is recessed from the bottom surface of the lead toward the side of the electronic component.
  • the trenches are filled with solder.
  • the grooves do not penetrate the pins. It can be understood that the pins are arranged with a gap relative to the exposed surface of the first circuit layer, and are connected to each other as a whole on the side close to the substrate. Exemplarily, a plurality of sub-pins separated by trenches use the same electrical network.
  • grooves are provided on the side of a single lead away from the substrate, which not only increases the exposed surface area of a single lead, but also enhances the welding strength of the lead in the three-dimensional direction, and improves the efficiency of the electronic component package and other parts. Soldering reliability.
  • the present application does not limit the width, depth or number of any trenches.
  • FIG. 1 is a partial structural schematic diagram of an electronic component assembly structure provided by an embodiment of the present application.
  • FIG. 2 is a partial cross-sectional schematic diagram of the electronic component assembly structure provided by the present application in Embodiment 1;
  • FIG. 3 is a schematic structural diagram of part A shown in FIG. 2 in a first implementation manner
  • FIG. 4 is a schematic structural diagram of part A shown in FIG. 2 in a second implementation manner
  • FIG. 5 is a partial structural schematic diagram of the electronic component package shown in FIG. 2 in a third implementation manner
  • FIG. 6 is a top view of the electronic component package shown in FIG. 2;
  • FIG. 7 is a top view of the electronic component assembly structure provided by the present application in Embodiment 2;
  • FIG. 8 is a partial cross-sectional schematic diagram of the electronic component package shown in FIG. 7 along B-B;
  • FIG. 9 is a schematic partial cross-sectional view of the pin shown in FIG. 7 along B-B in another implementation
  • FIG. 10 is a partial cross-sectional schematic diagram of the electronic component assembly structure provided by the present application in Embodiment 3;
  • FIG. 11 is a schematic structural diagram of the electronic component package provided by the present application in Embodiment 4.
  • FIG. 12 is a schematic partial cross-sectional view of the electronic component package shown in FIG. 11 .
  • the present application provides an electronic device.
  • the electronic device includes a housing and an electronic component assembly structure.
  • the electronic component assembly structure is mounted on the casing.
  • Electronic devices can be mobile phones, tablets, laptops, in-vehicle devices, wearable devices, drones, routers, and other products.
  • the electronic device may also be a power supply module, a communication signal transmitting base station, a network switching device, and other devices. In this embodiment, description is made by taking the electronic device as an in-vehicle device as an example.
  • FIG. 1 is a partial structural schematic diagram of an electronic component assembly structure 100 provided by an embodiment of the present application.
  • the electronic component assembly structure 100 includes an electronic component package 10 , a circuit board 20 , and solder joints 30 connected between the electronic component package 10 and the circuit board 20 .
  • An electronic component 11 is included in the electronic component package 10 .
  • the electronic component 11 may be an active device such as a chip, or may be a passive device such as a capacitor, an inductor, and a resistor.
  • the electronic component package 10 is a carrier for packaging the electronic components 11 , and provides functions such as electrical connection, protection, support, heat dissipation, and assembly for the packaged electronic components 11 .
  • the number of electronic components 11 is plural. As shown in FIG. 1 , the electronic component 11 exemplarily includes a first component 111 , a second component 112 and a third component 113 .
  • the second element 112 is spaced between the first element 111 and the third element 113 .
  • the second element 112 is a chip
  • the first element 111 is a resistor
  • the second element 112 is a capacitor.
  • the electronic component package 10 may adopt a system-in-package (SIP), a power supply-in-package (PSiP), or an embedded chip substrate (embedded chip substrate, ECP).
  • SIP system-in-package
  • PSiP power supply-in-package
  • ECP embedded chip substrate
  • System-in-package is to integrate a variety of functional electronic components, such as processors, memory, power management chips and other functional electronic components in a package to achieve a basically complete function.
  • the chip-embedded substrate can be understood as a substrate structure in which chips are mounted inside the substrate, and then the chips are encapsulated by packaging materials, and interconnected by copper holes, copper pillars, etc.
  • the electronic component package 10 will be described in detail by taking an embedded chip substrate (ECP) as an example.
  • ECP embedded chip substrate
  • the circuit board 20 can be understood as a carrier of the electronic component package 10 , which can carry the electronic component package 10 and be assembled with the electronic component package 10 .
  • the circuit board 20 and the electronic component package 10 are electrically connected by soldering through the solder joints 30, thereby realizing electrical interconnection with the electronic component package 10.
  • the electronic component package 10 is mounted on the circuit board 20 as an example for description. In other embodiments, the electronic component package 10 can also be installed in other structures, which is not limited in the present application.
  • FIG. 1 is only to schematically describe the connection relationship between the circuit board 20 and the electronic component package 10 , and not to specifically limit the connection position, specific structure and quantity of each device.
  • the structures shown in the embodiments of the present application do not constitute a specific limitation on the electronic component assembly structure 100 .
  • the electronic component assembly structure 100 may include more components than shown, or combine some components, or separate some components, or arrange different components.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the electronic component package body and the circuit board are welded by means of a land grid array (LGA).
  • LGA land grid array
  • the contact array package is a surface mount package.
  • the reliability of the electronic component package and the circuit board welding is poor.
  • the electronic equipment may be unstable in welding and lead to electrical failure. risk.
  • the pins of the electronic component package are flush with the outer surface of the electronic component package, and the surface of the circuit board is attached to the surface of the electronic component package to connect the pins of the electronic component package with the corresponding pins on the circuit board ,
  • the solder joints between the electronic component package and the circuit board experience fatigue failure, resulting in breakage of the solder joints and affecting the reliability of electronic equipment.
  • the present application provides an electronic component package 10 .
  • the pins in the electronic component package 10 have welding areas of different dimensions, which improves the reliability of welding between the electronic component package 10 and the circuit board 20 and reduces the electronic components.
  • the risk of soldering failure between the electronic component package 10 and the circuit board 20 is caused by the assembly structure 100 after long-term vibration, which effectively improves the board-level reliability of the electronic component assembly structure 100 .
  • the following will mainly describe in detail the electronic component assembly structure 100 and the corresponding electronic component package body 10 provided by the present application through four embodiments.
  • FIG. 2 is a partial cross-sectional schematic diagram of the electronic component assembly structure 100 provided by the present application in the first embodiment.
  • the electronic component package 10 is mounted on the mounting surface 201 of the circuit board 20 .
  • the solder joints 30 are used to realize electrical connection between the electronic component package 10 and the circuit board 20 .
  • the electronic component package 10 includes a substrate 110 , electronic components 11 and pins 130 .
  • the electronic components 11 are packaged inside the substrate 110 .
  • the pins 130 are electrically connected to the electronic components 11 , and part of the structures of the pins 130 are exposed to the substrate 110 for soldering with the circuit board 20 .
  • the substrate 110 includes an encapsulation layer 12 and a first circuit layer 13 .
  • the electronic components 11 are encapsulated inside the encapsulation layer 12 .
  • the first circuit layer 13 and the encapsulation layer 12 are stacked.
  • the first circuit layer 13 is provided with a first surface 1301 and a second surface 1302 disposed opposite to each other.
  • the first surface 1301 is located between the encapsulation layer 12 and the second surface 1302 .
  • the mounting surface 201 faces the second surface 1302 , and the solder joints 30 are connected between the pins 130 and the circuit board 20 . It can be understood that the second surface 1302 is the bottom surface of the substrate 110 . As shown in FIG.
  • the first surface 1301 of the first circuit layer 13 is in contact with the encapsulation layer 12 as an example for description.
  • other structures such as a circuit layer, may also be provided between the encapsulation layer 12 and the first circuit layer 13 , which is not limited in this application.
  • Those skilled in the art can design the structure between the first circuit layer 13 and the encapsulation layer 12 according to actual requirements.
  • the number of pins 130 is multiple, and the multiple pins 130 are arranged at intervals.
  • the plurality of pins 130 are made of conductive material, and are arranged at intervals by insulating material, and the insulating material may be, but not limited to, liquid photoresist (green oil).
  • the plurality of pins 130 are electrically connected to the electronic component 11 and are electrically connected to the circuit board 20 through the plurality of solder joints 30 .
  • the number of pins 130 corresponds to the number of solder joints 30 .
  • the signal generated by a certain working module electrically connected to the circuit board 20 is transmitted to the electronic component package 10 through the circuit board 20 and the pins 130 in sequence;
  • the solder joints 30 and the circuit board 20 are connected to the corresponding working modules, so as to realize the communication between the electronic component package 10 and the corresponding working modules.
  • FIG. 3 is a schematic structural diagram of part A shown in FIG. 2 in the first implementation manner.
  • the pin 130 includes a first portion 131 and a second portion 132 connected to the first portion 131 .
  • the first portion 131 is embedded in the first circuit layer 13 , and the second portion 132 protrudes from the substrate 110 .
  • the first part 131 is directly connected with the second part 132 .
  • the first part 131 and the second part 132 may also be indirectly connected, which is not limited in this application. It can be understood that each pin 130 penetrates through the second surface 1302 from the first surface 1301 and protrudes from the second surface 1302 .
  • part of the structure of the lead 130 protrudes from the second surface 1302 (the outer surface of the electronic component package 10 ) to form the lead 130 with a three-dimensional structure.
  • the second surface 1302 is the bottom surface of the electronic component package body 10, and the electronic component package body 10 provided in the present application has leads from the bottom surface.
  • the second portion 132 includes a bottom surface 1321 and a side surface 1322 .
  • the bottom surface 1321 is the outer surface of the lead 130 away from the encapsulation layer 12
  • the side surface 1322 is located between the bottom surface 1321 and the second surface 1302 . It can be understood that both the bottom surface 1321 and the side surface 1322 are exposed relative to the second surface 1302 .
  • the bottom surface 1321 contacts the reference plane or is parallel to the reference plane
  • the side surface 1322 is connected between the second surface 1302 and the reference plane.
  • the side surface 1322 may be a curved surface or a flat surface, which is not limited in the present application.
  • the solder joint 30 surrounds the second portion 132 of the lead 130 protruding from the second surface 1302 . That is, the solder joint 30 surrounds the bottom surface 1321 and the side surface 1322 of the second portion 132 . As shown in FIG. 3 , the solder joint 30 is not only located on the bottom surface 1321 of the lead 130 , but also on the side surface 1322 of the second part 132 to surround the second part 132 .
  • the pins 130 protrude from the substrate 110 , so that the parts of the pins 130 welded with the circuit board 20 are three-dimensional pins 130 , the pins 130 have welding areas of different dimensions, and the solder joints 30 can not only connect the pins
  • the bottom surface 1321 of the pin 130 can also be connected to the side surface 1322 of the pin 130, which not only increases the welding area of the pin 130, but also enhances the welding strength of the pin 130 in different dimensions, and improves the welding of the electronic component package 10 and the circuit board 20. reliability.
  • the bottom wall of the lead 130 and the side wall of the protruding lead 130 can be soldered, so that the solder joint 30 surrounds the bottom surface 1321 and the side surface 1322 of the lead 130 .
  • the first circuit layer 13 further includes an insulating material, and the insulating material is spaced between the plurality of pins 130 .
  • the part of the pin 130 embedded in the first circuit layer 13 and the part of the pin 130 protruding from the first circuit layer 13 may be integrally formed, or may be formed in steps.
  • the present application is not limited, and the process of forming the pins 130 in the electronic component package 10 may be an etching process or a laser welding process, which can be designed by those skilled in the art according to actual needs.
  • the first circuit layer 13 is first etched to form the patterned first circuit layer 13, after the conductive material is filled along the patterned first circuit layer 13, the conductive material is continuously plated along the filled conductive material structure to form bumps step by step out the pins 130 of the first circuit layer 13 .
  • the conductive material in the patterned first circuit layer 13 is covered by photoresist, and a partial structure of the insulating material in the patterned first circuit layer 13 is etched through a mask, so as to protrude the first circuit layer by integral molding 13 to pin 130.
  • the material used for the solder joint 30 includes tin, and the material used for the solder joint 30 is different from the material used for the second portion 132 .
  • the solder joints 30 will be remelted to wrap the second part 132 .
  • the second part 132 will not be remelted, that is, the approximate shape of the second part 132 during the assembly process. It does not change, so that the solder joint 30 can effectively surround the second part 132 , thereby improving the reliability of soldering the electronic component package 10 and the circuit board 20 .
  • remelting is the process of secondary melting of metals or alloys.
  • the material used for the first portion 131 is the same as the body material used for the second portion 132 .
  • the material used for the first part 131 and the second part 132 may be, but not limited to, copper, aluminum or gold. It can be understood that the main parts of the first part 131 and the second part 132 of the pin 130 will not be remelted during the secondary assembly process.
  • the main body material used for the first part 131 and the second part 132 of the lead 130 is different from the material used for the solder joint 30 .
  • the first part of the lead 130 The main body structures of the 131 and the second part 132 will not be remelted, and the shapes of the first part 131 and the second part 132 are substantially unchanged, so as to improve the reliability of the soldering of the electronic component assembly structure 100 .
  • the solder balls are remelted and deformed during the soldering process.
  • the side of the substrate 110 facing away from the circuit board 30 includes pads 140 .
  • the substrate 110 further includes a second circuit layer 14 stacked with the encapsulation layer 12 .
  • the second circuit layer 14 is disposed on the top surface of the electronic component package 10
  • the first circuit layer 13 is disposed on the bottom surface of the electronic component package 10 .
  • the second circuit layer 14 includes a plurality of pads 140 for electrical connection.
  • the pattern designs of the second circuit layer 14 and the first circuit layer 13 may be differentiated, that is, the pattern designs of the first circuit layer 13 and the second circuit layer 14 may be different. Make strict restrictions.
  • the pattern design of the first circuit layer 13 and the pattern design of the second circuit layer 14 can be set according to the needs of the electronic components 11 packaged by the electronic component package 10 .
  • the pins 130 of the first wiring layer 13 and the pads 140 of the second wiring layer 14 may be copper.
  • the electronic component package body 10 is provided with a first circuit layer 13 and a second circuit layer 14 arranged opposite to each other, so that both sides (top and bottom surfaces) of the electronic component package body 10 have the ability to conduct electricity
  • the circuit layer that is electrically connected can provide a good foundation for the double-sided interconnection of the electronic components 11 packaged in the electronic component package body 10, which is beneficial to realize the shortest interconnection path and realize the packaging layer 12 in the limited space layout.
  • the thin package has strong practicability and good reliability.
  • the side surface 1322 of at least one lead 130 of the plurality of leads 130 includes an inclined surface.
  • the side surfaces 1322 of the plurality of pins 130 include inclined surfaces.
  • the second portion 132 of the pin 130 may be a trapezoid or a pyramid.
  • the side surface 1322 of the pin 130 is a curved surface, and the sectional surface of the side surface 1322 of at least one pin 130 of the plurality of pins 130 is not perpendicular to the bottom surface 1321 .
  • a plane and a surface have one and only one intersection point, then this plane is the tangent of the surface.
  • the second portion 132 of the pin 130 may be in the shape of a circular frustum. As shown in FIG. 3 , in the direction perpendicular to the thickness of the electronic component package 10 , the cross-section of the second portion 132 of the lead 130 is trapezoidal. At this time, the second portion 132 of the pin 130 may be a circular truncated table or a trapezoidal table.
  • the cross-sectional shape of the second portion 132 may be a trapezoid, and the second portion 132 may be a trapezoidal truncated, prismatic or circular truncated frustum.
  • the side surface 1322 of the second portion 132 is enlarged. , so as to further increase the soldering area of the pins 130 and improve the reliability of soldering between the electronic component package 10 and the circuit board 20 .
  • the application does not limit the inclination rate of the side surface 1322 of the pin 130 , and those skilled in the art can reasonably design the inclination angle of the side surface 1322 of the pin 130 by the area of the second surface 1302 and the gap between the pins 130 .
  • the area of the bottom surface 1321 is larger than the area of the cross section of the lead 130 along the surface (the second surface 1302 ) of the substrate 110 .
  • the length of the lower side of the trapezoid is greater than the length of the upper side of the trapezoid.
  • the second portion 132 is a circular truncated cone
  • the area of the lower surface of the circular truncated cone is larger than the area of the upper surface of the circular truncated cone.
  • the solder joint 30 includes a first segment 31 and a second segment 32 connected to the first segment 31 .
  • the first segment 31 is connected between the bottom surface 1321 of the pin 130 and the circuit board 20
  • the second segment 32 is arranged around the periphery of the side surface 1322 of the pin 130 .
  • the projection of the second segment 32 on the circuit board 20 partially overlaps the projection of the bottom surface 1321 of the pin 130 on the circuit board 20 .
  • the area of the bottom surface 1321 of the lead 130 is larger than the area of the cross section of the lead 130 along the second surface 1302 , so that the solder joint 30 and the lead 130 are perpendicular to each other after the electronic component package 10 and the circuit board 20 are welded.
  • the direction can form an interlocking force, further improving the strength of the solder joint 30 in the thickness direction of the electronic component package 10, avoiding the failure of the solder joint due to the long-term vibration of the electronic component 11, thereby improving the reliability of the electronic component assembly structure 100. sex.
  • FIG. 4 is a schematic structural diagram of part A shown in FIG. 2 in a second implementation manner.
  • the side surface 1322 of at least one pin 130 of the plurality of pins 130 is a stepped surface.
  • the side surfaces 1322 of the plurality of pins 130 are all stepped surfaces.
  • the cross section of the second portion 132 of the lead 130 is stepped.
  • the second portion 132 of the pin 130 may be in the shape of stacking at least two trapezoidal stages, or may be in the shape of stacking two circular stages.
  • the steps show an upward trend, and the solder joints 30 and the pins 130 of the electronic component package 10 and the circuit board 20 form an interlocking structure, thereby improving the height of the electronic component package 10 and the circuit board 20 . Soldering reliability.
  • FIG. 3 and FIG. 4 respectively illustrate schematic cross-sectional views of the pins 130 protruding from the first circuit layer 13 in different implementations.
  • the cross-sectional shape of the second part 132 of the lead 130 can be a stepped shape, and the area of the side surface 1322 of the second part 132 is enlarged to further increase the welding area of the lead 130 and improve the welding of the electronic component package 10 and the circuit board 20 . reliability.
  • the embodiment of the present application does not limit the specific shape of the second portion 132 of the pin 130, and those skilled in the art can design this according to actual needs.
  • FIG. 5 is a partial structural schematic diagram of the electronic component package 10 shown in FIG. 2 in a third implementation manner. Specifically, the structure of the electronic component package 10 shown in this implementation manner can be combined with the structure of any one of the electronic component packages 10 in FIGS. 3 and 4 .
  • the pin 130 further includes a protective layer 133 .
  • the protective layer 133 is located on the outer surface of the second part 132 .
  • the protective layer 133 wraps the outer surface of the second part 132 by means of electroplating.
  • the oxidation resistance of the material used for the protective layer 133 is stronger than that of the material used for the second part 132 .
  • the material used for the second portion 132 includes, but is not limited to, copper or aluminum.
  • Materials used for the protective layer 133 include, but are not limited to, tin or gold.
  • the lead 130 further includes a protective layer 133 that wraps the second part 132.
  • the anti-oxidation performance of the protective layer 133 is stronger than that of the second part 132, and is used to protect the second part 132 and avoid The second portion 132 is oxidized, thereby further improving the reliability of the electronic component package 10 .
  • FIG. 6 is a top view of the electronic component package 10 shown in FIG. 2 .
  • the shapes of the plurality of pins 130 may be the same or may be different, which is not limited in the present application.
  • the area of the bottom surface 1321 of the lead 130 located in the middle part of the electronic component package 10 is larger than the area of the bottom surface 1321 of the edge lead 130 .
  • the gaps between the pins 130 can be designed by those skilled in the art according to actual conditions, so as to avoid mutual interference between adjacent pins 130 .
  • the present application does not limit the arrangement of the plurality of pins 130, which may be symmetrical or asymmetrical.
  • the plurality of pins 130 are symmetrically arranged along the length direction X and the width direction Y of the electronic component package 10 .
  • the plurality of pins 130 may also be arranged asymmetrically, which is not limited in the present application.
  • each pin 130 does not limit the shape of each pin 130 , and the shapes of the plurality of pins 130 may be the same or different.
  • the top view of each pin 130 is rectangular in shape.
  • the shape of the top view of each pin 130 may also be other geometric shapes, such as a circle, etc., which is not limited in this application.
  • FIG. 7 is a top view of the electronic component assembly structure 100 provided by the present application in the second embodiment
  • FIG. 8 is a partial cross-sectional schematic diagram of the electronic component package 10 shown in FIG. Wherein, the electronic component assembly structure 100 shown in FIG. 7 does not illustrate the solder joints and the circuit board.
  • the electronic component package 10 includes a substrate 110 , an electronic component 11 packaged inside the substrate 110 , and pins 130 electrically connected to the electronic component 11 .
  • the pins 130 protrude from the surface of the substrate 110 .
  • the portion of the pin 130 protruding from the substrate 110 may be in the shape of a truncated cone or a trapezoid.
  • a groove 1300 is provided on the side of at least one pin 130 facing away from the substrate 110 .
  • the groove 1300 is recessed from the bottom surface 1321 of the lead 130 toward the substrate 110 side. That is, at least one of the pins 130 is provided with a groove 1300 on the side facing the circuit board. It can be understood that the grooves 1300 do not penetrate the pins 130 .
  • the number of trenches 1300 is multiple.
  • the second portion 132 of the at least one pin 130 includes a plurality of sub-pins 1320 .
  • the plurality of sub-pins 1320 are arranged with gaps, and the plurality of sub-pins 1320 are all connected to the first part 131 .
  • the trenches 1300 divide the second portion 132 into a plurality of spaced sub-leads 1320.
  • the plurality of sub-pins 1320 are arranged symmetrically. As shown in FIG. 7 , the plurality of sub-pins 1320 are arranged in a matrix. Wherein, the gap between any two adjacent sub-pins 1320 is smaller than the gap between any two adjacent pins 130 .
  • a plurality of sub-leads 1320 arranged at intervals in the lead 130 are arranged in the gap between the exposed surfaces of the opposite substrate 110, and the structures embedded in the first circuit layer 13 in the substrate 110 are connected to each other as a whole, that is,
  • the plurality of sub-pins 1320 are pins 130 with the same function.
  • the plurality of sub-pins 1320 use the same electrical network.
  • the trench 1300 is recessed until the first portion 131 of the pin 130 ends. In other embodiments, the trench 1300 may also be recessed to other depths, which is not limited in the present application.
  • the solder joints not only surround the bottom and side surfaces of the pins 130 , but also fill the grooves 1300 , increasing the contact area between the solder joints and the pins 130 . That is, when the electronic component assembly structure adopts the electronic component package provided in this embodiment, a part of the structure of the solder joint is embedded in the groove 1300 .
  • a groove 1300 is provided on the side of the single lead 130 away from the substrate 110 , which increases the exposed surface area of the single lead 130 and further increases the welding area of the single lead 130 , and the electronic component package 10 is welded.
  • the solder can fill the trench 1300 , which further improves the reliability of the soldering between the electronic component package 10 and the circuit board 20 .
  • the present application does not limit the width, depth or number of any trenches 1300 .
  • Those skilled in the art can design the size of the groove 1300 according to actual needs or machine requirements.
  • the second part 132 of the single lead 130 may be divided into a plurality of sub-leads arranged at intervals. Feet 1320.
  • the dicing method can be, but is not limited to, etching or laser.
  • the electronic component package 10 is provided with a first side surface 101 and a second side surface 102 which are disposed opposite to each other.
  • the second side 1302 is connected between the first side 101 and the second side 102 .
  • the second surface 1302 is parallel to the reference plane, and both the first side surface 101 and the second side surface 102 are perpendicular to the reference plane.
  • the plurality of pins 130 include a first pin 1311 and a second pin 1312 .
  • the first pin 1311 is closest to the first side surface 101
  • the second pin 1312 is closest to the second side surface 102
  • both the first pin 1311 and the second pin 1312 are provided with a plurality of sub-pins 1320 . It can be understood that both the first lead 1311 and the second lead 1312 are located at the edge of the electronic component package 10 .
  • the possibility of fatigue failure of the leads 130 on the edge of the electronic component package 10 due to vibration of the electronic component assembly structure 100 is relatively high, so the leads 130 on the edge of the electronic component package 10 are cut to form
  • the plurality of sub-pins 1320 arranged at intervals not only increases the reliability of the welding of the edge pins 130, but also avoids the cost increase by cutting all the pins 130.
  • the second portion 132 of each pin 130 may also be provided with a plurality of sub-pins 1320 arranged at intervals, which is not limited in the present application.
  • the electronic component package 10 is substantially rectangular.
  • the plurality of pins 130 includes a first pin 1311 , a second pin 1312 , a third pin 1313 and a fourth pin 1314 , the first pin 1311 , the second pin 1312 , the third pin 1313 and the fourth pin 1313
  • the pins 1314 are respectively located at four corners of the first circuit layer 13 , and the first pin 1311 , the second pin 1312 , the third pin 1313 and the fourth pin 1314 are all provided with a plurality of sub-pins 1320 .
  • the pins 130 at the four diagonal corners of the electronic component package 10 are at greater risk of oscillating and detaching, and the pins 130 at the four diagonal corners are each provided with a plurality of sub-pins 1320 arranged at intervals , so as to improve the reliability of the electronic component assembly structure 100 .
  • the plurality of pins 130 further include fifth pins 1315 , the fifth pins 1315 are located in the middle area of the electronic component package 10 , and the fifth pins 1315 are provided with a plurality of Spaced sub-pins 1320.
  • FIG. 9 is a partial cross-sectional schematic diagram of the pin 130 shown in FIG. 7 in another implementation manner along B-B.
  • the standard size of the trench 1300 gradually increases from the opening of the trench 1300 toward the bottom surface of the trench 1300 . It can be understood that the opening area of the trench 1300 is smaller than the area of the bottom surface of the trench 1300 .
  • the cross-sectional shape of the trench 1300 is an inverted trapezoid.
  • the standard size of the groove 1300 gradually increases from the opening of the groove 1300 to the bottom surface of the groove 1300 .
  • FIG. 10 is a partial cross-sectional schematic diagram of the electronic component assembly structure 100 provided by the present application in the third embodiment. Specifically, the electronic component assembly structure 100 shown in this embodiment can be combined with any one of the structures of the electronic component package body 10 in FIGS. 2 to 9 .
  • the electronic component package 10 includes a substrate 110 , an electronic component 11 packaged inside the substrate 110 , and pins 130 electrically connected to the electronic component 11 .
  • the pins 130 protrude from the surface of the substrate 110 .
  • the portion of the pin 130 protruding from the substrate 110 may be in the shape of a truncated cone or a trapezoid.
  • a groove 1300 is provided on a side of at least one pin 130 facing away from the substrate 110 .
  • the second circuit layer 14 in the substrate 110 includes a first pad 141 and a second pad 142 .
  • the first pads 141 are spaced apart from the second pads 142 .
  • the electronic component package 10 also includes bonding wires 16 .
  • the bonding wire 16 is electrically connected between the first pad 141 and the second pad 142 to electrically connect the first pad 141 and the second pad 142 .
  • the bonding wire 16 electrically connects the first element 111 and the second element 112 , and at least part of the structure of the bonding wire 16 is located outside the encapsulation layer 12 .
  • the application does not limit the shape or quantity of the first pads 141 and the second pads 142, and those skilled in the art can design the first pads 141 and the second pads 142 according to actual needs.
  • the bonding wire 16 may be a metal wire or a metal strip. That is, the second wiring layer 14 is bonded by wire bonding and/or clip bonding. This application does not limit the number, position and shape of the pads 140 in the second circuit layer 14, and those skilled in the art can design them according to actual needs.
  • the second circuit layer 14 is formed on the upper surface of the encapsulation layer 12 , and the first pad 141 and the second pad 142 in the second circuit layer 14 are electrically connected through the bonding wire 16 to avoid the first When the pads 141 and the second pads 142 are soldered by solder reflow, they are remelted during the solder reflow process, thereby improving the reliability of the electronic component package 10 .
  • the electronic component package body 10 further includes a package body 15 .
  • the package body 15 is located on the side of the substrate 110 away from the circuit board 20 .
  • the package body 15 is located on the side of the substrate 110 on the side of the second circuit layer 14 away from the package layer 12 , and the bonding wires 16 are packaged inside the package body 15 .
  • the package body 15 is made of magnetic material.
  • the magnetic material is a liquid magnetic material
  • the bonding wire 16 is encapsulated by the liquid magnetic material to form the package body 15 using the magnetic material.
  • the application does not limit the types of magnetic materials, which can be designed by those skilled in the art according to actual needs.
  • the pads 140 in the second circuit layer 14 are connected by the bonding wires 16 , and the surface of the second circuit layer 14 is the package body 15 made of magnetic material, and the package body 15 and the bonding wires 16 are formed together.
  • Complete windings of magnetic components eg, transformers, inductors
  • the package body 15 is seamlessly connected with the first circuit layer 13 , which facilitates heat dissipation of the electronic components 11 in the package layer 12 , thereby improving the heat dissipation performance of the electronic component package body 10 .
  • the magnetic material is a microscopic insulating material, and the appearance is non-conductive, and the encapsulation body 15 using the magnetic material is not electrically connected to the bonding wire 16 .
  • the inside of the bonding wire 16 is made of a metal material, and the outside is wrapped with an insulating material, so as to avoid mutual interference between the bonding wire 16 and the package body 15 .
  • FIG. 11 is a schematic structural diagram of the electronic component package 10 provided by the present application in Embodiment 4;
  • FIG. 12 is a partial cross-sectional schematic view of the electronic component package 10 shown in FIG. 11 .
  • the electronic component package 10 includes a substrate 110 , an electronic component 11 packaged inside the substrate 110 , and pins 130 electrically connected to the electronic component 11 .
  • the plurality of pins 130 are used for soldering with the circuit board 20 to realize electrical connection between the electronic component package 10 and the circuit board 20 .
  • the pins 130 are not protruded from the substrate 110 , and at least one side of the pins 130 facing away from the substrate 110 is provided with a groove 1300 .
  • the groove 1300 is recessed from the bottom surface 1321 of the lead 130 toward the substrate 110 side.
  • the bottom surface of the pin 130 is flush with the second surface 1302 of the substrate 110 .
  • the bottom surface of the pin 130 can also be located between the first surface 1301 and the second surface 1302 of the first circuit layer 13 .
  • the grooves 1300 do not penetrate the pins 130 . It can be understood that the pins 130 are disposed with a gap relative to the exposed surface of the first circuit layer 13 , and are connected to each other as a whole on the side close to the substrate 110 . Exemplarily, the plurality of sub-pins 1320 separated by the trenches 1300 use the same electrical network.
  • a groove 1300 is provided on the side of a single pin 130 away from the substrate 110 , and the solder joint can be embedded in the groove 1300 , which not only increases the exposed surface area of the single pin 130 , but also enables the pin to be placed in different Welding is performed in different dimensions, thereby increasing the welding strength of a single pin 130 and improving the reliability of the welding between the electronic component package 10 and the circuit board 20 .
  • the present application does not limit the width, depth or number of any trenches 1300 . Those skilled in the art can design the size of the groove 1300 according to actual needs or machine requirements.
  • the bottom of the single lead 130 may be cut to divide the bottom of the single lead 130 into a plurality of sub-leads 1320 arranged at intervals.
  • the dicing method can be, but is not limited to, etching or laser.
  • a groove 1300 is provided on a side of the lead 130 located at the edge of the electronic component package 10 away from the substrate 110 among the plurality of leads 130 .
  • the electronic component package body 10 is substantially rectangular, and the pins 130 of the plurality of pins 130 located at four opposite corners of the electronic component package body 10 are provided with grooves 1300 . That is, the plurality of pins 130 located at the four opposite corners of the electronic component package 10 include a plurality of sub-pins 1320 arranged in gaps.
  • the solder joint not only surrounds the bottom surface of the lead, but also fills the groove on the bottom surface of the lead, increasing the number of solder joints.
  • the soldered area of the point to the pin is not only surrounds the bottom surface of the lead, but also fills the groove on the bottom surface of the lead, increasing the number of solder joints.
  • the possibility of fatigue failure of the leads 130 on the edge of the electronic component package 10 due to vibration of the electronic component assembly structure 100 is relatively high, so the leads 130 on the edge of the electronic component package 10 are cut to form
  • the plurality of sub-pins 1320 arranged at intervals not only increases the reliability of the welding of the edge pins 130, but also avoids the cost increase by cutting all the pins 130.
  • the side of each pin 130 away from the substrate 110 may also be provided with a plurality of sub-pins 1320 arranged at intervals, which is not limited in the present application.
  • the pin 130 with the largest surface area among the plurality of pins 130 includes a plurality of sub-pins 1320 arranged in a gap.
  • the lead 130 located in the middle area of the electronic component package 10 has the largest surface area, and the lead 130 includes a plurality of sub-leads 1320 arranged in gaps, so as to further improve the electronic component package 10 and the circuit board 20 Soldering reliability.

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Abstract

本申请实施例公开了一种电子元件封装体、电子元件组装结构及电子设备。电子元件组装结构包括：电子元件封装体，电子元件封装体包括基板、电子元件和引脚，电子元件封装于基板的内部，引脚与电子元件电性连接，引脚包括第一部分和与第一部分连接的第二部分，第一部分嵌设于基板，第二部分相对基板凸出；第二部分包括底面和侧面，底面为引脚远离基板的外表面，侧面连接在底面和基板之间；电路板，电子元件封装体安装于电路板，且电路板与电子元件电性连接；焊点，焊点连接在引脚与电路板之间，并包围第二部分的底面和侧面。本申请提供的电子元件组装结构中电子元件封装体与电路板焊接的可靠性较高。

Description

电子元件封装体、电子元件组装结构及电子设备
本申请要求于2021年02月10日提交中国专利局、申请号为202110183926.9、申请名称为“电子元件封装体、电子元件组装结构及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到封装技术领域，尤其涉及一种电子元件封装体、电子元件组装结构及电子设备。
背景技术
随着电子产品朝着多功能化和轻便化方向发展，芯片埋入式封装成为电子元件封装技术领域的研究热点。现有的芯片埋入式封装基板，一般采用触点阵列封装(land grid array，LGA)来实现封装组件和电路板之间的固定。然而，由于触点阵列封装是一种表面贴装封装，封装组件与电路板通过表面接触实现焊接，焊接的可靠性较差，容易造成焊点处断裂，影响封装组件的可靠性。
发明内容
本申请提供了一种电子元件封装体、电子元件组装结构及电子设备。本申请提供的电子元件封装体的引脚具有不同维度的焊接面积，提高了电子元件组装结构中电子元件封装体与电路板焊接的可靠性。
第一方面，本申请提供一种电子元件组装结构。电子元件组装结构包括电子元件封装体、电路板及焊接在电路板与电子元件封装体之间的焊点。电子元件封装体包括基板、电子元件和引脚。电子元件封装于基板的内部。引脚与电子元件电性连接，且引脚的部分结构相对基板露出，用于与电路板进行焊接。其中，电子元件可以为芯片等有源器件，也可以为电容、电感、电阻等无源器件。示例性的，电子元件的数量为多个。在本申请中，电子元件封装于封装体内，基板为电子元件封装的载体，为封装的电子元件提供电连接、保护、支撑、散热、组装等功效。
示例性的，基板包括封装层和第一线路层。电子元件封装于封装层的内部。第一线路层与封装层层叠设置。第一线路层设有相背设置的第一面和第二面。第一面位于基板与第二面之间。各引脚包括第一部分和与第一部分连接的第二部分。第一部分嵌设于第一线路层。第二部分相对第二面凸出。可以理解的，第二面为电子元件封装体的底面，电子元件封装体自底面出引脚。
在一些可能的实现方式中，第二部分包括底面和侧面。底面为引脚远离封装层的外表面，侧面位于底面和第二面之间。可以理解的，底面和侧面均相对第二面外露。焊点包围引脚凸出第二面的第二部分。也即，焊点包围第二部分的底面和侧面。如图3所示，焊点不仅位于引脚的底面，也位于第二部分的侧面，以包围第二部分。
在本实施例中，引脚相对基板凸出，使得与电路板焊接的引脚部分为立体引脚，引脚具有不同维度的焊接面积，焊点不仅能够连接引脚的底面，也能够连接引脚的侧面，不仅增加了引脚的焊接面积，也增强了引脚在不同维度的焊接强度，提高了电子元件封装体与电路板焊接的可靠性。电子元件封装体与电路板组装焊接时，引脚的底壁及凸出的引脚的侧壁均可以爬锡，以使焊点包围引脚的底面和侧面。
在一些可能的实现方式中，引脚的数量为多个，多个引脚间隔设置。可以理解的，引脚 采用导电材料，绝缘材料间隔在多个引脚之间。在一些实施例中，引脚嵌设于第一线路层的部分与引脚凸出第一线路层的部分可以一体成型，也可以分步形成。本申请并不限定，电子元件封装体中形成引脚的工艺，可以是刻蚀工艺，也可以是激光焊接工艺，本领域技术人员能够根据实际需求进行设计。
其中，第一部分采用的材料与第二部分采用的主体材料相同。示例性的，第一部分和第二部分采用的主体材料可以是但不仅限于铜、铝或金。可以理解的，引脚嵌设于第一线路层中的第一部分采用的材料在焊接过程中不会重熔，以保证电子元件封装体电路的可靠性。其中，第一部分采用的材料与第二部分采用的主体材料相同，也即引脚的第一部分和第二部分均不会重熔。
在本实施例中，引脚的第一部分和第二部分采用的主体材料与焊点采用的材料不同，电子元件封装体与电路板焊接的过程中引脚的第一部分和第二部分不会重熔，第一部分和第二部分形状大致不变，以提高电子设备焊接的可靠性。而现有技术中通过焊球阵列(ballgrid array，BGA)来实现电子元件封装体与电路板焊接时，焊球在焊接的过程中会重熔发生形变。
在一些可能的实现方式中，至少一个引脚的侧面包括倾斜面。示例性的，引脚的第二部分可以呈梯形台或棱台。
在本实施例中，第二部分的侧面包括倾斜面，第二部分的截面形状可以为梯形，在第二部分高度相同的基础上，扩大第二部分的侧面的表面积，以进一步地增加引脚的焊接面积，提高了电子元件封装体与电路板焊接的可靠性。
在一些可能的实现方式中，至少一个引脚的侧面包括台阶面。示例性的，引脚的第二部分可以呈台阶结构。在本实施例中，引脚中第二部分的截面形状可以为台阶形状，扩大第二部分的侧面的表面积，以进一步地增加引脚的焊接面积，提高了电子元件封装体与电路板焊接的可靠性。本申请实施例并不限定引脚中第二部分的具体形状，本领域技术人员能够根据实际需求对此进行设计。
在一些可能的实现方式中，至少一个引脚的第二部分包括曲面。示例性的，引脚的第二部分呈圆台。在此实施例中，引脚的侧面呈曲面。在本实施例中，第二部分呈圆台，在第二部分高度相同的基础上，扩大第二部分的侧面的表面积，以进一步地增加引脚的焊接面积，提高了电子元件封装体与电路板焊接的可靠性。
在一些可能的实现方式中，底面的面积大于引脚沿基板表面的截面的面积。也即，底面的面积大于引脚沿第二面的截面的面积。
在本实施例中，引脚中底面的面积大于引脚沿第二面的截面的面积，使得电子元件封装体与电路板焊接完成后焊点与引脚在垂直方向可以形成互锁的力，进一步地提高焊点在电子元件封装体的厚度方向的强度，避免因电子元件的长期振动而导致焊点失效，从而提高了电子设备的可靠性。
在一些可能的实现方式中，焊点包括第一段和与第一段连接的第二段。第一段位于引脚的底面与电路板之间，第二段围设在引脚的侧面。第二段在电路板的投影与引脚的底面在电路板的投影部分重叠。可以理解的，电子元件封装体与电路板焊接后，电子设备中连接电子元件封装体与电路板的焊点与引脚形成互锁结构。
在本实施例中，引脚中底面的面积大于引脚沿第二面的截面的面积，使得焊点与引脚在垂直方向可以形成互锁的力，进一步地提高焊点在电子元件封装体的厚度方向的强度，避免因电子元件的长期振动而导致焊点失效，从而提高了电子设备的可靠性。
在一些可能的实现方式中，焊点采用的材料包括锡，且第二部分采用的主体材料不同于 焊点采用的材料。可以理解的，焊点采用的材料包括锡，电子元件封装体与电路板焊接的过程中焊点会重熔，以包裹第二部分，有效地将电子元件封装体与电路板焊接。
在此实施例中，焊点采用的材料包括锡，且焊点采用的材料不同于第二部分采用的主体材料，电子元件封装体与电路板焊接的过程中第二部分不会重熔，也即第二部分在焊接过程中大致形状不会改变，以使焊点有效地包围第二部分，从而提高电子元件封装体与电路板焊接的可靠性。
在一些可能的实现方式中，至少一个引脚背离基板的一侧设有沟槽。也即，引脚朝电路板的一侧设有沟槽。沟槽自引脚的底面朝基板的一侧凹陷。焊点的部分结构嵌设于沟槽。可以理解的，沟槽并未贯穿引脚。示例性的，沟槽的数量为多个。至少一个引脚的第二部分包括多个子引脚。多个子引脚间隙设置，且多个子引脚均与第一部分连接。多个引脚中的部分引脚的第二部分包括多个间隔设置的子引脚。沟槽将第二部分分隔成多个间隔设置的子引脚。示例性的，多个子引脚对称排布。多个子引脚呈矩阵排布。其中，任意相邻的两个子引脚之间的间隙小于任意相邻的两个引脚之间的间隙。
在本实施例中，单个引脚背离基板的一侧设有沟槽，增加了单个引脚外露的表面积，焊点的部分结构嵌设于沟槽，进一步地增加了单个引脚的焊接面积，电子元件封装体焊接时焊料可以填充沟槽，进一步地提高了电子元件封装体与电路板焊接的可靠性。其中，本申请并不限定任意沟槽的宽度、深度或数量等。本领域技术人员能够根据实际需求或机台要求设计沟槽的尺寸。示例性的，在制备电子元件封装体的方法中，可以对单个引脚的第二部分进行切分，以将单个引脚的第二部分分割成多个间隔设置的子引脚。切分方法可以是但不仅限于刻蚀或激光。
在一些可能的实现方式中，电子元件封装体设有相背设置的第一侧面和第二侧面。第二面连接在第一侧面和第二侧面之间，多个引脚包括第一引脚和第二引脚。第一引脚最靠近第一侧面，第二引脚最靠近第二侧面，且第一引脚和第二引脚背离基板的一侧均设有沟槽。
在本实施例中，针对电子元件封装体边缘的引脚因电子设备的振动而疲劳失效的可行性较大，因此针对电子元件封装体边缘的引脚进行切分形成多个间隔设置的子引脚，不仅增加了边缘引脚焊接的可靠性，也避免了对全部的引脚进行切分而增加成本。在其他实施例中，各引脚的第二部分也可以均设有多个间隔设置的子引脚，本申请对此并不限定。
在一些可能的实现方式中，基板背离电路板的一侧设有焊盘。示例性的，基板还包括与封装层层叠设置的第二线路层。焊盘嵌设于第二线路层。可以理解的，第二线路层设置于电子元件封装体的顶面，第一线路层设置于电子元件封装体的底面。
在本实施例中，电子元件封装体设有相背设置的第一线路层和第二线路层，使得电子元件封装体的双面(顶面和底面)均具有能够起到电性连接的线路层，能够为封装于电子元件封装体内的电子元件的双面互连提供良好的基础，有利于在局限化的空间布局内实现最短的互连路径及实现基板的薄型封装，实用性强，可靠性佳。
在一些可能的实现方式中，电子元件封装体还包括键合线。焊盘包括第一焊盘和第二焊盘。第一焊盘与第二焊盘间隔设置，并通过键合线电性连接。其中，键合线可以是金属线，也可以是金属条。也即，第二线路层通过金属线键合(wire bonding)和/或带状金属键合(clip bonding)。本申请并不限定，第二线路层中焊盘的数量、位置及形状等，本领域技术人员能够根据实际需求对此设计。
本实施例中，在基板的上表面形成第二线路层，通过键合线电性连接第二线路层中的第一焊盘和第二焊盘，避免了第一焊盘与第二焊盘通过焊锡回流焊接时，在焊锡回流过程中重 熔，从而提高了电子元件封装体的可靠性。
在一些可能的实现方式中，电子元件封装体还包括封装体。封装体位于基板远离电路板的一侧。键合线封装于封装体的内部，且封装体采用磁性材料。示例性的，磁性材料为液态磁性材料，通过液态磁材料灌胶封装键合线，以形成采用磁性材料的封装体。本申请并不限定，磁性材料的种类，本领域技术人员能够根据实际需求对此进行设计。
在本实施例中，第二线路层中的焊盘通过键合线连接，并且第二线路层的表面为采用磁性材料的封装体，封装体与键合线一起形成完整的磁元件(例如变压器、电感)的绕组，能够阻止电子元件封装体内部的电流过大，有利于提高电子设备的可靠性。与此同时，封装体与第一线路层无缝连接，有利于基板内各电子元件的散热，从而提高了电子元件封装体的散热性能。
第二方面，本申请还提供一种电子元件组装结构。电子元件组装结构包括电子元件封装体、电路板和焊接在电子元件封装体与电路板之间的焊点。电子元件封装体包括基板、电子元件和引脚。电子元件封装于基板的内部，引脚与电子元件电性连接。引脚背离电子元件的一侧设有沟槽。沟槽自引脚的底面朝电子元件的一侧凹陷。焊点嵌设于沟槽。其中，沟槽并未贯穿引脚。可以理解的，引脚相对第一线路层露出的表面间隙设置，在靠近基板的一侧相互连接为一整体。示例性的，被沟槽间隔的多个子引脚采用同一电性网络。
在本实施例中，单个引脚背离基板的一侧设有沟槽，焊点嵌设于沟槽，不仅增加了单个引脚外露的表面积，也增强了引脚在三维方向的焊接强度，提高了电子元件封装体与电路板焊接的可靠性，从而提高了电子元件组装结构的可靠性。其中，本申请并不限定任意沟槽的宽度、深度或数量等。
第三方面，本申请还提供一种电子设备。电子设备包括壳体和第一方面或第二方面提供的电子元件组装结构。电子元件组装结构安装于壳体。
在此实施例中，电子设备包括第一方面与第二方面提供的电子元件组装结构，电子元件组装结构中电子元件封装体与电路板具有不同维度的焊接面积，提高了电子元件组装结构二次焊接的可靠性，从而提高了电子设备的可靠性。
第四方面，本申请还提供一种电子元件封装体。电子元件封装体包括基板、电子元件和引脚。电子元件封装于基板的内部。引脚与电子元件电性连接，且引脚的部分结构相对基板露出，用于与电路板进行焊接。示例性的，基板包括封装层和第一线路层。电子元件封装于封装层的内部。第一线路层与封装层层叠设置。第一线路层设有相背设置的第一面和第二面。第一面位于基板与第二面之间。第一线路层包括多个间隔设置的引脚。多个引脚与电子元件电性连接。
各引脚包括第一部分和与第一部分连接的第二部分。第一部分嵌设于第一线路层。第二部分相对第二面凸出。可以理解的，第二面为电子元件封装体的底面，电子元件封装体自底面出引脚。第二部分包括底面和侧面。底面为引脚远离封装层的外表面，侧面位于底面和第二面之间。可以理解的，底面和侧面均相对第二面外露。底面和侧面均用于与焊料焊接。
在本实施例中，引脚相对基板凸出，使得与电路板焊接的引脚部分为立体引脚，引脚具有不同维度的焊接面积，焊点不仅能够连接引脚的底面，也能够连接引脚的侧面，不仅增加了引脚的焊接面积，也增强了引脚在不同维度的焊接强度，提高了电子元件封装体与电路板焊接的可靠性。
在一些可能的实现方式中，引脚的数量为多个，多个引脚间隔设置。至少一个引脚的侧面包括倾斜面。示例性的，引脚的第二部分可以呈台阶结构。或者，至少一个引脚的侧面包 括台阶面。示例性的，引脚的第二部分可以呈台阶结构。或者，至少一个引脚的第二部分包括曲面。示例性的，引脚的第二部分呈圆台。
在本实施例中，第二部分的侧面包括倾斜面、台阶面或曲面，在第二部分高度相同的基础上，扩大第二部分的侧面的表面积，以进一步地增加引脚的焊接面积，提高了电子元件封装体与电路板焊接的可靠性。
在一些可能的实现方式中，底面的面积大于引脚沿基板表面的截面的面积。也即，底面的面积大于引脚沿第二面的截面的面积。
在本实施例中，引脚中底面的面积大于引脚沿第二面的截面的面积，使得电子元件封装体与电路板焊接完成后焊点与引脚在垂直方向可以形成互锁的力，进一步地提高焊点在电子元件封装体的厚度方向的强度，避免因电子元件的长期振动而导致焊点失效，从而提高了电子设备的可靠性。
在一些可能的实现方式中，第一部分采用的材料与第二部分采用的主体材料相同。示例性的，第一部分和第二部分采用的主体材料可以是但不仅限于铜、铝或金。可以理解的，引脚嵌设于第一线路层中的第一部分采用的材料在焊接过程中不会重熔，以保证电子元件封装体电路的可靠性。其中，第一部分采用的材料与第二部分采用的主体材料相同，也即引脚的第一部分和第二部分均不会重熔。
在本实施例中，引脚的第一部分和第二部分采用的主体材料且与焊点采用的材料不同，电子元件封装体与电路板焊接的过程中引脚的第一部分和第二部分不会重熔，第一部分和第二部分形状大致不变，以提高电子设备焊接的可靠性。
在一些可能的实现方式中，至少一个引脚背离基板的一侧设有沟槽。也即，引脚朝电路板的一侧设有沟槽。沟槽自引脚的底面朝基板的一侧凹陷。
在本实施例中，单个引脚背离基板的一侧设有沟槽，增加了单个引脚外露的表面积，进一步地增加了单个引脚的焊接面积，电子元件封装体焊接时焊料可以填充沟槽，进一步地提高了电子元件封装体与电路板焊接的可靠性。其中，本申请并不限定任意沟槽的宽度、深度或数量等。
在一些可能的实现方式中，基板背离引脚的一侧包括第一焊盘和第二焊盘。第一焊盘与第二焊盘间隔设置。电子元件组装结构还包括键合线和封装体。键合线电性连接在第一焊盘与第二焊盘之间。封装体位于基板远离电路板的一侧，键合线封装于封装体的内部，且封装体采用磁性材料。
在本实施例中，基板背离引脚的一侧的焊盘通过键合线连接，并且嵌设于采用磁性材料的封装体，封装体与键合线一起形成完整的磁元件(例如变压器、电感)的绕组，能够阻止电子元件封装体内部的电流过大，有利于提高电子设备的可靠性。与此同时，封装体与第一线路层无缝连接，有利于基板内各电子元件的散热，从而提高了电子元件封装体的散热性能。
第五方面，本申请还提供一种电子元件封装体。电子元件封装体包括包括基板、电子元件和引脚。电子元件封装于基板的内部，引脚与电子元件电性连接。引脚背离电子元件的一侧设有沟槽。沟槽自引脚的底面朝电子元件的一侧凹陷。沟槽用于填充焊料。其中，沟槽并未贯穿引脚。可以理解的，引脚相对第一线路层露出的表面间隙设置，在靠近基板的一侧相互连接为一整体。示例性的，被沟槽间隔的多个子引脚采用同一电性网络。
在本实施例中，单个引脚背离基板的一侧设有沟槽，不仅增加了单个引脚外露的表面积，也增强了引脚在三维方向的焊接强度，提高了电子元件封装体与其他部分焊接的可靠性。其中，本申请并不限定任意沟槽的宽度、深度或数量等。
附图说明
为了说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1是本申请实施例提供的电子元件组装结构的部分结构示意图；
图2是本申请提供的电子元件组装结构在实施例一中的部分截面示意图；
图3是图2所示A部分在第一实现方式中的结构示意图；
图4是图2所示A部分在第二实现方式中的结构示意图；
图5是图2所示电子元件封装体在第三实现方式中的部分结构示意图；
图6是图2所示电子元件封装体的俯视图；
图7是本申请提供的电子元件组装结构在实施例二中的俯视图；
图8是图7所示电子元件封装体沿B-B处的部分截面示意图；
图9是图7所示引脚沿B-B处在另一实现方式中的部分截面示意图；
图10是本申请提供的电子元件组装结构在实施例三中的部分截面示意图；
图11是本申请提供的电子元件封装体在实施例四中的结构示意图；
图12是图11所示电子元件封装体的部分截面示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
本申请提供一种电子设备。电子设备包括壳体和电子元件组装结构。电子元件组装结构安装于壳体。电子设备可以是手机、平板电脑、笔记本电脑、车载设备、可穿戴设备、无人机、路由器等产品。电子设备也可以是功率电源模块、通讯信号发射基站、网络交换设备等设备。在本实施例中，以电子设备为车载设备为例来进行描写。
请参阅图1，图1是本申请实施例提供的电子元件组装结构100的部分结构示意图。如图1所示，电子元件组装结构100包括电子元件封装体10、电路板20和连接在电子元件封装体10和电路板20之间的焊点30。电子元件封装体10内包括电子元件11。电子元件11可以为芯片等有源器件，也可以为电容、电感、电阻等无源器件。本领域技术人员能够根据实际需求选择电子元件11的种类及数量，本申请对此并不限定。电子元件封装体10为电子元件11封装的载体，为封装的电子元件11提供电连接、保护、支撑、散热、组装等功效。
在一些实施例中，电子元件11的数量为多个。如图1所示，示例性的，电子元件11包括第一元件111、第二元件112和第三元件113。第二元件112间隔在第一元件111和第三元件113之间。在一些可能的实现方式中，第二元件112为芯片，第一元件111为电阻，第二元件112为电容。
在本申请实施例中，电子元件封装体10可以采用系统级封装(system in package，SIP)或电源系统级封装(power supply-in-package，PSiP)或芯片埋入式基板(embedded chip substrate，ECP)。系统级封装是将多种功能电子元件，例如处理器、存储器、电源管理芯片等功能电子元件集成在一个封装体内，以实现一个基本完整的功能。芯片埋入式基板可理解为在基板内部贴装芯片，再将芯片通过封装材料封装，通过铜孔、铜柱等方式实现互连的一种基板结构。在本实施例中，以电子元件封装体10将以芯片埋入式基板(embedded chip substrate，ECP)为例进行具体说明。
电路板20可理解为电子元件封装体10的载体，其能够承载电子元件封装体10并与电子元件封装体10组装。电路板20与电子元件封装体10通过焊点30焊接以电性连接，进而实 现与电子元件封装体10的电气互联。本申请实施例中，以电子元件封装体10安装于电路板20为例来进行描写。在其他实施例中，电子元件封装体10也能够安装于其他结构，本申请对此并不限定。
需说明的是，图1的目的仅在于示意性的描述电路板20和电子元件封装体10的连接关系，并非是对各个设备的连接位置、具体构造及数量做具体限定。而本申请实施例所示意的结构并不构成对电子元件组装结构100的具体限定。在本申请另一些实施例中，电子元件组装结构100可以包括比图示更多的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
在本实施例中，电子元件封装体与电路板通过触点阵列封装(land grid array，LGA)的方式实现焊接。触点阵列封装是一种表面贴装封装，电子元件封装体与电路板焊接的可靠性较差，电子设备在长期机械振动或温度变化冲击的场景下，存在焊接不稳固而导致电性失效的风险。例如，电子元件封装体的引脚与电子元件封装体的外表面齐平，电路板的表面贴合电子元件封装体的表面，以连接电子元件封装体的引脚与电路板上对应的引脚，电子设备在长期机械振动过程中，电子元件封装体与电路板的焊点发生疲劳失效，造成焊点处断裂，影响电子设备的可靠性。
由此，本申请提供一种电子元件封装体10，电子元件封装体10中的引脚具有不同维度的焊接面积，提高了电子元件封装体10与电路板20焊接的可靠性，降低了电子元件组装结构100在长期振动后造成电子元件封装体10与电路板20焊接失效的风险，有效提高了电子元件组装结构100的板级可靠性。下文主要通过四个实施例来具体描写，本申请提供的电子元件组装结构100和对应的电子元件封装体10。
请参阅图2，图2是本申请提供的电子元件组装结构100在实施例一中的部分截面示意图。电子元件封装体10安装于电路板20的安装面201。焊点30用于实现电子元件封装体10与电路板20之间的电性连接。示例性的，电子元件封装体10包括基板110、电子元件11和引脚130。电子元件11封装于基板110的内部。引脚130与电子元件11电性连接，且引脚130的部分结构相对基板110露出，用于与电路板20进行焊接。
示例性的，基板110包括封装层12和第一线路层13。电子元件11封装于封装层12的内部。第一线路层13与封装层12层叠设置。第一线路层13设有相背设置的第一面1301和第二面1302。第一面1301位于封装层12与第二面1302之间。安装面201面向第二面1302，焊点30连接在引脚130与电路板20之间。可以理解的，第二面1302为基板110的底面。如图2所示，在本实施例中，以第一线路层13的第一面1301接触封装层12为例来进行描写。在其他实施例中，封装层12与第一线路层13之间还可以设有其他结构，例如线路层，本申请对此并不限定。本领域技术人员能够根据实际需求，设计第一线路层13与封装层12之间的结构。
其中，引脚130的数量为多个，多个引脚130间隔设置。多个引脚130采用导电材料，并通过绝缘材料间隔设置，绝缘材料可以但不仅限于液态光致阻焊剂(绿油)。多个引脚130与电子元件11电性连接，并通过多个焊点30与电路板20电性连接。示例性的，引脚130与焊点30的数量对应。电子元件封装体10组装于电路板20时，通过引脚130与焊点30实现电性连接。与电路板20电连接的某个工作模块产生的信号依次经过电路板20、引脚130传输至电子元件封装体10内；或者，电子元件封装体10内处理产生的信号依次经过引脚130、焊点30、电路板20至对应的工作模块，从而实现电子元件封装体10与对应的工作模块之间的通信。
请一并参阅图2和图3，图3是图2所示A部分在第一实现方式中的结构示意图。引脚130包括第一部分131和与第一部分131连接的第二部分132。第一部分131嵌设于第一线路层13，第二部分132相对基板110凸出。示例性的，第一部分131与第二部分132直接连接。在其他实施例中，第一部分131与第二部分132也可以间接连接，本申请对此并不限定。可以理解的，每个引脚130自第一面1301贯穿第二面1302，并相对第二面1302凸出。也即，引脚130的部分结构相对第二面1302(电子元件封装体10的外表面)凸出，以形成立体结构的引脚130。可以理解的，第二面1302为电子元件封装体10的底面，本申请提供的电子元件封装体10自底面出引脚。
第二部分132包括底面1321和侧面1322。底面1321为引脚130远离封装层12的外表面，侧面1322位于底面1321和第二面1302之间。可以理解的，底面1321和侧面1322均相对第二面1302外露。其中，电子元件封装体10放置于一参考平面时，底面1321接触参考平面或平行于参考平面，侧面1322连接在第二面1302与参考平面之间。侧面1322可以是曲面，也可以是平面，本申请对此并不限定。
其中，焊点30包围引脚130凸出第二面1302的第二部分132。也即，焊点30包围第二部分132的底面1321和侧面1322。如图3所示，焊点30不仅位于引脚130的底面1321，也位于第二部分132的侧面1322，以包围第二部分132。
在本实施例中，引脚130相对基板110凸出，使得与电路板20焊接的引脚130部分为立体引脚130，引脚130具有不同维度的焊接面积，焊点30不仅能够连接引脚130的底面1321，也能够连接引脚130的侧面1322，不仅增加了引脚130的焊接面积，也增强了引脚130在不同维度的焊接强度，提高了电子元件封装体10与电路板20焊接的可靠性。电子元件封装体10与电路板20组装焊接时，引脚130的底壁及凸出的引脚130的侧壁均可以爬锡，以使焊点30包围引脚130的底面1321和侧面1322。
可以理解的，第一线路层13还包括绝缘材料，绝缘材料间隔在多个引脚130之间。在一些实施例中，引脚130嵌设于第一线路层13的部分与引脚130凸出第一线路层13的部分可以一体成型，也可以分步形成。本申请并不限定，电子元件封装体10中形成引脚130的工艺，可以是刻蚀工艺，也可以是激光焊接工艺，本领域技术人员能够根据实际需求进行设计。例如，先刻蚀第一线路层13以形成图案化的第一线路层13，沿图案化的第一线路层13填充导电材料后，沿填充的导电材料结构继续电镀导电材料，以分步形成凸出第一线路层13的引脚130。或者，通过光刻胶遮盖图案化的第一线路层13中导电材料，通过掩膜板刻蚀图案化的第一线路层13中的绝缘材料的部分结构，以一体成型凸出第一线路层13的引脚130。
在一些实施例中，焊点30采用的材料包括锡，且焊点30采用的材料不同于第二部分132采用的材料。电子元件封装体10与电路板20焊接的过程中焊点30会重熔，以包裹第二部分132，此时第二部分132不会重熔，也即第二部分132在组装过程中大致形状不会改变，以使焊点30有效地包围第二部分132，从而提高电子元件封装体10与电路板20焊接的可靠性。其中，重熔是对金属或合金的二次熔化的过程。
在一些实施例中，第一部分131采用的材料与第二部分132采用的主体材料相同。示例性的，第一部分131和第二部分132采用的材料可以是但不仅限于铜、铝或金。可以理解的，引脚130的第一部分131和第二部分132的主体部分在二次组装过程中不会重熔。
在本实施例中，引脚130的第一部分131和第二部分132采用的主体材料与焊点30采用的材料不同，电子元件封装体10与电路板20焊接的过程中引脚130的第一部分131和第二部分132的主体结构不会重熔，第一部分131和第二部分132形状大致不变，以提高电子元 件组装结构100焊接的可靠性。而现有技术中通过焊球阵列(ball grid array，BGA)来实现电子元件封装体10与电路板20焊接时，焊球在焊接的过程中会重熔发生形变。
请继续参阅图2，在一些实施例中，基板110背离电路板30的一侧包括焊盘140。示例性的，基板110还包括与封装层12层叠设置的第二线路层14。可以理解的，第二线路层14设置于电子元件封装体10的顶面，第一线路层13设置于电子元件封装体10的底面。示例性的，第二线路层14包括设有多个用于电性连接的焊盘140。其中，第二线路层14和第一线路层13的图案设计可具有差异化的可能，也即第一线路层13和第二线路层14的图案设计可以不同，本申请的实施例对此不做严格限制。第一线路层13的图案设计和第二线路层14的图案设计均可根据电子元件封装体10封装的电子元件11的需要进行设置。示例性地，第一线路层13的引脚130和第二线路层14的焊盘140可以为铜。
在本实施例中，电子元件封装体10设有相背设置的第一线路层13和第二线路层14，使得电子元件封装体10的双面(顶面和底面)均具有能够起到电性连接的线路层，能够为封装于电子元件封装体10内的电子元件11的双面互连提供良好的基础，有利于在局限化的空间布局内实现最短的互连路径及实现封装层12的薄型封装，实用性强，可靠性佳。
请继续参阅图3，在一些实施例中，多个引脚130中至少一个引脚130的侧面1322包括倾斜面。示例性的，多个引脚130的侧面1322均包括倾斜面。引脚130的第二部分132可以呈梯形台或棱台。在其他实施例中，引脚130的侧面1322呈曲面，多个引脚130中至少一个引脚130的侧面1322的一切面与底面1321不垂直。其中，某个平面与某个曲面有且仅有一个交点，那么这个平面就是曲面的切面。示例性的，引脚130的第二部分132可以呈圆台。如图3所示，在沿垂直于电子元件封装体10的厚度方向上，引脚130的第二部分132的截面呈梯形。此时，引脚130的第二部分132可以呈圆台，也可以呈梯形台。
在本实施例中，第二部分132的截面形状可以为梯形，第二部分132可以呈梯形台、棱台或圆台，在第二部分132高度相同的基础上，扩大第二部分132的侧面1322的表面积，以进一步地增加引脚130的焊接面积，提高了电子元件封装体10与电路板20焊接的可靠性。其中，本申请并不限定引脚130的侧面1322的倾斜率，本领域技术人员能够第二面1302的面积及各引脚130之间的间隙合理设计引脚130的侧面1322的倾斜角度。
请继续参阅图3，在一些实施例中，底面1321的面积大于引脚130沿基板110表面(第二面1302)的截面的面积。示例性的，图3所示梯形截面图中，梯形的下边长度大于梯形的上边长度。第二部分132呈圆台时，圆台的下表面的面积大于圆台的上表面的面积。
其中，焊点30包括第一段31和与第一段31连接的第二段32。第一段31连接在引脚130的底面1321与电路板20之间，第二段32围设在引脚130的侧面1322的周缘。第二段32在电路板20的投影与引脚130的底面1321在电路板20的投影部分重叠。可以理解的，电子元件封装体10与电路板20焊接后，电子元件组装结构100中连接电子元件封装体10与电路板20的焊点30与引脚130形成互锁结构。
在本实施例中，引脚130中底面1321的面积大于引脚130沿第二面1302的截面的面积，使得电子元件封装体10与电路板20焊接完成后焊点30与引脚130在垂直方向可以形成互锁的力，进一步地提高焊点30在电子元件封装体10的厚度方向的强度，避免因电子元件11的长期振动而导致焊点失效，从而提高了电子元件组装结构100的可靠性。
请继续参阅图4，图4是图2所示A部分在第二实现方式中的结构示意图。在此实现方式中，多个引脚130中至少一个引脚130的侧面1322为台阶面。示例性的，多个引脚130的侧面1322均为台阶面。如图4所示，在沿垂直于电子元件封装体10的厚度方向上，引脚130 的第二部分132的截面呈阶梯状。此时，引脚130的第二部分132可以是至少两个梯形台堆叠的形状，也可以是两个圆台堆叠的形状。示例性的，图4所示阶梯截面图中，阶梯呈向上趋势，电子元件封装体10与电路板20的焊点30与引脚130形成互锁结构，提高电子元件封装体10与电路板20焊接的可靠性。
可以理解的，图3和图4分别列举引脚130凸出第一线路层13在不同实现方式中的截面示意图。引脚130中第二部分132的截面形状可以为台阶形状，扩大第二部分132的侧面1322的面积，以进一步地增加引脚130的焊接面积，提高了电子元件封装体10与电路板20焊接的可靠性。本申请实施例并不限定引脚130中第二部分132的具体形状，本领域技术人员能够根据实际需求对此进行设计。
请参阅图5，图5是图2所示电子元件封装体10在第三实现方式中的部分结构示意图。具体地，本实现方式所示电子元件封装体10的结构能够与图3和图4中任意一种电子元件封装体10的结构相结合。
在此实现方式中，引脚130还包括保护层133。保护层133位于第二部分132的外表面。示例性的，保护层133通过电镀的方式包裹第二部分132的外表面。保护层133采用材料的抗氧化性强于第二部分132采用材料的抗氧化性。示例性的，第二部分132采用的材料包括但不仅限于铜或铝。保护层133采用的材料包括但不仅限于锡或金。
在本实施例中，引脚130还包括一层包裹第二部分132的保护层133，保护层133的抗氧化性能强于第二部分132的抗氧化性能，用于保护第二部分132，避免第二部分132氧化，从而进一步地提高了电子元件封装体10的可靠性。
请参阅图6，图6是图2所示电子元件封装体10的俯视图。多个引脚130的形状可以相同与可以不同，本申请对此并不限定。如图6所示，位于电子元件封装体10中间部分引脚130的底面1321的面积大于位于边缘引脚130的底面1321的面积。各引脚130之间的间隙，本领域技术人员能够根据实际情况设计，以避免相邻的引脚130之间相互干扰。本申请并不限定多个引脚130的排布方式，可以是对称排布，也可以是非对称排布。示例性的，多个引脚130沿电子元件封装体10的长度方向X及宽度方向Y均对称排布。在其他实施方式中，多个引脚130也可以不对称排布，本申请对此并不限定。
其中，本申请并不限定各引脚130的形状，多个引脚130的形状可以相同，也可以不同。示例性的，如图6所示，各引脚130的俯视图的形状呈矩形。在其他实施例中，各引脚130的俯视图的形状也可以是其他几何形状，例如圆等，本申请对此并不限定。
请继续参阅图7和图8，图7是本申请提供的电子元件组装结构100在实施例二中的俯视图；图8是图7所示电子元件封装体10沿B-B处的部分截面示意图。其中，图7所示电子元件组装结构100未示意出焊点和电路板。
以下主要描述本实施例与实施例一的不同，本实施例与实施例一相同的大部分内容不再赘述。例如，电子元件封装体10包括基板110、封装于基板110内部的电子元件11和与电子元件11电性连接的引脚130。引脚130相对基板110的表面凸出。示例性的，引脚130凸出基板110的部分可以呈圆台或梯形状。
在此实施例中，至少一个引脚130背离基板110的一侧设有沟槽1300。沟槽1300自引脚130的底面1321朝基板110一侧凹陷。也即，至少一个引脚130朝电路板的一侧设有沟槽1300。可以理解的，沟槽1300并未贯穿引脚130。示例性的，沟槽1300的数量为多个。至少一个引脚130的第二部分132包括多个子引脚1320。多个子引脚1320间隙设置，且多个子引脚1320均与第一部分131连接。沟槽1300将第二部分132分隔成多个间隔设置的子引 脚1320。示例性的，多个子引脚1320对称排布。如图7所示，多个子引脚1320呈矩阵排布。其中，任意相邻的两个子引脚1320之间的间隙小于任意相邻的两个引脚130之间的间隙。
可以理解的，引脚130中多个间隔设置的子引脚1320在相对基板110露出的表面间隙设置，在嵌设于基板110中第一线路层13内部的结构相互连接为一整体，也即多个子引脚1320为同一功能的引脚130。示例性的，多个子引脚1320采用同一电性网络。如图7所示，示例性的，沟槽1300凹陷至引脚130的第一部分131截止。在其他实施例中，沟槽1300也可以凹陷至其他深度，本申请对此并不限定。其中，电子元件封装体10安装于电路板时，焊点不仅包围引脚130的底面与侧面，焊点也填充沟槽1300，增大了焊点与引脚130的接触面积。也即，电子元件组装结构采用本实施例提供的电子元件封装体时，焊点的部分结构嵌设于沟槽1300。
在本实施例中，单个引脚130背离基板110的一侧设有沟槽1300，增加了单个引脚130外露的表面积，进一步地增加了单个引脚130的焊接面积，电子元件封装体10焊接时焊料可以填充沟槽1300，进一步地提高了电子元件封装体10与电路板20焊接的可靠性。其中，本申请并不限定任意沟槽1300的宽度、深度或数量等。本领域技术人员能够根据实际需求或机台要求设计沟槽1300的尺寸。示例性的，在制备电子元件封装体10的方法中，可以对单个引脚130的第二部分132进行切分，以将单个引脚130的第二部分132分割成多个间隔设置的子引脚1320。切分方法可以是但不仅限于刻蚀或激光。
请继续参阅图7，在一些实施例中，电子元件封装体10设有相背设置的第一侧面101和第二侧面102。第二面1302连接在第一侧面101和第二侧面102之间。其中，电子元件封装体10放置于一参考平面时，第二面1302平行于参考平面，第一侧面101和第二侧面102均垂直于参考平面。
多个引脚130包括第一引脚1311和第二引脚1312。第一引脚1311最靠近第一侧面101，第二引脚1312最靠近第二侧面102，且第一引脚1311和第二引脚1312均设有多个子引脚1320。可以理解的，第一引脚1311和第二引脚1312均位于电子元件封装体10的边缘。
在本实施例中，针对电子元件封装体10边缘的引脚130因电子元件组装结构100的振动而疲劳失效的可行性较大，因此针对电子元件封装体10边缘的引脚130进行切分形成多个间隔设置的子引脚1320，不仅增加了边缘引脚130焊接的可靠性，也避免了对全部的引脚130进行切分而增加成本。在其他实施例中，各引脚130的第二部分132也可以均设有多个间隔设置的子引脚1320，本申请对此并不限定。
如图7所示，示例性的，电子元件封装体10大致呈矩形。多个引脚130包括第一引脚1311、第二引脚1312、第三引脚1313和第四引脚1314，第一引脚1311、第二引脚1312、第三引脚1313和第四引脚1314分别位于第一线路层13的四角，且第一引脚1311、第二引脚1312、第三引脚1313和第四引脚1314均设有多个子引脚1320。
在本实施例中，电子元件封装体10的四个对角处的引脚130震荡脱离的风险较大，在四个对角处的引脚130均设有多个间隔设置的子引脚1320，以提高电子元件组装结构100的可靠性。如图7所示，在一些实施例中，多个引脚130还包括第五引脚1315，第五引脚1315位于电子元件封装体10的中间区域，且第五引脚1315设有多个间隔设置的子引脚1320。
请继续参阅图7和图9，图9是图7所示引脚130沿B-B处在另一实现方式中的部分截面示意图。在此实现方式中，自沟槽1300的开口朝沟槽1300底面的方向上，沟槽1300的标准尺寸逐渐增大。可以理解的，沟槽1300的开口面积小于沟槽1300底面的面积。如图9所示，示例性的，沟槽1300的截面形状呈倒梯形。
在此实现方式中，自沟槽1300的开口朝沟槽1300底面的方向上，沟槽1300的标准尺寸逐渐增大，电子元件封装体10与电路板20焊接后，电子元件组装结构100中连接电子元件封装体10与电路板20的焊点与引脚130形成互锁结构，进一步地提高焊点在电子元件封装体10的厚度方向的强度，避免因电子元件11的长期振动而导致焊点失效，从而提高了电子元件组装结构100的可靠性。
请继续参阅图10，图10是本申请提供的电子元件组装结构100在实施例三中的部分截面示意图。具体地，本实施例所示电子元件组装结构100能够与图2至图9中任意一种电子元件封装体10的结构相结合。
以下主要描述本实施例与前述实施例的不同，本实施例与前述实施例相同的大部分内容不再赘述。电子元件封装体10包括基板110、封装于基板110内部的电子元件11和与电子元件11电性连接的引脚130。引脚130相对基板110的表面凸出。示例性的，引脚130凸出基板110的部分可以呈圆台或梯形状。示例性的，至少一个引脚130背离基板110的一侧设有沟槽1300。
在此实施例中，基板110中第二线路层14包括第一焊盘141和第二焊盘142。第一焊盘141与第二焊盘142间隔设置。电子元件封装体10还包括键合线16。键合线16电性连接在第一焊盘141与第二焊盘142之间，以使第一焊盘141与第二焊盘142电性连接。示例性的，键合线16电性连接第一元件111和第二元件112，且键合线16的至少部分结构位于封装层12的外侧。
其中，本申请并不限定，第一焊盘141和第二焊盘142的形状或数量等，本领域技术人员能够根据实际需求设计第一焊盘141与第二焊盘142。其中，键合线16可以是金属线，也可以是金属条。也即，第二线路层14通过金属线键合(wire bonding)和/或带状金属键合(clip bonding)。本申请并不限定，第二线路层14中焊盘140的数量、位置及形状等，本领域技术人员能够根据实际需求对此设计。
本实施例中，在封装层12的上表面形成第二线路层14，通过键合线16电性连接第二线路层14中的第一焊盘141和第二焊盘142，避免了第一焊盘141与第二焊盘142通过焊锡回流焊接时，在焊锡回流过程中重熔，从而提高了电子元件封装体10的可靠性。
请继续参阅图10，在一些实施例中，电子元件封装体10还包括封装体15。封装体15位于基板110远离电路板20的一侧。示例性的，封装体15位于基板110中第二线路层14远离封装层12的一侧，且键合线16封装于封装体15的内部。其中，封装体15采用磁性材料。示例性的，磁性材料为液态磁性材料，通过液态磁材料灌胶封装键合线16，以形成采用磁性材料的封装体15。本申请并不限定，磁性材料的种类，本领域技术人员能够根据实际需求对此进行设计。
在本实施例中，第二线路层14中的焊盘140通过键合线16连接，并且第二线路层14的表面为采用磁性材料的封装体15，封装体15与键合线16一起形成完整的磁元件(例如变压器、电感)的绕组，能够阻止电子元件封装体10内部的电流过大，有利于提高电子元件组装结构100的可靠性。与此同时，封装体15与第一线路层13无缝连接，有利于封装层12内各电子元件11的散热，从而提高了电子元件封装体10的散热性能。
其中，磁材料内部微观绝缘材料，外观不导电，采用磁材料的封装体15与键合线16不会电性连接。示例性的，键合线16的内部采用金属材料，外部通过绝缘材料包裹，以避免键合线16与封装体15相互干扰。
请继续参阅图11和图12，图11是本申请提供的电子元件封装体10在实施例四中的结 构示意图；图12是图11所示电子元件封装体10的部分截面示意图。
以下主要描述本实施例与前述实施例的不同，本实施例与前述实施例相同的大部分内容不再赘述。例如，电子元件封装体10包括基板110、封装于基板110内部的电子元件11和与电子元件11电性连接的引脚130。多个引脚130用于与电路板20焊接，以实现电子元件封装体10与电路板20的电性连接。
在此实施例中，引脚130未相对基板110凸出，且至少一个引脚130背离基板110的一侧设有沟槽1300。沟槽1300自引脚130的底面1321朝基板110一侧凹陷。示例性的，引脚130的底面与基板110的第二面1302齐平。在其他实施例中，引脚130的底面也能够位于第一线路层13的第一面1301与第二面1302之间。
其中，沟槽1300并未贯穿引脚130。可以理解的，引脚130相对第一线路层13露出的表面间隙设置，在靠近基板110的一侧相互连接为一整体。示例性的，被沟槽1300间隔的多个子引脚1320采用同一电性网络。
在本实施例中，单个引脚130背离基板110的一侧设有沟槽1300，焊点能够嵌设于沟槽1300，不仅增加了单个引脚130外露的表面积，也使得引脚能够在不同维度进行焊接，从而增加了单个引脚130的焊接强度，提高了电子元件封装体10与电路板20焊接的可靠性。其中，本申请并不限定任意沟槽1300的宽度、深度或数量等。本领域技术人员能够根据实际需求或机台要求设计沟槽1300的尺寸。示例性的，在制备电子元件封装体10的方法中，可以对单个引脚130的底部进行切分，以将单个引脚130的底部分割成多个间隔设置的子引脚1320。切分方法可以是但不仅限于刻蚀或激光。
在一些实施例中，多个引脚130中位于电子元件封装体10边缘的引脚130背离基板110的一侧设有沟槽1300。示例性的，电子元件封装体10大致呈矩形，多个引脚130位于电子元件封装体10四个对角的引脚130设有沟槽1300。也即，多个引脚130位于电子元件封装体10四个对角的引脚130包括多个间隙设置的子引脚1320。可以理解的，电子设备中与电路板焊接的电子元件封装体采用实施例四提供的电子元件封装体时，焊点不仅包围引脚的底面，也填充引脚底面的沟槽，增大了焊点与引脚的焊接面积。
在本实施例中，针对电子元件封装体10边缘的引脚130因电子元件组装结构100的振动而疲劳失效的可行性较大，因此针对电子元件封装体10边缘的引脚130进行切分形成多个间隔设置的子引脚1320，不仅增加了边缘引脚130焊接的可靠性，也避免了对全部的引脚130进行切分而增加成本。在其他实施例中，各引脚130远离基板110的一侧也可以均设有多个间隔设置的子引脚1320，本申请对此并不限定。
在一些实施例中，多个引脚130中表面积最大的引脚130包括多个间隙设置的子引脚1320。如图11所示，位于电子元件封装体10中间区域的引脚130的表面积最大，此引脚130包括多个间隙设置的子引脚1320，以进一步地提高电子元件封装体10与电路板20焊接的可靠性。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种电子元件组装结构，其特征在于，包括：
    电子元件封装体，所述电子元件封装体包括基板、电子元件和引脚，所述电子元件封装于所述基板的内部，所述引脚与所述电子元件电性连接，所述引脚包括第一部分和与所述第一部分连接的第二部分，所述第一部分嵌设于所述基板，所述第二部分相对所述基板凸出；所述第二部分包括底面和侧面，所述底面为所述引脚远离所述基板的外表面，所述侧面连接在所述底面和所述基板之间；
    电路板，所述电子元件封装体安装于所述电路板，且所述电路板与所述电子元件电性连接；
    焊点，所述焊点连接在所述引脚与所述电路板之间，并包围所述第二部分的底面和侧面。
  2. 根据权利要求1所述的电子元件组装结构，其特征在于，所述引脚的数量为多个，多个所述引脚间隔设置，至少一个所述引脚的侧面包括倾斜面、台阶面或曲面。
  3. 根据权利要求2所述的电子元件组装结构，其特征在于，所述底面的面积大于所述引脚沿所述基板表面的截面的面积。
  4. 根据权利要求1所述的电子元件组装结构，其特征在于，所述焊点包括第一段和与所述第一段连接的第二段，所述第一段连接在所述底面与所述电路板之间，所述第二段围设在所述侧面的周缘，且所述第二段在所述电路板的投影与所述底面在所述电路板的投影部分重叠。
  5. 根据权利要求1所述的电子元件组装结构，其特征在于，所述焊点采用的材料包括锡，且所述第一部分和所述第二部分采用的主体材料不同于所述焊点采用的材料。
  6. 根据权利要求1至5中任一项所述的电子元件组装结构，其特征在于，所述引脚朝所述电路板的一侧设有沟槽，所述沟槽自所述引脚的底面朝所述基板的一侧凹陷，且所述焊点的部分结构嵌设于所述沟槽。
  7. 根据权利要求1至6中任一项所述的电子元件组装结构，其特征在于，所述基板背离所述电路板的一侧包括第一焊盘和第二焊盘，所述第一焊盘与所述第二焊盘间隔设置；电子元件组装结构还包括键合线，所述键合线电性连接在所述第一焊盘与所述第二焊盘之间。
  8. 根据权利要求7所述的电子元件组装结构，其特征在于，所述电子元件封装体还包括封装体，所述封装体位于所述基板远离所述电路板的一侧，所述键合线封装于所述封装体的内部，且所述封装体采用磁性材料。
  9. 一种电子元件组装结构，其特征在于，包括：
    电子元件封装体，所述电子元件封装体包括基板、电子元件和引脚，所述电子元件封装于所述基板的内部，所述引脚与所述电子元件电性连接，所述引脚背离所述电子元件的一侧设有沟槽，所述沟槽自所述引脚的底面朝所述电子元件的一侧凹陷；
    电路板，所述电子元件封装体安装于所述电路板，且所述电路板与所述电子元件电性连接；
    焊点，所述焊点连接在所述引脚与所述电路板之间，且所述焊点嵌设于所述沟槽。
  10. 一种电子设备，其特征在于，包括壳体和如权利要求1至9中任一项所述的电子元件组装结构，所述电子元件组装结构安装于所述壳体。
  11. 一种电子元件封装体，其特征在于，包括基板、电子元件和引脚，所述电子元件封装于所述基板的内部，所述引脚与所述电子元件电性连接；所述引脚包括第一部分和与所述第一部分连接的第二部分，所述第一部分嵌设于所述基板，所述第二部分相对所述基板凸出； 所述第二部分包括底面和侧面，所述底面为所述引脚远离所述基板的外表面，所述侧面连接在所述底面和所述基板之间，所述底面和所述侧面均用于与焊料焊接。
  12. 根据权利要求11所述的电子元件封装体，其特征在于，所述引脚的数量为多个，多个所述引脚间隔设置，至少一个所述引脚的侧面包括倾斜面或台阶面；或者，至少一个所述引脚的第二部分呈圆台。
  13. 根据权利要求12所述的电子元件封装体，其特征在于，所述底面的面积大于所述引脚沿所述基板表面的截面的面积。
  14. 根据权利要求12所述的电子元件封装体，其特征在于，所述第二部分采用的材料包括铜或铝。
  15. 根据权利要求11至14中任一项所述的电子元件封装体，其特征在于，所述引脚背离所述基板的一侧设有沟槽，所述沟槽自所述引脚的底面朝所述基板的一侧凹陷。
  16. 根据权利要求11至15中任一项所述的电子元件封装体，其特征在于，所述基板背离所述引脚的一侧包括第一焊盘和第二焊盘，所述第一焊盘与所述第二焊盘间隔设置；电子元件组装结构还包括键合线和封装体，所述键合线电性连接在所述第一焊盘与所述第二焊盘之间，所述封装体位于所述基板远离所述引脚的一侧，所述键合线封装于所述封装体的内部，且所述封装体采用磁性材料。
  17. 一种电子元件封装体，其特征在于，包括基板、电子元件和引脚，所述电子元件封装于所述基板的内部，所述引脚与所述电子元件电性连接，所述引脚背离所述电子元件的一侧设有沟槽，所述沟槽自所述引脚的底面朝所述电子元件的一侧凹陷，所述沟槽用于填充焊料。
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