WO2022166216A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2022166216A1
WO2022166216A1 PCT/CN2021/120205 CN2021120205W WO2022166216A1 WO 2022166216 A1 WO2022166216 A1 WO 2022166216A1 CN 2021120205 W CN2021120205 W CN 2021120205W WO 2022166216 A1 WO2022166216 A1 WO 2022166216A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode layer
lower electrode
upper electrode
semiconductor structure
Prior art date
Application number
PCT/CN2021/120205
Other languages
English (en)
French (fr)
Inventor
平尔萱
周震
白卫平
郁梦康
苏星松
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/648,666 priority Critical patent/US20220254874A1/en
Publication of WO2022166216A1 publication Critical patent/WO2022166216A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the embodiments of the present application relate to, but are not limited to, a semiconductor structure and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell includes a capacitor and a transistor.
  • a sufficiently large capacitance is the basic requirement to ensure the normal operation of the DRAM and sufficient storage retention time.
  • the DRAM adopts a stacked capacitor structure.
  • the capacitor of the DRAM cell adopts The first is a hexagonal honeycomb layout, and the capacitors are cylindrical or columnar structures with extremely large aspect ratios.
  • the current capacitor layout structure results in that the pitch ratio of word lines and bit lines is fixed at the left and right.
  • the fixed pitch ratio of word and bit lines limits the diversity of DRAM processes.
  • Increasing the area of the capacitor electrode plate as much as possible is a technical problem that those skilled in the art need to solve urgently.
  • An embodiment of the present application provides a method for forming a semiconductor structure, including: providing a stacked substrate and an insulating layer, wherein the substrate has a plurality of storage node contact structures spaced apart from each other; forming a grid-like structure on the surface of the insulating layer an upper electrode layer, the upper electrode layer has a plurality of mesh holes penetrating the upper electrode layer, and the orthographic projection of each mesh hole on the insulating layer is connected to a storage node contact structure in the insulating layer
  • the orthographic projection on the layer has an overlapping area; a dielectric layer is formed on the sidewall of the mesh hole; the insulating layer exposed by the mesh hole is removed to expose the storage node contact structure; and a dielectric layer is formed in the mesh hole a lower electrode layer, the lower electrode layer is located on the side of the dielectric layer away from the upper electrode layer, and is also in contact with the exposed storage node contact structure, different from the lower electrode layer in the mesh hole electrically isolated from each other.
  • Embodiments of the present application further provide a semiconductor structure, comprising: a stacked substrate and an insulating layer, the substrate has a plurality of storage node contact structures spaced apart from each other, and the insulating layer exposes the storage node contact structure; a grid-shaped upper electrode layer, the upper electrode layer is located on the surface of the insulating layer, the upper electrode layer has a plurality of mesh holes penetrating the upper electrode layer, and each of the mesh holes exposes the storage node Contact structure; dielectric layer, the dielectric layer is located on the sidewall of the mesh; lower electrode layer, the lower electrode layer is located in the mesh, the lower electrode layer is located in the dielectric layer away from the upper electrode The layer side is also in contact with the exposed storage node contact structure, and the lower electrode layers in different mesh holes are electrically insulated from each other.
  • 1 to 20 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure provided in the first embodiment of the present application;
  • 21 to 30 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to the second embodiment of the present application.
  • FIG. 31 is a schematic structural diagram of a semiconductor structure provided by the third embodiment of the application.
  • 33 is a schematic structural diagram of yet another semiconductor structure provided by the third embodiment of the present application.
  • FIG. 34 is a schematic structural diagram of still another semiconductor structure provided by the third embodiment of the present application.
  • the capacitor of the semiconductor structure adopts a hexagonal honeycomb layout, and the capacitor is a cylindrical or columnar structure with a very large aspect ratio.
  • the hexagonal honeycomb layout results in that the pitch ratio of the word line and the bit line of the semiconductor structure is fixed on the left and right, and the fixed word bit line pitch ratio limits the diversity of the semiconductor structure process; or cylindrical capacitors, in order to prevent the capacitor from collapsing due to an excessive aspect ratio, a support layer needs to be formed first. After the capacitor is formed, the support layer needs to be removed later. Such a formation method is cumbersome and wastes materials and process costs. Higher; because the hexagonal honeycomb layout of the capacitor cannot completely cover the rectangular word bit line structure, the electrode plate area of the capacitor does not maximize under the given word bit line pitch ratio.
  • an embodiment of the present application provides a method for forming a semiconductor structure.
  • the formed upper electrode layer is an interconnected grid-like structure, and the structure is stable, which can effectively avoid the problem of collapse of the capacitor structure;
  • the grid-shaped upper electrode layer completely covers the rectangular word bit line structure, so under a given word bit line pitch ratio, the area of the formed capacitor electrode plate is maximized, and the performance of the semiconductor structure is improved.
  • 1 to 20 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to the first embodiment of the present application.
  • the semiconductor structure includes a capacitor region A and a peripheral region B around the capacitor region A; a stacked substrate 100 and an insulating layer 102 are provided, and the substrate 100 and the insulating layer 102 are located in the capacitor region A and the peripheral region B.
  • the material of the substrate 100 is a semiconductor material.
  • the material of the substrate 100 is silicon.
  • the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
  • the substrate 100 has a plurality of storage node contact structures 101 spaced apart from each other.
  • the storage node contact structures 101 are located in the capacitor region A.
  • the storage node contact structures 101 are used in the semiconductor structure to connect transistors and capacitors.
  • the material of the storage node contact structure 101 is metal.
  • the material of the storage node contact structure 101 may be tungsten metal.
  • the material of the storage node contact structure may also be copper metal, aluminum metal, gold metal, silver metal, or the like.
  • the insulating layer 102 plays the role of insulating protection.
  • the material of the insulating layer 102 is silicon oxide.
  • the material of the insulating layer may also be a high-K material.
  • a grid-shaped upper electrode layer needs to be formed on the surface of the insulating layer 102 , and the steps of forming the grid-shaped upper electrode layer will be described in detail below with reference to the accompanying drawings.
  • a chemical vapor deposition process is used to form a model layer 110 on the surface of the insulating layer 102 , and the model layer 110 completely covers the insulating layer 102 .
  • a mask layer 111 is formed on the surface of the model layer 110 by a chemical vapor deposition process.
  • the mask layer 111 has a plurality of openings passing through the mask layer 111 by a double-layer patterning process, and the orthographic projection of the openings on the insulating layer 102 is different from the orthographic projection of the storage node contact structure 101 on the insulating layer 102 .
  • the openings may also be formed by a four-pass patterning process or an EUV lithography process.
  • a double-layer patterning process is used to make the shape of the model layer 110 exactly the same as that of the patterned mask layer 111 (refer to FIG. 3 ).
  • the orthographic projection on the insulating layer 102 does not overlap with the orthographic projection of the storage node contact structure 101 on the insulating layer 102, and the mask layer 111 is removed.
  • the initial upper electrode layer a103 filling the opening is formed by an atomic layer deposition process, and the top surface of the initial upper electrode layer a103 is higher than the top surface of the model layer 110 .
  • a chemical mechanical polishing process is used to remove part of the initial upper electrode layer a103 (refer to FIG. 5 ), so that the top surface of the remaining initial upper electrode layer a103 is flush with the top surface of the model layer 110 (refer to FIG. 5 ), and the remaining The initial upper electrode layer a103 is used as the upper electrode layer 103; the model layer 110 is removed by a wet etching process.
  • a grid-shaped upper electrode layer 103 is formed on the surface of the insulating layer 102, and the upper electrode layer 103 has a plurality of mesh holes penetrating the upper electrode layer 103.
  • the orthographic projection of each mesh hole on the insulating layer 102 corresponds to a memory
  • the orthographic projection of the node contact structure 101 on the insulating layer 102 has an overlapping area, the mesh is located in the capacitor area A, and the upper electrode layer 103 is located not only in the capacitor area A, but also in the peripheral area B.
  • the grid-shaped upper electrode layer 103 facing the storage node contact structures 101 is Rectangular grid.
  • the upper electrode layer 103 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc. In this embodiment, the upper electrode layer 103 is made of tungsten material. .
  • a grid-shaped upper electrode layer 103 is formed, and a plurality of mesh holes penetrating the upper electrode layer 103 in the upper electrode layer 103 are directly opposite to each storage node contact structure 101 , because the grid-shaped grid directly opposite to the storage node contact structure 101 is formed.
  • the upper electrode layer 103 is naturally densely packed, so the pitch ratio of word lines and bit lines does not need to be fixed, which is beneficial to reduce the limitations and difficulties of the semiconductor structure in terms of structural design and material requirements; at the same time, the natural dense packing of the upper electrode layer 103 makes the Under the given word bit line pitch ratio, the electrode plate area of the capacitor is maximized; since the upper electrode layer 103 is grid-like, it indicates that the upper electrode layers 103 are connected and are a stable whole, so it is effectively avoided. The problem of the collapse of the capacitor structure.
  • a dielectric film a104 is formed on the sidewalls of the mesh, the top surface of the upper electrode layer 103, and the surface of the insulating layer 102 exposed by the mesh.
  • the material of the dielectric film a104 is a high dielectric constant material, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used. Subsequently, a dielectric layer is formed on the basis of the dielectric film a104.
  • the dielectric film a104 is formed by the atomic layer deposition process, and the dielectric film a104 formed by the atomic layer deposition process has good coverage; in other embodiments, the chemical vapor deposition process can also be used to form the dielectric film.
  • a dry etching process is used to remove the dielectric film a104 (refer to FIG. 7 ) on the top surface of the upper electrode layer 103 and the surface of the insulating layer 102 exposed by the mesh, so that the remaining dielectric film a104 is only located on both sides of the mesh , the remaining dielectric film a104 is used as the dielectric layer 104 .
  • a dry etching process is used to remove the insulating layer 102 exposed by the mesh to expose the storage node contact structure 101 . Subsequently, a lower electrode layer needs to be formed on the surface of the exposed storage node contact structure 101 .
  • a lower electrode film a105 is formed, the lower electrode film a105 is located in the mesh, the side of the dielectric layer 104 away from the upper electrode layer 103 and the exposed surface of the storage node contact structure 101 is also located in The upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103 .
  • the chemical vapor deposition process is used to form the lower electrode film a105, and the chemical vapor deposition process is used to form the lower electrode film a105, which speeds up the formation rate and is beneficial to improve the formation efficiency of the semiconductor structure.
  • the atomic layer deposition process can also be used to form the lower electrode film.
  • the lower electrode film a105 can be made of a conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the lower electrode film a105 is made of nitrided Titanium material. Subsequently, the lower electrode layer 105 is formed on the basis of the lower electrode film a105.
  • a planarization process is used to remove the lower electrode film a105 (refer to FIG. 9) located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103, and the remaining lower electrode film a105 is the lower electrode layer 105, and the lower electrode layer 105 is filled with mesh holes, the formed lower electrode layer 105 is located on the side of the dielectric layer 104 away from the upper electrode layer 103, and is also in contact with the exposed storage node contact structure 101, and the lower electrode layers 105 in different mesh holes are electrically insulated from each other .
  • the used planarization process is a chemical mechanical polishing process.
  • the chemical mechanical polishing process not only removes the lower electrode film a105 located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103, but also electrically isolates the lower electrode layers 105 in different meshes from each other. , and make the upper surface of the lower electrode layer 105 flatter.
  • a lower electrode film a105 is formed, the lower electrode film a105 is located in the mesh, the side of the dielectric layer 104 away from the upper electrode layer 103 and the exposed surface of the storage node contact structure 101 , and also The lower electrode film a105 located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103, and at the same time located in each mesh hole, forms a through hole.
  • a dry etching process is used to etch and remove the lower electrode film a105 (refer to FIG. 11 ) located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103 , and also etch and remove the part under the bottom of the through hole.
  • the electrode film a105, and the remaining lower electrode film a105 serves as the lower electrode layer.
  • a conductive filling layer 106 is formed in each grid, and the conductive filling layer 106 fills the via holes, and the conductive filling layer 106 contacts the storage node contact structure 101 exposed by the via holes .
  • the chemical vapor deposition process is used to form the conductive filling layer 106
  • the chemical vapor deposition process is used to form the conductive filling layer 106 , which speeds up the formation rate and helps to improve the formation efficiency of the semiconductor structure.
  • an atomic layer deposition process can also be used to form the conductive filling layer.
  • the material of the conductive filling layer 106 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the conductive filling layer 106 is doped polysilicon.
  • the lower electrode film a105 located in each mesh hole forms a through hole; a chemical vapor deposition process is used to form a sacrificial layer 107 filling the through hole.
  • the sacrificial layer 107 is used to prevent the removal process from affecting the rest of the lower electrode film a105 when the lower electrode film a105 located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103 is subsequently removed; the material of the sacrificial layer 107 is doped boron and phosphorous silica (BPSG) or oxygen-containing materials.
  • BPSG boron and phosphorous silica
  • a planarization process is used to remove the lower electrode film a105 (refer to FIG. 14 ) located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103 , and the remaining lower electrode film a105 is the lower electrode Layer 105.
  • the formed lower electrode layer 105 is located on the side of the dielectric layer 104 away from the upper electrode layer 103, and is also located on the surface of the exposed storage node contact structure 101, and the lower electrode layers 105 in different meshes are electrically insulated from each other.
  • the used planarization process is a chemical mechanical polishing process.
  • the chemical mechanical polishing process not only removes the lower electrode film a105 located on the upper surface of the dielectric layer 104 and the upper surface of the upper electrode layer 103, but also electrically isolates the lower electrode layers 105 in different meshes from each other. , and make the upper surface of the lower electrode layer 105 flatter.
  • the sacrificial layer 107 (refer to FIG. 15 ) is removed by means of targeted etching using a wet etching process. Due to the specificity of the wet etching process, the lower electrode layer 105 will not be affected during the process of removing the sacrificial layer 107 .
  • a conductive filling layer 106 is formed in each grid, and the conductive filling layer 106 fills the via holes, and the conductive filling layer 106 is located on the surface of the lower electrode layer 105 .
  • the chemical vapor deposition process is used to form the conductive filling layer 106
  • the chemical vapor deposition process is used to form the conductive filling layer 106 , which speeds up the formation rate and helps to improve the formation efficiency of the semiconductor structure.
  • an atomic layer deposition process can also be used to form the conductive filling layer.
  • the material of the conductive filling layer 106 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the conductive filling layer 106 is doped polysilicon.
  • an initial second insulating layer a108 is formed, and the initial second insulating layer a108 is located on the upper surface of the upper electrode layer 103 , the upper surface of the dielectric layer 104 and the lower electrode layer 105 surface.
  • the atomic layer deposition process is used to form the initial second insulating layer a108.
  • the material of the initial second insulating layer a108 is silicon oxide. In other embodiments, the material of the initial second insulating layer may also be For high K material.
  • the initial second insulating layer a108 serves as a basis for the subsequent formation of the second insulating layer 108 .
  • a dry etching process is used to remove part of the initial second insulating layer a108 located in the peripheral region B (refer to FIG. 18 ), and the remaining initial second insulating layer a108 is used as the second insulating layer 108 , and the second insulating layer 108 is exposed At least part of the surface of the upper electrode layer 103 in the peripheral region B is used to facilitate the electrical connection between the upper electrode layer 103 and the subsequently formed upper electrode layer filling layer.
  • an atomic layer deposition process is used to form an upper electrode layer filling layer 109 , which covers at least part of the surface of the upper electrode layer 103 in the exposed peripheral region B, and is also located on the surface of the second insulating layer 108 .
  • the material of the upper electrode layer filling layer 109 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the upper electrode layer filling layer 109 is doped polysilicon.
  • the semiconductor structure formed by the method of this embodiment has a bit line pitch of 20 nanometers to 40 nanometers, a word bit line pitch ratio of 20 nanometers to 40 nanometers, and the formed dielectric layer 104
  • the thickness of the semiconductor structure is 5.5 nanometers
  • the thickness of the upper electrode layer 103 in this embodiment is 4 nanometers
  • the thickness of the upper electrode layer of the semiconductor structure in the hexagonal honeycomb layout is 2.5 nanometers
  • the capacitance ratio of the semiconductor structure in the honeycomb-shaped layout is 1.2:1, and the cell capacitance value of the semiconductor structure formed in this embodiment is increased by 20%.
  • a grid-shaped upper electrode layer 103 is firstly formed, and a plurality of mesh holes penetrating the upper electrode layer 103 in the upper electrode layer 103 are directly opposite to each storage node contact structure 101; because The grid-shaped upper electrode layer 103 facing the storage node contact structure 101 is naturally densely packed, so the pitch ratio of the word line and the bit line does not need to be fixed, which is beneficial to reduce the limitations of the semiconductor structure in terms of structural design and material requirements.
  • the upper electrode layer 103 is naturally densely packed, so that the electrode plate area of the capacitor can be maximized under a given word bit line pitch ratio; since the upper electrode layer 103 is grid-shaped, it shows that the upper electrode layer 103 It is connected and stable as a whole, so it can effectively avoid the problem of the collapse of the capacitor structure and improve the performance of the semiconductor structure.
  • the second embodiment of the present application provides a method for forming a semiconductor structure, which is substantially the same as that of the first embodiment of the present application, except that in this embodiment, a protective layer is formed in the mesh before removing the insulating layer exposed by the mesh.
  • a protective layer is formed in the mesh before removing the insulating layer exposed by the mesh.
  • 21 to 30 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to the second embodiment of the present application.
  • the formed semiconductor structure includes: a capacitor region A and a peripheral region B located around the capacitor region A; a stacked substrate 200 and an insulating layer 202 are provided, and the substrate 200 and the insulating layer 202 are located in the capacitor region A and the peripheral region B; the substrate 200 has a plurality of mutually spaced storage node contact structures 201, and the storage node contact structures 201 are located in the capacitor region A; a grid-shaped upper electrode layer 203 is formed on the surface of the insulating layer 202, and the upper electrode layer 203 There are a plurality of mesh holes penetrating the upper electrode layer 203 ; a dielectric layer 204 is formed on the sidewall of the upper electrode layer 203 .
  • a protective film a220 is formed in the mesh by an atomic layer deposition process, and the protective film a220 is located on the sidewall of the dielectric layer 204, the surface of the insulating layer 202 exposed by the mesh, the top surface of the upper electrode layer 203 and the dielectric layer 204. top.
  • the material of the protective film a220 is a conductive material.
  • the material of the protective film a220 is the same as the material of the lower electrode layer to be formed subsequently, and may specifically be a titanium nitride material; in other embodiments, the material of the protective film may be doped polysilicon, titanium, titanium nitride, Tungsten and tungsten complexes, etc.
  • a protective layer is formed on the basis of the protective film a220.
  • a dry etching process is used to remove the protective film a220 (refer to FIG. 22 ) on the surface of the insulating layer 202 exposed by the mesh, the top surface of the upper electrode layer 203 and the top surface of the dielectric layer 204 (refer to FIG. 22 ), and the remaining protective film a220 As the protective layer 220 , the protective layer 220 covers the sidewalls of the dielectric layer 204 .
  • the protective layer 220 can protect the dielectric layer 204 from being affected by the removal process; even when the insulating layer 202 is removed, part of the protective layer 220 is removed, since it needs to be formed on the protective layer 220 later.
  • a lower electrode layer is formed in the through hole of 1, and the material of the lower electrode layer is the same as that of the protective layer 220, which can also compensate for the damage to the protective layer 220 when the insulating layer 202 is removed.
  • the insulating layer 202 exposed by the via is removed.
  • a lower electrode layer 205 is formed that fills up the through holes formed by the protective layer 220 , and the formed lower electrode layer 205 is located on the sidewall of the protective layer 220 .
  • a conformal covering dielectric film a204 is formed, and the dielectric film a204 is located on the bottom and sidewalls of the mesh holes, and is also located on the upper surface of the upper electrode layer 203 .
  • a conformal covering protective film a220 is formed, and the protective film a220 is located on the surface of the dielectric film a204.
  • the protective film a220 (refer to FIG. 27 ) and the dielectric film a204 (refer to FIG. 27 ) are etched until the upper surface of the upper electrode layer 203 and the insulating layer 202 at the bottom of the mesh are exposed, and then the bottom of the mesh is removed by etching.
  • the insulating layer 202; the remaining protective film a220 is used as the protective layer 220, and the remaining dielectric film a204 is used as the dielectric layer 204; wherein, the sidewall surface of the dielectric layer 204 between the insulating layer 202 and the protective layer 220 is exposed.
  • a lower electrode layer 205 is formed in the mesh, and the formed lower electrode layer 205 is also located on the sidewall surface of the exposed dielectric layer 204 .
  • the second insulating layer 208 and the upper electrode layer filling layer 209 are formed.
  • the specific conditions of the second insulating layer 208 and the upper electrode layer filling layer 209 are the same as those in the first embodiment. No longer.
  • a protective layer 220 covering the sidewall of the dielectric layer 204 is formed in the mesh, so that when the insulating layer 202 exposed by the mesh is removed, the protective layer 220 can protect the dielectric layer 204 It is not affected by the removal process; at the same time, since the lower electrode layer 205 needs to be formed in the through hole formed by the protective layer 220, and the material of the lower electrode layer 205 is the same as that of the protective layer 220, it is removed even when the insulating layer 202 is removed. Part of the protective layer 220 is removed, and the lower electrode layer 205 of the same material can also compensate for the damage to the protective layer 220 when the insulating layer 202 is removed.
  • the third embodiment of the present application provides a semiconductor structure, and the semiconductor structure can be formed by using the formation method provided in the first embodiment or the second embodiment.
  • the semiconductor structure provided by the third embodiment of the present application will be described in detail below with reference to the accompanying drawings.
  • FIG. 31 is a schematic structural diagram of a semiconductor structure provided by the third embodiment of the present application.
  • the semiconductor structure includes: a substrate 300 and an insulating layer 302 arranged in layers, the substrate 300 has a plurality of storage node contact structures 301 spaced apart from each other, and the insulating layer 302 exposes the storage node contact structure 301;
  • the dielectric layer 304 , the dielectric layer 304 is located on the sidewall of the mesh;
  • the lower electrode layer 305, the lower electrode layer 305 is located in the mesh, the lower electrode layer 305 is located on the side of the dielectric layer 304 away from the upper electrode layer 303, and is also in contact with the exposed storage node
  • the structures 301 are in contact, and the lower electrode layers 305 in different meshes are electrically insulated from each other.
  • the semiconductor structure includes a capacitor region A and a peripheral region B around the capacitor region A, the substrate 300 and the insulating layer 302 are located in the capacitor region A and the peripheral region B; the substrate 300 is made of semiconductor material.
  • the material of the substrate 300 is silicon.
  • the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
  • the storage node contact structure 301 is located in the capacitor region A, and the storage node contact structure 301 is used to connect the transistor and the capacitor in the semiconductor structure.
  • the material of the storage node contact structure 301 is metal.
  • the material of the storage node contact structure 301 may be tungsten metal.
  • the material of the storage node contact structure may also be copper metal, aluminum metal, gold metal, silver metal, or the like.
  • the insulating layer 302 plays the role of insulating protection.
  • the material of the insulating layer 302 is silicon oxide.
  • the material of the insulating layer can also be a high-K material.
  • the upper electrode layer 303 has a plurality of mesh holes penetrating the upper electrode layer 303, each mesh hole exposes a storage node contact structure 301, the mesh hole is located in the capacitor region A, and the upper electrode layer 303 is not only located in the capacitor region A, but also in the periphery. District B.
  • the grid-shaped upper electrode layer 303 facing the storage node contact structure 301 is Rectangular grid.
  • the upper electrode layer 303 can be made of a conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten and a compound of tungsten, etc. In this embodiment, the upper electrode layer 303 is made of tungsten material .
  • the pitch ratio of the word line and the bit line does not need to be fixed, which is beneficial to reduce the structural design and material requirements of the semiconductor structure. limitations and difficulties; at the same time, the upper electrode layer 303 is naturally densely packed, so that under a given word bit line pitch ratio, the electrode plate area of the capacitor can be maximized; since the upper electrode layer 303 is grid-like, it shows that the upper electrode layer 303 It is connected and is a solid whole, so it can effectively avoid the problem of the collapse of the capacitor structure.
  • the material of the dielectric layer 304 is a high dielectric constant material, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used.
  • the lower electrode layer 305 in each mesh hole is filled with the mesh.
  • the lower electrode layer 305 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the lower electrode layer 305 is made of nitride. Titanium material.
  • the semiconductor structure further includes a second insulating layer 308.
  • the second insulating layer 308 is located on the upper surface of the upper electrode layer 303, the upper surface of the dielectric layer 304 and the upper surface of the lower electrode layer 305, and at least part of the peripheral region B is exposed.
  • the surface of the electrode layer 303 is used to facilitate the electrical connection between the upper electrode layer 303 and the subsequently formed upper electrode layer filling layer.
  • the material of the second insulating layer 308 is silicon oxide. In other embodiments, the material of the second insulating layer can also be a high-K material.
  • This embodiment further includes: an upper electrode layer filling layer 309 , which covers at least part of the surface of the upper electrode layer 303 in the exposed peripheral region B, and is also located on the surface of the second insulating layer 308 .
  • the material of the upper electrode layer filling layer 309 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the upper electrode layer filling layer 309 is doped polysilicon.
  • FIG. 32 is a schematic structural diagram of another semiconductor structure provided by the third embodiment of the present application.
  • the lower electrode layer 305 in each mesh is surrounded by a through hole, and the through hole exposes a part of the surface of the storage node contact structure 301; the semiconductor structure further includes a conductive filling layer 306, a conductive filling layer 306 fills the via.
  • the material of the conductive filling layer 306 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the conductive filling layer 306 is doped polysilicon.
  • FIG. 33 is a schematic structural diagram of still another semiconductor structure provided by the third embodiment of the present application.
  • the lower electrode layer 305 in each mesh is surrounded by through holes, and the lower electrode layer 305 is located on the side of the dielectric layer 304 away from the upper electrode layer 303 and is also located on the surface of the storage node contact structure 301 ;
  • the semiconductor structure further includes a conductive filling layer 306, and the conductive filling layer 306 fills the through hole.
  • the material of the conductive filling layer 306 includes semiconductor conductive materials such as doped polysilicon and polysilicon. In this embodiment, the material of the conductive filling layer 306 is doped polysilicon.
  • FIG. 34 is a schematic structural diagram of still another semiconductor structure provided by the third embodiment of the present application.
  • the semiconductor structure further includes: a protective layer 320 , and the protective layer 320 covers the sidewalls of the dielectric layer 304 .
  • the material of the protective layer 320 is a conductive material.
  • the material of the protective layer 320 is the same as the material of the lower electrode layer 305, and specifically can be a titanium nitride material, doped polysilicon, titanium, titanium nitride, tungsten, a compound of tungsten, and the like.
  • the protective layer 320 can protect the dielectric layer 304 from being affected by the removal process; at the same time, the lower electrode layer 305 needs to be formed in the through holes formed by the protective layer 320 later, and the lower electrode layer 305
  • the material is the same as that of the protective layer 320 , even when the insulating layer 302 is removed, part of the protective layer 320 is removed, and the lower electrode layer 305 of the same material can also compensate for the damage to the protective layer 320 when the insulating layer 302 is removed.
  • the semiconductor structure provided in this embodiment has a grid-shaped upper electrode layer 303, and a plurality of mesh holes in the upper electrode layer 303 penetrating the upper electrode layer 303 are directly opposite to each storage node contact structure 301, because they are in contact with the storage nodes.
  • the grid-shaped upper electrode layer 303 facing the structure 301 is naturally densely packed, so the pitch ratio of the word line and the bit line does not need to be fixed, which is beneficial to reduce the limitations and difficulties of the semiconductor structure in terms of structural design and material requirements;
  • the upper electrode layer 303 is naturally densely packed, so that the electrode plate area of the capacitor can be maximized under the given word bit line pitch ratio; It is a stable whole, so it can effectively avoid the problem of the collapse of the capacitor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请实施例提供一种半导体结构及其形成方法，半导体结构的形成方法，包括：提供层叠设置的基底以及绝缘层，基底内具有多个相互间隔的存储节点接触结构；在绝缘层表面形成网格状的上电极层，上电极层内具有多个贯穿上电极层的网孔，每一网孔在绝缘层上的正投影与一存储节点接触结构在绝缘层上的正投影具有重叠区域；在网孔的侧壁形成介质层；去除网孔露出的绝缘层，以暴露出存储节点接触结构；在网孔内形成下电极层，下电极层位于介质层远离上电极层一侧，且还与暴露出的存储节点接触结构相接触，不同网孔内的下电极层相互电绝缘。

Description

半导体结构及其形成方法
相关申请的交叉引用
本申请基于申请号为202110163948.9、申请日为2021年02月05日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元包括一个电容器和一个晶体管，足够大的电容是保证DRAM正常工作和足够的存储保持时间的基本要求，在DRAM制程中，DRAM均采用堆栈式的电容构造，目前DRAM单元的电容器采用的是六边形蜂巢布局，电容为具有极大深宽比的筒状或柱状结构。
目前的电容器布局结构导致字线和位线的节距比被固定在左右，固定的字位线节距比限制了DRAM制程的多样性，如何在不限制DRAM中字位线节距比的同时，尽可能地增大电容电极板的面积，是本领域技术人员亟须解决的技术问题。
发明内容
本申请实施例提供一种半导体结构的形成方法，包括：提供层叠设置的基底以及绝缘层，所述基底内具有多个相互间隔的存储节点接触结构； 在所述绝缘层表面形成网格状的上电极层，所述上电极层内具有多个贯穿所述上电极层的网孔，每一所述网孔在所述绝缘层上的正投影与一所述存储节点接触结构在所述绝缘层上的正投影具有重叠区域；在所述网孔的侧壁形成介质层；去除所述网孔露出的所述绝缘层，以暴露出所述存储节点接触结构；在所述网孔内形成下电极层，所述下电极层位于所述介质层远离所述上电极层一侧，且还与暴露出的所述存储节点接触结构相接触，不同所述网孔内的所述下电极层相互电绝缘。
本申请实施例还提供一种半导体结构，包括：层叠设置的基底以及绝缘层，所述基底内具有多个相互间隔的存储节点接触结构，所述绝缘层暴露出所述存储节点接触结构；网格状的上电极层，所述上电极层位于所述绝缘层表面，所述上电极层内具有多个贯穿所述上电极层的网孔，每一所述网孔暴露出所述存储节点接触结构；介质层，所述介质层位于所述网孔的侧壁；下电极层，所述下电极层位于所述网孔内，所述下电极层位于所述介质层远离所述上电极层一侧，且还与暴露出的所述存储节点接触结构相接触，不同所述网孔内的所述下电极层相互电绝缘。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1～图20为本申请第一实施例提供的一种半导体结构的形成方法的各步骤对应的结构示意图；
图21～图30为本申请第二实施例提供的一种半导体结构的形成方法的各步骤对应的结构示意图；
图31为本申请第三实施例提供的一种半导体结构的结构示意图；
图32为本申请第三实施例提供的另一种半导体结构的结构示意图；
图33为本申请第三实施例提供的又一种半导体结构的结构示意图；
图34为本申请第三实施例提供的再一种半导体结构的结构示意图。
具体实施方式
由背景技术可知，现有技术的半导体结构电容的电极板的面积较小。
半导体结构的电容采用六边形蜂巢布局，电容为具有极大深宽比的筒状或柱状结构。六边形蜂巢布局导致半导体结构的字线和位线的节距比被固定在左右，固定的字位线节距比限制了半导体结构制程的多样性；在形成具有极大深宽比的柱状或筒状的电容时，为防止电容由于深宽比过大造成坍塌，需要先形成支撑层，在形成电容后，后续需要再去除支撑层，这样的形成方法工艺繁琐，同时浪费材料，工艺成本较高；由于电容的六边形蜂巢布局不能完全覆盖矩形的字位线结构，所以在既定的字位线节距比下，电容的电极板面积没有达到最大化。
为解决上述问题，本申请实施例提供一种半导体结构的形成方法，形成的上电极层为互连的网格状结构，结构稳固，可以有效避免电容结构坍塌的问题；由于天然密排的网格状的上电极层完全覆盖矩形的字位线结构，所以在既定的字位线节距比下，形成的电容电极板面积达到最大化，提高半导体结构的性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1～图20为本申请第一实施例提供的一种半导体结构的形成方法的各步骤对应的结构示意图。
参考图1，半导体结构包括电容区A和位于电容区A周边的周边区B； 提供层叠设置的基底100以及绝缘层102，基底100和绝缘层102位于电容区A和周边区B。
其中，基底100的材料为半导体材料。本实施例中，基底100的材料为硅。在其他实施例中，基底也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。
基底100内具有多个相互间隔的存储节点接触结构101，存储节点接触结构101位于电容区A，存储节点接触结构101在半导体结构中用于连接晶体管和电容器。
存储节点接触结构101的材料为金属。本实施例中，存储节点接触结构101的材料可以为钨金属。在其他实施例中，存储节点接触结构的材料也可以为铜金属、铝金属、金金属或者银金属等。
绝缘层102起到绝缘保护的作用，本实施例中，绝缘层102的材料为氧化硅，在其他实施例中，绝缘层的材料也可以为高K材料。
后续需要在绝缘层102表面形成网格状的上电极层，以下将结合附图对形成网格状的上电极层的步骤进行详细说明。
参考图1，采用化学气相沉积工艺在绝缘层102表面形成模型层110，模型层110完全覆盖绝缘层102。
参考图2，采用化学气相沉积工艺在模型层110表面形成掩膜层111。
参考图3，采用双层图形化工艺使得掩膜层111具有多个贯穿掩膜层111的开口，开口在绝缘层102上的正投影与存储节点接触结构101在绝缘层102上的正投影不重叠，在其他实施例中，也可以采用四次图形化工艺或极紫外线光刻工艺形成开口。
参考图4，采用双层图形化工艺使得模型层110的形状与图形化的掩膜层111(参考图3)的形状完全相同，模型层110内具有多个贯穿模型层110的开口，开口在绝缘层102上的正投影与存储节点接触结构101在绝缘层 102上的正投影不重叠，并去除掩膜层111。
参考图5，采用原子层沉积工艺形成填充满开口的初始上电极层a103，且初始上电极层a103的顶面高于模型层110的顶面。
参考图6，采用化学机械研磨工艺去除部分初始上电极层a103(参考图5)，使得剩余的初始上电极层a103的顶面与模型层110(参考图5)的顶面齐平，剩余的初始上电极层a103作为上电极层103；采用湿法刻蚀工艺去除模型层110。
这样，在绝缘层102表面形成了网格状的上电极层103，上电极层103内具有多个贯穿上电极层103的网孔，每一网孔在绝缘层102上的正投影与一存储节点接触结构101在绝缘层102上的正投影具有重叠区域，网孔位于电容区A，上电极层103不仅位于电容区A，而且位于周边区B。
由于半导体结构的字线和位线呈有规律的纵横排布，多个存储节点接触结构101呈规则的四方排布，所以与存储节点接触结构101正对的网格状的上电极层103为矩形网格。
上电极层103可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，上电极层103采用钨材料。
形成网格状的上电极层103，上电极层103内的多个贯穿上电极层103的网孔与每一存储节点接触结构101正对，因为与存储节点接触结构101正对的网格状的上电极层103实现天然密排，所以字线和位线的节距比无须固定，有利于减少半导体结构在结构设计和材料需求等方面的局限和困难；同时上电极层103天然密排使得在既定的字位线节距比下，电容的电极板面积达到最大化；由于上电极层103是网格状的，表明上电极层103之间是相连的，是稳固的整体，所以有效避免电容结构坍塌的问题。
参考图7，形成介质膜a104，介质膜a104位于网孔的侧壁、上电极层 103的顶面和网孔暴露出的绝缘层102的表面。
介质膜a104的材料为为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。后续在介质膜a104的基础上形成介质层。
本实施例中，采用原子层沉积工艺形成介质膜a104，采用原子层沉积工艺形成的介质膜a104具有良好的覆盖性；在其他实施例中，还可以采用化学气相沉积工艺形成介质膜。
参考图8，采用干法刻蚀工艺去除位于上电极层103顶面和网孔暴露出的绝缘层102表面的介质膜a104(参考图7)，使得剩余的介质膜a104只位于网孔两侧，剩余的介质膜a104作为介质层104。
采用干法刻蚀工艺去除网孔露出的绝缘层102，以暴露出存储节点接触结构101。后续需要在暴露出的存储节点接触结构101表面形成下电极层。
参考图9，本实施例中，形成下电极膜a105，下电极膜a105位于网孔内、介质层104远离上电极层103的一侧以及暴露出的存储节点接触结构101的表面，且还位于介质层104上表面和上电极层103上表面。
本实施例中，采用化学气相沉积工艺形成下电极膜a105，形成下电极膜a105采用化学气相沉积工艺，加快形成速率，有利于提高半导体结构的形成效率。在其他实施例中，也可以采用原子层沉积工艺形成下电极膜。
下电极膜a105可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极膜a105采用氮化钛材料。后续在下电极膜a105的基础上形成下电极层105。
参考图10，采用平坦化工艺，去除位于介质层104上表面和上电极层103上表面的下电极膜a105(参考图9)，剩余的下电极膜a105为下电极层105，且下电极层105填充满网孔，形成的下电极层105位于介质层104远离上电极层103一侧，且还与暴露出的存储节点接触结构101相接触，不 同网孔内的下电极层105相互电绝缘。
采用的平坦化工艺为化学机械研磨工艺，化学机械研磨工艺不仅去除了位于介质层104上表面和上电极层103上表面的下电极膜a105，使得不同网孔内的下电极层105相互电绝缘，而且使得下电极层105的上表面更平坦。
参考图11，在其他实施例中，形成下电极膜a105，下电极膜a105位于网孔内、介质层104远离上电极层103的一侧以及暴露出的存储节点接触结构101的表面，且还位于介质层104上表面和上电极层103上表面，同时位于每一网孔内的下电极膜a105围成通孔。
参考图12，采用干法刻蚀工艺，刻蚀去除位于介质层104上表面和上电极层103上表面的下电极膜a105(参考图11)，且还刻蚀去除位于通孔底部的部分下电极膜a105，剩余的下电极膜a105作为下电极层。
参考图13，在形成下电极层105之后，在每一网格内形成导电填充层106，且导电填充层106填充满通孔，导电填充层106与通孔暴露出的存储节点接触结构101接触。
本实施例中，采用化学气相沉积工艺形成导电填充层106，形成导电填充层106采用化学气相沉积工艺，加快形成速率，有利于提高半导体结构的形成效率。在其他实施例中，也可以采用原子层沉积工艺形成导电填充层。
导电填充层106的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，导电填充层106的材料为掺杂多晶硅。
在其他实施例中，参考图14，位于每一网孔内的下电极膜a105围成通孔；采用化学气相沉积工艺形成填充满通孔的牺牲层107。
牺牲层107用于在后续去除位于介质层104上表面和上电极层103上表面的下电极膜a105时，防止去除工艺对其余的下电极膜a105产生影响； 牺牲层107的材料为掺杂硼和磷的二氧化硅(BPSG)或者含氧材料。
参考图15，在形成牺牲层107之后，采用平坦化工艺，去除位于介质层104上表面和上电极层103上表面的下电极膜a105(参考图14)，剩余的下电极膜a105为下电极层105。形成的下电极层105位于介质层104远离上电极层103一侧，且还位于暴露出的存储节点接触结构101表面，不同网孔内的下电极层105相互电绝缘。
采用的平坦化工艺为化学机械研磨工艺，化学机械研磨工艺不仅去除了位于介质层104上表面和上电极层103上表面的下电极膜a105，使得不同网孔内的下电极层105相互电绝缘，而且使得下电极层105的上表面更平坦。
参考图16，在平坦化工艺之后，采用湿法刻蚀工艺进行针对性刻蚀的方式去除牺牲层107(参考图15)。由于湿法刻蚀工艺的具有针对性，在除去牺牲层107的过程中并不会对下电极层105产生影响。
参考图17，在形成下电极层105之后，在每一网格内形成导电填充层106，且导电填充层106填充满通孔，导电填充层106位于下电极层105的表面上。
本实施例中，采用化学气相沉积工艺形成导电填充层106，形成导电填充层106采用化学气相沉积工艺，加快形成速率，有利于提高半导体结构的形成效率。在其他实施例中，也可以采用原子层沉积工艺形成导电填充层。
导电填充层106的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，导电填充层106的材料为掺杂多晶硅。
参考图18，本实施例中，在形成下电极层105后，形成初始第二绝缘层a108，初始第二绝缘层a108位于上电极层103上表面、介质层104上表面以及下电极层105上表面。
本实施例中，采用原子层沉积工艺形成初始第二绝缘层a108，本实施例中，初始第二绝缘层a108的材料为氧化硅，在其他实施例中，初始第二绝缘层的材料也可以为高K材料。初始第二绝缘层a108作为后续形成第二绝缘层108的基础。
参考图19，采用干法刻蚀工艺去除位于周边区B的部分初始第二绝缘层a108(参考图18)，剩余的初始第二绝缘层a108作为第二绝缘层108，第二绝缘层108暴露出周边区B的至少部分上电极层103表面，用于方便上电极层103与后续形成的上电极层填充层电连接。
参考图20，采用原子层沉积工艺形成上电极层填充层109，上电极层填充层109覆盖露出的周边区B的至少部分上电极层103表面，且还位于第二绝缘层108表面。
上电极层填充层109的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，上电极层填充层109的材料为掺杂多晶硅。
本实施例的方法形成的半导体结构与六边形蜂巢布局的半导体结构相比，在半导体结构的位线节距为20纳米～40纳米，字位线节距比为，且形成的介质层104的厚度都为5.5纳米时，本实施例的上电极层103的厚度为4纳米，六边形蜂巢布局的半导体结构的上电极层的厚度为2.5纳米；本实施例形成的半导体结构与六边形蜂巢布局的半导体结构的电容比为1.2：1，本实施例形成的半导体结构的单元电容值提高20％。
本实施例提供的半导体结构的形成方法，先形成网格状的上电极层103，上电极层103内的多个贯穿上电极层103的网孔与每一存储节点接触结构101正对；因为与存储节点接触结构101正对的网格状的上电极层103实现天然密排，所以字线和位线的节距比无须固定，有利于减少半导体结构在结构设计和材料需求等方面的局限和困难；同时上电极层103天然密排使得在既定的字位线节距比下，电容的电极板面积达到最大化；由于上 电极层103是网格状的，表明上电极层103之间是相连的，是稳固的整体，所以有效避免电容结构坍塌的问题，提高半导体结构的性能。
本申请第二实施例提供一种半导体结构的形成方法，与本申请第一实施例大致相同，主要区别在于本实施例刻蚀去除网孔露出的绝缘层之前，在网孔内形成保护层，以下将结合附图对本申请第二实施例提供的半导体结构的形成方法进行详细说明，与前一实施例相同或者相应的部分，可参考前述实施例的说明，以下将不做赘述。
图21～图30为本申请第二实施例提供的一种半导体结构的形成方法的各步骤对应的结构示意图。
参考图21，本实施例中，形成的半导体结构包括：电容区A和位于电容区A周边的周边区B；提供层叠设置的基底200以及绝缘层202，基底200和绝缘层202位于电容区A和周边区B；基底200内具有多个相互间隔的存储节点接触结构201，存储节点接触结构201位于电容区A；在绝缘层202表面形成网格状的上电极层203，上电极层203内具有多个贯穿上电极层203的网孔；在上电极层203侧壁形成介质层204。
参考图22，采用原子层沉积工艺在网孔内形成保护膜a220，保护膜a220位于介质层204侧壁、网孔暴露出的绝缘层202的表面、上电极层203顶面和介质层204的顶面。
保护膜a220的材料为导电材料。本实施例中，保护膜a220的材料与后续形成的下电极层材料相同，具体可以为氮化钛材料；在其他实施例中，保护膜的材料可以为掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。后续在保护膜a220的基础上形成保护层。
参考图23，采用干法刻蚀工艺去除位于网孔暴露出的绝缘层202表面、上电极层203顶面和介质层204的顶面的保护膜a220(参考图22)，剩余的保护膜a220作为保护层220，保护层220覆盖介质层204侧壁。
这样在去除网孔露出的绝缘层202时，保护层220可以保护介质层204不受去除工艺的影响；即使在去除绝缘层202时也去除了部分保护层220，由于后续需要在保护层220形成的通孔中形成下电极层，且下电极层的材料与保护层220的材料相同，也可以弥补去除绝缘层202时对保护层220的损伤。
参考图24，去除通孔暴露出的绝缘层202。
参考图25，形成填满保护层220形成的通孔的下电极层205，形成的下电极层205位于保护层220的侧壁。
参考图26，在其他实施例中，形成保形覆盖的介质膜a204，介质膜a204位于网孔底部和侧壁，且还位于上电极层203上表面。
参考图27，形成保形覆盖的保护膜a220，保护膜a220位于介质膜a204表面。
参考图28，刻蚀保护膜a220(参考图27)以及介质膜a204(参考图27)，直至露出上电极层203的上表面以及网孔底部的绝缘层202，再刻蚀去除网孔底部的绝缘层202；剩余保护膜a220作为保护层220，剩余介质膜a204作为介质层204；其中，位于绝缘层202与保护层220之间的介质层204侧壁表面被露出。
参考图29，在网孔中形成下电极层205，形成的下电极层205还位于暴露出的介质层204侧壁表面。
本实施例中，在形成下电极层105后，形成第二绝缘层208和上电极层填充层209，第二绝缘层208和上电极层填充层209的具体情况与第一实施例相同，这里不再赘述。
本实施例在去除网孔露出的绝缘层202之前，在网孔内形成覆盖介质层204侧壁的保护层220，这样在去除网孔露出的绝缘层202时，保护层220可以保护介质层204不受去除工艺的影响；同时由于后续需要在保护层 220形成的通孔中形成下电极层205，且下电极层205的材料与保护层220的材料相同，即使在去除绝缘层202时也去除了部分保护层220，相同材料的下电极层205也可以弥补去除绝缘层202时对保护层220的损伤。
本申请第三实施例提供一种半导体结构，该半导体结构可采用第一实施例或者第二实施例提供的形成方法形成。以下将结合附图对本申请第三实施例提供的半导体结构进行详细说明。
图31为本申请第三实施例提供的一种半导体结构的结构示意图。
参考图31，本实施例中，半导体结构包括：层叠设置的基底300以及绝缘层302，基底300内具有多个相互间隔的存储节点接触结构301，绝缘层302暴露出存储节点接触结构301；网格状的上电极层303，上电极层303位于绝缘层302表面，上电极层303内具有多个贯穿上电极层303的网孔，每一网孔暴露出存储节点接触结构301；介质层304，介质层304位于网孔的侧壁；下电极层305，下电极层305位于网孔内，下电极层305位于介质层304远离上电极层303一侧，且还与暴露出的存储节点接触结构301相接触，不同网孔内的下电极层305相互电绝缘。
本实施例中，半导体结构包括电容区A和位于电容区A周边的周边区B，基底300和绝缘层302位于电容区A和周边区B；基底300的材料为半导体材料。本实施例中，基底300的材料为硅。在其他实施例中，基底也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。
本实施例中，存储节点接触结构301位于电容区A，存储节点接触结构301在半导体结构中用于连接晶体管和电容器。存储节点接触结构301的材料为金属。本实施例中，存储节点接触结构301的材料可以为钨金属。在其他实施例中，存储节点接触结构的材料也可以为铜金属、铝金属、金金属或者银金属等。
绝缘层302起到绝缘保护的作用，本实施例中，绝缘层302的材料为 氧化硅，在其他实施例中，绝缘层的材料也可以为高K材料。
上电极层303内具有多个贯穿上电极层303的网孔，每一网孔暴露出一存储节点接触结构301，网孔位于电容区A，上电极层303不仅位于电容区A，而且位于周边区B。
由于半导体结构的字线和位线呈有规律的纵横排布，多个存储节点接触结构301呈规则的四方排布，所以与存储节点接触结构301正对的网格状的上电极层303为矩形网格。
上电极层303可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，上电极层303采用钨材料。
因为与存储节点接触结构301正对的网格状的上电极层303实现天然密排，所以字线和位线的节距比无须固定，有利于减少半导体结构在结构设计和材料需求等方面的局限和困难；同时上电极层303天然密排使得在既定的字位线节距比下，电容的电极板面积达到最大化；由于上电极层303是网格状的，表明上电极层303之间是相连的，是稳固的整体，所以有效避免电容结构坍塌的问题。
介质层304的材料为为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。
本实施例中，每一网孔内的下电极层305填充满网格。
下电极层305可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极层305采用氮化钛材料。
本实施例中，半导体结构还包括第二绝缘层308，第二绝缘层308位于上电极层上303表面、介质层304上表面和下电极层305上表面，且露出周边区B的至少部分上电极层303表面，用于方便上电极层303与后续形 成的上电极层填充层电连接。
第二绝缘层308的材料为氧化硅，在其他实施例中，第二绝缘层的材料也可以为高K材料。
本实施例还包括：上电极层填充层309，上电极层填充层309覆盖露出的周边区B的至少部分上电极层303表面，且还位于第二绝缘层308表面。
上电极层填充层309的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，上电极层填充层309的材料为掺杂多晶硅。
图32为本申请第三实施例提供的另一种半导体结构的结构示意图。
参考图32，在其他实施例中，每一网孔内的下电极层305围成通孔，通孔暴露出存储节点接触结构301的部分表面；半导体结构还包括导电填充层306，导电填充层306填充满所述通孔。
导电填充层306的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，导电填充层306的材料为掺杂多晶硅。
图33为本申请第三实施例提供的又一种半导体结构的结构示意图。
参考图33，在其他实施例中，每一网孔内的下电极层305围成通孔，下电极层305位于介质层304远离上电极层303一侧且还位于存储节点接触结构301的表面；半导体结构还包括导电填充层306，导电填充层306填充满所述通孔。
导电填充层306的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，导电填充层306的材料为掺杂多晶硅。
图34为本申请第三实施例提供的再一种半导体结构的结构示意图。
参考图34，在其他实施例中，半导体结构还包括：保护层320，保护层320覆盖介质层304的侧壁。
保护层320的材料为导电材料。保护层320的材料与下电极层305材料相同，具体可以为氮化钛材料、掺杂多晶硅、钛、氮化钛、钨以及钨的 复合物等。
在去除网孔露出的绝缘层302时，保护层320可以保护介质层304不受去除工艺的影响；同时由于后续需要在保护层320形成的通孔中形成下电极层305，且下电极层305的材料与保护层320的材料相同，即使在去除绝缘层302时也去除了部分保护层320，相同材料的下电极层305也可以弥补去除绝缘层302时对保护层320的损伤。
本实施例提供的半导体结构，具有网格状的上电极层303，上电极层303内的多个贯穿上电极层303的网孔与每一存储节点接触结构301正对，因为与存储节点接触结构301正对的网格状的上电极层303实现天然密排，所以字线和位线的节距比无须固定，有利于减少半导体结构在结构设计和材料需求等方面的局限和困难；同时上电极层303天然密排使得在既定的字位线节距比下，电容的电极板面积达到最大化；由于上电极层303是网格状的，表明上电极层303之间是相连的，是稳固的整体，所以有效避免电容结构坍塌的问题。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构的形成方法，包括：
    提供层叠设置的基底以及绝缘层，所述基底内具有多个相互间隔的存储节点接触结构；
    在所述绝缘层表面形成网格状的上电极层，所述上电极层内具有多个贯穿所述上电极层的网孔，每一所述网孔在所述绝缘层上的正投影与一所述存储节点接触结构在所述绝缘层上的正投影具有重叠区域；
    在所述网孔的侧壁形成介质层；
    去除所述网孔露出的所述绝缘层，以暴露出所述存储节点接触结构；
    在所述网孔内形成下电极层，所述下电极层位于所述介质层远离所述上电极层一侧，且还与暴露出的所述存储节点接触结构相接触，不同所述网孔内的所述下电极层相互电绝缘。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成所述下电极层的步骤包括：形成下电极膜，所述下电极膜位于所述网孔内、所述介质层远离所述上电极层的一侧以及暴露出的所述存储节点接触结构的表面，且还位于所述介质层上表面和所述上电极层上表面；
    去除位于所述介质层上表面和所述上电极层上表面的所述下电极膜，剩余的所述下电极膜为所述下电极层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述下电极膜填充满所述网孔；采用平坦化工艺，去除位于所述介质层上表面和所述上电极层上表面的所述下电极膜，且所述下电极层填充满所述网孔。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，位于每一所述网孔内的所述下电极膜围成通孔；去除位于所述介质层上表面和所述上电极层上表面的所述下电极膜的工艺步骤包括：
    对所述下电极膜进行干法刻蚀，刻蚀去除位于所述介质层上表面和 所述上电极层上表面的所述下电极膜，且还刻蚀去除位于所述通孔底部的部分所述下电极膜。
  5. 根据权利要求2所述的半导体结构的形成方法，其中，位于每一所述网孔内的所述下电极膜围成通孔；去除位于所述介质层上表面和所述上电极层上表面的所述下电极膜的工艺步骤包括：
    形成填充满所述通孔的牺牲层；
    在形成所述牺牲层之后，采用平坦化工艺，去除位于所述介质层上表面和所述上电极层上表面的所述下电极膜；
    在所述平坦化工艺之后，去除所述牺牲层。
  6. 根据权利要求4所述的半导体结构的形成方法，其中，在形成所述下电极层之后，还包括：在每一所述网格内形成导电填充层，且所述导电填充层填充满所述通孔。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，采用干法刻蚀工艺，刻蚀去除所述网孔露出的所述绝缘层；在进行所述干法刻蚀工艺之前，还包括：在所述网孔内形成保护层，所述保护层覆盖所述介质层侧壁；形成的所述下电极层还位于所述保护层的侧壁。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，形成所述介质层以及所述保护层的工艺步骤包括：
    形成保形覆盖的介质膜，所述介质膜位于所述网孔底部和侧壁，且还位于所述上电极层上表面；
    形成保形覆盖的保护膜，所述保护膜位于所述介质膜表面；
    刻蚀所述保护膜以及所述介质膜，直至露出所述上电极层的上表面以及所述网孔底部的所述绝缘层，剩余所述保护膜作为所述保护层，剩余所述介质膜作为所述介质层；
    其中，位于所述绝缘层与所述保护层之间的所述介质层侧壁表面被 露出，且形成的所述下电极层还位于暴露出的所述介质层侧壁表面。
  9. 根据权利要求7所述的半导体结构的形成方法，其中，所述保护层的材料为导电材料。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，形成所述上电极层的工艺步骤包括：
    在所述绝缘层表面形成模型层，所述模型层内具有多个贯穿所述模型层的开口；
    形成所述上电极层，所述上电极层填充满所述开口；
    去除所述模型层。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，采用湿法刻蚀工艺，去除所述模型层。
  12. 根据权利要求1所述的半导体结构的形成方法，其中，所述半导体结构包括电容区以及周边区，所述网孔位于所述电容区，且所述上电极层还位于所述周边区；所述形成方法还包括：
    形成第二绝缘层，所述第二绝缘层位于所述上电极层上表面、所述介质层上表面以及所述下电极层上表面，且露出所述周边区的至少部分所述上电极层表面；
    形成上电极层填充层，所述上电极层填充层覆盖露出的所述周边区的至少部分所述上电极层表面，且还位于所述第二绝缘层表面。
  13. 一种半导体结构，包括：
    层叠设置的基底以及绝缘层，所述基底内具有多个相互间隔的存储节点接触结构，所述绝缘层暴露出所述存储节点接触结构；
    网格状的上电极层，所述上电极层位于所述绝缘层表面，所述上电极层内具有多个贯穿所述上电极层的网孔，每一所述网孔暴露出所述存储节点接触结构；
    介质层，所述介质层位于所述网孔的侧壁；
    下电极层，所述下电极层位于所述网孔内，所述下电极层位于所述介质层远离所述上电极层一侧，且还与暴露出的所述存储节点接触结构相接触，不同所述网孔内的所述下电极层相互电绝缘。
  14. 根据权利要求13所述的半导体结构，其中，每一所述网孔内的下电极层填充满所述网格。
  15. 根据权利要求13所述的半导体结构，其中，每一所述网孔内的所述下电极层围成通孔，所述通孔暴露出所述存储节点接触结构的部分表面。
  16. 根据权利要求13所述的半导体结构，其中，每一所述网孔内的所述下电极层围成通孔，所述下电极层位于所述介质层远离所述上电极层一侧且还位于所述存储节点接触结构的表面。
  17. 根据权利要求15所述的半导体结构，还包括：导电填充层，所述导电填充层填充满所述通孔。
  18. 根据权利要求13所述的半导体结构，其中，所述半导体结构包括电容区以及周边区，所述网孔位于所述电容区，且所述上电极层还位于所述周边区；
    还包括：第二绝缘层，所述第二绝缘层位于所述上电极层上表面、所述介质层上表面和所述下电极层上表面，且露出所述周边区的至少部分所述上电极层表面。
  19. 根据权利要求18所述的半导体结构，还包括：上电极层填充层，所述上电极层填充层覆盖露出的所述周边区的至少部分所述上电极层表面，且还位于所述第二绝缘层表面。
  20. 根据权利要求13所述的半导体结构，还包括：保护层，所述保护层覆盖所述介质层的侧壁。
PCT/CN2021/120205 2021-02-05 2021-09-24 半导体结构及其形成方法 WO2022166216A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/648,666 US20220254874A1 (en) 2021-02-05 2022-01-21 Semiconductor structure and method for forming same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110163948.9A CN114883271A (zh) 2021-02-05 2021-02-05 半导体结构及其形成方法
CN202110163948.9 2021-02-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/648,666 Continuation US20220254874A1 (en) 2021-02-05 2022-01-21 Semiconductor structure and method for forming same

Publications (1)

Publication Number Publication Date
WO2022166216A1 true WO2022166216A1 (zh) 2022-08-11

Family

ID=82667149

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/120205 WO2022166216A1 (zh) 2021-02-05 2021-09-24 半导体结构及其形成方法

Country Status (2)

Country Link
CN (1) CN114883271A (zh)
WO (1) WO2022166216A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044181A1 (en) * 1996-11-06 2001-11-22 Fujitsu Limited Semiconductor device and method for fabricating the same
US20010050392A1 (en) * 2000-05-29 2001-12-13 Fujitsu Limited Semiconductor device and method for fabricating the same
CN101685801A (zh) * 2008-09-22 2010-03-31 南亚科技股份有限公司 堆叠电容的存储电极的制作方法
CN108447864A (zh) * 2018-03-14 2018-08-24 睿力集成电路有限公司 半导体存储器件结构及其制作方法
CN111106095A (zh) * 2018-10-29 2020-05-05 长鑫存储技术有限公司 沟槽及其形成方法、电容器的制备方法及电容器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044181A1 (en) * 1996-11-06 2001-11-22 Fujitsu Limited Semiconductor device and method for fabricating the same
US20010050392A1 (en) * 2000-05-29 2001-12-13 Fujitsu Limited Semiconductor device and method for fabricating the same
CN101685801A (zh) * 2008-09-22 2010-03-31 南亚科技股份有限公司 堆叠电容的存储电极的制作方法
CN108447864A (zh) * 2018-03-14 2018-08-24 睿力集成电路有限公司 半导体存储器件结构及其制作方法
CN111106095A (zh) * 2018-10-29 2020-05-05 长鑫存储技术有限公司 沟槽及其形成方法、电容器的制备方法及电容器

Also Published As

Publication number Publication date
CN114883271A (zh) 2022-08-09

Similar Documents

Publication Publication Date Title
CN210272255U (zh) 掩膜结构和存储器
CN209785930U (zh) 电容器、dram单元和存储器
JP3086403B2 (ja) サブリソグラフィ・サイズの細溝およびフィーチャの形成方法
JP2011166071A (ja) 半導体装置およびその製造方法
JP3681490B2 (ja) 半導体装置用コンデンサの製造方法
KR19980064364A (ko) 자기-정렬된 다중 크라운 저장 커패시터 및 그 형성 방법
CN112951770B (zh) 存储器的制作方法及存储器
US11856749B2 (en) Memory and method for forming memory
WO2023279567A1 (zh) 电容器的形成方法及半导体器件
CN115241372A (zh) 存储器件、半导体结构及其形成方法
WO2022166216A1 (zh) 半导体结构及其形成方法
US20220149049A1 (en) Method of manufacturing capacitor connecting line of memory and memory
US20220336462A1 (en) Method for manufacturing memory and memory
CN215299254U (zh) 半导体器件
CN214797421U (zh) 半导体器件
WO2022077947A1 (zh) 电容结构及其制作方法
US20220271042A1 (en) Dynamic random access memory and method of manufacturing the same
CN117222220A (zh) 存储器、半导体结构及其形成方法
US20220254874A1 (en) Semiconductor structure and method for forming same
WO2021233269A1 (zh) 半导体器件中孔、半导体器件的制备方法及半导体器件
CN113130495B (zh) 半导体器件及其形成方法
EP3958293A1 (en) Semiconductor device holes, semiconductor device preparation method, and semiconductor device
WO2024093031A1 (zh) 半导体结构及其制作方法
EP4239667A1 (en) Manufacturing method for semiconductor structure, and semiconductor structure
CN114743973A (zh) 一种半导体电容器结构及其制造方法、存储器、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21924213

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21924213

Country of ref document: EP

Kind code of ref document: A1