WO2022160279A1 - 阵列基板、显示面板及电子设备 - Google Patents

阵列基板、显示面板及电子设备 Download PDF

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Publication number
WO2022160279A1
WO2022160279A1 PCT/CN2021/074475 CN2021074475W WO2022160279A1 WO 2022160279 A1 WO2022160279 A1 WO 2022160279A1 CN 2021074475 W CN2021074475 W CN 2021074475W WO 2022160279 A1 WO2022160279 A1 WO 2022160279A1
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WIPO (PCT)
Prior art keywords
layer
substrate
pattern
sub
array substrate
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PCT/CN2021/074475
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English (en)
French (fr)
Inventor
王继国
孙建
张昭
田亮
秦伟达
王珍
张寒
秦文文
杨小艳
山岳
闫伟
张健
王德帅
张亚东
刘建涛
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/074475 priority Critical patent/WO2022160279A1/zh
Priority to DE112021001266.5T priority patent/DE112021001266T5/de
Priority to CN202180000094.0A priority patent/CN115668041B/zh
Priority to US17/622,708 priority patent/US11984453B2/en
Publication of WO2022160279A1 publication Critical patent/WO2022160279A1/zh
Priority to US18/630,971 priority patent/US20240258335A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a display panel and an electronic device.
  • the traditional ink-based electronic paper is gradually unable to meet the market demand due to technical bottlenecks such as high price and single color. , has great market potential in the fields of smart retail, electronic labels, e-books, etc.
  • the purpose of the present disclosure is to provide an array substrate, a display panel and an electronic device, thereby at least to a certain extent overcoming one or more problems due to limitations and defects of the related art.
  • a first aspect of the present disclosure provides an array substrate, including:
  • a first substrate having a plurality of sub-pixel regions arranged in an array along the row direction and the column direction;
  • the pixel circuit layer formed on the first substrate, the pixel circuit layer including a plurality of sub-pixel circuits, at least part of the sub-pixel circuits is located in the sub-pixel region;
  • planarization layer formed on the pixel circuit layer, the planarization layer is provided with a first via hole in the sub-pixel region, and the planarization layer includes at least one pattern portion, the pattern portion includes a plurality of pattern units arranged in an array along the row direction and the column direction, the pattern units are uneven and are located at least in the sub-pixel area, wherein the pattern units include a plurality of pattern units sequentially arranged in the circumferential direction Arranged first bumps and spaced grooves surrounding each of the first bumps, and two adjacent first bumps in the circumferential direction of the pattern unit share a portion of the spaced grooves;
  • a reflective electrode layer is formed on the planarization layer, the reflective electrode layer includes a plurality of mutually disconnected reflective electrodes, each of the reflective electrodes is located in one of the sub-pixel regions, and passes through the first pass through The hole is electrically connected to the sub-pixel circuit, and the portion of the reflective electrode corresponding to the pattern unit is in an uneven shape matching the pattern unit.
  • the orthographic projection pattern of the first bumps on the first substrate is a symmetrical pattern
  • the symmetrical pattern includes at least two symmetry axes, which are respectively perpendicular to each other
  • the first axis of symmetry and the second axis of symmetry wherein the length of the first axis of symmetry is greater than the length of the second axis of symmetry, and the first axis of symmetry and the second axis of symmetry
  • the thickness directions of the substrates are perpendicular to each other.
  • the extending directions of the first symmetry axes of two adjacent symmetrical patterns intersect.
  • extension directions of the first symmetry axes of two adjacent symmetrical patterns are perpendicular to each other.
  • the pattern unit includes four first bumps, and in the circumferential direction of the pattern unit, one of the symmetrical patterns of two adjacent first bumps
  • the first axis of symmetry of the other is collinear with the second axis of symmetry of the other.
  • the first symmetry axis of one of the symmetrical patterns of the adjacent two first bumps extends in the row direction, and the other one extends in the row direction.
  • the first axis of symmetry of each extends in the column direction.
  • the axis of symmetry of the symmetrical pattern includes only the first axis of symmetry and the second axis of symmetry.
  • the symmetrical pattern is a rhombus, a rectangle, an ellipse or an octagon.
  • a ratio of the length of the first axis of symmetry of the symmetrical pattern to the length of the second axis of symmetry of the first bump is 1.5 to 2.5.
  • the length of the second axis of symmetry is 6 ⁇ m to 10 ⁇ m.
  • the pattern unit further includes a second bump located in a central area surrounded by each of the first bumps;
  • the parts of each of the spacing grooves in the pattern unit close to the second bumps are connected end to end in sequence along the circumferential direction and surround the second bumps.
  • the slope angles of the first bump and the second bump are both 6° to 13°.
  • the smallest distance between two adjacent first bumps in the pattern unit in the circumferential direction thereof is a first distance
  • the second distance in the pattern unit The minimum distance between the bump and the first bump is the second distance
  • the ratio between the first distance and the second distance is 1 to 1.5.
  • the second pitch is 1.5 ⁇ m to 5 ⁇ m.
  • the maximum thickness of the first bump is the same as the maximum thickness of the second bump.
  • the thickness of the planarization layer is greater than or equal to 1 ⁇ m.
  • a distance between the first via hole and the spacing groove is greater than or equal to 5 ⁇ m.
  • the first substrate further has a plurality of rows of first wiring regions and a plurality of columns of second wiring regions, the first wiring regions and each row of sub-pixel regions are located in the columns overlapping in the direction, the second wiring area and each column of sub-pixel areas are alternately arranged in the row direction;
  • the pixel circuit layer further includes a plurality of rows of gate lines and a plurality of columns of data lines, the gate lines are located in the first wiring area, the data lines are located in the second wiring area, the gate lines and the data lines They are respectively electrically connected to the sub-pixel circuits.
  • the sub-pixel circuit includes a storage capacitor and a transistor
  • the storage capacitor is located in the sub-pixel region, and the storage capacitor includes a first electrode plate and a second electrode plate opposite in the thickness direction of the first substrate, the first electrode plate and the gate
  • the lines are arranged in the same layer and are disconnected from each other, the second electrode plate and the data line are arranged in the same layer and disconnected from each other, and the second electrode plate is connected to the reflective electrode through the first via hole;
  • the transistor includes an active layer, a gate, a source and a drain; the active layer is located on the side of the gate line close to the first substrate, and the active layer includes a side located on the second wiring A first active part in the sub-pixel region, a second active part opposite to the first active part in the row direction, and a third active part in the sub-pixel region, the first active part in the
  • the orthographic projection on the first substrate overlaps with the orthographic projection of the gate line on the first substrate, and the first end of the first active part is located at the gate line away from the first end.
  • the second end of the first active part is connected to the first end of the third active part, and the first end and the second end of the second active part are respectively located at On two adjacent sub-pixel regions in the row direction, the first end of the second active portion is located on the side of the gate line away from the third active portion, and the second active portion The second end is connected with the second end of the third active part;
  • the portion of the gate line that overlaps with the first active portion and the second active portion in the thickness direction of the first substrate constitutes the gate of the transistor
  • the data A portion of the line that overlaps with the first end of the first active portion in the thickness direction of the first substrate constitutes a source of the transistor
  • the source and the first active portion The first end of the second electrode plate is connected through a second via hole
  • the part of the second electrode plate that overlaps with the first end of the second active part in the thickness direction of the first substrate constitutes the transistor
  • the drain is connected to the first end of the second active part through a third via hole.
  • the first electrode plates of the storage capacitors of any two adjacent sub-pixel circuits in the same sub-pixel circuit are connected by a common line, and the common line is on the same layer as the first electrode plate set up.
  • the planarization layer further includes a non-pattern portion located at least in the first wiring region, the non-pattern portion extends in the row direction, and the non-pattern portion is far away from The surface of the first substrate is flat.
  • each of the pattern units in the pattern portion is continuously arranged
  • the pattern portion extends in the row direction, and the orthographic projection of the pattern portion on the first substrate overlaps with the sub-pixel regions located in the same row.
  • a plurality of the pattern parts and the non-pattern parts are provided, and the pattern parts and the non-pattern parts are alternately arranged in the column direction.
  • a second aspect of the present disclosure provides a display panel, which includes the array substrate described in any one of the above and a counter substrate arranged in a cell-to-cell manner with the array substrate.
  • the opposite substrate includes a second substrate and a spacer on a side of the second substrate close to the array substrate, the spacer on the side of the array substrate.
  • the orthographic projection on the first substrate overlaps with the overlapping portion of the first wiring area and the second wiring area, and the surface of the spacer close to the array substrate is on the first substrate.
  • the orthographic projection on the bottom is within the orthographic projection of the non-patterned portion of the planarization layer on the first substrate.
  • a distance between a surface of the spacer close to the array substrate and the spacing grooves of the pattern unit is greater than or equal to 5 ⁇ m.
  • the opposite substrate further includes a shielding layer located between the spacer and the second substrate, and a plurality of arrays are arranged on the shielding layer.
  • the aperture area, the orthographic projection of each aperture area on the first substrate is located in one of the sub-pixel areas, and is located in the reflective electrode and the pattern portion on the first substrate in the orthographic projection on.
  • the opposing substrate further includes:
  • the color filter layer located between the spacer and the second substrate, the color filter layer includes a plurality of filter blocks, at least part of the filter blocks is located in the opening area;
  • a protective film layer located on the side of the color filter layer and the blocking layer away from the second substrate, and on the side of the spacer close to the second substrate, the protective film layer covers the color filter layer and the blocking layer;
  • a common electrode layer is located between the protective film layer and the spacer.
  • a third aspect of the present disclosure provides an electronic device, including the display panel described in any one of the above.
  • FIG. 1 is a schematic diagram showing the distribution of each area in the display area of the first substrate in the array substrate according to the embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of forming an active layer on the first substrate shown in FIG. 1;
  • FIG. 3 shows a schematic structural diagram of forming gate lines, first electrode plates and common lines on the first substrate shown in FIG. 2;
  • Fig. 4 shows the enlarged structural schematic diagram of the A part shown in Fig. 3;
  • FIG. 5 shows a schematic structural diagram of forming a second via hole and a third via hole on the first substrate shown in FIG. 3;
  • FIG. 6 shows a schematic structural diagram of forming a data line and a second electrode plate on the first substrate shown in FIG. 5;
  • FIG. 7 shows an enlarged schematic view of the structure at the transistor shown in FIG. 6;
  • FIG. 8 shows a schematic structural diagram of forming a planarization layer on the first substrate shown in FIG. 6;
  • FIG. 9 shows a schematic structural diagram of a planarization layer according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic structural diagram of the minimum repeating pattern unit of the planarization layer shown in FIG. 9;
  • FIG. 11 shows a schematic structural diagram of a pattern portion in a planarization layer according to another embodiment of the present disclosure
  • FIG. 12 shows a schematic structural diagram of a pattern portion in a planarization layer according to another embodiment of the present disclosure
  • FIG. 13 shows a schematic structural diagram of the pattern portion in the planarization layer described in the related art
  • FIG. 14 shows a schematic structural diagram of forming a reflective electrode on the first substrate shown in FIG. 8;
  • FIG. 15 shows a schematic structural diagram of the reflective electrode in the structure shown in FIG. 14;
  • FIG. 16 shows a schematic structural diagram of a reflective electrode according to another embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram showing the positional relationship between the array substrate and the spacers according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram showing the positional relationship between the planarization layer and the spacer according to an embodiment of the present disclosure
  • FIG. 19 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Fig. 20 shows a schematic structural diagram of the shielding layer shown in Fig. 19;
  • Figure 21 shows a schematic cross-sectional view along the M-M' direction shown in Figure 19;
  • FIG. 22 shows a schematic cross-sectional view of a part of the GOA region shown in an embodiment of the present disclosure
  • FIG. 23 shows a schematic diagram of refraction and reflection according to an embodiment of the present disclosure.
  • the first substrate; 10a the glass layer; 10b, the buffer layer; 101, the sub-pixel area; 102, the first wiring area; 103, the second wiring area;
  • transistor; 110 active layer; 1101, first active part; 1102, second active part; 1103, third active part; 111, gate; 112, source; 113, drain; 12 121, the first electrode plate; 122, the second electrode plate; 13, the gate line; 14, the data line; 15, the gate insulating layer; 16, the interlayer dielectric layer; 160, the second via hole; 161, third via hole; 17, planarization layer; 170, first via hole; 171, pattern part; 171a, pattern unit; 1710, first bump; 1711, spacing groove; 1712, second bump; 172, non- pattern part; 18, reflective electrode; 19, common line; 20, spacer; 21, shielding layer; 210, opening area; 211, shielding area; 22, second substrate; 23, filter block; 24, protective film layer; 25. common electrode layer.
  • RLCD technology reflective display technology
  • RLCD technology can directly replace the screen light source by reflecting ambient light without the need for a backlight. It has significant advantages in ultra-low power consumption and thin and light body.
  • the array substrate may include a first substrate 10, a pixel circuit layer, a planarization layer 17 and a reflective electrode layer, wherein:
  • the first substrate 10 may be a single-layer structure, for example, the first substrate 10 may be a glass substrate, but not limited thereto, and may also be a PI (polyimide) substrate or the like. It should be noted that the first substrate 10 is not limited to a single-layer structure, but may also be a multi-layer composite structure. For example, as shown in FIGS. 21 and 22 , the first substrate 10 may include a glass layer 10a and a buffer layer 10b located on the glass layer 10a, the buffer layer 10b can be an inorganic insulating layer, such as: silicon oxide, silicon nitride, silicon oxynitride, etc. It should be understood that the first substrate 10 is a multilayer When the composite structure is used, it is not limited to include the aforementioned glass layer 10a and the buffer layer 10b, and may also include other layers, etc., depending on the specific situation.
  • the first substrate 10 may include a display area and a non-display area disposed around the display area.
  • the display area may have a plurality of sub-pixel areas 101 arranged in an array along the row direction X and the column direction Y, a plurality of rows of first wiring areas 102 and a plurality of columns of second wiring areas 103, wherein the first A wiring area 102 and each row of sub-pixel areas 101 are alternately arranged in the column direction Y, and the second wiring area 103 and each column of sub-pixel areas 101 are arranged to overlap in the row direction X.
  • the non-display area may include a GOA (ie, gate driving circuit) area, a bonding area, and the like.
  • the pixel circuit layer can be formed on the first substrate 10.
  • the pixel circuit layer can be located on the side of the buffer layer 10b away from the glass layer 10a.
  • the pixel circuit layer may include multiple rows of gate lines 13 , multiple columns of data lines 14 and multiple sub-pixel circuits.
  • the gate lines 13 and data lines 14 are respectively electrically connected to the sub-pixel circuits, as shown in FIG. 1 to FIG. 7 .
  • the gate lines 13 may extend in the row direction X and be located in the first wiring area 102 ; for example, as shown in FIG. 3 , each row of the first wiring areas 102 may be provided with a row of gate lines 13 , but not limited to this, the first wiring region 102 located between two adjacent rows of sub-pixel regions 101 may also be provided with two rows of gate lines 13, depending on the specific situation.
  • the data lines 14 extend in the column direction Y and are located in the second wiring area 103; for example, as shown in FIG. 6 , each column of the second wiring areas 103 may be provided with a column of data lines 14, but not limited to this, located adjacent to The second wiring region 103 between the two columns of sub-pixel regions 101 may also be provided with two columns of data lines 14, depending on the specific situation.
  • At least part of the sub-pixel circuits is located in the sub-pixel region 101 ; for example, the number of sub-pixel circuits can be equal to the number of the sub-pixel regions 101 , wherein at least part of each sub-pixel circuit is located in a sub-pixel region 101 .
  • each row of gate lines 13 can be electrically connected to the same row of sub-pixel circuits, and each column of data lines 14 can be connected to The sub-pixel circuits in the same column are electrically connected.
  • the orthographic shapes of the data lines 14 in each column and the gate lines 13 in each row on the first substrate 10 may be similar to the shape of a straight line, but not limited to this, and may also be Other shapes, on a case-by-case basis.
  • the material of the gate line 13 may be copper (Cu), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti) and other metals or alloys, but not limited thereto;
  • the material of the data line 14 can be a composite material, that is, the data line 14 can be a composite structure, for example, the data line 14 can be composed of three layers of titanium (Ti), aluminum (Al), and titanium (Ti) stacked in sequence.
  • the data line 14 is Ti/Al/
  • the Ti sandwich structure can also be a single-layer structure, which can be selected from materials with good electrical conductivity, etc., depending on the specific situation.
  • the data lines 14 and the gate lines 13 are located in different layers in the embodiment of the present disclosure.
  • the data lines 14 may be located on the side of the gate lines 13 away from the first substrate 10 , that is, when the array substrate is fabricated , the gate line 13 can be made first, and then the data line 14 can be made; wherein, in order to avoid the direct contact between the data line 14 and the gate line 13, it can be seen from FIG. 19 and FIG. 21 that a layer is sandwiched between the data line 14 and the gate line 13
  • the interlayer dielectric layer 16, for example, the interlayer dielectric layer 16 can be an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the interlayer dielectric layer 16 is provided on the entire surface of the array substrate, that is, the orthographic projection of the interlayer dielectric layer 16 on the first substrate 10 except for covering the gate lines 13 on the first substrate 10
  • other structures located on the first substrate 10 may also be covered, for example, structures such as the active layer 110, the first electrode plate 121 and other structures mentioned later.
  • the interlayer dielectric layer 16 is not only located in the display area, but also in the non-display area, as shown in FIG. 21 and FIG. 22 .
  • the sub-pixel circuit may include a storage capacitor 12 and a transistor 11 ; wherein, the storage capacitor 12 is located in the sub-pixel region 101 , and as shown in FIG. 3 to FIG. 7 and FIG. 21 , the storage capacitor 12 is included in the thickness direction Z of the first substrate 10
  • the first electrode plate 121 and the second electrode plate 122 are opposite to each other.
  • the first electrode plate 121 and the grid line 13 can be arranged in the same layer and disconnected from each other, and the second electrode plate 122 can be connected to the grid line 13 .
  • the data lines 14 are arranged in the same layer and are disconnected from each other, so that the processing steps, the cost and the thickness of the array substrate can be reduced while meeting the performance requirements.
  • the first electrode plate 121 of the storage capacitor 12 can be configured to apply a reference voltage, wherein, as shown in FIG. 3 , the first electrode of the storage capacitor 12 of any two adjacent sub-pixel circuits in the same sub-pixel circuit
  • the plates 121 are connected by a common line 19 , and the common line 19 is arranged on the same layer as the first electrode plate 121 .
  • the same layer refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through one patterning process. That is, one patterning process corresponds to one mask (mask, also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the production process is simplified, the production cost is saved, and the production efficiency is improved.
  • the transistor 11 may include an active layer 110 , a gate 111 , a source 112 and a drain 113 ; for example, the transistor 11 may be a top-gate type, that is, the active layer 110 may Located on the side of the gate line 13 close to the first substrate 10 , that is to say, when fabricating the array substrate, the active layer 110 can be fabricated first, and then the gate line 13 can be fabricated; but not limited to this, the transistor 11 can also be the bottom The gate type, that is, when fabricating the array substrate, the gate line 13 may be fabricated first, and then the active layer 110 may be fabricated.
  • the gate insulating layer 15 when the transistor 11 is a top-gate type, a gate insulating layer 15 is sandwiched between the active layer 110 and the gate electrode 111 .
  • the gate insulating layer 15 may be an inorganic insulating layer. layers, such as: silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the gate insulating layer 15 is disposed on the entire surface of the array substrate, the gate insulating layer 15 is located on the side of the interlayer dielectric layer 16 close to the first substrate 10 , and the orthographic projection of the gate insulating layer 15 on the first substrate 10 The orthographic projection of the active layer 110 on the first substrate 10 may be covered.
  • the gate insulating layer 15 is not only located in the display area, but also in the non-display area.
  • the active layer 110 may be low temperature polysilicon (abbreviation: LTPS), but not limited thereto, and may also be amorphous silicon (abbreviation: a-Si), indium gallium zinc oxide (abbreviation: IGZO) And so on, depending on the situation. It should be noted that, in the present disclosure, the active layer 110 is mainly made of low-temperature polysilicon as an example for description.
  • LTPS low temperature polysilicon
  • a-Si amorphous silicon
  • IGZO indium gallium zinc oxide
  • the orthographic shape of the active layer 110 on the first substrate 10 may be similar to a U shape.
  • the active layer 110 may include a first active portion located in the second wiring region 103 . 1101 , a second active portion 1102 opposite to the first active portion 1101 in the row direction X, and a third active portion 1103 located at least in the sub-pixel region 101 .
  • first active portion 1101 and the second active portion 1102 extend in the column direction Y respectively, and the third active layer 110 extends in the row direction X.
  • the first active portion 1101 and the second active portion 1101 and the second active layer The source portion 1102 and the third active portion 1103 each have a first end and a second end opposite in the extending direction thereof.
  • the orthographic projection of the first active part 1101 on the first substrate 10 overlaps with the orthographic projection of the gate line 13 on the first substrate 10 , and the first end of the first active part 1101 Located on the side of the gate line 13 away from the third active part 1103, the second end of the first active part 1101 is connected to the first end of the third active part 1103; the first end of the second active part 1102 is connected to the first end of the third active part 1103; The two ends are respectively located on two adjacent sub-pixel regions 101 in the row direction X, that is to say, the orthographic projection of the second active portion 1102 on the first substrate 10 and the projection of the gate line 13 on the first substrate 10 There is overlap in the orthographic projection, and the transistor 11 can be a dual gate type to ensure the performance of the transistor 11 .
  • the first end of the second active portion 1102 is located on the side of the gate line 13 away from the third active portion 1103 , and the second end of the second active portion 1102 is connected to the second end of the third
  • the gate line 13 and the first active portion 1101 and the second active portion 1102 have overlapping portions in the thickness direction Z of the first substrate 10 .
  • the gate 111 of the transistor 11 is formed; it can be seen from FIG. 6 and FIG.
  • the source 112 of the source electrode 112 is connected to the first end of the first active part 1101 through the second via hole 160 , and the second electrode plate 122 is connected to the first end of the second active part 1102 on the first substrate 10
  • the overlapping portion in the thickness direction Z of the transistor 11 constitutes the drain 113 of the transistor 11 , and the drain 113 is connected to the first end of the second active portion 1102 through the third via hole 161 .
  • the second via hole 160 and the third via hole 161 mentioned in the present disclosure may penetrate through the interlayer dielectric layer 16 and the gate insulating layer 15 and expose the first end and the first end of the first active part 1101 respectively.
  • the transistor 11 in the embodiment of the present disclosure may be an N-type, but not limited thereto, and may also be a P-type, depending on the specific situation.
  • the first end of the first active portion 1101 in the embodiment of the present disclosure can be farther away from the gate line 13 than the first end of the second active portion 1102 .
  • the dimension of the source part 1101 in the column direction Y may be larger than the dimension of the second active part 1102 in the column direction Y; but not limited to this, the dimension of the first active part 1101 in the column direction Y may be equal to or smaller than the dimension of the first active part 1101 in the column direction Y.
  • the size of the two active parts 1102 in the column direction Y depends on the specific situation.
  • the gate line 13 can be led out from the GOA to control the switching of the transistors 11 of the sub-pixel circuits of the entire row, and is combined with the data line 14 to complete the charging and discharging of the pixel.
  • the GOA can be concentrated on the array substrate, the GOA can be understood as the circuit structure in the non-display area in the array substrate, and the pixel circuit layer can be understood as the circuit structure in the display area in the array substrate.
  • the GOA may include a transistor TFT as shown in FIG. 22 .
  • the transistor structure of the GOA is different from that of the transistor 11 of the sub-pixel circuit, but is not limited to this.
  • the structure of the transistor 11 of the sub-pixel circuit may also be the same as the transistor structure of the GOA. ,As the case may be.
  • the GOA capacitor may also include a storage capacitor or the like.
  • the planarization layer 17 may be formed on the pixel circuit layer, but not limited thereto, and may also be located on the GOA. In other words, the planarization layer 17 may be located in the display area or the non-display area.
  • the material of the planarization layer 17 can be an organic material such as optical resin, but is not limited thereto, depending on the specific situation.
  • the planarization layer 17 may be a single-layer structure, but is not limited thereto, and may also be a multi-layer composite structure, depending on the specific situation.
  • the planarization layer 17 may be provided with a first via hole 170 in the sub-pixel region 101 , and the first via hole 170 may expose the second electrode plate 122 , in other words, the orthographic projection of the first via hole 170 on the first substrate 10 may be located within the orthographic projection of the second electrode plate 122 on the first substrate 10 .
  • the number of the first via holes 170 in the planarization layer 17 is multiple, and the number of the first via holes 170 is equal to the number of the sub-pixel regions 101 .
  • the holes 170 are located in a sub-pixel area 101 correspondingly, and the position of each first via hole 170 in the sub-pixel area 101 can be the same. In other words, any two adjacent first via holes 170 in the same row are in the same row.
  • the distances in the direction X are equal, and the distances in the column direction Y of any two adjacent second via holes 160 in the first via holes 170 in the same row are the same, so as to reduce the design difficulty.
  • the planarization layer 17 may further include at least one pattern portion 171 located in the display area, and may include a plurality of patterns arranged in an array along the row direction X and the column direction Y
  • the unit 171a, the pattern unit 171a is uneven and can be located at least in the sub-pixel area 101, but is not limited to this, and can also be located in at least one of the first wiring area 102 and the second wiring area 103, depending on the specific situation .
  • the uneven pattern unit 171 a may at least include a plurality of first bumps 1710 arranged in sequence along the circumferential direction C and a space surrounding each first bump 1710
  • the grooves 1711 that is, each first bump 1710 is surrounded by a spacer groove 1711 , and two adjacent first bumps 1710 in the circumferential direction of the pattern unit 171 a share a portion of the spacer groove 1711 .
  • the pattern unit 171a may further include a second bump 1712, and the second bump 1712 is located in the central area surrounded by each of the first bumps 1710, wherein, in the pattern unit 171a The parts of each of the spacing grooves 1711 close to the second bumps 1712 are sequentially connected end to end along the circumferential direction C of the pattern unit 171a and surround the second bumps 1712 . interval setting.
  • the surfaces of the first bump 1710 and the second bump 1712 away from the first substrate 10 may be arc surfaces, but not limited thereto, and may also be flat surfaces, depending on the specific situation.
  • the maximum thickness of the first bump 1710 may be the same as the maximum thickness of the second bump 1712 to reduce the design difficulty, but not limited thereto, the maximum thickness of the first bump 1710 may also be the same as the maximum thickness of the second bump 1712 The thickness can also be different, depending on the specific situation.
  • the second bumps 1712 may not be provided, depending on the specific situation.
  • the thicknesses of the first bump 1710 and the second bump 1712 refer to the bottom of the spacing groove to the top of the first bump 1710 away from the first substrate 10 and the distance of the second bump 1712 away The thickness between the tips of the first substrate 10 .
  • the aforementioned first bumps 1710 arranged in sequence along the circumferential direction C means that the centers of the first bumps 1710 in the pattern unit 171a are located on the same circumference.
  • the reflective electrode layer may be formed on the planarization layer 17 , that is, in the process of fabricating the array substrate, the planarization layer 17 may be fabricated first, and then the reflection electrode layer may be fabricated. 14 to 19 and 21, the reflective electrode layer may include a plurality of reflective electrodes 18 that are disconnected from each other. Each reflective electrode 18 is located in a sub-pixel region 101 and communicates with the sub-pixels through the first via hole 170.
  • the pixel circuit is electrically connected; for example, each reflective electrode 18 can be connected to the second electrode plate 122 of the storage capacitor 12 in a sub-pixel circuit through the first via 170, and it can also be understood that each reflective electrode 18 is connected to a sub-pixel circuit.
  • the drain 113 of the transistor 11 in the pixel circuit is connected.
  • the material of the reflective electrode 18 can be a composite material, that is, the reflective electrode 18 can be a composite structure, for example, the reflective electrode 18 can be made of ITO (indium tin oxide), Ag (silver), ITO (indium oxide tin) three-layer material composite, because Ag is easily oxidized, therefore, the Ag layer is sandwiched between two ITO layers, which can effectively prevent the Ag layer from being oxidized, thereby ensuring the performance of the reflective electrode 18, but not limited to this, the reflection
  • the electrode 18 can also be a single-layer structure, which can be selected from materials with good electrical conductivity and reflection properties, etc., depending on the specific situation.
  • the shape of the orthographic projection of the reflective electrode 18 on the first substrate 10 in the embodiment of the present disclosure may be the rectangular shape shown in FIG. 15 , but it is not limited thereto, and may also be other shapes.
  • the corner shown in FIG. 16 is Pattern design of cut corners, depending on the situation.
  • the planarization layer 17 has pattern units 171a in uneven shapes, the reflective electrode layer is subsequently fabricated, as shown in FIG.
  • the pattern units 171a have matching uneven shapes.
  • the design can improve the viewing angle and maintain the isotropic uniformity while reducing the cost.
  • planarization layer 17 in the embodiments of the present disclosure will be described in detail below with reference to the specific drawings.
  • each pattern unit 171a of the pattern portion 171 in the planarization layer 17 may be arranged continuously, wherein the entire pattern portion 171 may extend in the row direction X, as shown in FIG. 8 .
  • the orthographic projection of the pattern portion 171 on the first substrate 10 overlaps with the sub-pixel regions 101 in the same row.
  • Part of the second wiring area 103 therefore, when the orthographic projection of the pattern portion 171 on the first substrate 10 and the sub-pixel area 101 in the same row both overlap, the pattern portion 171 may also overlap with the adjacent sub-pixel area 101. There is an overlap between the second wiring regions 103 .
  • planarization layer 17 located in the display area in the embodiment of the present disclosure may further include a non-patterned portion 172 in addition to the aforementioned first via hole 170 and the patterned portion 171.
  • the pattern portion 172 may be located at least in the first wiring area 102 of the first substrate 10, and the non-pattern portion 172 may extend in the row direction X as a whole. It should be understood that the main portion of the non-pattern portion 172 is located in the first wiring area 102 , a small part may be located in the sub-pixel area 101 and the second wiring area 103 .
  • the non-patterned portion 172 mentioned in the embodiment of the present disclosure refers to a portion without through holes and grooves, that is to say, as shown in FIG. It should be understood that the plane of the non-patterned portion 172 away from the first substrate 10 may be located in the same plane as the top of the first bump 1710 or the second bump 1712 away from the first substrate 10, but not limited to this , the top of the first bump 1710 or the second bump 1712 away from the first substrate 10 may also be closer to the first substrate 10 than the plane of the non-patterned portion 172 away from the first substrate 10, depending on the specific situation .
  • each pattern portion 171 corresponds to a row of sub-pixel regions 101
  • the number of non-pattern portions 172 may be equal to the number of first wiring regions 102
  • each non-pattern portion 172 corresponds to a row of first wiring regions 102; That is to say, the pattern portion 171 and the non-pattern portion 172 in the embodiment of the present disclosure may be arranged to overlap in the column direction Y. As shown in FIG.
  • the pattern unit 171a in the pattern portion 171 that is in contact with the non-pattern portion 172 may be the entire pattern unit 171a or a part of the pattern unit 171a.
  • the planarization layer 17 in the embodiment of the present disclosure is not only located on the pixel circuit layer in the display area, but also on the GOA in the non-display area. As shown in FIG. 22 , the planarization layer 17 is located in the non-display area.
  • the entire surface away from the first substrate 10 may be flat, that is, the portion of the planarization layer 17 located in the non-display area may also be a non-patterned portion.
  • the orthographic pattern of the first bumps 1710 in the pattern unit 171a on the first substrate 10 may be a symmetrical pattern, so as to reduce the design difficulty, but not limited to this, the first bumps 1710 in the first
  • the orthographic pattern on a substrate 10 can also be an asymmetric pattern, depending on the circumstances.
  • the symmetrical pattern may include at least two symmetry axes, as shown in FIG.
  • the first symmetry axis a and the second symmetry axis b mentioned in the present disclosure are both perpendicular to the thickness direction Z of the array substrate.
  • the extending directions of the first symmetry axes a of two adjacent symmetrical patterns intersect, so that the design can effectively reduce the macroscopic Mura (brightness) while enabling the array substrate to achieve diffuse reflection. uneven) or streaks appear.
  • the extension directions of the first symmetry axes a of two adjacent symmetrical patterns are perpendicular to each other, so as to reduce the difficulty of design.
  • the pattern unit 171 a of the embodiment of the present disclosure may include four first bumps 1710 , in the circumferential direction C of the pattern unit 171 a , in a symmetrical pattern of two adjacent first bumps 1710
  • the first symmetry axis a of one can be collinear with the second symmetry axis b of the other, so as to further reduce the design difficulty of the pattern unit 171a.
  • FIG. 10 the pattern unit 171 a of the embodiment of the present disclosure may include four first bumps 1710 , in the circumferential direction C of the pattern unit 171 a , in a symmetrical pattern of two adjacent first bumps 1710
  • the first symmetry axis a of one can be collinear with the second symmetry axis b of the other, so as to further reduce the design difficulty of the pattern unit 171a.
  • the first symmetry axis a of one of the symmetrical patterns of the adjacent two first bumps 1710 extends in the row direction X, and the other
  • the first symmetry axis a extends in the column direction Y to further reduce the design difficulty, but not limited to this, the first symmetry axis a can also extend in other directions intersecting the row direction X and the column direction Y, depending on the specific situation Certainly.
  • the number of the first bumps 1710 in the pattern unit 171a is not limited to the aforementioned four, and may also be six, eight, and so on.
  • the symmetry axes of the symmetry pattern of the first bumps 1710 may only include two, namely: the aforementioned first symmetry axis a and the second symmetry axis b.
  • the entire symmetrical pattern can be or approximate a rhombus as shown in FIG. 9 , an octagon as shown in FIG. 11 or an ellipse as shown in FIG. 12 , but it is not limited thereto, and can also be a rectangle or the like shape.
  • the outer contour of the orthographic projection of the spacing grooves 1711 surrounding the first bumps 1710 on the first substrate 10 can also be similar to a rhombus
  • the orthographic pattern of the second bump 1712 located in the center of the pattern unit 171a on the first substrate 10 may be a parallelogram; as shown in FIG.
  • the outer contour of the orthographic projection of the spacing groove 1711 surrounding the first bump 1710 on the first substrate 10 can also be similar to an octagon, and the second bump 1712 located in the center of the pattern unit 171 a is on the first substrate 10 . As shown in FIG.
  • the second bump 1712 located in the center of the pattern unit 171a on the first substrate 10
  • the orthographic pattern can be a circle or an ellipse, and the shape of the orthographic projection of the spacer grooves 1711 surrounding the first bump 1710 on the first substrate 10 can be based on the shapes of the first bump 1710 , the second bump 1712 and the Depends on the arrangement.
  • the ratio of the length L1 of the first symmetry axis a of the symmetry pattern of the first bumps 1710 to the length L2 of the second symmetry axis b of the first bumps 1710 may be 1.5 to 2.5, for example: 1.5, 2, 2.5, etc. This design can reduce the design difficulty while improving the diffuse reflection of the product.
  • the length L2 of the second symmetry axis b may be 6 ⁇ m to 10 ⁇ m, such as 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc.
  • the length L1 of the first symmetry axis a may be 9 ⁇ m to 25 ⁇ m, such as: 9 ⁇ m , 13 ⁇ m, 17 ⁇ m, 25 ⁇ m, etc., in order to improve the diffuse reflection of the product, but also reduce the design difficulty, but not limited to this, the first symmetry axis a and the second symmetry axis b can also be within other value ranges, depending on Depends on the specific situation.
  • the minimum distance between two adjacent first bumps 1710 in the circumferential direction C of the pattern unit 171 a is the first distance S1
  • the second distance S1 in the pattern unit 171 a is the second distance S2; wherein, the ratio between the first distance S1 and the second distance S2 may be 1 to 1.5, for example: 1, 1.1, 1.2, 1.3 , 1.4, 1.5, etc., this design can reduce the design difficulty while improving the diffuse reflection of the product.
  • the second spacing S2 can be 1.5 ⁇ m to 5 ⁇ m, such as: 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, etc.; and the first spacing S1 can be 1.5 ⁇ m to 7 ⁇ m , for example: 1.5 ⁇ m, 2.5 ⁇ m, 3.5 ⁇ m, 4.5 ⁇ m, 5.5 ⁇ m, 6.5 ⁇ m, 7 ⁇ m, etc., in order to improve the diffuse reflection of the product, but also reduce the design difficulty, but not limited to this, the first spacing S1 and The second distance S2 may also be in other value ranges, depending on the specific situation.
  • the first bump 1710 of the embodiment of the present disclosure is The symmetrical pattern can be a rhombus, the length L1 of the first symmetry axis a of the diamond-shaped symmetrical pattern can be approximately equal to 15.7 ⁇ m, and the length L2 of the second symmetry axis b can be approximately equal to 9 ⁇ m, that is: the length of the first symmetry axis a
  • the ratio of L1 to the length L2 of the second axis of symmetry b is about 1.74; the aforementioned first spacing S1 may be approximately equal to 5.4 ⁇ m, and the second spacing S2 may be approximately equal to 4 ⁇ m, namely: the first spacing S1 and the second spacing The ratio of S2 is about 1.35.
  • the pattern unit 171 a is the smallest repeating unit, and the pattern unit 171 a may include four first bumps 1710 with symmetrical patterns in the shape of a rhombus, on the circumferential direction C of the pattern unit 171 a , one of the two adjacent first bumps 1710 is rotated 90° compared to the other, that is to say, the four first bumps 1710 in the pattern unit 171a can be arranged in a pinwheel shape, wherein a plurality of these The smallest repeating units are densely packed in the row direction X and the column direction Y. As shown in FIG.
  • the first bump 1710 and the second bump 1712 are arranged overlappingly, so that the spacing grooves 1711 on the same side of the first bump 1710 and the second bump 1712 are in the shape of a snake as a whole, that is, non-linear.
  • This design is compared to the regular arrangement shown in FIG. 13 .
  • the spacing grooves 1711 located on the same side of the first bump 1710 and the second bump 1712 in the oblique direction are overall linear, which can alleviate the situation that the light passes through the structure at the spacing groove 1711 to form a fixed phase difference, that is, , to alleviate the interference fringes.
  • the pattern unit 171a includes four first bumps 1710 with a symmetrical pattern in the shape of a rhombus and a second bump 1712 located in the center of the pattern unit 171a, and the spacing between the bumps adopts a fixed size
  • the advantages of design (for example, refer to the content of the first spacing S1 and the second spacing S2 mentioned above), compared with the scheme of random arrangement, it can ensure that the topography of the pattern unit 171a meets the requirements and alleviates the In some cases, the slope angle of the bump is too large and the reflectivity of the reflective electrode 18 is low.
  • optical design of the reflection model of the present disclosure is disclosed as follows:
  • the embodiment of the present disclosure needs to ensure that the light source is reflected at 0°.
  • the slopes of the bumps ie, the first bump 1710 and the second bump 1712 ) can be calculated according to the laws of reflection and refraction.
  • angle ⁇ specifically:
  • n1 is the refractive index of the liquid crystal panel, specifically, the upper polarizer, glass substrate, color filter layer and liquid crystal layer are regarded as one
  • the slope angle ⁇ of the first bump 1710 and the second bump 1712 can be controlled within a range of 9.5° to 10°.
  • the first bump 1710 and The slope angle ⁇ of the second bump 1712 is controlled at 6° to 13°, such as 6°, 7°, 8°, 9°, 10°, 11°, 12°, 13°, etc.°.
  • the thickness H1 of the planarization layer 17 may be greater than or equal to 1 ⁇ m, that is, the groove bottom of the spacing groove 1711 and the second electrode plate 122 are far away from the second electrode plate 122 .
  • the minimum distance H1 between one side of the substrate 10 can be greater than or equal to 1 ⁇ m, which can reduce the coupling capacitance between the reflective electrode 18 and the second electrode plate 122 or the data line 14 , thereby reducing the flicker phenomenon.
  • the first via hole 170 of the planarization layer 17 is coincident with the spacing groove 1711 or the distance is relatively close, the first via hole 170 actually formed will be too large and a relatively large via hole 170 will be formed around the periphery. In the deep pit area, it is easy to cause the residual PI (alignment liquid) to cause a high risk of small black spots.
  • the first via 170 on the planarization layer 17 is The distance H2 from the spacer groove 1711 can be designed to be greater than or equal to 5 ⁇ m, as shown in FIG. 9 , so as to effectively avoid the risk of small black spots.
  • the array substrate of the embodiment of the present disclosure may further include an alignment film (not shown in the figure), and the alignment film may be located on the reflective electrode layer away from the first substrate 10 . side.
  • the manufacturing method of the array substrate described in the foregoing specific embodiment of the present disclosure may be as follows:
  • the active film layer can be deposited first, and then etched and cleaned after exposure through a Mask (mask) to form the aforementioned active layer 110 with a U-shaped design in a specific area, as shown in FIG. 2 ; wherein , the first end of the first active portion 1101 in the U-shaped active layer 110 may be the connection end of the source electrode 112 , and the first end of the second active portion 1102 may be the connection end of the drain electrode 113 .
  • a Mask mask
  • the gate insulating layer 15 and the first metal layer are deposited in sequence, and then the first metal layer is etched and cleaned after mask exposure, so as to form the gate line 13 in an in-line design as shown in FIG.
  • a first electrode plate 121 in the shape of a second electrode and a common line 19 connecting two adjacent first electrode plates 121 in the row direction X, and doping at a specific position around the gate line 13 is used to form an N-type thin film transistor, wherein the gate The portion of the line 13 located between the doped regions can be formed as the gate 111 of the transistor 11 , as shown in FIG. 4 .
  • the interlayer dielectric layer 16 is deposited.
  • a second metal layer is deposited, etched and cleaned after mask exposure to form the aforementioned data line 14 and the second electrode plate 122 shown in FIG. 6 , wherein, as shown in FIG. 7 , the data line The part of 14 is connected to the first end of the first active part 1101 through the second via hole 160, and the part of the second electrode plate 122 is connected to the first end of the second active part 1102 through the third via hole 161, wherein,
  • the portion of the data line 14 corresponding to the first end of the first active layer 110 may be defined as the source electrode 112 of the transistor 11
  • the portion of the second electrode plate 122 corresponding to the second end of the second active layer 110 It can be defined as the drain 113 of the transistor 11 .
  • the optical resin layer is deposited, and after mask exposure, etching and cleaning are performed to form the aforementioned planarization layer 17, as shown in FIG. 8 and FIG. 9 .
  • the optical resin is a positive adhesive
  • the mask used in forming the planarization layer 17 can be an HTM (semi-transparent) mask, and the HTM mask includes three transmittances
  • the regions are respectively a first region for fabricating the first via hole 170 , a second region for fabricating the pattern portion 171 , and a third region for fabricating the non-pattern portion 172 .
  • the transmittance of the first area in the HTM mask is 100% to ensure the formation of the first via hole 170;
  • the transmittance of the second area in the HTM mask is The pass rate is less than 100% and greater than 0.
  • the transmittance of the second region can be 20%, but it is not limited to this, it can be determined according to the specific situation, as long as effective spacing grooves 1711 can be formed to form the aforementioned pattern Part 171 is enough;
  • the transmittance of the third area in the HTM mask is 0, that is, the third area is a non-transmissive area;
  • the third metal layer is deposited, etched and cleaned after mask exposure, to form the square reflective electrode 18 mentioned above, the reflective electrode 18 is connected to the second electrode plate 122 through the first via 170, As shown in FIG. 11; wherein, the reflective electrode 18 can be understood as the pixel electrode in the product.
  • An embodiment of the present disclosure further provides a display panel, wherein the display panel includes the array substrate described in any of the foregoing embodiments, which will not be repeated here.
  • the display panel of the embodiment of the present disclosure may be a liquid crystal display panel, which, in addition to the aforementioned array substrate, may further include an opposite substrate arranged in a cell-to-cell manner with the array substrate, and may further include an opposite substrate located between the opposite substrate and the array substrate. Liquid crystal molecules between substrates (not shown in the figure).
  • the opposite substrate includes a second substrate 22 and a spacer 20 on a side of the second substrate 22 close to the array substrate.
  • the spacer 20 is located at The orthographic projection on the first substrate 10 overlaps with the overlapping portion of the first wiring area 102 and the second wiring area 103, so that the design can ensure the aperture ratio and avoid the spacer 20 during the stress test process. Slide out of the occluded area, which can improve the problem of poor light leakage in the dark state.
  • the second substrate 22 in the embodiment of the present disclosure may be a glass substrate, but not limited thereto, and may also be other transparent structures.
  • the number of spacers 20 in the opposite substrate may be set in multiples, and the plurality of spacers 20 may include main spacers and auxiliary spacers, and both of the main spacers and auxiliary spacers are multiple, And evenly distributed in the display panel, the number of main spacers is much smaller than the number of auxiliary spacers.
  • the surface of the main spacer away from the second substrate 22 can be in contact with the array substrate to play a main supporting role; while the auxiliary spacer is not received by the display panel. Under external pressure, there is a gap between the surface of the main spacer away from the second substrate 22 and the array substrate, as shown in FIG.
  • the display panel 8 that is, the surface of the main spacer away from the second substrate 22 and the auxiliary spacer away from the first spacer
  • the thickness of the display panel can be fine-tuned by adjusting the step difference between the main spacer and the auxiliary spacer; wherein, when the display panel is subjected to external pressure, the main spacer first Under all pressure and compression, when the main spacer is compressed to the point where the step difference between the main spacer and the auxiliary spacer is reduced to 0, the main spacer and the auxiliary spacer jointly bear the external pressure.
  • a part of the spacers 20 may be located in the display area of the display panel, and the other part may be located in the non-display area of the display panel.
  • the orthographic projection of the surface of the spacer 20 in the display area close to the array substrate on the first substrate 10 can be located in the non-patterned portion 172 of the planarization layer 17 In the orthographic projection on the first substrate 10 , it is ensured that the structure and thickness of the film layer at the supporting position of the spacer 20 are substantially consistent.
  • the pattern unit 171a should avoid the surface of the spacer close to the array substrate.
  • the distance H3 As shown in Figure 18) is greater than or equal to 5 ⁇ m to ensure the consistency of the cell thickness between the display area and the non-display area during the pressure or drop test process, so as to avoid image quality problems related to wireframe Mura.
  • the opposite substrate may further include a blocking layer 21 (ie: black matrix BM) located between the spacer 20 and the second substrate 22 , that is, a black matrix BM.
  • a blocking layer 21 ie: black matrix BM located between the spacer 20 and the second substrate 22 , that is, a black matrix BM.
  • the blocking layer 21 can be fabricated on the second substrate 22 first, and then the spacer 20 can be fabricated.
  • the shielding layer 21 is provided with a plurality of opening areas 210 arranged in an array, and the orthographic projection of each opening area 210 on the first substrate 10 is located in a sub-pixel area 101, and is located in the reflective electrode 18 and the pattern
  • the pattern units 171a of the pattern portion 171 are continuously arranged, it can be seen that the pattern units 171a can fill the opening area 210 as much as possible, so that the reflective electrode 18 has uneven shapes.
  • the portion of the opening area 210 is filled as much as possible, so as to ensure the reflection effect.
  • the shielding layer 21 in the embodiment of the present disclosure is the shielding area 211 except for the opening area 210 mentioned above, and the orthographic projection of the shielding area 211 on the first substrate 10 should cover the transistor 11, the first An orthographic projection of the via hole 170 , the data line 14 , the gate line 13 and the spacer 20 on the first substrate 10 , namely: the transistor 11 , the first via hole 170 , the data line 14 , the gate line 13 , and the spacer
  • the orthographic projection of 20 on the first substrate 10 is located within the orthographic projection of the shielding region 211 on the first substrate 10, wherein the shielding region 211 may also cover part of the structure of the storage capacitor 12 and part of the structure of the reflective electrode 18; That is to say, the orthographic projection of the shielding region 211 on the first substrate 10 can cover the entire first wiring region 102 , the second wiring region 103 and part of the sub-pixel region 101 . It should be noted that the shielding region 211 can also cover non- display area.
  • the opposite substrate may further include a color filter layer, a protective film layer 24 and a common electrode layer 25 , wherein,
  • the color filter layer can be located between the spacer 20 and the second substrate 22 , that is, when fabricating the opposite substrate, the color filter layer can be fabricated on the second substrate 22 first, and then the spacer 20 can be fabricated ; More specifically, when fabricating the opposite substrate, the blocking layer 21 may be fabricated on the second substrate 22 first, the color filter layer may then be fabricated, and then the spacer 20 may be fabricated.
  • the color filter layer may include a plurality of filter blocks 23, and the plurality of filter blocks 23 include, for example, red (R), green (G), and blue (B) filter blocks 23, at least part of the filter blocks 23 in the opening area 210 .
  • each opening area 210 may also be provided with three filter blocks 23 respectively.
  • 210 corresponds to a filter block 23 set.
  • the protective film layer 24 can be located on the side of the color filter layer and the blocking layer 21 away from the second substrate 22, and located on the side of the spacer 20 close to the second substrate 22, that is, when fabricating the opposite substrate,
  • the blocking layer 21 and the color filter layer can be sequentially formed on the second substrate 22, and then the protective film layer 24 can be formed, and then the spacer 20 can be formed; wherein, the protective film layer 24 can cover the color filter layer and the blocking layer 21. , to protect the color filter layer and the blocking layer 21 .
  • the material of the protective film layer 24 may be optical resin glue, but it is not limited thereto, and may also be other materials, depending on the specific situation.
  • the common electrode layer 25 can be located between the protective film layer 24 and the spacer 20 , that is to say, when fabricating the opposite substrate, the shielding layer 21 , the color filter layer and the protection film can be fabricated in sequence on the second substrate 22 first. layer 24, and then the common electrode layer 25 is formed, and then the spacer 20 is formed.
  • the common electrode layer 25 is configured to apply a reference voltage, and the liquid crystal molecules can be driven to deflect under the action of the common electrode layer 25 and the reflective electrode 18 .
  • the common electrode layer 25 can be a transparent electrode layer, and the material of the common electrode layer 25 can be ITO or the like, but is not limited thereto, and can also be other conductive materials.
  • the opposite substrate may further include an alignment film, and the alignment film may be fabricated after the spacers 20 are fabricated, but not limited to this, and may also be fabricated after fabrication of the common electrode layer 25 and The spacer 20 was previously fabricated, as the case may be.
  • the opposite substrate in the embodiment of the present disclosure may not be provided with a color filter layer, and the color filter layer may be located in the array substrate.
  • An embodiment of the present disclosure also provides an electronic device, which includes the display panel described in any of the foregoing embodiments.
  • the electronic device of the embodiment of the present disclosure adopts the RLCD technology.
  • the electronic device may also include other components and components, such as polarizers, batteries, motherboards, housings, etc. The usage requirements are supplemented accordingly, which will not be repeated here.
  • the specific type of the electronic device is not particularly limited, and any type of electronic device commonly used in the art can be used, such as electronic tags, e-books, smart wearable devices, smart retail devices, and so on. Personnel can make corresponding selections according to the specific use of the electronic device, which will not be repeated here.

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Abstract

一种阵列基板、显示面板及电子设备。阵列基板包括：第一衬底(10)，具有多个沿行方向(X)和列方向(Y)阵列排布的子像素区(101)；像素电路层，形成在第一衬底(10)上，像素电路层包括多个子像素电路，子像素电路的至少部分位于子像素区(101)；平坦化层(17)，形成在像素电路层上，平坦化层(17)设有位于子像素区(101)内的第一过孔(170)，且平坦化层(17)包括至少一个图案部(171)，图案部(171)包括多个且沿行方向(X)和列方向(Y)阵列排布的图案单元(171a)，图案单元(171a)呈凹凸不平状且至少位于子像素区(101)，其中，图案单元(171a)包括多个沿周向(C)依次排布的第一凸块(1710)及环绕各第一凸块(1710)的间隔槽(1711)，且在图案单元(171a)的周向(C)上相邻两第一凸块(1710)共用间隔槽(1711)的部分；反射电极层，形成在平坦化层(17)上，反射电极层包括多个相互断开的反射电极(18)，每个反射电极(18)位于一子像素区(101)内，并通过第一过孔(170)与子像素电路电连接，且反射电极(18)与图案单元(171a)相对应的部位呈与图案单元(171a)相匹配的凹凸不平状。提高反射效果的同时，降低成本。

Description

阵列基板、显示面板及电子设备 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板、显示面板及电子设备。
背景技术
目前，传统墨水型电子纸由于价格昂贵、色彩单一等技术瓶颈，逐渐不能满足市场需求，全反射型LCD(Liquid Crystal Display，液晶显示器)由于其低功耗、低成本、可实现多色等优点，在智能零售、电子标签、电子书等领域具有极大的市场潜力。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板、显示面板及电子设备，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开第一方面提供了一种阵列基板，其中，包括：
第一衬底，具有多个沿行方向和列方向阵列排布的子像素区；
像素电路层，形成在所述第一衬底上，所述像素电路层包括多个子像素电路，所述子像素电路的至少部分位于所述子像素区；
平坦化层，形成在所述像素电路层上，所述平坦化层设有位于所述子像素区内的第一过孔，且所述平坦化层包括至少一个图案部，所述图案部包括多个且沿所述行方向和所述列方向阵列排布的图案单元，所述图案单元呈凹凸不平状且至少位于所述子像素区，其中，所述图案单元包括多个沿周向依次排布的第一凸块及环绕各所述第一凸块的间隔槽，且在所述图案单元的周向上相邻两所述第一凸块共用所述间隔槽的部分；
反射电极层，形成在所述平坦化层上，所述反射电极层包括多个相互断开的反射电极，每个所述反射电极位于一所述子像素区内，并通过所述第一过孔与所述子像素电路电连接，且所述反射电极与所述图案单元相对应的部位呈与所述图案单元相匹配的凹凸不平状。
在本公开的一种示例性实施例中，所述第一凸块在所述第一衬底上的正投影图案为对称图案，且所述对称图案至少包括两条对称轴，分别为相互垂直的第一对称轴和第二对称轴，其中，所述第一对称轴的长度大于所述第二对称轴的长度，且所述第一对称轴和所述第二对称轴均与 所述阵列基板的厚度方向相互垂直。
在本公开的一种示例性实施例中，在所述图案单元的周向上，相邻两所述对称图案的第一对称轴的延伸方向相交。
在本公开的一种示例性实施例中，在所述图案单元的周向上，相邻两所述对称图案的第一对称轴的延伸方向相互垂直。
在本公开的一种示例性实施例中，所述图案单元包括四个所述第一凸块，在所述图案单元的周向上，相邻两所述第一凸块的对称图案中一者的第一对称轴与另一者的第二对称轴共线。
在本公开的一种示例性实施例中，在所述图案单元的周向上，相邻两所述第一凸块的对称图案中一者的第一对称轴在所述行方向上延伸，另一者的第一对称轴在所述列方向上延伸。
在本公开的一种示例性实施例中，所述对称图案的对称轴仅包括所述第一对称轴和所述第二对称轴。
在本公开的一种示例性实施例中，所述对称图案为菱形、长方形、椭圆形或八边形。
在本公开的一种示例性实施例中，所述对称图案的第一对称轴的长度与所述第一凸块的第二对称轴的长度之比为1.5至2.5。
在本公开的一种示例性实施例中，所述第二对称轴的长度为6μm至10μm。
在本公开的一种示例性实施例中，所述图案单元还包括第二凸块，位于各所述第一凸块所围成的中心区域内；
其中，所述图案单元中各所述间隔槽靠近所述第二凸块的部分沿所述周向依次首尾相连并环绕所述第二凸块。
在本公开的一种示例性实施例中，所述第一凸块和所述第二凸块的坡度角均为6°至13°。
在本公开的一种示例性实施例中，所述图案单元中在其周向上相邻两所述第一凸块之间的最小间距为第一间距，且所述图案单元中所述第二凸块与所述第一凸块之间的最小间距为第二间距；
其中，所述第一间距与所述第二间距之间的比值为1至1.5。
在本公开的一种示例性实施例中，所述第二间距为1.5μm至5μm。
在本公开的一种示例性实施例中，所述第一凸块的最大厚度与所述第二凸块的最大厚度相同。
在本公开的一种示例性实施例中，在所述间隔槽的位置处，所述平坦化层的厚度大于等于1μm。
在本公开的一种示例性实施例中，所述第一过孔与所述间隔槽之间的间距大于等于5μm。
在本公开的一种示例性实施例中，所述第一衬底还具有多行第一布线区和多列第二布线区，所述第一布线区与每行子像素区在所述列方向上交叠排布，所述第二布线区与每列子像素区在所述行方向上交替排布；
所述像素电路层还包括多行栅线和多列数据线，所述栅线位于所述第一布线区，所述数据线位于所述第二布线区，所述栅线和所述数据线分别与所述子像素电路电连接。
在本公开的一种示例性实施例中，所述子像素电路包括存储电容及晶体管；
所述存储电容位于所述子像素区，且所述存储电容包括在所述第一衬底的厚度方向上相对的第一电极板和第二电极板，所述第一电极板与所述栅线同层设置且相互断开，所述第二电极板与所述数据线同层设置且相互断开，所述第二电极板通过所述第一过孔与所述反射电极连接；
所述晶体管包括有源层、栅极、源极和漏极；所述有源层位于所述栅线靠近所述第一衬底的一侧，所述有源层包括位于所述第二布线区的第一有源部、与所述第一有源部在所述行方向上相对的第二有源部以及位于所述子像素区的第三有源部，所述第一有源部在所述第一衬底上的正投影与所述栅线在所述第一衬底上的正投影存在交叠，所述第一有源部的第一端位于所述栅线远离所述第三有源部的一侧，所述第一有源部的第二端和所述第三有源部的第一端连接，所述第二有源部的第一端和第二端分别位于在所述行方向上相邻两所述子像素区上，所述第二有源部的第一端位于所述栅线远离所述第三有源部的一侧，所述第二有源部的第二端与所述第三有源部的第二端连接；
其中，所述栅线中与所述第一有源部和所述第二有源部在所述第一衬底的厚度方向上存在交叠的部分构成所述晶体管的栅极，所述数据线中与所述第一有源部的第一端在所述第一衬底的厚度方向上存在交叠的部分构成所述晶体管的源极，所述源极与所述第一有源部的第一端通过第二过孔连接，所述第二电极板中与所述第二有源部的第一端在所述第一衬底的厚度方向上存在交叠的部分构成所述晶体管的漏极，所述漏极与所述第二有源部的第一端通过第三过孔连接。
在本公开的一种示例性实施例中，同行子像素电路中任意相邻两子像素电路的存储电容的第一电极板通过公共线连接，所述公共线与所述第一电极板同层设置。
在本公开的一种示例性实施例中，所述平坦化层还包括至少位于所述第一布线区的非图案部，所述非图案部在所述行方向上延伸，所述非图案部远离所述第一衬底的面为平面。
在本公开的一种示例性实施例中，所述图案部中各所述图案单元呈连续设置；
其中，所述图案部在所述行方向上延伸，所述图案部在所述第一衬底上的正投影与位于同一行的子像素区均存在交叠。
在本公开的一种示例性实施例中，所述图案部和所述非图案部均设置多个，且所述图案部与所述非图案部在所述列方向上交替排布。
本公开第二方面提供了一种显示面板，其中，包括上述任一项所述 的阵列基板和与所述阵列基板对盒设置的对置基板。
在本公开的一种示例性实施例中，所述对置基板包括第二衬底及位于所述第二衬底靠近所述阵列基板一侧的隔垫物，所述隔垫物在所述第一衬底上的正投影与所述第一布线区和所述第二布线区的交叠部分存在交叠，且所述隔垫物中靠近所述阵列基板的面在所述第一衬底上的正投影位于所述平坦化层的非图案部在所述第一衬底上的正投影内。
在本公开的一种示例性实施例中，所述隔垫物中靠近所述阵列基板的面与所述图案单元的间隔槽之间的间距大于等于5μm。
在本公开的一种示例性实施例中，所述对置基板还包括位于所述隔垫物与所述第二衬底之间的遮挡层，所述遮挡层上开设有多个阵列排布的开孔区，每个所述开孔区在所述第一衬底上的正投影位于一所述子像素区内，并位于所述反射电极和所述图案部在所述第一衬底上的正投影内。
在本公开的一种示例性实施例中，所述对置基板还包括：
彩膜层，位于所述隔垫物与所述第二衬底之间，所述彩膜层包括多个滤光块，所述滤光块的至少部分位于所述开孔区；
保护膜层，位于所述彩膜层和所述遮挡层远离所述第二衬底的一侧，并位于所述隔垫物靠近所述第二衬底的一侧，所述保护膜层覆盖所述彩膜层和所述遮挡层；
公共电极层，位于所述保护膜层与所述隔垫物之间。
本公开第三方面提供了一种电子设备，其中，包括上述任一项所述的显示面板。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施例所述的阵列基板中第一衬底的显示区中各区域分布示意图；
图2示出了在图1所示的第一衬底上形成有源层的结构示意图；
图3示出了在图2所示的第一衬底上形成栅线、第一电极板和公共线的结构示意图；
图4示出了图3中所示的A部的放大结构示意图；
图5示出了在图3所示的第一衬底上形成第二过孔和第三过孔的结构示意图；
图6示出了在图5所示的第一衬底上形成数据线、第二电极板的结构示意图；
图7示出了图6中所示的晶体管处的放大结构示意图；
图8示出了在图6所示的第一衬底上形成平坦化层的结构示意图；
图9示出了本公开一实施例所述的平坦化层的结构示意图；
图10示出了图9中所示出的平坦化层的最小重复图案单元的结构示意图；
图11示出了本公开另一实施例所述的平坦化层中图案部的结构示意图；
图12示出了本公开又一实施例所述的平坦化层中图案部的结构示意图；
图13示出了相关技术中所述的平坦化层中图案部的结构示意图；
图14示出了在图8所示的第一衬底上形成反射电极的结构示意图；
图15示出了图14中所示的结构中反射电极的结构示意图；
图16示出了本公开另一实施例所示的反射电极的结构示意图；
图17示出了本公开一实施例所示的阵列基板与隔垫物之间的位置关系示意图；
图18示出了本公开一实施例所示的平坦化层与隔垫物之间的位置关系示意图；
图19示出了本公开一实施例所述的显示面板的结构示意图；
图20示出了图19所示出的遮挡层的结构示意图；
图21示出了沿图19所示出的M-M’方向的截面示意图；
图22示出了本公开实施例所示的部分GOA区域的截面示意图；
图23示出了本公开实施例所示的折射反射原理图。
附图标记：
10、第一衬底；10a、玻璃层；10b、缓冲层；101、子像素区；102、第一布线区；103、第二布线区；
11、晶体管；110、有源层；1101、第一有源部；1102、第二有源部；1103、第三有源部；111、栅极；112、源极；113、漏极；12、存储电容；121、第一电极板；122、第二电极板；13、栅线；14、数据线；15、栅绝缘层；16、层间介质层；160、第二过孔；161、第三过孔；17、平坦化层；170、第一过孔；171、图案部；171a、图案单元；1710、第一凸块；1711、间隔槽；1712、第二凸块；172、非图案部；18、反射电极；19、公共线；20、隔垫物；21、遮挡层；210、开孔区；211、遮挡区；22、第二衬底；23、滤光块；24、保护膜层；25、公共电极层。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。
本公开中使用的“包括”或者“具有”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
目前，反射式显示技术(简称：RLCD技术)在户外及健康显示领域具有极高应用前景；RLCD技术在无需背光的情况下，可以直接通过反射环境光替代屏幕光源，因此在低蓝光护眼、超低功耗、机身轻薄等方面具有显著优势。
基于此，本公开实施例提供一种阵列基板，此阵列基板可应用于反射式显示技术领域。具体地，如图1至图8所示，此阵列基板可包括第一衬底10、像素电路层、平坦化层17及反射电极层，其中：
第一衬底10可为单层结构，举例而言，此第一衬底10可为玻璃衬底，但不限于此，也可为PI(聚酰亚胺)衬底等等。需要说明的是，此第一衬底10不限于为单层结构，其还可为多层复合结构，举例而言，如图21和图22可知，此第一衬底10可包括玻璃层10a和位于玻璃层10a上的缓冲层10b，此缓冲层10b可为无机绝缘层，比如：氧化硅、氮化硅、氮氧化硅等等，应当理解的是，在第一衬底10为多层复合结构时，不限于包括前述提到的玻璃层10a和缓冲层10b，也可包括其他层等等，视具体情况而定。
在本公开的实施例，此第一衬底10可包括显示区和环绕显示区设置的非显示区。其中，如图1所示，显示区可具有多个沿行方向X和列方向Y阵列排布的子像素区101、多行第一布线区102和多列第二布线区103，其中，第一布线区102与每行子像素区101在列方向Y上交替排布，第二布线区103与每列子像素区101在行方向X上交叠排布。非显示区可包括GOA(即：栅极驱动电路)区、绑定区等等。
像素电路层可形成在第一衬底10上，举例而言，在第一衬底10包括玻璃层10a和缓冲层10b时，此像素电路层可位于缓冲层10b远离玻 璃层10a的一侧。此像素电路层可包括多行栅线13、多列数据线14及多个子像素电路，栅线13和数据线14分别与子像素电路电连接，结合图1至图7所示。
在本公开的实施例中，栅线13可在行方向X上延伸，且位于第一布线区102；举例而言，如图3所示，每行第一布线区102可设置一行栅线13，但不限于此，位于相邻两行子像素区101之间的第一布线区102也可设置两行栅线13，视具体情况而定。
数据线14在列方向Y上延伸，且位于第二布线区103；举例而言，如图6所示，每列第二布线区103可设置一列数据线14，但不限于此，位于相邻两列子像素区101之间的第二布线区103也可设置两列数据线14，视具体情况而定。
子像素电路的至少部分位于子像素区101；举例而言，子像素电路的个数可与子像素区101的个数相等，其中，每个子像素电路的至少部分位于一子像素区101。
在每行第一布线区102设置一行栅线13，每列第二布线区103设置一列数据线14时，每行栅线13可与同一行子像素电路电连接，每列数据线14可与同一列子像素电路电连接。
本公开实施例中，如图6所示，每列数据线14和每行栅线13在第一衬底10上的正投影形状分别可类似为一字型，但不限于此，也可为其他形状，视具体情况而定。
举例而言，栅线13的材质可为铜(Cu)、银(Ag)、铝(Al)、钼(Mo)、铬(Cr)、钛(Ti)等金属或合金，但不限于此；而数据线14的材质可为复合材质，即：数据线14可为复合结构，比如：数据线14可由依次堆叠的钛(Ti)、铝(Al)、钛(Ti)三层材质复合而成，由于铝容易氧化，因此，将铝层夹在两层钛层之间，可有效防止铝层氧化，从而可保证数据线14的性能，但不限于此，数据线14除了为Ti/Al/Ti夹层结构，也可为单层结构，其可选用具有良好导电性的材质等等，视具体情况而定。
应当理解的是，本公开实施例数据线14与栅线13位于不同层，具体地，数据线14可位于栅线13远离第一衬底10的一侧，也就是说，在制作阵列基板时，可先制作栅线13，然后再制作数据线14；其中，为了避免数据线14与栅线13直接接触，结合图19及图21可知，此数据线14与栅线13之间夹有层间介质层16，举例而言，此层间介质层16可为无机绝缘层，比如：氧化硅、氮化硅、氮氧化硅等等。
需要说明的是，层间介质层16在阵列基板中为整面设置，也就是说，层间介质层16在第一衬底10上的正投影除了覆盖栅线13在第一衬底10上的正投影之外，还可覆盖位于第一衬底10上的其他结构，例如：后文提到的有源层110、第一电极板121等等结构。此外，还应当说明的是，此层间介质层16不仅位于显示区，也可位于非显示区，如图21 和图22所示。
子像素电路可包括存储电容12及晶体管11；其中，存储电容12位于子像素区101，结合图3至图7及图21所示，此存储电容12包括在第一衬底10的厚度方向Z上相对的第一电极板121和第二电极板122，举例而言，如图3所示，第一电极板121可与栅线13同层设置且相互断开，第二电极板122可与数据线14同层设置且相互断开，这样可在满足性能要求时，减少加工步骤、降低成本及减薄阵列基板的厚度。
需要说明的是，存储电容12的第一电极板121可被配置为施加参考电压，其中，如图3所示，同行子像素电路中任意相邻两子像素电路的存储电容12的第一电极板121通过公共线19连接，此公共线19与第一电极板121同层设置。
应该理解的是，在本公开中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩膜版通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩膜版(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。从而简化制作工艺，节省制作成本，提高生产效率。
结合图2至图7所示，晶体管11可包括有源层110、栅极111、源极112和漏极113；举例而言，此晶体管11可为顶栅型，即：有源层110可位于栅线13靠近第一衬底10的一侧，也就是说，在制作阵列基板时，可先制作有源层110，然后再制作栅线13；但不限于此，晶体管11也可为底栅型，即：在制作阵列基板时，可先制作栅线13，然后在制作有源层110。
需要说明的是，如图21所示，在晶体管11为顶栅型时，有源层110与栅极111之间夹有栅绝缘层15，举例而言，此栅绝缘层15可为无机绝缘层，比如：氧化硅、氮化硅、氮氧化硅等等。此栅绝缘层15在阵列基板中为整面设置，此栅绝缘层15位于层间介质层16靠近第一衬底10的一侧，且栅绝缘层15在第一衬底10上的正投影可覆盖有源层110在第一衬底10上的正投影。此外，还应当说明的是，此栅绝缘层15不仅位于显示区，也可位于非显示区。
在本公开实施例中，有源层110可为低温多晶硅(简称：LTPS)，但不限于此，也可为非晶硅(简称：a-Si)，铟镓锌氧化物(简称：IGZO)等等，视具体情况而定。需要说明的是，本公开主要以有源层110为低温多晶硅为例进行说明。
其中，如图2所示，有源层110在第一衬底10上的正投影形状可类似为U型，具体地，有源层110可包括位于第二布线区103的第一有源部1101、与第一有源部1101在行方向X上相对的第二有源部1102以及至少位于子像素区101的第三有源部1103。
需要说明的是，第一有源部1101和第二有源部1102分别在列方向Y上延伸，第三有源层110在行方向X上延伸，此第一有源部1101、第二有源部1102及第三有源部1103均具有在其延伸方向上相对的第一端和第二端。
如图3所示，第一有源部1101在第一衬底10上的正投影与栅线13在第一衬底10上的正投影存在交叠，第一有源部1101的第一端位于栅线13远离第三有源部1103的一侧，第一有源部1101的第二端和第三有源部1103的第一端连接；第二有源部1102的第一端和第二端分别位于在行方向X上相邻两子像素区101上，也就是说，第二有源部1102在第一衬底10上的正投影与栅线13在第一衬底10上的正投影存在交叠，此晶体管11可为双栅型，以保证晶体管11的性能。其中，第二有源部1102的第一端位于栅线13远离第三有源部1103的一侧，第二有源部1102的第二端与第三有源部1103的第二端连接。
在本公开的实施例中，结合图3和图4可知，栅线13中与第一有源部1101和第二有源部1102在第一衬底10的厚度方向Z上存在交叠的部分构成晶体管11的栅极111；结合图6和图7可知，数据线14中与第一有源部1101的第一端在第一衬底10的厚度方向Z上存在交叠的部分构成晶体管11的源极112，源极112与第一有源部1101的第一端通过第二过孔160连接，第二电极板122中与第二有源部1102的第一端在第一衬底10的厚度方向Z上存在交叠的部分构成晶体管11的漏极113，漏极113与第二有源部1102的第一端通过第三过孔161连接。
应当理解的是，本公开中提到的第二过孔160和第三过孔161可贯穿层间介质层16和栅绝缘层15，并分别露出第一有源部1101的第一端和第二有源部1102的第一端。
举例而言，本公开实施例的晶体管11可为N型，但不限于此，也可为P型，视具体情况而定。
结合图2至图4可知，本公开实施例的第一有源部1101的第一端相比于第二有源部1102的第一端可更加远离栅线13，也就是说，第一有源部1101在列方向Y上的尺寸可大于第二有源部1102在列方向Y上的尺寸；但不限于此，也可第一有源部1101在列方向Y上的尺寸等于或小于第二有源部1102在列方向Y上的尺寸，视具体情况而定。
在本公开的实施例中，栅线13可从GOA引出用来控制整行的子像素电路的晶体管11开关，并结合数据线14共同完成像素的充电和放电。需要说明的是，此GOA可集中在阵列基板上，此GOA可理解为阵列基板中位于非显示区的电路结构，而像素电路层可理解为阵列基板中位于显示区的电路结构。
其中，GOA可包括如图22所示的晶体管TFT，此GOA的晶体管结构与子像素电路的晶体管11结构不相同，但不限于此，子像素电路的晶体管11结构也可与GOA的晶体管结构相同，视具体情况而定。此外， GOA电容中也可包括存储电容等。
结合图8至图10，平坦化层17可形成在像素电路层上，但不限于此，也可位于GOA上，换言之，平坦化层17即可位于显示区，又可位于非显示区。举例而言，平坦化层17的材质可为光学树脂等有机材质，但不限于此，视具体情况而定。此外，平坦化层17可为单层结构，但不限于此，也可为多层复合结构，视具体情况而定。
在本公开的实施例中，结合图8至图9所示，平坦化层17可设有位于子像素区101内的第一过孔170，此第一过孔170可露出第二电极板122的部分，换言之，第一过孔170在第一衬底10上的正投影可位于第二电极板122在第一衬底10上的正投影内。
需要说明的是，如图8和9所示，平坦化层17中第一过孔170的数量为多个，第一过孔170的数量与子像素区101的数量相等，每个第一过孔170对应位于一子像素区101内，且每个第一过孔170在子像素区101内的位置可相同，换言之，同行第一过孔170中任意相邻两第一过孔170在行方向X上的间距相等，且同列第一过孔170中任意相邻两第二过孔160在列方向Y上的间距相等，以降低设计难度。
如图8和图9所示，平坦化层17还可包括至少一个图案部171，此图案部171位于显示区，且其可包括多个沿行方向X和列方向Y上阵列排布的图案单元171a，此图案单元171a呈凹凸不平状且至少可位于子像素区101，但不限于此，也可位于第一布线区102和第二布线区103中的至少一者，视具体情况而定。
在本公开的实施例中，如图10所示，呈凹凸不平状的图案单元171a可至少包括多个沿周向C依次排布的第一凸块1710及环绕各第一凸块1710的间隔槽1711，即：每个第一凸块1710周围均环绕有间隔槽1711，且在图案单元171a的周向上相邻两第一凸块1710共用间隔槽1711的部分。
此外，如图9和图10所示，图案单元171a还可包括第二凸块1712，此第二凸块1712位于各第一凸块1710所围成的中心区域内，其中，图案单元171a中各间隔槽1711靠近第二凸块1712的部分沿图案单元171a的周向C依次首尾相连并环绕第二凸块1712，也就是说，第二凸块1712与各第一凸块1710之间呈间隔设置。
需要说明的是，第一凸块1710和第二凸块1712远离第一衬底10的面可为弧面，但不限于此，也可为平面，视具体情况而定。其中，第一凸块1710的最大厚度可与第二凸块1712的最大厚度相同，以降低设计难度，但不限于此，第一凸块1710的最大厚度也可与第二凸块1712的最大厚度也可不相同，视具体情况而定。
举例而言，在图案单元171a中各第一凸块1710排布较密集时，也可不设置第二凸块1712，视具体情况而定。
在本公开的实施例中，第一凸块1710和第二凸块1712的厚度指的 是间隔槽的槽底至第一凸块1710远离第一衬底10的顶端和第二凸块1712远离第一衬底10的顶端之间的厚度。此外，前述提到的沿周向C依次排布的第一凸块1710指的是图案单元171a中各第一凸块1710的中心位于同一圆周上。
反射电极层可形成在平坦化层17上，即：在制作阵列基板的过程中，可先制作平坦化层17，然后再制作反射电极层。其中，结合图14至图19及21所示，反射电极层可包括多个相互断开的反射电极18，每个反射电极18位于一子像素区101内，并通过第一过孔170与子像素电路电连接；举例而言，每个反射电极18可通过第一过孔170与一子像素电路中存储电容12的第二电极板122连接，也可理解为每个反射电极18与一子像素电路中晶体管11的漏极113连接。
举例而言，此反射电极18的材质可为复合材质，即：反射电极18可为复合结构，比如：反射电极18可由依次堆叠的ITO(氧化铟锡)、Ag(银)、ITO(氧化铟锡)三层材质复合而成，由于Ag容易氧化，因此，将Ag层夹在两层ITO层之间，可有效防止Ag层氧化，从而可保证反射电极18的性能，但不限于此，反射电极18除了为ITO/Ag/ITO夹层结构，也可为单层结构，其可选用具有良好导电性和反射性能的材质等等，视具体情况而定。
此外，本公开实施例的反射电极18在第一衬底10上的正投影形状可为图15所示的矩形状，但不限于此，也可为其他形状，例如图16所示的拐角为切角的图案设计，视具体情况而定。
需要说明的是，由于平坦化层17具有呈凹凸不平状的图案单元171a，因此，在后续制作反射电极层，如图21所示，可使反射电极18与图案单元171a相对应的部位呈与图案单元171a相匹配的凹凸不平状，这样设计相比于额外增加散热膜的方案，在提高视角并保持各向均一性的同时，还可降低成本。
下面可结合具体附图对本公开实施例的平坦化层17的结构进行详细说明。
在本公开的实施例中，如图9所示，平坦化层17中图案部171的各图案单元171a可呈连续设置，其中，图案部171整体可在行方向X上延伸，如图8所示，此图案部171在第一衬底10上的正投影与位于同一行的子像素区101均存在交叠，应当理解的是，由于在行方向X上相邻子像素区101之间具有部分第二布线区103，因此，本公开实施例的图案部171在第一衬底10上的正投影与同一行的子像素区101均存在交叠时，还可与相邻子像素区101之间的第二布线区103存在交叠。
需要说明的是，本公开实施例的位于显示区的平坦化层17除了前述提到的第一过孔170和图案部171之外还可包括非图案部172，如图9所示，此非图案部172可至少位于第一衬底10的第一布线区102，此非图案部172整体可在行方向X上延伸，应当理解的是，此非图案部172 的主要部分位于第一布线区102，少部分可位于子像素区101和第二布线区103。
其中，本公开实施例提到的非图案部172指的是未开设通孔和凹槽的部分，也就是说，如图21所示，非图案部172远离第一衬底10的面整体为平面，应当理解的是，此非图案部172远离第一衬底10的平面可与第一凸块1710或第二凸块1712远离第一衬底10的顶端位于同一平面内，但不限于此，第一凸块1710或第二凸块1712远离第一衬底10的顶端也可相比于非图案部172远离第一衬底10的平面更靠近第一衬底10，视具体情况而定。
在本公开的实施例中，如图9所示，平坦化层17的图案部171和非图案部172均可设置有多个，具体地，图案部171的数量可与子像素区101的行数相等，每个图案部171对应于一行子像素区101，非图案部172的数量可与第一布线区102的数量相等，每个非图案部172对应于一行第一布线区102；也就是说，本公开实施例的图案部171与非图案部172可在列方向Y上交叠排布。
需要说明的是，图案部171中与非图案部172相接触的图案单元171a可为整个图案单元171a，也可为图案单元171a的部分。
其中，本公开实施例的平坦化层17不仅位于显示区的像素电路层上，还可位于非显示区的GOA上，其中，如图22所示，平坦化层17位于非显示区的部位中远离第一衬底10的表面整体可为平面，即：平坦化层17位于非显示区的部位也可为非图案部。
在本公开的实施例中，图案单元171a中第一凸块1710在第一衬底10上的正投影图案可为对称图案，以降低设计难度，但不限于此，第一凸块1710在第一衬底10上的正投影图案也可为非对称图案，视具体情况而定。
可选地，当第一凸块1710在第一衬底10上的正投影图案为对称图案时，此对称图案可至少包括两条对称轴，如图10所示，分别为相互垂直的第一对称轴a和第二对称轴b，其中，第一对称轴a的长度可大于第二对称轴b的长度。需要说明的是，本公开提到的第一对称轴a和第二对称轴b均与阵列基板的厚度方向Z相互垂直。
进一步地，在图案单元171a的周向C上，相邻两对称图案的第一对称轴a的延伸方向相交，这样设计在使阵列基板能够实现漫反射的同时，还可有效缓解宏观Mura(亮度不均匀)或者条纹出现的情况。更进一步地，在图案单元171a的轴向上，相邻两对称图案的第一对称轴a的延伸方向相互垂直，以降低设计难度。
举例而言，如图10所示，本公开实施例的图案单元171a可包括四个第一凸块1710，在图案单元171a的周向C上，相邻两第一凸块1710的对称图案中一者的第一对称轴a可与另一者的第二对称轴b共线，以进一步降低图案单元171a的设计难度。具体地，如图10所示，在图案 单元171a的周向C上，相邻两第一凸块1710的对称图案中一者的第一对称轴a在行方向X上延伸，另一者的第一对称轴a在列方向Y上延伸，以进一步降低设计难度，但不限于此，第一对称轴a也可在与行方向X和列方向Y相交的其他方向上延伸，视具体情况而定。
应当理解的是，图案单元171a中第一凸块1710的数量不限于前述提到的四个，也可为六个、八个等等。
在本公开的实施例中，第一凸块1710的对称图案的对称轴可仅包括两个，即：前述提到的第一对称轴a和第二对称轴b。
举例而言，此对称图案整体可为或近似为如图9所示的菱形、如图11所示的八边形或如图12所示的椭圆形，但不限于此，也可为长方形等形状。
其中，如图10所示，在第一凸块1710的对称图案为菱形时，第一凸块1710外围环绕的间隔槽1711在第一衬底10上的正投影的外轮廓也可类似为菱形，且位于图案单元171a中心的第二凸块1712在第一衬底10上的正投影图案可为平行四边形；如图11所示，在第一凸块1710的对称图案为八边形时，第一凸块1710外围环绕的间隔槽1711在第一衬底10上的正投影的外轮廓也可类似为八边形，且位于图案单元171a中心的第二凸块1712在第一衬底10上的正投影图案可为八边形；如图12所示，在第一凸块1710的对称图案为椭圆形时，位于图案单元171a中心的第二凸块1712在第一衬底10上的正投影图案可为圆形或椭圆形，而第一凸块1710外围环绕的间隔槽1711在第一衬底10上的正投影形状可根据第一凸块1710、第二凸块1712的形状及排布方式而定。
在本公开的实施例中，如图10所示，第一凸块1710的对称图案的第一对称轴a的长度L1与第一凸块1710的第二对称轴b的长度L2之比可为1.5至2.5，比如：1.5、2、2.5等等，这样设计在提高产品漫反射的同时，还可降低设计难度。
举例而言，第二对称轴b的长度L2可为6μm至10μm，比如：6μm、7μm、8μm、9μm、10μm等等，而第一对称轴a的长度L1可为9μm至25μm，比如：9μm、13μm、17μm、25μm等等，以在提高产品漫反射的同时，还可降低设计难度，但不限于此，第一对称轴a和第二对称轴b也可在其他取值范围内，视具体情况而定。
在本公开的实施例中，如图10所示，图案单元171a中在其周向C上相邻两第一凸块1710之间的最小间距为第一间距S1，且图案单元171a中第二凸块1712与第一凸块1710之间的最小间距为第二间距S2；其中，第一间距S1与第二间距S2之间的比值可为1至1.5，比如：1、1.1、1.2、1.3、1.4、1.5等等，这样设计在提高产品漫反射的同时，还可降低设计难度。
举例而言，第二间距S2可为1.5μm至5μm，比如：1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等等；而第一间距 S1可为1.5μm至7μm，比如：1.5μm、2.5μm、3.5μm、4.5μm、5.5μm、6.5μm、7μm等等，以在提高产品漫反射的同时，还可降低设计难度，但不限于此，第一间距S1和第二间距S2也可在其他取值范围内，视具体情况而定。
在此阵列基板应用于10.5寸的RLCD XGA产品时，需要说明的是，分辨率为1024*768的液晶屏被称为XGA；如图10所示，本公开的实施例的第一凸块1710的对称图案可为菱形，此呈菱形的对称图案的第一对称轴a的长度L1可约等于15.7μm，第二对称轴b的长度L2可约等于9μm，即：第一对称轴a的长度L1与第二对称轴b的长度L2之比为约为1.74；前述提到的第一间距S1可约等于5.4μm，第二间距S2可约等于4μm，即：第一间距S1与第二间距S2之比为约为1.35。
在本公开的实施例中，如图10所示，图案单元171a为最小重复单元，此图案单元171a可包括四个对称图案呈菱形的第一凸块1710，在图案单元171a的周向C上，相邻两第一凸块1710中一者相比于另一者进行90°旋转，也就是说，图案单元171a中四个第一凸块1710可按照风车状进行排列，其中，多个此最小重复单元在行方向X和列方向Y上进行密排，如图9所示，在斜向(与行方向X和列方向Y相交的方向)上，第一凸块1710和第二凸块1712交叠排布，使得第一凸块1710和第二凸块1712中位于同一侧的间隔槽1711整体呈蛇形状，即：非直线型，这样设计相比于图13所示的规律排布的方案，即：在行方向X上相邻两第一凸块1710的第一对称轴a共线，在列方向Y上相邻两第一凸块1710的第二对称轴b共线，且在斜向上第一凸块1710和第二凸块1712中位于同一侧的间隔槽1711整体呈直线型的方案，可缓解光经过间隔槽1711处的结构而形成某固定的相位差的情况，即，缓解干涉条纹的情况。
在本公开的实施例中，图案单元171a包括四个对称图案呈菱形的第一凸块1710及位于图案单元171a找中心的第二凸块1712，且各凸块之间的间隔出采用固定尺寸设计(例如：可参考前述提到的第一间距S1和第二间距S2的内容)好处，这样相比于毫无规则的排列的方案，可保证图案单元171a各处的形貌符合要求，缓解部分凸块坡度角过大而导致反射电极18的反射率低的情况。
其中，下面公开了本公开方式的反射模型光学设计：
根据测试要求，本公开实施例需要保证光源呈0°反射出，为了实现这一目的，可根据反射及折射定律计算出凸块(即：第一凸块1710及第二凸块1712)的坡度角γ，具体地：
Sinα÷Sinβ＝n1÷n2，β＝arc sin(Sinα×n2÷n1)，其中，n1为液晶面板的折射率，具体为将上偏光片、玻璃衬底、彩膜层及液晶层看做一个整体等效出的折射率，n1≈1.5；n2为空气的折射率，此n1＝1.0；因此，在α为30°时，β≈19.4。此外，根据反射定律可知，如图23所示，β＝β1+β2，β2＝β1＝γ，因此可知，第一凸块1710及第二凸 块1712的坡度角γ≈β÷2＝9.7°。
基于前述可知，为了实现最佳反射率，可将第一凸块1710及第二凸块1712的坡度角γ控制在9.5°至10°的范围内，考虑到工艺波动，第一凸块1710及第二凸块1712的坡度角γ控制在6°至13°，比如：6°、7°、8°、9°、10°、11°、12°、13等等°。
在本公开的实施例中，如图21所示，在间隔槽1711的位置处，平坦化层17的厚度H1可大于等于1μm，即：间隔槽1711的槽底与第二电极板122远离第一衬底10的一侧之间的最小间距H1可大于等于1μm，这样可减小反射电极18与第二电极板122或数据线14之间的耦合电容，从而可缓解出现闪屏现象。
此外，在本公开的实施例中，若平坦化层17的第一过孔170与间隔槽1711重合或距离较近，会导致实际形成的第一过孔170过大并且在周边形成比较大的深坑区域，容易造成PI(配向液)残留而导致小黑点风险较高的情况，为了解决这一问题，且考虑到成膜工艺以及工艺波动，平坦化层17上的第一过孔170与间隔槽1711之间的间距H2可设计为大于等于5μm，如图9所示，以有效避免小黑点风险。
应当理解的是，本公开实施例的阵列基板除了包括前述提到的膜层之外，还可包括配向膜(图中未示出)，此配向膜可位于反射电极层远离第一衬底10的一侧。
其中，本公开前述一具体实施例所描述的阵列基板的制作方法可如下所示：
在玻璃层10a上沉积缓冲层10b以形成第一衬底10之后。
可先进行有源膜层沉积，然后通过Mask(掩膜)曝光后进行刻蚀和清洗，以在特定区域形成前述提到的呈U型设计的有源层110，如图2所示；其中，U型有源层110中第一有源部1101的第一端可为源极112连接端，第二有源部1102的第一端可为漏极113连接端。
之后，依次进行栅绝缘层15和第一金属层沉积，然后通过Mask曝光后对第一金属层进行刻蚀和清洗，形成如图3所示的呈一字型设计的栅线13、呈平板状的第一电极板121及连接在行方向X上相邻两第一电极板121的公共线19，并在栅线13周围特定的位置进行掺杂用来形成N型薄膜晶体管，其中，栅线13中位于掺杂区之间的部位可构成为晶体管11的栅极111，如图4所示。
之后，进行层间介质层16沉积，为了后续金属层与有源层110相应位置点的连接，需要通过Mask曝光和刻蚀，将需要连接的位置进行过孔处理，即：形成贯穿层间介质层16和栅绝缘层15的第二过孔160和第三过孔161，如图5所示，此第二过孔160露出第一有源部1101的第一端，第三过孔161露出第二有源部1102的第二端。
之后，进行第二金属层沉积，通过Mask曝光后进行刻蚀和清洗，形成前述提到的如图6所示的数据线14和第二电极板122，其中，如图 7所示，数据线14的部分通过第二过孔160与第一有源部1101的第一端连接，第二电极板122的部分通过第三过孔161与第二有源部1102的第一端连接，其中，数据线14中与第一有源层110的第一端相对应的部分可定义为晶体管11的源极112，第二电极板122中与第二有源层110的第二端相对应的部分可定义为晶体管11的漏极113。
之后，进行光学树脂层沉积，Mask曝光后进行刻蚀和清洗，形成前述提到的平坦化层17，如图8和图9所示。举例而言，此光学树脂为正性胶，其中，在形成平坦化层17时用到的掩膜版可为HTM(半透膜)掩膜版，此HTM掩膜版包括三种透过率区域，分别为用于制作第一过孔170的第一区域、用于制作图案部171的第二区域、用于制作非图案部172的第三区域。
应当理解的是，在光学树脂为正性胶时，HTM掩膜版中第一区域的透过率为100％，以保证第一过孔170的形成；HTM掩膜版中第二区域的透过率小于100％且大于0，例如：第二区域的透过率可为20％，但不限于此，可根据具体情况而定，只要能够形成有效的间隔槽1711从而形成前述提到的图案部171即可；HTM掩膜版中第三区域的透过率为0，即：第三区域为非透光区；
之后，进行第三金属层沉积，通过Mask曝光后进行刻蚀和清洗，形成相应前述提到的呈方形的反射电极18，此反射电极18通过第一过孔170与第二电极板122连接，如图11所示；其中，反射电极18可理解为产品中的像素电极。
本公开实施例还提供了一种显示面板，其中，此显示面板包括前述任一实施方式所描述的阵列基板，在此不作重复赘述。本公开实施例的显示面板可为液晶显示面板，其除了包括前述提到的阵列基板之外，还可包括与此阵列基板对盒设置的对置基板，且还可包括位于对置基板与阵列基板之间的液晶分子(图中未示出)。
在本公开的实施例中，对置基板包括第二衬底22及位于第二衬底22靠近阵列基板一侧的隔垫物20，如图17至图22所示，此隔垫物20在第一衬底10上的正投影与第一布线区102和第二布线区103的交叠部分存在交叠，这样设计在保证开口率的同时，还可避免隔垫物20在压力测试过程中滑出遮挡区域，从而可改善暗态漏光不良的问题。
举例而言，本公开实施例的第二衬底22可为玻璃衬底，但不限于此，也可为其他透明结构。对置基板中隔垫物20的数量可设置有多个，多个隔垫物20中可包括主隔垫物和辅助隔垫物，此主隔垫物和辅助隔垫物均为多个，并均匀分布在显示面板中，主隔垫物的数量远小于辅助隔垫物的数量。
其中，主隔垫物在显示面板未受到收到外界压力时，其远离第二衬底22的面可与阵列基板相接触，起主要支撑作用；而辅助隔垫物在显示面板未收到受到外界压力时，其远离第二衬底22的面与阵列基板之间具 有间隙，如图8所示，也就是说，主隔垫物远离第二衬底22的面与辅助隔垫物远离第二衬底22的面之间存在段差，通过调节主隔垫物与辅助隔垫物之间的段差可以对显示面板的厚度进行微调；其中，当显示面板受到外界压力时，主隔垫物先承受所有压力并压缩，当主隔垫物压缩至主隔垫物与辅助隔垫物之间的段差降为0时，主隔垫物和辅助隔垫物共同承受外界压力。
在本公开的实施例中，一部分隔垫物20可位于显示面板的显示区，另一部分可位于显示面板的非显示区，其中，为了保证显示区与非显示区处的盒厚一致性以避免出现线框Mura相关画质问题，如图所示，可使位于显示区的隔垫物20中靠近阵列基板的面在第一衬底10上的正投影位于平坦化层17的非图案部172在第一衬底10上的正投影内，以保证隔垫物20的支撑位置处膜层结构和厚度基本一致。
应当理解的是，图案单元171a应避开隔垫物中靠近阵列基板的面，考虑工艺波动，可使隔垫物中靠近阵列基板的面与图案单元171a的间隔槽1711之间的间距H3(如图18所示)大于等于5μm，以保证在压力或跌落测试过程中显示区与非显示区处的盒厚一致性，从而避免出现线框Mura相关画质问题。
在本公开的实施例中，结合图19和图20所示，对置基板还可包括位于隔垫物20与第二衬底22之间的遮挡层21(即：黑矩阵BM)，也就是说，在制作对置基板时，可先在第二衬底22上制作遮挡层21，然后再制作隔垫物20。其中，遮挡层21上开设有多个阵列排布的开孔区210，每个开孔区210在第一衬底10上的正投影位于一子像素区101内，并位于反射电极18和图案部171在第一衬底10上的正投影内，由于图案部171的图案单元171a呈连续设置，因此可知，图案单元171a可尽量填满开孔区210，以使得反射电极18中凹凸不平状的部分尽量填满开孔区210，从而可保证反射效果。
应当理解的是，本公开实施例的遮挡层21除了前述提到的开孔区210，其余区域为遮挡区211，此遮挡区211在第一衬底10上的正投影应覆盖晶体管11、第一过孔170、数据线14、栅线13、隔垫物20在第一衬底10上的正投影，即：晶体管11、第一过孔170、数据线14、栅线13、隔垫物20在第一衬底10上的正投影位于遮挡区211在第一衬底10上的正投影内，其中，遮挡区211也可覆盖存储电容12的部分结构和反射电极18的部分结构；也就是说，遮挡区211在第一衬底10上的正投影可覆盖整个第一布线区102、第二布线区103及子像素区101的部分，需要说明的是，遮挡区211还可覆盖非显示区。
在本公开的实施例中，如图21和图22所示，对置基板还可包括彩膜层、保护膜层24及公共电极层25，其中，
彩膜层可位于隔垫物20与第二衬底22之间，也就是说，在制作对置基板时，可先在第二衬底22上制作彩膜层，然后再制作隔垫物20； 更具体地，在制作对置基板时，可先在第二衬底22上制作遮挡层21，之后制作彩膜层，然后再制作隔垫物20。其中，彩膜层可包括多个滤光块23，多个滤光块23包括例如：红(R)、绿(G)、蓝(B)滤光块23，此滤光块23的至少部分位于开孔区210。需要说明的是，每个开孔区210内可对应设置有三个分别为红(R)、绿(G)、蓝(B)滤光块23，但不限于此，也可每个开孔区210对应设置一个滤光块23。
保护膜层24可位于彩膜层和遮挡层21远离第二衬底22的一侧，并位于隔垫物20靠近第二衬底22的一侧，也就是说，在制作对置基板时，可先在第二衬底22上依次制作遮挡层21和彩膜层，然后再制作保护膜层24，之后再制作隔垫物20；其中，保护膜层24可覆盖彩膜层和遮挡层21，以对彩膜层和遮挡层21进行保护。举例而言，保护膜层24的材质可为光学树脂胶，但不限于此，也可为其他材料，视具体情况而定。
公共电极层25可位于保护膜层24与隔垫物20之间，也就是说，在制作对置基板时，可先在第二衬底22上依次制作遮挡层21、彩膜层及保护膜层24，然后再制作公共电极层25，之后再制作隔垫物20。此公共电极层25被配置为施加参考电压，在公共电极层25与反射电极18的作用下可驱动液晶分子偏转。
举例而言，公共电极层25可为透明电极层，此公共电极层25的材质可为ITO等，但不限于此，也可为其他导电材料。
此外，还需说明的是，对置基板还可包括配向膜，此配向膜可在制作完隔垫物20之后制作而成，但不限于此，也可在制作完公共电极层25之后及制作隔垫物20之前制作而成，视具体情况而定。
应当理解的是，本公开实施例的对置基板也可不设置彩膜层，此彩膜层可位于阵列基板中。
本公开实施例还提供了一种电子设备，其包括前述任一实施方式所描述的显示面板。本公开实施例的电子设备采用RLCD技术。
需要说明的是，该电子设备除了前述提到的显示面板以外，还可包括其他部件和组成，例如：偏光片、电池、主板、壳体等等，本领域技术人员可根据该电子设备的具体使用要求进行相应地补充，在此不再赘述。
在本公开的实施例中，电子设备的具体类型不受特别的限制，本领域常用的电子设备类型均可，具体例如电子标签、电子书、智能穿戴设备、智能零售设备等等，本领域技术人员可根据该电子设备的具体用途进行相应地选择，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权 利要求指出。

Claims (29)

  1. 一种阵列基板，其中，包括：
    第一衬底(10)，具有多个沿行方向(X)和列方向(Y)阵列排布的子像素区(101)；
    像素电路层，形成在所述第一衬底(10)上，所述像素电路层包括多个子像素电路，所述子像素电路的至少部分位于所述子像素区(101)；
    平坦化层(17)，形成在所述像素电路层上，所述平坦化层(17)设有位于所述子像素区(101)内的第一过孔(170)，且所述平坦化层(17)包括至少一个图案部(171)，所述图案部(171)包括多个且沿所述行方向(X)和所述列方向(Y)阵列排布的图案单元(171a)，所述图案单元(171a)呈凹凸不平状且至少位于所述子像素区(101)，其中，所述图案单元(171a)包括多个沿周向(C)依次排布的第一凸块(1710)及环绕各所述第一凸块(1710)的间隔槽(1711)，且在所述图案单元(171a)的周向(C)上相邻两所述第一凸块(1710)共用所述间隔槽(1711)的部分；
    反射电极层，形成在所述平坦化层(17)上，所述反射电极层包括多个相互断开的反射电极(18)，每个所述反射电极(18)位于一所述子像素区(101)内，并通过所述第一过孔(170)与所述子像素电路电连接，且所述反射电极(18)与所述图案单元(171a)相对应的部位呈与所述图案单元(171a)相匹配的凹凸不平状。
  2. 根据权利要求1所述的阵列基板，其中，所述第一凸块(1710)在所述第一衬底(10)上的正投影图案为对称图案，且所述对称图案至少包括两条对称轴，分别为相互垂直的第一对称轴(a)和第二对称轴(b)，其中，所述第一对称轴(a)的长度(L1)大于所述第二对称轴(b)的长度(L2)，且所述第一对称轴(a)和所述第二对称轴(b)均与所述阵列基板的厚度方向(Z)相互垂直。
  3. 根据权利要求2所述的阵列基板，其中，在所述图案单元(171a)的周向(C)上，相邻两所述对称图案的第一对称轴(a)的延伸方向相交。
  4. 根据权利要求3所述的阵列基板，其中，在所述图案单元(171a)的周向(C)上，相邻两所述对称图案的第一对称轴(a)的延伸方向相互垂直。
  5. 根据权利要求4所述的阵列基板，其中，所述图案单元(171a)包括四个所述第一凸块(1710)，在所述图案单元(171a)的周向(C)上，相邻两所述第一凸块(1710)的对称图案中一者的第一对称轴(a)与另一者的第二对称轴(b)共线。
  6. 根据权利要求5所述的阵列基板，其中，在所述图案单元(171a)的周向(C)上，相邻两所述第一凸块(1710)的对称图案中一者的第 一对称轴(a)在所述行方向(X)上延伸，另一者的第一对称轴(a)在所述列方向(Y)上延伸。
  7. 根据权利要求2至6中任一项所述的阵列基板，其中，所述对称图案的对称轴仅包括所述第一对称轴(a)和所述第二对称轴(b)。
  8. 根据权利要求7所述的阵列基板，其中，所述对称图案为菱形、长方形、椭圆形或八边形。
  9. 根据权利要求2至8中任一项所述的阵列基板，其中，所述对称图案的第一对称轴(a)的长度(L1)与所述第一凸块(1710)的第二对称轴(b)的长度(L2)之比为1.5至2.5。
  10. 根据权利要求9所述的阵列基板，其中，所述第二对称轴(b)的长度(L2)为6μm至10μm。
  11. 根据权利要求1至10中任一项所述的阵列基板，其中，所述图案单元(171a)还包括第二凸块(1712)，位于各所述第一凸块(1710)所围成的中心区域内；
    其中，所述图案单元(171a)中各所述间隔槽(1711)靠近所述第二凸块(1712)的部分沿所述周向(C)依次首尾相连并环绕所述第二凸块(1712)。
  12. 根据权利要求11所述的阵列基板，其中，所述第一凸块(1710)和所述第二凸块(1712)的坡度角(γ)均为6°至13°。
  13. 根据权利要求11至12中任一项所述的阵列基板，其中，所述图案单元(171a)中在其周向(C)上相邻两所述第一凸块(1710)之间的最小间距为第一间距(S1)，且所述图案单元(171a)中所述第二凸块(1712)与所述第一凸块(1710)之间的最小间距为第二间距(S2)；
    其中，所述第一间距(S1)与所述第二间距(S2)之间的比值为1至1.5。
  14. 根据权利要求13所述的阵列基板，其中，所述第二间距(S2)为1.5μm至5μm。
  15. 根据权利要求11至14中任一项所述的阵列基板，其中，所述第一凸块(1710)的最大厚度与所述第二凸块(1712)的最大厚度相同。
  16. 根据权利要求1至15中任一项所述的阵列基板，其中，在所述间隔槽(1711)的位置处，所述平坦化层(17)的厚度(H1)大于等于1μm。
  17. 根据权利要求1至16中任一项所述的阵列基板，其中，所述第一过孔(170)与所述间隔槽(1711)之间的间距(H2)大于等于5μm。
  18. 根据权利要求1至17中任一项所述的阵列基板，其中，
    所述第一衬底(10)还具有多行第一布线区(102)和多列第二布线区(103)，所述第一布线区(102)与每行子像素区(101)在所述列方向(Y)上交叠排布，所述第二布线区(103)与每列子像素区(101)在所述行方向(X)上交替排布；
    所述像素电路层还包括多行栅线(13)和多列数据线(14)，所述栅线(13)位于所述第一布线区(102)，所述数据线(14)位于所述第二布线区(103)，所述栅线(13)和所述数据线(14)分别与所述子像素电路电连接。
  19. 根据权利要求18所述的阵列基板，其中，所述子像素电路包括存储电容(12)及晶体管(11)；
    所述存储电容(12)位于所述子像素区(101)，且所述存储电容(12)包括在所述第一衬底(10)的厚度方向(Z)上相对的第一电极板(121)和第二电极板(122)，所述第一电极板(121)与所述栅线(13)同层设置且相互断开，所述第二电极板(122)与所述数据线(14)同层设置且相互断开，所述第二电极板(122)通过所述第一过孔(170)与所述反射电极(18)连接；
    所述晶体管(11)包括有源层(110)、栅极(111)、源极(112)和漏极(113)；所述有源层(110)位于所述栅线(13)靠近所述第一衬底(10)的一侧，所述有源层(110)包括位于所述第二布线区(103)的第一有源部(1101)、与所述第一有源部(1101)在所述行方向(X)上相对的第二有源部(1102)以及至少位于所述子像素区(101)的第三有源部(1103)，所述第一有源部(1101)在所述第一衬底(10)上的正投影与所述栅线(13)在所述第一衬底(10)上的正投影存在交叠，所述第一有源部(1101)的第一端位于所述栅线(13)远离所述第三有源部(1103)的一侧，所述第一有源部(1101)的第二端和所述第三有源部(1103)的第一端连接，所述第二有源部(1102)的第一端和第二端分别位于在所述行方向(X)上相邻两所述子像素区(101)上，所述第二有源部(1102)的第一端位于所述栅线(13)远离所述第三有源部(1103)的一侧，所述第二有源部(1102)的第二端与所述第三有源部(1103)的第二端连接；
    其中，所述栅线(13)中与所述第一有源部(1101)和所述第二有源部(1102)在所述第一衬底(10)的厚度方向(Z)上存在交叠的部分构成所述晶体管(11)的栅极(111)，所述数据线(14)中与所述第一有源部(1101)的第一端在所述第一衬底(10)的厚度方向(Z)上存在交叠的部分构成所述晶体管(11)的源极(112)，所述源极(112)与所述第一有源部(1101)的第一端通过第二过孔(160)连接，所述第二电极板(122)中与所述第二有源部(1102)的第一端在所述第一衬底(10)的厚度方向(Z)上存在交叠的部分构成所述晶体管(11)的漏极(113)，所述漏极(113)与所述第二有源部(1102)的第一端通过第三过孔(161)连接。
  20. 根据权利要求19所述的阵列基板，其中，同行子像素电路中任意相邻两子像素电路的存储电容(12)的第一电极板(121)通过公共线(19)连接，所述公共线(19)与所述第一电极板(121)同层设置。
  21. 根据权利要求18至20中任一项所述的阵列基板，其中，
    所述平坦化层(17)还包括至少位于所述第一布线区(102)的非图案部(172)，所述非图案部(172)在所述行方向(X)上延伸，所述非图案部(172)远离所述第一衬底(10)的面为平面。
  22. 根据权利要求21所述的阵列基板，其中，所述图案部(171)中各所述图案单元(171a)呈连续设置；
    其中，所述图案部(171)在所述行方向(X)上延伸，所述图案部(171)在所述第一衬底(10)上的正投影与位于同一行的子像素区(101)均存在交叠。
  23. 根据权利要求22所述的阵列基板，其中，所述图案部(171)和所述非图案部(172)均设置多个，且所述图案部(171)与所述非图案部(172)在所述列方向(Y)上交替排布。
  24. 一种显示面板，其中，包括如权利要求1至23中任一项所述的阵列基板和与所述阵列基板对盒设置的对置基板。
  25. 根据权利要求24所述的显示面板，其中，
    所述阵列基板为如权利要求21所述的阵列基板；
    所述对置基板包括第二衬底(22)及位于所述第二衬底(22)靠近所述阵列基板一侧的隔垫物(20)，所述隔垫物(20)在所述第一衬底(10)上的正投影与所述第一布线区(102)和所述第二布线区(103)的交叠部分存在交叠，且所述隔垫物(20)中靠近所述阵列基板的面在所述第一衬底(10)上的正投影位于所述平坦化层(17)的非图案部(172)在所述第一衬底(10)上的正投影内。
  26. 根据权利要求25所述的显示面板，其中，
    所述隔垫物(20)中靠近所述阵列基板的面与所述图案单元(171a)的间隔槽(1711)之间的间距(H3)大于等于5μm。
  27. 根据权利要求25或26所述的显示面板，其中，所述对置基板还包括位于所述隔垫物(20)与所述第二衬底(22)之间的遮挡层(21)，所述遮挡层(21)上开设有多个阵列排布的开孔区(210)，每个所述开孔区(210)在所述第一衬底(10)上的正投影位于一所述子像素区(101)内，并位于所述反射电极(18)和所述图案部(171)在所述第一衬底(10)上的正投影内。
  28. 根据权利要求27所述的显示面板，其中，所述对置基板还包括：
    彩膜层，位于所述隔垫物(20)与所述第二衬底(22)之间，所述彩膜层包括多个滤光块(23)，所述滤光块(23)的至少部分位于所述开孔区(210)；
    保护膜层(24)，位于所述彩膜层和所述遮挡层(21)远离所述第二衬底(22)的一侧，并位于所述隔垫物(20)靠近所述第二衬底(22)的一侧，所述保护膜层(24)覆盖所述彩膜层和所述遮挡层(21)；
    公共电极层(25)，位于所述保护膜层(24)与所述隔垫物(20)之 间。
  29. 一种电子设备，其中，包括权利要求24至28中任一项所述的显示面板。
PCT/CN2021/074475 2021-01-29 2021-01-29 阵列基板、显示面板及电子设备 WO2022160279A1 (zh)

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US17/622,708 US11984453B2 (en) 2021-01-29 2021-01-29 Array substrate, display panel and electronic device
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