WO2022160245A1 - Élément d'encapsulation de circuit intégré, son procédé de préparation et borne - Google Patents

Élément d'encapsulation de circuit intégré, son procédé de préparation et borne Download PDF

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Publication number
WO2022160245A1
WO2022160245A1 PCT/CN2021/074398 CN2021074398W WO2022160245A1 WO 2022160245 A1 WO2022160245 A1 WO 2022160245A1 CN 2021074398 W CN2021074398 W CN 2021074398W WO 2022160245 A1 WO2022160245 A1 WO 2022160245A1
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WIPO (PCT)
Prior art keywords
metal
heat dissipation
integrated circuit
layer
circuit package
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PCT/CN2021/074398
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English (en)
Chinese (zh)
Inventor
张童龙
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180091460.8A priority Critical patent/CN116806368A/zh
Priority to PCT/CN2021/074398 priority patent/WO2022160245A1/fr
Publication of WO2022160245A1 publication Critical patent/WO2022160245A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to an integrated circuit package, a preparation method and a terminal thereof.
  • the flip-chip integrated circuit package is usually equipped with a lid (Lid) that can help heat dissipation, which can be called a heat dissipation cover, and the heat dissipation cover set above the chip and the chip are generally made of a thermal interface material (TIM). ) are connected.
  • TIM should have good flexibility and good deformation ability.
  • TIM materials are usually organic materials with good flexibility (such as thermally conductive silicone grease, thermally conductive silicone, etc.), but their thermal conductivity is limited. Therefore, it is necessary to provide a TIM that can achieve both high thermal conductivity and high flexibility.
  • the embodiments of the present application provide an integrated circuit package, which uses the metal connection structure spaced on the back of the chip as a TIM connecting the chip and the heat dissipation cover, which can take into account high thermal conductivity and good flexibility at the same time.
  • the heat is fully dissipated while taking into account the reliability.
  • a first aspect of the embodiments of the present application provides an integrated circuit package, which includes a substrate, a chip and a heat dissipation cover sequentially arranged on the substrate, and the chip is located in a container surrounded by the heat dissipation cover and the substrate.
  • the surface of the side of the chip away from the substrate is provided with a metal primer layer and a plurality of metal connection structures arranged on the metal primer layer at intervals, and the metal connection structures are metal sheets or metal wires. Two opposite sides of each of the metal sheets or two ends of each of the metal wires are respectively connected with the metal base layer and the heat dissipation cover.
  • the metal connection structure distributed at intervals on the back of the chip is used as the heat dissipation medium material for connecting the chip and the heat dissipation cover in the package.
  • the overall structure arranged by the metal connection structure not only has good thermal conductivity, but also has good flexibility. , the deformation ability is strong, and the heat generated by the chip can be effectively conducted to the heat dissipation cover, and at the same time, the warpage of the package can be reduced/compensated for the displacement caused by the warpage of the package. Therefore, the integrated circuit package can achieve better heat dissipation effect and at the same time have good quality reliability.
  • the material of the metal connection structure includes at least one of copper, silver, gold, and alloys thereof. These metals have high thermal conductivity and have a strong ability to conduct heat.
  • the thickness of the metal sheet is nanometer. In some embodiments, the thickness of the metal sheet is 10 nm-100 nm. Metal sheets with nanometer thickness can be densely distributed on the metal base layer to achieve good toughness and certain mechanical strength.
  • the aspect ratio of the metal wire is greater than or equal to 10.
  • the wire diameter of the metal wire is 10 nm-100 nm.
  • the overall structure formed by the metal nanowires with suitable wire diameters can have good toughness without increasing the difficulty of manufacturing the metal nanowires.
  • the aspect ratio of the metal wire is greater than or equal to 200. At this time, the flexibility of the structure arranged by the metal wires is relatively high.
  • the length of the metal wire is 20 ⁇ m-1000 ⁇ m.
  • a metal wire with a suitable extension length can avoid that the length is too short to effectively compensate for the displacement caused by the warpage of the package, and it will not increase the difficulty of manufacturing the metal wire and increase the thermal resistance due to the too long length.
  • the total coverage ratio of the plurality of metal connection structures on the surface of the metal primer layer is 10%-70%.
  • the coverage of the multiple metal connection structures on the surface of the metal base layer is appropriate, and the overall structure arranged by them has a suitable toughness to resist package warpage while achieving good thermal conductivity.
  • the distance between any two adjacent metal connection structures is 10 nm-200 nm.
  • the distribution spacing of the adjacent metal connection structures is appropriate, so that the critical pressure for instability is large and the deformation capacity under compression is good under the condition of achieving good thermal conductivity.
  • the thickness of the metal primer layer is 50 nm-1000 nm.
  • a thinner metal base layer can provide stress buffering between the metal connection structure and the chip, and improve the adhesion strength of the metal connection structure without significantly increasing the internal stress of the package.
  • the material of the metal primer layer includes one or more of copper, titanium, gold, silver, palladium, nickel, tungsten, molybdenum, zinc, aluminum and alloys thereof. At this time, the thermal conductivity of the metal base layer is also relatively good. In some embodiments, the material of the metal base layer is silver, copper, gold, aluminum or molybdenum and other metals with high thermal conductivity.
  • the metal primer layer contains the same metal element as the metal connection structure. This can further help reduce the difference in thermal expansion coefficient between the metal base layer and the metal connection structure, and improve the bonding force of the two.
  • the metal primer layer is a copper layer, a gold layer, a silver layer, a titanium-gold alloy layer or a titanium-target-gold alloy layer.
  • the metal sheet or the metal wire is welded with the heat dissipation cover.
  • a welded portion may be formed therebetween, and the thickness of the welded portion is less than or equal to 1/10 of the height of the metal connection structure. Soldering parts of suitable thickness can have lower thermal resistance and reduce the stress between the increased heat dissipation cover and the metal connection structure.
  • the surface of the substrate facing away from the chip is provided with an array of solder balls.
  • the solder ball array is formed by arranging a plurality of solder balls, and the package at this time is a BGA package, which has the advantages of multi-function, high density, and small volume at the same time.
  • a second aspect of the embodiments of the present application provides a method for preparing an integrated circuit package, including:
  • a plurality of metal connection structures distributed at intervals are formed on the metal base layer to obtain a wafer intermediate structure; wherein, the metal connection structures are metal sheets or metal wires;
  • the encapsulation core includes a chip, the metal base layer disposed on one side surface of the chip, and a plurality of base layers arranged on the metal base layer at intervals. the metal connection structure;
  • the side of the chip away from the metal connection structure and the heat dissipation cover are mounted on the substrate, so that the package core is located in the accommodating space surrounded by the heat dissipation cover and the substrate, and the metal
  • the connection structure is connected with the heat dissipation cover to obtain an integrated circuit package; wherein, opposite sides of each of the metal sheets or two ends of each of the metal wires are respectively in contact with the metal base layer and the heat dissipation cover connect.
  • the metal connection structure is formed by the following method: placing a porous template with a plurality of through holes on the metal underlayer, and depositing the metal connection structure in the through holes.
  • the morphology of the metal connection structure formed by the template method is relatively uniform and high in integrity.
  • the pore size of the through holes is nanometer size, for example, 10 nm-100 nm. This method is especially suitable for the preparation of metal wires with large aspect ratios.
  • the method further includes: forming a solder layer in the through hole, so that the solder layer is located on the metal connection structure.
  • the solder layer can improve the solderability between the metal connection structure and the heat dissipation cover.
  • the solder layer can form a low thermal resistance metal-to-metal interconnection with the metal connection structure of the heat dissipation cover.
  • the solder layer may include pure tin plating layer or lead-free tin-based alloy plating layer or the like.
  • the method before or after cutting the wafer intermediate structure, the method further includes: removing the porous template.
  • the method further includes: coating and forming solder on one end of the metal wire away from the metal underlayer or at the side of the metal sheet away from the metal underlayer Floor.
  • the method before the heat dissipation cover is mounted on the substrate, the method further includes: coating a flux and/or plating a surface treatment layer on a region where the heat dissipation cover and the metal connection structure are to be connected. All of these treatments help to improve the welding strength between the heat dissipation cover and the metal connection structure.
  • the surface treatment layer may be, but not limited to, a tin plating layer, a nickel plating layer, a gold plating layer, a nickel gold plating layer, a nickel palladium gold plating layer, or the like.
  • the method for preparing an integrated circuit package provided by the second aspect of the embodiment of the present application has the advantages of simple process, low cost and high production efficiency, and is suitable for industrialized batch preparation.
  • the prepared package has strong heat dissipation capability, better anti-warping capability and high quality reliability.
  • a third aspect of the embodiments of the present application provides a terminal, where the terminal has built-in integrated circuit packages as described above in the embodiments of the present application.
  • Figure 1 is a schematic diagram of a common structure of a BGA package
  • FIG. 2a is a schematic structural diagram of an integrated circuit package provided by an embodiment of the present application.
  • Figure 2b shows a schematic structural diagram of a metal sheet
  • FIG. 3 is another schematic structural diagram of an integrated circuit package provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for manufacturing an integrated circuit package according to an embodiment of the present application
  • FIG. 5 is a specific flowchart of steps S20-S30 in FIG. 4 provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of a terminal provided in an embodiment of the present application.
  • FIG. 1 shows the general structure of a package commonly used in the field of integrated circuits—BGA (Ball Grid Array, Ball Grid Array, or Solder Ball Array) package.
  • the BGA package generally includes a substrate 100 and is attached to the substrate 100.
  • On the chip 10 a plurality of solder balls 10 a on the bottom outer surface of the substrate 100 , the plurality of solder balls 10 a are arranged in an array to form a solder ball array, and the BGA package further includes a heat dissipation cover 20 on the back of the chip 10 .
  • the heat dissipation cover 20 and the chip 10 are connected by a heat dissipation medium layer 12.
  • the heat dissipation medium layer 12 is generally formed by coating a TIM material such as thermally conductive silica gel.
  • the TIM material is usually an organic material. Although its flexibility is good, its thermal conductivity is not sufficient. .
  • the embodiments of the present application provide a novel integrated circuit package and a preparation method thereof.
  • an integrated circuit package 300 provided by an embodiment of the present application includes a substrate 100 , a chip 10 and a heat dissipation cover 20 arranged on the substrate 100 in sequence, and the chip 10 is located in the area surrounded by the heat dissipation cover 20 and the substrate 100 . into the accommodating space.
  • the side surface of the chip 10 away from the substrate 100 is provided with a metal base layer 11, and a plurality of metal connection structures 121 are distributed on the metal base layer 11 at intervals.
  • the metal connection structures 121 can be metal wires or metal sheets. The ends or opposite sides of each metal sheet are respectively connected with the metal base layer 11 and the heat dissipation cover 20 .
  • the metal wire For the metal wire, it extends in the direction away from the metal base layer 11, one end is connected to the metal base layer 11, and the other end (ie, the end away from the metal base layer 11) is fixedly connected to the heat dissipation cover 20, specifically with the heat dissipation
  • the top of the cover 20 is fixedly attached.
  • the metal connection structure is a metal sheet, see FIG. 2 b , the metal sheet includes opposite sides 121 a and 121 b , wherein the side 121 a can be connected to the metal base layer 11 , and the side 121 b can be connected to the top side of the heat dissipation cover 20 . That is to say, the metal sheet is not laid flat on the metal base layer, but "stands" on the metal base layer.
  • the surface of the metal sheet (indicated by the arrow in FIG. 2 b , the surface perpendicular to the thickness direction of the metal sheet) is not connected to the metal base layer 11 and the heat dissipation cover 20 .
  • the thickness direction of the metal sheet is not perpendicular to the metal underlayer 11 , and its thickness direction is parallel or approximately parallel to the metal underlayer.
  • a plurality of metal connection structures 121 distributed at intervals on the back of the chip are used as the TIM for connecting the chip 10 and the heat dissipation cover 20 , wherein the material of the metal connection structure has good thermal conductivity.
  • the metal can effectively conduct the heat generated by the chip 10 to the heat dissipation cover 20, and then dissipate it into the external environment; at the same time, the structure formed by a plurality of metal connecting structures 121 arranged at intervals also has good flexibility and strong deformation ability. Overall package warpage can be reduced or displacement due to package warpage can be compensated. Therefore, the integrated circuit package provided by the embodiments of the present application can achieve a better heat dissipation effect and at the same time have good quality reliability.
  • each metal connection structure 121 can be grown in-situ on the metal primer layer 11 to be integrally formed with the metal primer layer, or can be fixedly connected to the metal primer layer 11 by other means (eg, welding). For example, for a metal wire with good toughness, it can be deposited in-situ on the surface of the metal primer layer 11 .
  • Each metal connection structure 121 may be fixedly connected to the heat dissipation cover 20 by welding, or may be fixedly connected to the heat dissipation cover 20 by other means, such as by thermally conductive glue.
  • the metal connection structure 121 When the metal connection structure 121 is a metal sheet, its thickness can be in nanometer order, for example, 10 nm-100 nm. Metal sheets with nanometer thickness can be densely distributed on the metal base layer to achieve good toughness and certain mechanical strength. In some embodiments, the maximum lateral dimension of the side surface of the metal sheet connected with the metal base layer 11 and the heat dissipation cover (ie, the side length of the side surface except for the thickness) may also be in the range of 10nm-100nm, so that the metal sheet distribution density is high.
  • the aspect ratio of the metal wire when the metal connection structure 121 is a metal wire, the aspect ratio of the metal wire may be greater than or equal to 10, and the metal wire has a certain flexibility in this case.
  • “aspect ratio” refers to the ratio of the length of the metal wire extending in the direction away from the metal base layer 11 and its wire diameter.
  • the wire diameter of the metal wire is also its maximum lateral dimension, specifically the distance between two points with the largest dimension on its cross-section, which can be determined according to the specific shape of the cross-section.
  • the cross-sectional shape of the metal connection structure 121 is not limited to a regular shape such as a circle, an ellipse, a triangle, a rectangle, a polygon, etc., or an irregular shape.
  • the maximum lateral dimension of the metal wire when the cross section is a circle; when the cross section is a polygon, the maximum lateral dimension is the diameter of the circumscribed circle of the polygon.
  • the aspect ratio of the metal wire is greater than 20, such as ⁇ 100, ⁇ 200, or even ⁇ 1000.
  • the metal wire has an aspect ratio greater than or equal to 200.
  • the flexibility of the structure arranged by the metal wires is relatively high.
  • the aspect ratio of the metal wire may be 200-10 5 , for example, 200-30000.
  • the wire diameter of the metal wire may be nanoscale, and the metal wire at this time may be referred to as a "metal nanowire".
  • the wire diameter of the metal wire may be 10 nm-100 nm.
  • the overall structure of metal nanowires with suitable wire diameters can have good toughness without increasing the difficulty of making metal nanowires.
  • the wire diameter specifically refers to the diameter of the metal nanowire.
  • the wire diameter of the metal nanowire may be 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm.
  • the extending direction of the metal lines is not coplanar with the metal underlayer 11 .
  • the metal wire may be straight or curvilinear. That is, the metal lines may extend straight or curved in a direction away from the metal underlayer 11 .
  • the straight line extension may be a vertical extension or an oblique extension.
  • the length of the metal wire is generally more than 1 ⁇ m. In the embodiment of the present application, the length of the metal wire (ie, the extension length in the direction away from the metal base layer) is 20 ⁇ m-1000 ⁇ m.
  • a metal wire with a suitable extension length can not only avoid the displacement caused by the warpage of the package due to being too short, but also will not increase the difficulty of manufacturing the metal wire and increase the thermal resistance due to the too long length.
  • the extension length of the metal wire may be 22 ⁇ m, 25 ⁇ m, 30 ⁇ m, 50 ⁇ m, 80 ⁇ m, 100 ⁇ m, 200 ⁇ m, 280 ⁇ m, 300 ⁇ m, 400 ⁇ m, 500 ⁇ m, 600 ⁇ m or 800 ⁇ m, and the like.
  • the extension length of the metal line is 20 ⁇ m-300 ⁇ m, so as to better balance the package warpage resistance and low thermal resistance.
  • the height of the metal connection structure 121 is 18 ⁇ m-990 ⁇ m.
  • the height refers to the distance between the side where the metal sheet is connected with the heat dissipation cover and the side where the metal sheet is connected with the metal base layer.
  • metal wires it refers to the distance between the two ends of the metal wire.
  • the total coverage ratio of the plurality of metal connection structures 121 on the surface of the metal base layer 11 may be 10%-70%.
  • the sum of the bottom surface areas of the plurality of metal connection structures 121 in contact with the metal underlayer 11 is 10%-70% of the surface area of the side of the metal underlayer 11 facing the metal connection structure.
  • the coverage of the plurality of metal connection structures 121 on the surface of the metal base layer 11 is appropriate, and the overall structure arranged therein can achieve good thermal conductivity and also have suitable toughness to resist package warpage.
  • the total coverage of the plurality of metal connection structures 121 on the surface of the metal primer layer 11 is 15%-50%. In this case, the effective heat conduction effect will not be achieved because the coverage is too low, and the overall structural toughness of the multiple metal connection structures will not be too low due to the coverage is too high.
  • the distance between any two adjacent metal connection structures 121 is in the range of 10 nm-200 nm.
  • the distribution gap of the metal connection structure is suitable, and under the condition of achieving good thermal conductivity, it can also have a large instability critical pressure and a good compressive deformation ability.
  • the spacing between any two adjacent metal connection structures 121 may be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 190 nm or 200nm.
  • the spacing may be 10 nm-100 nm.
  • the material of the metal connection structure 121 may be, but not limited to, at least one of copper (Cu), silver (Ag), gold (Au) and alloys thereof with excellent thermal conductivity.
  • the metal connection structure 121 may be elemental Cu, Ag, or Au, which has a lower thermal conductivity than the corresponding alloy.
  • the metal connection structure may be prepared by electroplating, electroless plating, physical vapor deposition (PVD) or chemical vapor deposition (CVD), etc., but is not limited thereto.
  • the metal connection structure 121 is Cu or Ag, which is low in cost and difficult to fabricate by electroplating technology.
  • the metal connection structures 121 distributed at intervals may be prepared by an electroplating method using a porous template, so as to have a relatively uniform and complete morphology. At this time, precise control of the morphology of the metal connection structure 121 can be achieved by adjusting the pore shape of the used porous template.
  • the metal base layer 11 can also be used as a conductive base layer for forming the metal connection structure 121 by electroplating, which is used as a working electrode for electroplating.
  • the formation method of the metal primer layer 11 includes, but is not limited to, at least one selected from electroplating, physical vapor deposition (PVD), and chemical vapor deposition (CVD).
  • the thickness of the metal primer layer 11 may be 50 nm-1000 nm.
  • the thinner metal base layer 11 can function as a working electrode for electroplating without significantly increasing the internal stress of the overall package.
  • the thickness of the metal underlayer 11 may be 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 200 nm, 300 nm, 400 nm, 600 nm, 700 nm, 800 nm, and 950 nm.
  • the thickness of the metal underlayer 11 may be 60 nm-900 nm.
  • the material of the metal base layer 11 may include copper (Cu), titanium (Ti), gold (Au), silver (Ag), palladium (Pd), nickel (Ni), tungsten (W), molybdenum (Mo) ), one or more of zinc (Zn), aluminum (Al) and its alloys.
  • the metal primer layer 11 may be a metal element layer, an alloy layer, or a composite layer of a metal element and an alloy, and may be a one-layer or multi-layer structure.
  • the alloy layer is preferably formed by an electroplating process, so that the cost is low and the preparation process is simple.
  • the metal primer layer 11 When the metal primer layer 11 is a one-layer structure, it can be a certain metal element layer or alloy layer; when the metal primer layer 11 is a multi-layer structure with more than two layers, it can be a stack of multiple metal element layers, Stacking of multiple alloy layers or stacking of metal element layers and alloy layers, etc.
  • the metal base layer 11 may contain the same metal elements as the following metal connection structure 121 , that is, the metal elements of the two may be completely or partially the same, which can help reduce the difference between the metal base layer and the metal The difference in thermal expansion coefficient between the connecting structures 121 improves the bonding force of the two.
  • the metal primer layer 11 is a Cu layer, an Au layer, an Ag layer, a TiAu alloy layer or a TiPdAu alloy layer. Under the condition that a firm bonding force is formed between the metal connecting structure 121 and the metal connecting structure 121 , the metal base layer itself also has high thermal conductivity.
  • the side surface of the chip 10 away from the substrate 100 may be referred to as the back surface of the chip 10 , and the active surface disposed opposite to the back surface may also be referred to as the “front surface”.
  • the active surface of the chip 10 is provided with functional transistors, various fine circuits, and the like.
  • the surface of the substrate 100 on which the chips 10 are provided may be referred to as the first surface 100a, and the surface opposite thereto may be referred to as the second surface 100b.
  • the chip 10 is attached to the substrate 100 in a “flip-chip” manner, with the active surface of the chip 10 facing the first surface 100 a of the substrate 100 .
  • the chip 10 may be fixed on the substrate 100 by reflow soldering through a surface mount process.
  • a plurality of solder bumps 101 are also provided on the active surface of the chip 10, and the electrical connection between the chip 10 and the substrate 100 can be realized by the remelting of the solder bumps 101, so that the two The connection strength is high and the precision is high.
  • the solder bumps 101 may be, but not limited to, a stack of copper (near chip 10 ) layers + SnAg alloy layers, or SnAgCu alloy layers.
  • the first surface 100 a of the substrate 100 has a mounting area for the chip 10 , and the mounting area may include an array of pads corresponding to the solder bumps 101 .
  • an underfill material 102 may also be provided in the gaps of the solder bumps 101 to fill the space between the chip 10 and the substrate 100 to provide a more stable connection.
  • the underfill material 102 may be formed by coating, specifically epoxy resin, thermoplastic adhesive or any other suitable type of underfill material.
  • the heat dissipation cover 20 has an open end, and the open end is mounted on the first surface 100 a of the substrate 100 so that the chip 10 is located in the accommodating space surrounded by the heat dissipation cover 20 and the substrate 100 .
  • the heat dissipation cover 20 surrounds the chip 10 and structures such as the metal base layer 11 and the metal connection structure 121 , which can provide environmental protection for the chip 10 and facilitate the heat dissipation of the chip.
  • the heat dissipation cover 20 can be made of thermally conductive metal materials, including but not limited to stainless steel, copper, copper alloy, aluminum alloy or nickel alloy. The specific shape and structure of the heat dissipation cover 20 is not limited.
  • the heat dissipation cover 20 includes a heat dissipation top and a surrounding side wall extending longitudinally from the heat dissipation top. 2a).
  • the side wall of the heat dissipation cover 20 is fixed on the substrate 100 , and the side wall of the heat dissipation cover 20 can be connected with the substrate 100 by glue or welding. That is, in FIG. 2a, the connection part 201 between the heat dissipation cover 20 and the substrate 100 may be an adhesive layer or a welding part.
  • the adhesive layer may specifically be conductive silver adhesive or organic adhesive (eg, epoxy adhesive) or the like.
  • the metal connection structure 121 in the integrated circuit package 300 may not be completely perpendicular to the back surface of the chip 10.
  • the metal connection structure 121 may be bent to a certain extent (as shown in FIG. 2a). , so that its height is lower than its length.
  • the metal connection structure 121 and the heat dissipation cover 20 are welded, and a welding portion 122 is formed therebetween.
  • the composition of the soldering portion 122 can be determined according to the solder base, solder, and the like.
  • the soldering portion 122 may be formed by remelting the solder layer provided on the heat dissipation cover 20 and/or the solder layer on the metal connection structure 121 , or the surface treatment layer on the heat dissipation cover 20 may be partially or completely connected with the metal provided on the heat dissipation cover 20 .
  • the solder on the structure 121 reacts and so on.
  • the thickness of the welding portion 122 should not be too thick in order not to affect the low thermal resistance metal-to-metal interconnection between the metal connection structure 121 and the heat dissipation cover. In some embodiments, the thickness of the welding portion 122 may be less than or equal to 1/10 of the height of the metal connecting structure 121 .
  • the chip 10 attached to the integrated circuit package 300 may be a chip with different functions, and may be selected according to the needs of different functions.
  • the integrated circuit package 300 may include multiple chips 10, and the multiple chips may be chips with different functions.
  • the integrated circuit package 300 further includes other electronic components disposed on the substrate 100 , and the other electronic components may include, but are not limited to, resistors, capacitors, inductors, thermal sensing elements, and the like. Other electronic components can also be packaged various types of devices.
  • the integrated circuit package 300 may further include a plastic package (not shown in FIG. 2 a ) covering the substrate 100 , the chip 10 and the heat dissipation cover 20 , and the heat dissipation top of the heat dissipation cover 20 exposes the top surface of the plastic package.
  • the material of the molding body 40 may be epoxy resin.
  • the material of the plastic sealing body is solid epoxy resin, which is obtained by liquefying the solid epoxy resin and then injection molding.
  • the plastic package has good heat dissipation performance and can form a good heat dissipation channel; at the same time, the plastic package can provide mechanical support for electronic components such as chips, and protect electronic components such as chips from external physical or chemical damage.
  • the integrated circuit package shown in FIG. 2a may be a Land Grid Array (LGA) package.
  • LGA Land Grid Array
  • a surface of the substrate 100 facing away from the chip 10 may further be provided with a solder ball array, which is formed by an array of a plurality of solder balls 103 (as shown in FIG. 3 ).
  • the solder balls 103 are not encapsulated by the plastic body, and are located at the outermost part of the entire integrated circuit package.
  • the integrated circuit package at this time may be referred to as a "BGA package", and the solder balls 103 are located at the bottom of the package.
  • the packages with the heat dissipation lids, metal connections, etc. described above may also be other types of integrated circuit packages for efficient thermal conduction and reduced package warpage song.
  • an embodiment of the present application provides a method for fabricating an integrated circuit package, including the following steps S10 to S40 .
  • the side surface of the wafer 10 ′ on which the metal primer layer 11 is formed may be the back surface 10 ′B of the wafer 10 ′, and the back surface of the wafer 10 ′ is disposed opposite to the active surface of the wafer 10 ′.
  • Face 10'A The wafer 10' is a base material for preparing a "chip" of a semiconductor component, and various fine circuits, functional transistors, a plurality of pads, etc. can be provided on the active surface 10'B of the wafer 10'.
  • the active surface 10'B may have staggered dicing lines, and the dicing lines may define a plurality of dies or chips.
  • the active surface of the wafer 10' may also have a plurality of solder bumps, and the chips cut from the wafer can be soldered to the substrate of the package through the solder bumps.
  • the solder bumps may also be fabricated after the wafer is diced into chips.
  • the metal underlayer 11 can be a whole metal layer, that is, the whole surface covers the back surface of the wafer 10', and its deposition method can be selected from at least one of electroplating, PVD, and CVD.
  • PVD may include one or more of evaporation, magnetron sputtering, ion plating (eg arc ion plating, radio frequency ion plating), etc.
  • CVD may include hot filament chemical vapor deposition (HFCVD), plasma enhanced chemical One or more of Vapor Deposition (PECVD) etc.
  • the material of the metal primer layer 11 may not be limited to include one or more of Cu, Ti, Au, Ag, Pd and their alloys, for example, a Cu layer, an Au layer, a Ti layer, a TiAu alloy layer or TiPdAu alloy layer, etc. Among them, the cost of forming the metal bottom layer 11 through the electroplating process is low and the preparation process is simple.
  • the package core includes a chip 10 , a metal primer layer 11 disposed on one side surface of the chip 10 , and metal connections arranged on the metal primer layer 11 at intervals Structure 121.
  • the metal connection structure 121 may be prepared by electroplating, electroless plating, PVD, chemical vapor deposition CVD or plasma etching, etc., but is not limited thereto.
  • the prepared metal connection structures 121 can be arranged in an array on the metal base layer 11, and can also be arranged in other ways as required.
  • step S20 when the metal connection structure is a metal wire, it extends in a direction away from the metal base layer 11, rather than laying on the metal base layer; when the metal connection structure is a metal sheet, it is not evenly spread on the metal base layer. On the bottom layer, but "standing" on the metal bottom layer, one side of the metal sheet is connected to the metal bottom layer 11, and the other side is away from the metal bottom layer.
  • the process of electroplating the metal nanowire 121 by a template method and subsequent operations are shown for the above steps S20-S30, as shown in FIG. 5 , the specific include:
  • the porous template 200 has a plurality of nano-holes 200a arranged at intervals, which penetrate the thickness direction of the porous template 200, the hole depth is equal to the thickness of the porous template 200, and the pore diameter can be the same as the wire diameter of the metal nanowires 121. Correspondingly, it can be in the range of 10nm-100nm.
  • the porous template 200 may specifically include a porous silicon template, a porous anodic aluminum oxide (AAO) template, a track etched membrane, or the like. Among them, the AAO template can be prepared by anodizing the aluminum substrate.
  • the track-etched film can prepare nano-holes by heavy ion track etching on the tracked polymer film material, and the hole morphology can be modulated by changing the etching conditions.
  • the material of the track etching film includes at least one of polycarbonate (PC), polyethylene terephthalate (PET), polyimide (PI) and the like.
  • the porous template 200 is a track etched film made of organic polymer, which can be easily removed by an organic solvent and will not cause damage to the metal nanowires.
  • place the porous template 200 on the metal primer layer 11 includes: placing the porous template 200 on the metal primer layer 11 by at least one method such as thermocompression bonding, gluing, or the like.
  • the adhesive tape used needs to be resistant to the electrochemical deposition solution used for electroplating.
  • the thermocompression bonding method is particularly suitable for fixing the track etching film with certain flexibility.
  • depositing to form metal nanowires 121 in the nano-via hole 200a by electroplating may specifically include: fixing the structure as shown in (a) in FIG. Electrode (connected to the cathode of the electrolytic cell), with an inert electrode as the counter electrode (connected to the anode of the electrolytic cell), electrochemical deposition is performed in the first electrochemical deposition solution to deposit in the nano-through holes 200a of the porous template 200 Metal nanowires 121 are formed.
  • the first electrochemical deposition solution contains metal ions corresponding to the metal nanowires 121 .
  • the deposition temperature, deposition time, deposition potential, current density, etc. can be adjusted according to the specific metal nanowire 121 and its thickness.
  • step S21 since the metal nanowires 121 are deposited in the pores of the porous template 200, the size of the metal nanowires 121 obtained by electroplating can be controlled by the pore shape and pore size of the porous template 200 used.
  • the aspect ratio of the metal nanowires is controlled by the pore size and the length. Therefore, the pore size of the metal nanowires 121 obtained by the template method can be precisely controlled, has good uniformity, and has a large aspect ratio.
  • using the template method to prepare metal nanowires has higher efficiency and lower cost, and is more suitable for industrial production.
  • step S21 after the metal nanowires 12 are deposited in the nanovias 200 a , the method further includes: forming a solder layer in the nanovias 200 122', so that the solder layer 122' is located on the metal nanowire 121, and the wafer intermediate structure as shown in FIG. 5(b) is obtained.
  • the solder layer 122' may be reflowed during the soldering process to realize the interconnection between the metal nanowires 121 and the heat dissipation cover 20.
  • a solder layer 122' is formed on one end of each metal nanowire away from the metal underlayer 11.
  • the solder layer 122' may be formed by electroplating deposition.
  • the structure shown in Fig. 5 (a) can be fixed in the electrolytic cell, the metal bottom layer 11 is used as the working electrode, the inert electrode is used as the counter electrode, and the first electrochemical deposition solution Electrochemical deposition is performed in the porous template 200 to form metal nanowires 121 in the nano-through holes 200a of the porous template 200; and then electrochemical deposition is performed in the second electrochemical deposition solution to form a solder layer 122' on the metal nanowires 121. .
  • the second electrochemical deposition solution contains metal ions corresponding to the solder layer 122'.
  • the deposition temperature, deposition time, deposition potential, current density, etc. can be adjusted according to the specific solder layer 122' and its thickness.
  • the size of the solder layer 122' can also be controlled by the pore size of the porous template 200 and its corresponding deposition process, and the like. Since the solder layers 122' are distributed on the top of the metal nanowires 121, the plurality of solder layers 122' are also arranged in an array, and the arrangement method is the same as that of the metal nanowires 121.
  • the thickness of the solder layer 122' may be 1 ⁇ m-20 ⁇ m.
  • a solder layer with a suitable thickness can form a low thermal resistance metal-to-metal interconnection between the metal nanowires 121 and the heat dissipation cover 20 , which can effectively improve the nail welding performance between the heat dissipation cover 20 and the metal nanowires 121 without excessive heat dissipation.
  • High thermal resistance it can also protect the metal nanowires 121 to prevent the metal nanowires 121 from being remelted and deformed during the welding process.
  • the length of the metal nanowire 121 may be 10-400 times, preferably 20-300 times, the thickness of the solder layer 122'.
  • the material of the solder layer 122' may be pure tin plating or lead-free tin-based alloy plating.
  • the lead-free tin-based alloy plating layer may not be limited to include Sn-Ag alloy, Sn-Cu alloy, Sn-Bi alloy, and the like. These coatings do not contain Pb, are environmentally friendly, and have good ductility and solderability.
  • the solder layer made of Sn-Ag alloy has faster plating speed, better uniformity, smoother surface morphology of the plating layer, and a smoother connection interface without holes.
  • the nano-through holes 200a of the porous template 200 are filled with metal nanowires 121 and solder layers 122' in sequence.
  • the metal nanowires 121 are close to the metal underlayer 11, and the sum of the thicknesses of the metal nanowires 121 and the solder layer 122' may be less than or equal to the depth of the nanovias 200a of the porous template.
  • the sum of the thicknesses of the metal nanowires 121 and the solder layer 122' is 21 ⁇ m-1020 ⁇ m, and further may be 21 ⁇ m-320 ⁇ m.
  • step S31 when cutting the wafer intermediate structure shown in (b) of FIG. 5, the active surface of the wafer 10' can be placed upward, and cutting is performed according to the cutting mark line marked on the active surface, Get multiple small cubes.
  • the overall structure of the obtained small squares is similar to that in FIG. 5( b ), except that the cross section of each small square is square, while the cross section of the structure shown in FIG. 5( b ) is circular.
  • the porous template is removed, and a plurality of encapsulated cores as shown in Fig. 5(c) can be obtained.
  • porous template 5 includes a chip 10 , a metal base layer 11 disposed on one side surface of the chip 10 , and metal nanowires 121 arranged on the metal base layer 11 at intervals, and the metal nanowires 121 are away from A solder layer 122 ′ is also provided at one end of the metal underlayer 11 .
  • porous template is a porous silicon template, an AAO template or a track etching membrane, it can be removed by dry ion etching.
  • the porous template is a track etched film, it can also be dissolved by an organic solvent, and the morphology of the metal nanowires can be better maintained.
  • the porous template When the porous template is an AAO template, it can also be removed by at least one template remover from NaOH, phosphoric acid, sulfuric acid, oxalic acid, etc. At this time, attention should be paid to the selected metal bottom layer 11, metal nanowires 121 and solder layer 122' Resistant to these template removers as needed.
  • the porous template on the wafer intermediate structure shown in (b) in FIG. 5 may also be removed first, and then cut to obtain a plurality of templates as shown in (c) in FIG. 5 . the packaged kernel shown.
  • the above-mentioned solder layer 122' may be formed by coating on the metal nanowires 121 of the encapsulation core.
  • Specific coating methods may include brushing or dipping.
  • the substrate 100 of the package has a first surface 100a and a second surface 100b that are oppositely disposed.
  • the chip 10 may be mounted on the first surface 100 a of the substrate 100 through solder bumps 101 .
  • the chip 10 is attached to the substrate 100 in a “flip-chip” manner, with the active surface of the chip 10 facing the substrate 100 . That is, all the solder bumps 101 on the chip 10 are located on the lower surface of the chip (the side to be connected with the substrate 100 , the active surface).
  • the chip 10 is attached to the substrate 100 by reflowing the solder bumps 101 .
  • the underfill material 102 may also be coated on the gaps of the solder bumps 101 to fill the space between the chip 10 and the substrate 100 to achieve a more stable connection.
  • the underfill material 102 may be epoxy, thermoplastic adhesive, or any other suitable type of underfill material.
  • the heat dissipation cover 20 has an open end, and the connection between the open end of the heat dissipation cover 20 and the first surface 100a of the substrate can be realized by gluing or welding. That is, in FIG. 4 , the connection part 201 between the heat dissipation cover 20 and the substrate 100 may be an adhesive layer or a welding part.
  • the heat dissipation top side will directly contact the metal connection structure 121 or directly contact the above-mentioned solder layer 122 ′, and the heat dissipation cover 20 will generate a certain downward pressure on the metal connection structure 121 .
  • the metal connection structure 121 may be bent to a certain extent, as shown in step S40 in FIG. 4 .
  • the above-mentioned solder layer 122' may also be formed by coating or dip coating on the metal connection structure 121 of the package core.
  • the welding between the metal connection structure 121 and the heat dissipation cover 20 may be achieved by remelting the solder layer 122' (see FIG. 5 ) on the metal connection structure 121.
  • the soldering portion 122 at this time may be a reaction alloy layer formed by the reaction between the material of the heat dissipation cover 20 and the solder layer, or may include the reaction alloy layer and the residual solder layer in sequence, wherein the residual solder layer is close to the metal connection structure 121 .
  • a surface treatment layer (not shown in FIG. 4 ) may be pre-plated on the area where the heat dissipation cover 20 and the metal connection structure 121 are to be connected.
  • the heat dissipation cover 20 includes a heat dissipation cover body and a surface treatment layer disposed on the inner surface of the heat dissipation top side of the heat dissipation cover.
  • the surface treatment layer can form an intermetallic compound (IMC, Intermetallic Compound) with the solder layer, which can improve the welding performance of the heat dissipation cover 20 and the connecting structure 121, and can improve the anti-oxidation performance of the formed welding part 122, effectively preventing the normal environment Oxidized during storage and packaging processes.
  • the soldering portion 122 may include a residual surface treatment layer, a reaction alloy layer and a residual solder layer in sequence, but the thicknesses of the residual surface treatment layer and the residual solder layer may be 0.
  • the reaction alloy layer is the surface treatment and the solder layer. reaction is formed.
  • the surface treatment layer may be Sn coating, Ni coating, Au coating, NiAu coating, NiPdAu coating and the like.
  • the surface treatment layer may be an electroless Ni plating immersion gold Au layer, an electroless Ni plating electroless Au plating layer, or an electroless Ni plating electroless plating Pd immersion Au layer, or the like.
  • the thickness of the surface treatment layer may be 0.03 ⁇ m-25 ⁇ m. In some embodiments, the thickness of the surface treatment layer may be 0.1 ⁇ m-20 ⁇ m. In other embodiments, the thickness of the surface treatment layer is 0.5 ⁇ m-15 ⁇ m. In some other embodiments, the thickness of the surface treatment layer is 1 ⁇ m-5 ⁇ m.
  • the improvement of welding performance and oxidation resistance can be taken into account, without increasing the plating cost of the surface treatment layer.
  • a flux may be pre-coated on the area where the heat dissipation cover 20 and the metal connection structure 121 are to be connected.
  • the flux can remove oxides on the soldering surface (specifically, the surface of the solder layer and the surface of the heat dissipation cover, etc.), prevent the reoxidation of the soldering surface, reduce the surface tension of the material to be soldered, and improve the soldering strength.
  • the flux is selected from one or more of SF64, SF36, NC 5070, SURF 20, TACFlux 025, etc., but not limited thereto.
  • the flux can be applied either to the inner surface of the heat dissipation top side of the heat dissipation cover 20 or to the solder layer 122' on the metal connection structure 121.
  • the above-mentioned surface treatment layer may still be plated on the heat dissipation cover 20 before the flux is applied on the heat dissipation cover 20 .
  • solder paste containing flux may also be directly coated on the inner surface of the heat dissipation cover 20 on the heat dissipation side.
  • the coated solder paste may not be limited to one or more of SAC305 (Sn96.5/Ag3/Cu0.5), SAC307 (Sn99/Ag0.3/Cu0.7) and the like.
  • the method may further include: plastic sealing the substrate 100 on which the chip 10 and the heat dissipation cover 20 are mounted with a plastic sealing mold and a plastic sealing material to form a plastic package. After being plastic-sealed, the heat-dissipating top of the heat-dissipating cover 20 is exposed from the plastic-sealing body, so as to conduct the heat generated by the chips inside the packaging body to the outside of the packaging body.
  • the plastic encapsulation material of the present application can be various plastic encapsulation materials commonly used in the field of semiconductor encapsulation, such as epoxy resin.
  • a specific plastic sealing process may be to inject a liquid plastic sealing material into a plastic sealing cavity of a plastic sealing mold, and obtain a plastic sealing body after the liquefied epoxy resin is cured.
  • the metal connection structure is formed on the back of the wafer and then cut, and then the metal connection structure and the heat dissipation cover are welded together.
  • the preparation method has simple process and low cost. Low cost, high production efficiency, suitable for industrial batch preparation.
  • the metal connection structure has good thermal conductivity and good flexibility, which can fully conduct the heat generated during the use of the chips in the package to the heat dissipation cover, and at the same time, the overall package has better anti-warping ability, High quality and reliability.
  • the embodiment of the present application further provides a terminal, where the terminal has a built-in integrated circuit package as described in the embodiment of the present application.
  • the terminal can be various handheld devices with wireless communication functions (such as various mobile phones, tablet computers), vehicle-mounted devices (such as driving recorders), wearable devices (such as smart watches), computing devices (such as notebook computers) ) or other processing equipment connected to a wireless modem, as well as various forms of user equipment (UE), mobile station (MS), terminal device, etc.
  • wireless communication functions such as various mobile phones, tablet computers
  • vehicle-mounted devices such as driving recorders
  • wearable devices such as smart watches
  • computing devices such as notebook computers
  • UE user equipment
  • MS mobile station
  • terminal device etc.
  • FIG. 6 is a schematic structural diagram of a terminal 400 according to an embodiment of the present application.
  • the terminal 400 includes a housing 401 assembled outside the terminal, and a circuit board and a battery (not shown in the figure) inside the housing 401, wherein the integrated circuit package provided by the above embodiments of the present application is provided on the circuit board.
  • the housing 401 may include a display screen assembled on the front side of the terminal and a back cover assembled on the back side, a battery may be fixed inside the back cover, and the battery is electrically connected to the circuit board for supplying power to the circuit board of the terminal 400 .
  • the above-mentioned terminal 400 includes the above-mentioned integrated circuit package, the heat generated during the operation of the terminal can be fully released, the use temperature of the terminal is not high, and the terminal has high quality reliability and long service life.

Abstract

La présente demande concerne, selon certains modes de réalisation, un élément d'encapsulation de circuit intégré, comprenant un substrat, ainsi qu'une puce et un couvercle de dissipation de chaleur qui sont disposés séquentiellement sur le substrat. La puce est située dans un espace de réception fermé et formé par le couvercle de dissipation de chaleur et le substrat. Une couche de fondation métallique et une pluralité de structures de connexion métalliques, qui sont agencées à intervalles, sont disposées sur la surface d'un côté de la puce opposé au substrat. Les structures de connexion métalliques sont des tôles métalliques ou des fils métalliques. Deux côtés de chaque tôle métallique ou deux extrémités de chaque fil métallique sont connectés à la couche de fondation métallique et au couvercle de dissipation de chaleur. Les structures de connexion métalliques agencées à intervalles sur la partie arrière de la puce servent de TIM pour la connexion de la puce et du couvercle de dissipation de chaleur, ce qui permet d'assurer simultanément une haute conductivité thermique et une excellente flexibilité, augmentant ainsi la fiabilité de la qualité de l'élément d'encapsulation. La présente demande concerne en outre un procédé de préparation de l'élément d'encapsulation de circuit intégré décrit, et une borne.
PCT/CN2021/074398 2021-01-29 2021-01-29 Élément d'encapsulation de circuit intégré, son procédé de préparation et borne WO2022160245A1 (fr)

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CN202180091460.8A CN116806368A (zh) 2021-01-29 2021-01-29 集成电路封装件及其制备方法和终端
PCT/CN2021/074398 WO2022160245A1 (fr) 2021-01-29 2021-01-29 Élément d'encapsulation de circuit intégré, son procédé de préparation et borne

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107946254A (zh) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 集成散热结构的硅基扇出型封装及晶圆级封装方法
JP2018093114A (ja) * 2016-12-06 2018-06-14 株式会社東芝 半導体装置
CN109786336A (zh) * 2017-11-13 2019-05-21 华为技术有限公司 封装结构及电子装置
CN111128912A (zh) * 2019-12-23 2020-05-08 海光信息技术有限公司 封装结构及其制备方法
CN111900142A (zh) * 2020-09-04 2020-11-06 星科金朋半导体（江阴）有限公司 一种芯片的封装结构及其封装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018093114A (ja) * 2016-12-06 2018-06-14 株式会社東芝 半導体装置
CN109786336A (zh) * 2017-11-13 2019-05-21 华为技术有限公司 封装结构及电子装置
CN107946254A (zh) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 集成散热结构的硅基扇出型封装及晶圆级封装方法
CN111128912A (zh) * 2019-12-23 2020-05-08 海光信息技术有限公司 封装结构及其制备方法
CN111900142A (zh) * 2020-09-04 2020-11-06 星科金朋半导体（江阴）有限公司 一种芯片的封装结构及其封装方法

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