WO2022160098A1 - Appareil et procédé de test de puce - Google Patents

Appareil et procédé de test de puce Download PDF

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Publication number
WO2022160098A1
WO2022160098A1 PCT/CN2021/073821 CN2021073821W WO2022160098A1 WO 2022160098 A1 WO2022160098 A1 WO 2022160098A1 CN 2021073821 W CN2021073821 W CN 2021073821W WO 2022160098 A1 WO2022160098 A1 WO 2022160098A1
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WO
WIPO (PCT)
Prior art keywords
chip
speed
circuit board
test
loopback circuit
Prior art date
Application number
PCT/CN2021/073821
Other languages
English (en)
Chinese (zh)
Inventor
王伟君
孙斌
宋海永
李亚
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/073821 priority Critical patent/WO2022160098A1/fr
Priority to CN202180082492.1A priority patent/CN116601503A/zh
Publication of WO2022160098A1 publication Critical patent/WO2022160098A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present application relates to the field of chip testing, and in particular, to a chip testing device and a chip testing method.
  • the chip testing device is an indispensable device for chip testing.
  • the chip In the process of testing the chip through the chip test device, the chip is electrically connected to the circuit board through the chip test seat to realize the electrical signal transmission between the chip and the circuit board to complete the chip test; therefore, the performance of the chip test device is It directly affects the reliability and accuracy of the chip test results.
  • the circuit board is connected through the probe set in the chip test seat to test the chip; however, in the connection method using the probe, there will be an air gap (gap) at the connection between the probe and the chip and the circuit board, and The length of the probe is too large, so that the conductive path between the chip and the circuit board is too large, which makes it difficult to meet the testing requirements of high-frequency and high-speed chips.
  • Embodiments of the present application provide a chip testing device and a chip testing method, which can meet the testing requirements of high-frequency and high-speed chips.
  • the present application provides a chip testing device, including a chip testing seat, a main circuit board, and a high-speed loopback circuit board; wherein, the chip testing seat includes an upper surface and a lower surface arranged oppositely, and the chip testing seat is provided with a through-chip testing seat
  • the probe the lower end of the probe protrudes from the lower surface and is connected to the main circuit board, and the upper end of the probe protrudes from the upper surface to connect to the pins set in the low-speed area of the chip; the test surface of the high-speed loopback circuit board Connect to the pins set in the high-speed area of the chip by conductive glue.
  • a main circuit board is set for the low-speed area of the chip, and the main circuit board is connected to the pins of the low-speed area of the chip through probes, so as to satisfy the power supply of the chip and the IO communication in the low-speed area;
  • the high-speed loopback circuit board is set in the high-speed area of the chip, and the high-speed loopback circuit board is directly connected to the pins of the high-speed area of the chip through conductive glue, so that the high-speed loopback circuit is used to connect the transmitting pin and the receiving pin of the high-speed area of the chip.
  • the high-speed loopback test is carried out between the high-speed loopback circuit board and the independent high-speed loopback circuit board, which reduces the air gap (gap) between the high-speed loopback circuit board and the pins of the chip high-speed area.
  • the isolation, bandwidth and crimping stability of the high-speed area of the chip are improved; at the same time, due to the small thickness of the conductive adhesive, the conductive path is shortened; thus, the requirements for high-speed testing of the chip can be met.
  • the high-speed loopback circuit board is set separately from the main circuit board, so that it is only necessary to iteratively optimize the high-speed loopback circuit board when designing the circuit board, thereby reducing the iterative cost and speeding up. iteration time.
  • the chip testing device provided by the embodiment of the present application is used to independently set the high-speed circuit board and the main circuit board. In this way, only the pins in the high-speed area of the chip need to be connected by conductive glue, and a large number of pins in the low-speed area of the chip are connected by a spring probe with a large stroke, which can well meet the stability of the chip's repeated crimping, and then While meeting the isolation and bandwidth requirements in the high-speed testing stage, it also solves the problem of poor crimping stability caused by large chip deformation.
  • a high-speed loopback may be placed on the edge area of the upper surface of the chip test seat.
  • the probe is arranged in the area outside the recessed part; the test surface of the high-speed loopback circuit board faces the same direction as the upper surface.
  • the test surface of the chip when testing the chip, can be facing down, so as to connect the pins of the low-speed area of the chip to the main circuit board through the probe to meet the power supply of the chip and the IO communication of the low-speed area;
  • the conductive glue directly connects the pins of the high-speed area of the chip to the high-speed loopback circuit board, so as to connect the transmitting pins and receiving pins of the high-speed area of the chip through the high-speed loopback circuit board, so as to perform high-speed loopback to the high-speed area of the chip. test.
  • the concave portion may be a groove structure disposed on the edge region of the upper surface, and the high-speed loopback circuit board can be placed into the groove from the notch position of the groove and fixed.
  • the recessed portion may be a stepped structure disposed in the edge region of the upper surface; compared with the recessed portion using the grooved structure, the recessed portion adopts the stepped structure arrangement, because the upper and lower parts of the stepped structure are arranged in a stepped structure.
  • the sides are all open, which makes it easier to place and fix the high-speed loopback circuit board.
  • the high-speed loopback circuit board is fixed in the concave portion by a fixing member; for example, the high-speed loopback circuit board can be fixed in the concave portion by a fixing member such as a screw fixing or a slot.
  • the high-speed loopback circuit board and the main circuit board may be arranged on opposite sides of the chip, respectively. On both sides, and set the test surface of the high-speed loopback circuit board to the side of the main circuit board.
  • the main circuit board when testing the chip, can be connected to the pins of the low-speed area of the chip through probes from the underside of the chip to meet the power supply of the chip and the IO communication in the low-speed area; the high-speed loopback circuit board It can be directly connected with the pins of the high-speed area from the upper side of the chip through conductive glue, so as to connect the transmitting pins and receiving pins of the high-speed area of the chip through the high-speed loopback circuit board, so as to perform high-speed loopback to the high-speed area of the chip. test.
  • the aforementioned high-speed loopback circuit board may be provided with a loopback circuit (or loopback wiring); in this case, the transmit pin and receive pin of the high-speed area of the chip are connected by the loopback circuit. connection, so as to realize the high-speed loopback test of the chip through the high-speed loopback circuit board.
  • the chip testing device may further include a connector connected to the high-speed loopback circuit board, and the connector is used to perform a loopback test on the chip through the high-speed loopback circuit board; in this case, the connector The high-speed loopback test of the chip is realized through the connector and the high-speed loopback circuit board by connecting the transmitting pin and the receiving pin in the high-speed area of the chip through the wiring arranged in the high-speed loopback circuit board.
  • the chip testing device further includes a chip clamping structure; the chip clamping structure is located at the edge of the upper surface of the chip test seat; the chip is fixed by the chip clamping structure, thereby ensuring the high-speed area of the chip. and low-speed areas with stable connections between the high-speed loopback circuit board and the main circuit board, respectively.
  • the above-mentioned probe may be a spring probe; the spring probe includes an upper moving needle, a lower moving needle, and a spring connecting the upper moving needle and the lower moving needle.
  • the above-mentioned probe can be a special-shaped probe; the special-shaped probe can include an upper moving needle, a lower moving needle, and a conductive elastic rubber strip connecting the upper moving needle and the lower moving needle.
  • the above-mentioned conductive adhesive can be anisotropic conductive adhesive; using the vertical conductivity of the conductive adhesive, each pin in the high-speed area of the chip and each test on the test surface of the high-speed loopback circuit board can be connected by the conductive adhesive.
  • the contact points correspond to electrical connections respectively to ensure the independent transmission of signals between each pin and the test contact point.
  • the embodiment of the present application also provides a chip testing method using the chip testing device provided in any of the foregoing possible implementation manners, and the chip testing method may include:
  • the pins set in the low-speed area of the chip are connected to the main circuit board through probes, and the pins set in the high-speed area of the chip are connected to the high-speed loopback circuit board through conductive glue to test the chip.
  • the pins based on the high-speed area of the chip are connected to the high-speed loopback circuit board through conductive glue, which has the advantages of high isolation and bandwidth, as well as short strokes (ie short conductive paths), which can meet the requirements of high-speed testing of the chip.
  • the low-speed test only provides chip power supply and interface functions due to the low requirements for isolation, bandwidth and conductive paths.
  • the probe connection method between the low-speed area of the chip and the main circuit board can also meet the requirements. test requirements.
  • FIG. 1 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a chip testing apparatus provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a chip test socket provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a chip test socket provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a chip testing apparatus provided by an embodiment of the present application.
  • a method, system, product or device is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the process, method, product or device.
  • “Top”, “bottom”, “left”, “right”, etc. are only used relative to the orientation of components in the drawings, these directional terms are relative concepts, and they are used for relative description and clarification , which may vary according to the orientation in which the components in the figures are placed.
  • the embodiment of the present application provides a chip testing device, which can meet the testing requirements of high isolation and bandwidth, and short conductive paths during high-speed testing of chips.
  • test object that is, the chip
  • chip testing apparatus provided by the embodiment of the present application
  • a chip 1 (which may also be referred to as a high-frequency high-speed chip) has a high-speed region 11 and a low-speed region 12 where pins p (which may also be referred to as pins) are set.
  • the pins set in the low-speed area 12 mainly include power supply pins, ground pins and control interface pins, etc., and the data transmission rate of the pins in the low-speed area 12 is usually lower than 500Mhz;
  • the pins set in the high-speed area 11 mainly include High-speed signal transmission pins, and the data transmission rate of the pins of high-speed area 11 is usually higher than 500Mhz.
  • the pins of the low-speed area 12 of the chip and the pins of the high-speed area 11 may be located on the same test surface (or the pin surface); in this case, the high-speed area 11
  • the pins of 1 can be set on a certain side area of the chip test surface, and other areas of the test surface can be set areas of the pins of the low-speed area 12 .
  • the pins of the low-speed area 12 of the chip and the pins of the high-speed area 11 may be located on two opposite test surfaces; in this case, the high-speed area of the chip
  • the pins of 11 can be set on a certain side area of a test surface (first test surface) of the chip, and the pins of the low-speed area 12 of the chip can be set on another test surface (second test surface) of the chip; of course,
  • the pins of the low-speed area 12 may be distributed on the entire second test surface, or may be distributed in a partial area of the second test surface, which is not limited in this application.
  • the pin p can be a solder ball pin; for example, in some possible implementations In this way, the pin p may be a gold-plated pad.
  • the high-speed area 11 and the low-speed area 12 may use pins p in the same setting form, or may use pins p in different setting forms; for example, in some possible implementations, both the high-speed area 11 and the low-speed area 12 may use solder balls
  • the low-speed area 12 may use solder ball pins
  • the high-speed area 11 may use gold-plated pads; this application does not limit this.
  • the pins in the low-speed area 12 of the chip do not have very high requirements on conductive paths, isolation and bandwidth, while the pins in the high-speed area 11 of the chip do not have very high requirements.
  • the chip testing device It includes a main circuit board 2 (also called a low-speed circuit board), a high-speed loopback circuit board 3 and a chip test socket 4 .
  • the chip test seat 4 includes an upper surface S1 and a lower surface S2 disposed opposite to each other, the upper surface S1 faces upward, and the lower surface S2 faces downward.
  • the main circuit board 2 can be connected to the test machine, and the test machine can supply power to the chip 1 through the main circuit board 2 and realize the interface function (that is, IO (input/output, input and output) communication), and
  • the high-speed loopback test is performed between the transmitting pin and the receiving pin in the high-speed area of the chip through the high-speed loopback circuit board 3, so as to complete the test of the chip.
  • the loopback test is a test in which the signal sent from the transmitter of the communication device is returned (looped back) to the receiver of the communication device, which determines whether the device is running normally or not.
  • the method of determining the failed node in the network in the embodiment of the present application, the high-speed loopback circuit board 3 is used to connect the transmitting pin and the receiving pin of the high-speed area of the chip, so that the high-speed loopback test is performed on the high-speed area of the chip to detect Data transmission quality in the high-speed area of the chip.
  • the recessed portion C is provided on the edge region of the upper surface S1 of the chip test seat 4, and the high-speed loopback circuit board 3 is arranged in the recessed portion C; and the test contact point of the high-speed loopback circuit board 3 faces toward , that is, the direction of the test surface of the high-speed loopback circuit board 3 and the upper surface S1 are the same, and both of them are facing upward.
  • the chip test seat 4 is provided with at least one probe 41 in the area outside the recess C, the probe 41 penetrates the chip test seat 4 , and the upper end of the probe 41 protrudes out of the chip test seat 4 The lower end of the probe 41 protrudes from the lower surface S2 of the chip test seat 4 , and the lower end of the probe 41 is connected to the main circuit board 2 .
  • a plurality of probes 41 may be provided in the chip test seat 4 in an area outside the recess C.
  • the setting form of the probe 41 is not limited, and may be set as required in practice.
  • the above-mentioned probe 41 can be a pogo pin, and the pogo pin is connected to the upper moving needle and the lower moving needle through a spring;
  • the moving pin is connected to the pin of the low-speed area 12 of the chip, and the lower moving pin is connected to the test contact point of the main circuit board 2, so as to realize the connection between the main circuit board 2 and the high-speed area 11 of the chip.
  • the probe 41 can be a special-shaped probe; illustratively, the special-shaped probe can be connected to the upper moving needle and the lower moving needle through a conductive elastic tape; in this case, the probe 41
  • the connection between the main circuit board 2 and the high-speed area 11 of the chip is realized through the connection between the upper moving pin and the pin of the low-speed area 12 of the chip, and the connection between the lower moving pin and the test contact point of the main circuit board 2 .
  • the test surface of the chip 1 can be faced down, so that the pins of the low-speed area 12 of the chip are connected to the main circuit board 2 through the probes 41 to meet the power supply of the chip and the low-speed area.
  • IO communication directly connect the pins of the chip high-speed area 11 to the high-speed loopback circuit board 3 through the conductive glue R (rubber), so as to connect the transmit pins and receive pins of the chip high-speed area through the high-speed loopback circuit board 3.
  • the high-speed loopback test is performed on the high-speed area of the chip; the conductive glue R is used to directly connect the independently set high-speed loopback circuit board 3 and the pins of the high-speed area of the chip, so that the high-speed loopback circuit board 3 and the chip can be directly connected.
  • the air gap (gap) of the pins of the high-speed area 11 is reduced, thereby improving the isolation, bandwidth and crimping stability of the high-speed area of the chip, and at the same time, due to the small thickness of the conductive adhesive R, the conductive path is shortened; High-speed test requirements for chips.
  • each pin of the chip high-speed area 11 can be electrically connected to each test contact point on the test surface of the high-speed loopback circuit board 3 through the conductive adhesive R, respectively. In order to ensure the independent transmission of signals between each pin and the test contact point.
  • the concave portion C may be a groove structure provided in the edge region of the upper surface S1 of the chip test seat 1; Position the high-speed loopback circuit board 3 into the groove and fix it.
  • the concave portion C may be a stepped structure disposed in the edge region of the upper surface S1 of the chip test seat 1 .
  • the recessed portion C shown in FIG. 5 adopts a stepped structure. It is easier to place and fix the high-speed loopback circuit board 3 .
  • the high-speed loopback circuit board 3 may be fixed in the recessed portion C by a fixing member, and the present application does not limit the arrangement of the fixing member.
  • the high-speed loopback circuit board 3 can be fixed in the concave portion C by screws; for another example, in some possible implementations, the high-speed loopback circuit board 3 can be fixed in the concave through a card slot Section C.
  • the chip testing apparatus includes Main circuit board 2 (ie low-speed circuit board), high-speed loopback circuit board 3, chip test socket 4.
  • the chip test seat 4 includes an upper surface S1 and a lower surface S2 disposed opposite to each other, the upper surface S1 faces upward, and the lower surface S2 faces downward.
  • the main circuit board 2 When testing the chip, the main circuit board 2 can be connected to the testing machine, and the testing machine can supply power to the chip 1 through the main circuit board 2 and realize the interface function (that is, IO (input/output, input and output) communication), And through the high-speed loopback circuit board 3, a high-speed loopback test can be performed between the launch pin and the high-speed connection pin of the chip high-speed area 11, so as to complete the chip test.
  • IO input/output, input and output
  • the chip test seat 4 is provided with at least one probe 41 (for example, there may be multiple), the probe 41 penetrates through the chip test seat 4 , and the upper end of the probe 41 protrudes out of the chip test seat 4 , the lower end of the probe 41 protrudes from the lower surface S2 of the chip test seat 4 , and the lower end of the probe 41 is connected to the main circuit board 2 .
  • the probe 41 penetrates through the chip test seat 4 , and the upper end of the probe 41 protrudes out of the chip test seat 4 , the lower end of the probe 41 protrudes from the lower surface S2 of the chip test seat 4 , and the lower end of the probe 41 is connected to the main circuit board 2 .
  • the above-mentioned probe 41 may be a pogo pin; in some possible implementations, the above-mentioned probe 41 may be a special-shaped probe; but not limited to this;
  • the spring probe and the special-shaped probe reference may be made to the relevant description in Implementation 1, which will not be repeated here.
  • the high-speed loopback circuit board 3 and the main circuit board 2 are distributed on the upper and lower sides of the chip 1, and the test contact points of the high-speed loopback circuit board 3 face downward, that is, the high-speed loopback circuit board 3
  • the test surface of the circuit board 3 faces the side of the main circuit board 2; in this case, the main circuit board 2 can be connected to the pin p of the low-speed area 12 of the chip through the probe 41 from the lower side of the chip 1 to meet the requirements of the chip.
  • the high-speed loopback circuit board 3 can be directly connected with the pin p of the high-speed area 11 from the upper side of the chip 1 through the conductive glue R to connect the transmitting pin and the receiving pin of the high-speed area 11.
  • the high-speed loopback test is performed between the high-speed loopback circuit boards 3 and the high-speed area 11 of the chip, which are independently set up, and the conductive adhesive R is used to directly connect them, which can make the air gap between the high-speed loopback circuit board 3 and the pins of the high-speed area 11 of the chip. (gap) is reduced, thereby improving the isolation, bandwidth, and crimping stability of the high-speed area of the chip.
  • the conductive path is shortened, thereby meeting the testing requirements of the high-speed area 11 of the chip.
  • the main circuit board 2 is set for the low-speed area 12 of the chip, and the main circuit board 2 is connected to the chip through the probes 41
  • the high-speed loopback circuit board 3 is set for the high-speed area 11 of the chip, and the independently set high-speed loopback circuit board 3 is directly connected to the pins of the high-speed area 11 of the chip through the conductive glue R.
  • the air gap (gap) between the high-speed loopback circuit board 3 and the pins of the high-speed area of the chip 11 is reduced, thereby improving the isolation, bandwidth and crimping stability of the high-speed area of the chip.
  • the high-speed loopback circuit board 3 is set separately from the main circuit board 1, so that it is only necessary to iteratively optimize the high-speed loopback circuit board when designing the circuit board, thereby reducing the iterative cost. Speed up iteration time.
  • the chip testing device provided by the embodiment of the present application is used to independently set the high-speed circuit board and the main circuit board. In this way, only the pins in the high-speed area of the chip need to be connected by conductive glue, and a large number of pins in the low-speed area of the chip are connected by a spring probe with a large stroke, which can well meet the stability of the chip's repeated crimping, and then While meeting the isolation and bandwidth requirements in the high-speed testing stage, it also solves the problem of poor crimping stability caused by large chip deformation.
  • the high-speed loopback circuit board 3 in the chip testing apparatus provided by the embodiments of the present application (including the aforementioned first and second embodiments)
  • it is necessary to lead the emission of the high-speed area of the chip to The external loopback test is performed from the pin to the receiving pin through the high-speed loopback circuit board 3 .
  • a loopback circuit (or loopback wiring) may be provided in the high-speed loopback circuit board 3, in this case, the transmission of the chip high-speed area 11 is guided by the loopback circuit.
  • the pin is directly electrically connected to the receiving pin, so that the high-speed loopback test of the chip 1 is realized through the high-speed loopback circuit board 3 .
  • a connector connected to the high-speed loopback circuit board 3 may be provided in the chip testing device, and the connector connects the high-speed area of the chip through the traces provided in the high-speed loopback circuit board 3 .
  • the transmitting pin of 11 is connected to the receiving pin, that is, the high-speed loopback test of the chip 1 is realized through the connector and the high-speed loopback circuit board 3 .
  • the connector can be connected by SMA (sub miniature coaxial cable, sub-miniature coaxial cable).
  • the connector can be a SMP (sub miniature push on, sub miniature push on) connector.
  • the chip clamping structure 5 is set at the edge position of the surface S1, and the chip 1 is fixed by the chip clamping structure 5, so as to ensure that the high-speed area 11 and the low-speed area 12 of the chip are connected to the high-speed loopback circuit board 3 and the main circuit board 2 respectively. stable connection between.
  • the fixed height of the chip clamping structure 5 can be adjusted, that is, the fixed height of the chip can be adjusted through the chip clamping structure 5 .
  • the chip clamping structure can be used for the chip testing device in the second embodiment. 5. Fix the high-speed loopback circuit board 3; of course, in some other possible implementation manners, a fixing structure may also be separately provided for the high-speed loopback circuit board 3.
  • the conductive adhesive R can be attached to the high-speed loopback circuit board 3 before the chip test.
  • the test surface of the chip is attached to the test contacts of the high-speed loopback circuit board 3, and then the pins of the high-speed area 11 of the chip are connected with the conductive adhesive R.
  • the chip testing device provided by the embodiment of the present application can be applied to chips of various packaging types.
  • the chip 1 may be a ball grid array (BGA) package, a land grid Array, LGA), etc., which are not limited in this application.
  • BGA ball grid array
  • LGA land grid Array
  • the embodiment of the present application also provides a chip testing method about the aforementioned chip testing device.
  • the testing method includes:
  • the pins set in the low-speed area 12 of the chip are connected to the main circuit board 2 through the upper end of the probe 41, and the pins set in the high-speed area 11 of the chip are connected to the high-speed loopback circuit board 3 through the conductive glue R, so that the chip 1 is connected. test.
  • the pins based on the high-speed area 11 of the chip are connected to the high-speed loopback circuit board 3 through the conductive glue R, which has the advantages of high isolation and bandwidth, and short stroke (ie, short conductive path), etc., so as to meet the requirements of the chip 1
  • the pin connection method can also meet the test requirements.
  • the high-speed test and the low-speed test are performed on the chip in no particular order by using the chip testing apparatus provided in the embodiment of the present application, and the two may be performed synchronously or asynchronously, which is not limited in the present application.
  • high-speed testing and low-speed testing of the chip may be performed simultaneously; for another example, in some possible implementations, the low-speed testing of the chip may be performed first, and then the high-speed testing of the chip may be performed.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

L'invention concerne un appareil et un procédé de test de puce, qui se rapportent au domaine des tests de puce, et qui peuvent répondre aux exigences de test d'une puce haute fréquence à grande vitesse. L'appareil de test de puce comprend une base de test de puce (4), une carte de circuit principal (2) et une carte de circuit en boucle à haute vitesse (3), la base de test de puce (4) comprenant une surface supérieure (S1) et une surface inférieure (S2), qui sont disposées de manière opposée, et une sonde (41) pénétrant dans la base de test de puce (4) est disposée dans la base de test de puce (4) ; l'extrémité inférieure de la sonde (41) fait saillie de la surface inférieure (S2) et est connectée à la carte de circuit imprimé principale (2), et l'extrémité supérieure de la sonde (41) fait saillie de la surface supérieure (S1), de manière à se connecter à une broche disposée dans une région à basse vitesse (12) d'une puce (1) ; et une face de test de la carte de circuit imprimé en boucle à haute vitesse (3) est connectée à une broche disposée dans une région à haute vitesse (11) de la puce (1) au moyen d'un adhésif conducteur (R).
PCT/CN2021/073821 2021-01-26 2021-01-26 Appareil et procédé de test de puce WO2022160098A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/CN2021/073821 WO2022160098A1 (fr) 2021-01-26 2021-01-26 Appareil et procédé de test de puce
CN202180082492.1A CN116601503A (zh) 2021-01-26 2021-01-26 芯片测试装置及芯片测试方法

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Application Number Priority Date Filing Date Title
PCT/CN2021/073821 WO2022160098A1 (fr) 2021-01-26 2021-01-26 Appareil et procédé de test de puce

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CN117172202B (zh) * 2023-09-05 2024-05-07 苏州异格技术有限公司 一种芯粒自检及芯粒间通信恢复方法、装置
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