WO2022148004A1 - 位线接触结构的形成方法及半导体结构 - Google Patents

位线接触结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022148004A1
WO2022148004A1 PCT/CN2021/108202 CN2021108202W WO2022148004A1 WO 2022148004 A1 WO2022148004 A1 WO 2022148004A1 CN 2021108202 W CN2021108202 W CN 2021108202W WO 2022148004 A1 WO2022148004 A1 WO 2022148004A1
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WO
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Prior art keywords
bit line
line contact
opening
mask layer
hole portion
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PCT/CN2021/108202
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English (en)
French (fr)
Inventor
石夏雨
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长鑫存储技术有限公司
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Priority to US17/676,283 priority Critical patent/US20220216217A1/en
Publication of WO2022148004A1 publication Critical patent/WO2022148004A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a bit line contact structure and a semiconductor structure.
  • Dynamic random access memory is a semiconductor memory widely used in multi-computer systems. With the continuous reduction of the feature size of semiconductor integrated circuit devices, the area of the contact hole is also getting smaller and smaller, and the contact resistance of the contact hole is getting larger and larger, and the reduction of the contact resistance is urgently required by the current integrated circuit manufacturing process.
  • the prior art mainly increases the contact area through the "fin type" structure to reduce the contact resistance. If the depth of the contact hole is not well controlled, it is easy to cause poor short circuit between word lines (WL).
  • a method for forming a bit line contact structure includes the following steps: sequentially disposing a first mask layer and a second mask on a surface of a substrate on which word lines and a protective layer are formed layer and photoresist, patterning the photoresist; using the patterned photoresist to sequentially etch the second mask layer and the first mask layer to form through the first mask film layer and the first opening of the second mask layer; a sacrificial layer is arranged on the surface of the second mask layer, the sacrificial layer covers the sidewall and bottom wall of the first opening, and the width of the opening is smaller than that of the first opening.
  • the bit line contact hole is used to form a bit line contact structure, the The bit line contact hole includes a first hole portion and a second hole portion, the first hole portion is opened on the surface of the protective layer, the diameter of the second hole portion is smaller than that of the first hole portion, and is opened at the surface of the protection layer. the bottom wall of the first hole portion.
  • the semiconductor structure includes a substrate, and a bit line contact structure is formed on a surface of the substrate, and the bit line contact structure includes a bit line contact hole,
  • the bit line contact hole includes a first hole portion and a second hole portion, the first hole portion is opened on the surface of the substrate, and the diameter of the second hole portion is smaller than that of the first hole portion, and is opened on the bottom wall of the first hole portion.
  • the bit line contact hole forms a topography including a first hole portion and a second hole portion, and opens in the first hole
  • the second hole part of the bottom wall of the part has a smaller hole diameter than the first hole part. Accordingly, with the bit line contact structure formed by the present disclosure, the contact area of the bit line contact hole is increased and the contact resistance is reduced, and the prior art problems such as poor short circuit between word lines can be avoided.
  • the present disclosure can improve the product performance of the semiconductor structure with a relatively simple process and low cost.
  • FIG. 1 is a cross-sectional view of a semiconductor structure in a bit line direction in a step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 2 is a cross-sectional view of the semiconductor structure shown in FIG. 1 in a word line direction;
  • FIG. 3 is a cross-sectional view of the semiconductor structure in the direction of the bit line in another step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 4 is a cross-sectional view of the semiconductor structure shown in FIG. 3 in a word line direction;
  • FIG. 5 is a cross-sectional view of the semiconductor structure in the direction of the bit line in another step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 6 is a cross-sectional view of the semiconductor structure shown in FIG. 5 in a word line direction;
  • FIG. 7 is a cross-sectional view of the semiconductor structure in the direction of the bit line in another step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 8 is a cross-sectional view of the semiconductor structure shown in FIG. 7 in a word line direction
  • FIG. 9 is a cross-sectional view of the semiconductor structure in the direction of the bit line in another step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 10 is a cross-sectional view of the semiconductor structure shown in FIG. 9 in a word line direction;
  • FIG. 11 is a cross-sectional view of the semiconductor structure along the bit line direction in another step of a method for forming a bit line contact structure according to an exemplary embodiment
  • FIG. 12 is a cross-sectional view of the semiconductor structure shown in FIG. 11 in a word line direction;
  • FIG. 13 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 to FIG. 12 it is representative to show the cross-sectional views of the semiconductor structure in each main step of the method for forming the bit line contact structure proposed by the present disclosure.
  • the method for forming a bit line contact structure proposed in the present disclosure is described by taking the application to a dynamic random access memory device as an example.
  • Those skilled in the art can easily understand that, in order to apply the related designs of the present disclosure to the fabrication process of other types of semiconductor structures, various modifications, additions, substitutions, deletions or other modifications may be made to the following specific embodiments. variations, which are still within the scope of the principles of the method of forming the bit line contact structure proposed by the present disclosure.
  • FIG. 1 , FIG. 3 , FIG. 5 , FIG. 7 , FIG. 9 , and FIG. 11 respectively show several main steps of the formation process proposed by the present disclosure, the semiconductor structure along the extension direction X of the bit line.
  • Cutaway view. 2 , 4 , 6 , 8 , 10 , and 12 respectively show the cross-sectional views of the semiconductor structure along the extension direction Y of the word line 200 in several main steps of the formation process proposed by the present disclosure.
  • Fig. 1 and Fig. 2 belong to the same step
  • Fig. 3 and Fig. 4 belong to the same step
  • Fig. 5 and Fig. 6 belong to the same step
  • Fig. 7 and Fig. 8 belong to the same step
  • FIG. 13 which typically shows a top view of the semiconductor structure proposed in the present disclosure
  • the above-mentioned cross-sectional views along the extension direction X of the bit line are the semiconductor structure shown in FIG. 13 along the bit line.
  • the cross-sectional structure diagrams taken along the extension direction X, the above-mentioned cross-sectional views along the extension direction Y of the word line 200 are the cross-sectional structure diagrams of the semiconductor structure along the extension direction Y of the word line 200 shown in FIG. 13 .
  • the process details, process sequence and functional relationship of each main step of the method for forming a bit line contact structure proposed by the present disclosure will be described in detail below with reference to the above drawings.
  • the method for forming a bit line contact structure proposed by the present disclosure includes the following steps:
  • a first mask layer 400, a second mask layer 500 and a photoresist 600 are sequentially arranged on the surface of the substrate 100 on which the word lines 200 and the protective layer 300 are formed, and the photoresist 600 is patterned;
  • patterned photoresist 600 to sequentially etch the second mask layer 500 and the first mask layer 400 to form a first opening 401 penetrating the first mask layer 400 and the second mask layer 500;
  • a sacrificial layer 700 is disposed on the surface of the second mask layer 500, and the sacrificial layer 700 covers the sidewall and bottom wall of the first opening 401 to form a second opening 701 with an opening width smaller than that of the first opening 401;
  • Corresponding third openings 301 are formed by etching on the surface of the protective layer 300 using the second openings 701, and the remaining sacrificial layer 700 is removed at the same time to expose the first openings 401;
  • the first opening 401 and the third opening 301 are used to etch through the protective layer 300 and form a bit line contact hole 110 on the surface of the substrate 100.
  • the bit line contact hole 110 is used to form a contact structure (such as a plug, etc.) of the bit line.
  • the line contact hole 110 includes a first hole portion 111 and a second hole portion 112 .
  • the first hole portion 111 is opened on the surface of the protective layer 300 , and the diameter of the second hole portion 112 is smaller than that of the first hole portion 111 and is opened in the first hole portion. 111 bottom wall.
  • the present disclosure can control the topography of the bit line contact hole 110 , so that the bit line contact hole 110 forms a topography including the first hole portion 111 and the second hole portion 112 and opens in the first hole portion 111
  • the second hole portion 112 of the bottom wall of the second hole has a smaller hole diameter than the first hole portion 111 . Accordingly, the contact area of the bit line contact hole 110 can be increased, thereby reducing the contact resistance, and avoiding problems in the prior art such as poor short circuit between the word lines 200 .
  • the present disclosure can improve the product performance of the semiconductor structure with a relatively simple process and low cost.
  • the semiconductor structure includes the substrate 100 , the first mask layer 400 , the second mask layer 500 and the photoresist 600 .
  • the word line 200 is formed in the substrate 100 , and the word line 200 adopts the structure of the buried word line 200 , and a protective layer 300 is provided on the surface of the substrate 100 .
  • the first mask layer 400 is disposed on the surface of the protective layer 300
  • the second mask layer 500 is disposed on the surface of the first mask layer 400
  • the photoresist 600 is disposed on the surface of the second mask layer 500 .
  • the photoresist 600 is patterned to form a photoresist opening pattern 601 , and the photoresist opening pattern 601 roughly corresponds to the two word lines of the substrate 100 . Above the section between 200.
  • the first mask layer 300 surface of the substrate 100 may be arranged by a deposition process.
  • mask layer 400 an atomic layer deposition process may be selected for the above-mentioned deposition process.
  • a second mask layer may be arranged on the surface of the first mask layer 400 through a deposition process.
  • Film layer 500 may be selected for the above-mentioned deposition process.
  • the photoresist 600 may be arranged on the surface of the second mask layer 500 through a deposition process. Further, an atomic layer deposition process may be selected for the above-mentioned deposition process.
  • the photoresist 600 may be patterned through exposure and development processes to The photoresist 600 is formed into a photoresist opening pattern 601 .
  • the material of the first mask layer 400 may include Si 3 N 4 , SiO at least one of 2 .
  • the second mask layer 500 includes an anti-reflection coating.
  • the semiconductor structure includes the substrate 100 , the first mask layer 400 , the second mask layer 500 and the photoresist 600 .
  • the patterned photoresist 600 is used to etch the second mask layer 500 first, and part of the second mask layer 500 is removed to form an opening, and the opening of the second mask layer 500 corresponds to the photoresist layer 500.
  • the photoresist opening pattern 601 will be used as a part of the first opening 401 formed in the subsequent process.
  • the above etching process can also be understood as transferring the photoresist opening pattern 601 to the second mask layer 500 .
  • a plasma etching process or a dry etching process may be used to control the material
  • the etching selectivity ratio is selected, and part of the second mask is removed, specifically, the part of the second mask layer 500 exposed by the photoresist opening pattern 601 is removed by etching, that is, the part of the second mask layer 500 located in the photoresist layer is removed by etching. Parts below the glue opening pattern 601 are removed by etching.
  • the semiconductor structure includes the substrate 100 , the first mask layer 400 , the second mask layer 500 and the photoresist 600 .
  • the first mask layer 400 is continuously etched, and part of the first mask layer 400 is removed to form an opening.
  • the first mask layer 400 The opening corresponds to the photoresist opening pattern 601 and the above-mentioned opening of the second mask layer 500 , in other words, the above-mentioned etching process can also be understood as transferring the opening of the second mask layer 500 to the first mask layer 400 superior.
  • the photoresist 600 is completely consumed and removed.
  • the second mask layer 500 and the first mask layer 400 are The openings together define a first opening 401 , and the first opening 401 penetrates through the second mask layer 500 and the first mask layer 400 .
  • a plasma etching process or a dry etching process may be used to control the material
  • the etching selectivity ratio is selected, and part of the first mask is removed, specifically, the part of the first mask layer 400 exposed by the photoresist opening pattern 601 and the second mask layer 500 is removed by etching, and the remaining part is removed by etching.
  • the photoresist 600 is removed.
  • the semiconductor structure includes the substrate 100 , the first mask layer 400 , the second mask layer 500 and the sacrificial layer 700 .
  • the sacrificial layer 700 covers the surface of the second mask layer 500 and covers the sidewall and bottom wall of the first opening 401 .
  • the sacrificial layer 700 fills the first opening 401 , and the portion of the sacrificial layer 700 located in the first opening 401 forms a second opening 701 , and the opening width of the second opening 701 is smaller than that of the first opening 401 . .
  • a deposition process may be performed on the surface of the second mask layer 500 and the side of the first opening 401 The walls and bottom walls are provided with a sacrificial layer 700 .
  • an atomic layer deposition process may be selected for the above-mentioned deposition process.
  • the opening width of the second opening 701 may be 30% of the opening width of the first opening 401 ⁇ 70%, eg 30%, 45%, 62%, 70%, etc.
  • the ratio of the opening width of the second opening 701 to the opening width of the first opening 401 may also be less than 30%, or may be greater than 70%, and less than 100%, such as 28%, 74%, 90%, etc., are not limited to this embodiment.
  • the material of the sacrificial layer 700 may include at least one of Si 3 N 4 and SiO 2 .
  • the semiconductor structure is in the step of “etching the protective layer 300 and forming the third opening 301 ” along the extension direction X of the bit line and along the word line 200 , respectively.
  • the semiconductor structure includes the substrate 100 and the first mask layer 400 .
  • the protective layer 300 on the surface of the substrate 100 is etched by using the second opening 701, and part of the surface of the protective layer 300 is removed to form a third opening 301, and the third opening 301 corresponds to the second opening 301. Opening 701.
  • the remaining sacrificial layer 700 is simultaneously removed to expose the first opening 401 . So far, the sacrificial layer 700 is completely consumed and removed.
  • the second opening 701 and the third opening 301 together define a substantially inverted “convex” opening space structure. In other words, the third opening 301 is opened in the second opening 301
  • the bottom wall of the opening 701 (the bottom wall of the second opening 701 is formed by the protective layer 300 ).
  • a self-aligned etching process may be used to partially remove the surface of the protective layer 300 corresponding to the first opening. Part of the second opening 701 .
  • the semiconductor structure includes the substrate 100 .
  • the protective layer 300 and the substrate 100 are etched by using the first opening 401 and the third opening 301, the part of the protective layer 300 located under the first opening 401 is removed, and the substrate is partially removed.
  • the portion of the substrate 100 under the first opening 401 is partially removed, and the portion of the substrate 100 under the third opening 301 is partially removed, thereby forming the bit line contact hole 110 .
  • the bit line contact hole 110 has a substantially inverted "convex" shape opening space structure.
  • the bit line contact hole 110 includes a first hole portion 111 and a second hole portion 112 .
  • the first hole portion 111 is opened on the surface of the protective layer 300
  • the second hole portion 112 is opened at the bottom wall of the first hole portion 111 . That is, the surface of the remaining portion of the substrate 100 below the first opening 401 forms the bottom wall of the first hole portion 111 , and the second hole portion 112 is opened to the surface of the substrate 100 .
  • the above etching process can also be understood as transferring the first opening 401 and the third opening 301 to the substrate 100 to form the bit line contact hole 110 .
  • the first hole portion 111 roughly corresponds to the first opening 401 (ie, corresponds to the photoresist opening pattern 601 ), and the second hole portion 112 roughly corresponds to the third opening 301 (ie, the second opening 701 ). That is, the diameter of the second hole portion 112 is smaller than that of the first hole portion 111 .
  • the hole diameter of the second hole portion 112 of the bit line contact hole 110 is compared with that of the first hole.
  • the ratio of the aperture of the portion 111 is approximately the same as the ratio of the opening width of the second opening 701 to the opening width of the first opening 401 .
  • the diameter of the second hole portion 112 may be 30% of the diameter of the first hole portion 111 . % ⁇ 70%, such as 30%, 45%, 62%, 70%, etc.
  • the ratio of the diameter of the second hole portion 112 to the diameter of the first hole portion 111 may also be less than 30%, or greater than 70%, and less than 100%, such as 28%, 74%, 90%, etc., are not limited to this embodiment.
  • the diameter of the bit line contact hole 110 may be larger than that of two adjacent word lines 200 the distance between.
  • the aperture diameter of the bit line contact hole 110 may be larger than the width of the active region 800 .
  • the side walls of the bit line contact hole 110 along the extension direction X of the bit line are respectively formed by the bit line contact hole 110 Shallow trench isolation 900 on both sides defines.
  • FIG. 13 a top view of the semiconductor structure proposed by the present disclosure is representatively shown.
  • the semiconductor structure proposed by the present disclosure is illustrated by taking a dynamic random access memory device as an example. It will be easily understood by those skilled in the art that, in order to apply the related designs of the present disclosure to other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes may be made to the following specific embodiments. Variations are still within the scope of the principles of semiconductor structures presented in this disclosure.
  • the semiconductor structure proposed in the present disclosure includes a substrate 100 , a surface of the substrate 100 is formed with a bit line contact structure, and the bit line contact structure includes a bit line contact hole 110 .
  • the bit line contact hole 110 includes a first hole portion 111 and a second hole portion 112 , the first hole portion 111 is opened on the surface of the substrate 100 , the diameter of the second hole portion 112 is smaller than that of the first hole portion 111 , and is open on the bottom wall of the first hole portion 111 .
  • the diameter of the second hole portion 112 may be 30% ⁇ 70% of the diameter of the first hole portion 111 , such as 30%, 45%, 62%, 70%, and the like.
  • the ratio of the diameter of the second hole portion 112 to the diameter of the first hole portion 111 may also be less than 30%, or greater than 70%, and less than 100%, such as 28%, 74%, 90%, etc., are not limited to this embodiment.
  • the diameter of the bit line contact hole 110 may be larger than the distance between two adjacent word lines 200 .
  • the aperture of the bit line contact hole 110 may be larger than the width of the active region 800 .
  • sidewalls on both sides of the bit line contact hole 110 along the extension direction X of the bit line are respectively defined by shallow trench isolations 900 on both sides of the bit line contact hole 110 .
  • the method for forming the bit line contact structure proposed in the present disclosure controls the topography of the bit line contact hole, so that the bit line contact hole forms the topography including the first hole portion and the second hole portion, and is opened in the The second hole portion of the bottom wall of the first hole portion has a diameter smaller than that of the first hole portion. Accordingly, with the bit line contact structure formed by the present disclosure, the contact area of the bit line contact hole is increased and the contact resistance is reduced, and the prior art problems such as poor short circuit between word lines can be avoided.
  • the present disclosure can improve the product performance of the semiconductor structure with a relatively simple process and low cost.

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Abstract

本公开提出一种位线接触结构的形成方法，包含以下步骤：在形成有字线和保护层的衬底的表面依次设置第一、第二掩膜层及光刻胶，图案化光刻胶；利用图案化后的光刻胶依次刻蚀第二、第一掩膜层，形成贯穿第一、第二掩膜层的第一开口；在第二掩膜层表面设置牺牲层，牺牲层覆盖第一开口的侧壁和底壁，形成开口宽度小于第一开口的第二开口；利用第二开口在保护层表面刻蚀形成相对应的第三开口，并同时去除剩余的牺牲层，以暴露出第一开口；利用第一开口和第三开口刻蚀贯穿保护层并在衬底的表面形成位线接触孔，位线接触孔包含第一孔部和第二孔部，第一孔部开口于保护层表面，第二孔部的孔径小于第一孔部的孔径，并开口于第一孔部的底壁。

Description

位线接触结构的形成方法及半导体结构
相关申请的交叉引用
本公开要求基于2021年1月5日提交的申请号为202110005940.X的中国申请“位线接触结构的形成方法及半导体结构”的优先权，通过援引将其全部内容并入本文中。
技术领域
本公开涉及半导体技术领域，特别涉及一种位线接触结构的形成方法及半导体结构。
背景技术
随着半导体集成电路器件特征尺寸的不断缩小，动态随机存储器(Dynamic Random Access Memory，DRAM)的特征尺寸(Critical Dimension，CD)也越来越小，制程工艺越来越复杂，成本也越来越高，因此需要开发出简单稳定的制备工艺，以简化制造流程，节约成本，提高产品性能。
动态随机存储器是一种广泛应用多计算机系统的半导体存储器。随着半导体集成电路器件特征尺寸的不断缩小，接触孔面积也越来越小，接触孔的接触电阻越来越大，减小接触电阻被当前集成电路制造工艺迫切地需要。为适应上述需要，现有技术主要通过“鳍式”结构增大接触面积，以减少接触电阻，如果接触孔深度控制不佳，容易导致字线(Word Line，WL)间短路不良。
发明内容
本公开实施例的一个方面，提供一种位线接触结构的形成方法；其中，包含以下步骤：在形成有字线和保护层的衬底的表面依次设置第一掩膜层、第二掩膜层及光刻胶，图案化所述光刻胶；利用图案化后的所述光刻胶依次刻蚀所述第二掩膜层和所述第一掩膜层，形成贯穿所述第一掩膜层和所述第二掩膜层的第一开口；在所述第二掩膜层表面设置牺牲层，所述牺牲层覆盖所述第一开口的侧壁和底壁，形成开口宽度小于所述第一开口的第二开口；利用所述第二开口在所述保护层表面刻蚀形成相对应的第三开口，并同时去除剩余的所述牺牲层，以暴露出所述第一开口；利用所述第一开口和所述第三开口刻蚀贯穿所述保护层并在所述衬底的表面形成位线接触孔，所述位线接触孔用以形成位线的接触结构，所述位线接触孔包含第一孔部和第二孔部，所述第一孔部开口于所述保护层表面，所述第 二孔部的孔径小于所述第一孔部的孔径，并开口于所述第一孔部的底壁。
本公开实施例的另一个方面，提供一种半导体结构；其中，所述半导体结构包含衬底，所述衬底的表面形成有位线接触结构，所述位线接触结构包含位线接触孔，所述位线接触孔包含第一孔部和第二孔部，所述第一孔部开口于所述衬底的表面，所述第二孔部的孔径小于所述第一孔部的孔径，并开口于所述第一孔部的底壁。
由上述技术方案可知，本公开实施例提出的位线接触结构的形成方法及半导体结构的优点和积极效果在于：
本公开实施例提出的位线接触结构的形成方法，通过控制位线接触孔的形貌，使得位线接触孔形成包含第一孔部和第二孔部的形貌，且开口于第一孔部的底壁的第二孔部，具有比第一孔部更小的孔径。据此，通过本公开形成的位线接触结构，其位线接触孔的接触面积增大且接触电阻减小，能够避免字线间短路不良等现有技术问题。本公开能够以相对简单的制程和较低的成本，提高半导体结构的产品性能。
附图说明
图1是根据一示例性实施方式示出的一种位线接触结构的形成方法的一步骤中，半导体结构在位线方向的剖视图；
图2是图1示出的半导体结构在字线方向的剖视图；
图3是根据一示例性实施方式示出的一种位线接触结构的形成方法的另一步骤中，半导体结构在位线方向的剖视图；
图4是图3示出的半导体结构在字线方向的剖视图；
图5是根据一示例性实施方式示出的一种位线接触结构的形成方法的另一步骤中，半导体结构在位线方向的剖视图；
图6是图5示出的半导体结构在字线方向的剖视图；
图7是根据一示例性实施方式示出的一种位线接触结构的形成方法的另一步骤中，半导体结构在位线方向的剖视图；
图8是图7示出的半导体结构在字线方向的剖视图；
图9是根据一示例性实施方式示出的一种位线接触结构的形成方法的另一步骤中，半导体结构在位线方向的剖视图；
图10是图9示出的半导体结构在字线方向的剖视图；
图11是根据一示例性实施方式示出的一种位线接触结构的形成方法的另一步骤中， 半导体结构在位线方向的剖视图；
图12是图11示出的半导体结构在字线方向的剖视图；
图13是根据一示例性实施方式示出的一种半导体结构的俯视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
参阅图1至图12，其代表性地示出了本公开提出的位线接触结构的形成方法的各主要步骤中的半导体结构的剖视图。在该示例性实施方式中，本公开提出的位线接触结构的形成方法是以应用于动态随机存取存储器件为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体结构的制程工艺中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的位线接触结构的形成方法的原理的范围内。
具体而言，图1、图3、图5、图7、图9、图11分别示出了本公开提出的形成工艺的几个主要步骤中，半导体结构在沿位线的延伸方向X上的剖视图。并且，图2、图4、图6、图8、图10、图12分别示出了本公开提出的形成工艺的几个主要步骤中，半导体结构在沿字线200的延伸方向Y上的剖视图，且图1与图2属于同一步骤、图3与图4属于同一步骤、图5与图6属于同一步骤、图7与图8属于同一步骤、图9与图10属于同一步骤、图11与图12属于同一步骤。另外，配合参阅图13，其代表性地示出了本公开提出的半导体结构的俯视图，据此，上述沿位线的延伸方向X的各剖视图是半导体结构在图13示出的沿位线的延伸方向X上所作的剖视结构示意图，上述沿字线200的延伸方向Y的各剖视图是半导体结构在图13示出的沿字线200的延伸方向Y上所作的剖视结构示意图。以下将结合上述附图，对本公开提出的位线接触结构的形成方法的各主要步骤的工艺细节、制程顺序和功能关系进行详细说明。
如图1至图12所示，在本实施方式中，本公开提出的位线接触结构的形成方法包含以下步骤：
在形成有字线200和保护层300的衬底100的表面依次设置第一掩膜层400、第二掩膜层500及光刻胶600，图案化光刻胶600；
利用图案化后的光刻胶600依次刻蚀第二掩膜层500和第一掩膜层400，形成贯穿第一掩膜层400和第二掩膜层500的第一开口401；
在第二掩膜层500表面设置牺牲层700，牺牲层700覆盖第一开口401的侧壁和底壁，形成即开口宽度小于第一开口401的第二开口701；
利用第二开口701在保护层300表面刻蚀形成相对应的第三开口301，并同时去除剩余的牺牲层700，以暴露出所述第一开口401；
利用第一开口401和第三开口301刻蚀贯穿保护层300并在衬底100表面形成位线接触孔110，位线接触孔110用以形成位线的接触结构(例如插塞等)，位线接触孔110包含第一孔部111和第二孔部112，第一孔部111开口于保护层300表面，第二孔部112的孔径小于第一孔部111，并开口于第一孔部111的底壁。
通过上述工艺设计，本公开能够通过控制位线接触孔110的形貌，使得位线接触孔110形成包含第一孔部111和第二孔部112的形貌，且开口于第一孔部111的底壁的第二孔部112，具有比第一孔部111更小的孔径。据此能够增大位线接触孔110的接触面积，从而减小接触电阻，避免字线200间短路不良等现有技术问题。本公开能够以相对简单的制程和较低的成本，提高半导体结构的产品性能。
如图1和图2所示，其分别代表性地示出了半导体结构在“依次设置第一掩膜层400、第二掩膜层500和光刻胶600，图案化光刻胶600”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100、第一掩膜层400、第二掩膜层500和光刻胶600。其中，衬底100中形成有字线200，字线200采用埋入式字线200结构，衬底100表面设置有保护层300。第一掩膜层400设置于保护层300表面，第二掩膜层500设置于第一掩膜层400表面。光刻胶600设置于第二掩膜层500表面，光刻胶600经由图案化工艺形成光刻胶开口图案601，且该光刻胶开口图案601大致对应于衬底100的位于两根字线200之间的部分上方。
可选地，如图1和图2所示，在本实施方式中，对于“设置第一掩膜层400”的步骤而言，可以通过沉积工艺在衬底100的保护层300表面设置第一掩膜层400。进一步地，上述沉积工艺可以选择原子层沉积工艺。
可选地，如图1和图2所示，在本实施方式中，对于“设置第二掩膜层500”的步骤而言，可以通过沉积工艺在第一掩膜层400表面设置第二掩膜层500。进一步地，上述沉积工艺可以选择原子层沉积工艺。
可选地，如图1和图2所示，在本实施方式中，对于“设置光刻胶600”的步骤而言， 可以通过沉积工艺在第二掩膜层500表面设置光刻胶600。进一步地，上述沉积工艺可以选择原子层沉积工艺。
可选地，如图1和图2所示，在本实施方式中，对于“图案化光刻胶600”的步骤而言，可以通过曝光和显影工艺对光刻胶600进行图案化处理，以使光刻胶600形成光刻胶开口图案601。
可选地，如图1和图2所示，在本实施方式中，对于“设置第一掩膜层400”的步骤而言，第一掩膜层400的材质可以包含Si 3N 4、SiO 2的至少其中之一。
可选地，如图1和图2所示，在本实施方式中，对于“设置第二掩膜层500”的步骤而言，第二掩膜层500包含抗反射涂层。
如图3和图4所示，其分别代表性地示出了半导体结构在“利用光刻胶600刻蚀第二掩膜层500”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100、第一掩膜层400、第二掩膜层500和光刻胶600。其中，该步骤中是先利用图案化的光刻胶600对第二掩膜层500进行刻蚀，去除部分第二掩膜层500而形成开口，第二掩膜层500的该开口对应于光刻胶开口图案601，且将会作为后续制程中形成的第一开口401的一部分，换言之，上述刻蚀制程亦可理解为是将光刻胶开口图案601转移到第二掩膜层500上。
可选地，如图3和图4所示，在本实施方式中，对于“刻蚀第二掩膜层500”的步骤而言，可以通过等离子刻蚀工艺或者干法刻蚀工艺，控制材料刻蚀选择比，而将第二掩膜部分去除，具体是将第二掩膜层500的被光刻胶开口图案601暴露出的部分刻蚀去除，即将第二掩膜层500的位于光刻胶开口图案601下方的部分刻蚀去除。
如图5和图6所示，其分别代表性地示出了半导体结构在“刻蚀第一掩膜层400，形成第一开口401”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100、第一掩膜层400、第二掩膜层500和光刻胶600。其中，在利用光刻胶600刻蚀第二掩膜层500形成开口后，继续对第一掩膜层400进行刻蚀，去除部分第一掩膜层400而形成开口，第一掩膜层400的该开口对应于光刻胶开口图案601和第二掩膜层500的上述开口，换言之，上述刻蚀制程亦可理解为是将第二掩膜层500的开口转移到第一掩膜层400上。并且，在上述对第二掩膜层500和第一掩膜层400的刻蚀过程中，光刻胶600被完全消耗去除，此时第二掩膜层500和第一掩膜层400各自的开口共同定义出第一开口401，该第一开口401贯穿第二掩膜层500和第一掩膜层400。
可选地，如图5和图6所示，在本实施方式中，对于“刻蚀第一掩膜层400”的步骤而言，可以通过等离子刻蚀工艺或者干法刻蚀工艺，控制材料刻蚀选择比，而将第一掩膜部分去除，具体是将第一掩膜层400的被光刻胶开口图案601和第二掩膜层500暴露出的部分刻蚀去除，并将剩余的光刻胶600去除。
如图7和图8所示，其分别代表性地示出了半导体结构在“设置牺牲层700，形成第二开口701”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100、第一掩膜层400、第二掩膜层500和牺牲层700。其中，牺牲层700覆盖于第二掩膜层500的表面，并覆盖于第一开口401的侧壁和底壁。并且，牺牲层700为将第一开口401填满，而使牺牲层700的位于第一开口401内的部分形成第二开口701，该第二开口701的开口宽度小于第一开口401的开口宽度。
可选地，如图7和图8所示，在本实施方式中，对于“设置牺牲层700”的步骤而言，可以通过沉积工艺在第二掩膜层500表面和第一开口401的侧壁和底壁设置牺牲层700。进一步地，上述沉积工艺可以选择原子层沉积工艺。
可选地，如图7和图8所示，在本实施方式中，对于“设置牺牲层700”的步骤而言，第二开口701的开口宽度可以为第一开口401的开口宽度的30％～70％，例如30％、45％、62％、70％等。在其他实施方式中，第二开口701的开口宽度相比于第一开口401的开口宽度的占比亦可小于30％，或可大于70％，且小于100％，例如28％、74％、90％等，并不以本实施方式为限。
可选地，如图7和图8所示，在本实施方式中，对于“设置牺牲层700”的步骤而言，牺牲层700的材质可以包含Si 3N 4、SiO 2的至少其中之一。
如图9和图10所示，其分别代表性地示出了半导体结构在“刻蚀保护层300，形成第三开口301”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100和第一掩膜层400。其中，在形成第二开口701之后，利用第二开口701对衬底100表面的保护层300进行刻蚀，去除保护层300表面的部分而形成第三开口301，第三开口301对应于第二开口701。并且，在上述对保护层300的刻蚀过程中，同时去除剩余的牺牲层700，以暴露出第一开口401。至此，牺牲层700被完全消耗去除，此时的第二开口701与第三开口301共同定义出大致呈倒置的“凸”字型的开口空间结构，换言之，第三开口301是开口于第二开口701的底壁(第二开口701的底壁是由保护层300形成)。
可选地，如图9和图10所示，在本实施方式中，对于“形成第三开口301”的步骤而言，可以通过自对准刻蚀工艺部分去除保护层300表面的对应于第二开口701的部分。
如图11和图12所示，其分别代表性地示出了半导体结构在“形成位线接触孔110”的步骤中，沿沿位线的延伸方向X和沿字线200的延伸方向Y的剖视结构。具体而言，在上述步骤中，半导体结构包含衬底100。其中，在形成第三开口301之后，利用第一开口401和第三开口301对保护层300和衬底100进行刻蚀，去除保护层300的位于第一开口401下方的部分，部分去除衬底100的位于第一开口401下方的部分，并部分去除衬底100的位于第三开口301下方的部分，以此形成位线接触孔110。该位线接触孔110大致呈倒置的“凸”字型的开孔空间结构。其中，位线接触孔110包含第一孔部111和第二孔部112，该第一孔部111开口于保护层300表面，该第二孔部112开口于第一孔部111的底壁。即，衬底100的位于第一开口401下方的剩余部分的表面形成第一孔部111的底壁，且第二孔部112开口于衬底100的该表面。换言之，上述刻蚀制程亦可理解为是将第一开口401和第三开口301转移到衬底100上，而形成位线接触孔110。根据上述制程，可知第一孔部111大致对应于第一开口401(即对应于光刻胶开口图案601)，且第二孔部112大致对应于第三开口301(即第二开口701)，即，第二孔部112的孔径小于第一孔部111。
可选地，基于第一孔部111与第一开口401及第二孔部112与第二开口701的对应关系，可知位线接触孔110的第二孔部112的孔径相比于第一孔部111的孔径的占比，是与上述第二开口701的开口宽度相比于第一开口401的开口宽度的占比大致相同。基于上述关于第二开口701的开口宽度相比于第一开口401的开口宽度的占比的说明，在本实施方式中，第二孔部112的孔径可以为第一孔部111的孔径的30％～70％，例如30％、45％、62％、70％等。在其他实施方式中，第二孔部112的孔径相比于第一孔部111的孔径的占比亦可小于30％，或可大于70％，且小于100％，例如28％、74％、90％等，并不以本实施方式为限。
可选地，在本实施方式中，对于“形成位线接触孔110”的步骤而言，在沿位线的延伸方向X上，位线接触孔110的孔径可以大于相邻两个字线200之间的距离。
可选地，在本实施方式中，对于“形成位线接触孔110”的步骤而言，在沿字线200的延伸方向Y上，位线接触孔110的孔径可以大于有源区800的宽度。
可选地，在本实施方式中，对于“形成位线接触孔110”的步骤而言，位线接触 孔110沿位线的延伸方向X上的两侧侧壁，分别由位线接触孔110两侧的浅沟槽隔离900界定。
基于上述对本公开提出的位线接触结构的形成方法的一示例性实施方式的详细说明，以下将结合图13，对本公开提出的半导体结构的一示例性实施方式进行说明。
参阅图13，其代表性地示出了本公开提出的半导体结构的俯视图。在该示例性实施方式中，本公开提出的半导体结构是以动态随机存取存储器件为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体结构中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的半导体结构的原理的范围内。
如图13所示，同时配合参阅图11和图12，本公开提出的半导体结构包含衬底100，衬底100表面形成有位线接触结构，位线接触结构包含位线接触孔110。其中，位线接触孔110包含第一孔部111和第二孔部112，第一孔部111开口于衬底100表面，第二孔部112的孔径小于第一孔部111的孔径，并开口于第一孔部111的底壁。
可选地，在本实施方式中，第二孔部112的孔径可以为第一孔部111的孔径的30％～70％，例如30％、45％、62％、70％等。在其他实施方式中，第二孔部112的孔径相比于第一孔部111的孔径的占比亦可小于30％，或可大于70％，且小于100％，例如28％、74％、90％等，并不以本实施方式为限。
可选地，在本实施方式中，在沿位线的延伸方向X上，位线接触孔110的孔径可以大于相邻两个字线200之间的距离。
可选地，在本实施方式中，在沿字线200的延伸方向Y上，位线接触孔110的孔径可以大于有源区800的宽度。
可选地，在本实施方式中，位线接触孔110沿位线的延伸方向X上的两侧侧壁，分别由位线接触孔110两侧的浅沟槽隔离900界定。
综上所述，本公开提出的位线接触结构的形成方法，通过控制位线接触孔的形貌，使得位线接触孔形成包含第一孔部和第二孔部的形貌，且开口于第一孔部的底壁的第二孔部，具有比第一孔部更小的孔径。据此，通过本公开形成的位线接触结构，其位线接触孔的接触面积增大且接触电阻减小，能够避免字线间短路不良等现有技术问题。本公开能够以相对简单的制程和较低的成本，提高半导体结构的产品性能。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所 以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (15)

  1. 一种位线接触结构的形成方法，包含以下步骤：
    在形成有字线和保护层的衬底的表面依次设置第一掩膜层、第二掩膜层及光刻胶，图案化所述光刻胶；
    利用图案化后的所述光刻胶依次刻蚀所述第二掩膜层和所述第一掩膜层，形成贯穿所述第一掩膜层和所述第二掩膜层的第一开口；
    在所述第二掩膜层表面设置牺牲层，所述牺牲层覆盖所述第一开口的侧壁和底壁，形成开口宽度小于所述第一开口的第二开口；
    利用所述第二开口在所述保护层表面刻蚀形成相对应的第三开口，并同时去除剩余的所述牺牲层，以暴露出所述第一开口；
    利用所述第一开口和所述第三开口刻蚀贯穿所述保护层并在所述衬底的表面形成位线接触孔，所述位线接触孔用以形成位线的接触结构，所述位线接触孔包含第一孔部和第二孔部，所述第一孔部开口于所述保护层表面，所述第二孔部的孔径小于所述第一孔部的孔径，并开口于所述第一孔部的底壁。
  2. 根据权利要求1所述的位线接触结构的形成方法，其中，在图案化所述光刻胶的步骤中，是对所述光刻胶进行曝光和显影，以使所述光刻胶形成光刻胶开口图案。
  3. 根据权利要求2所述的位线接触结构的形成方法，其中，在刻蚀所述第二掩膜层的步骤中，是通过干法刻蚀工艺去除所述第二掩膜层的被所述光刻胶开口图案暴露出的部分。
  4. 根据权利要求3所述的位线接触结构的形成方法，其中，在刻蚀所述第一掩膜层的步骤中，是通过干法刻蚀工艺去除所述第一掩膜层的被所述光刻胶开口图案和所述第二掩膜层暴露出的部分，并将所述光刻胶去除。
  5. 根据权利要求1所述的位线接触结构的形成方法，其中，在设置所述牺牲层的步骤中，是通过原子层沉积工艺在所述第二掩膜层表面形成所述牺牲层。
  6. 根据权利要求1所述的位线接触结构的形成方法，其中，在刻蚀所述保护层的步骤中，是通过自对准刻蚀工艺去除所述牺牲层和部分所述保护层。
  7. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，在设置所述牺牲层的步骤中，所述第二开口的开口宽度为所述第一开口的开口宽度的30％～70％。
  8. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，在沿所述位线的延伸方向上，所述位线接触孔的孔径大于相邻两个所述字线之间的距离。
  9. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，在沿所述字线的延伸方向上，所述位线接触孔的孔径大于有源区的宽度。
  10. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，所述位线接触孔在沿所述位线延伸方向上的两侧侧壁，分别由所述位线接触孔两侧的浅沟槽隔离界定。
  11. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，所述第一掩膜层的材质包含Si 3N 4、SiO 2的至少其中之一。
  12. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，所述第二掩膜层包含抗反射涂层。
  13. 根据权利要求1～6任一项所述的位线接触结构的形成方法，其中，所述牺牲层的材质包含Si 3N 4、SiO 2的至少其中之一。
  14. 一种半导体结构，其中，所述半导体结构包含衬底，所述衬底的表面形成有位线接触结构，所述位线接触结构包含位线接触孔，所述位线接触孔包含第一孔部和第二孔部，所述第一孔部开口于所述衬底的表面，所述第二孔部的孔径小于所述第一孔部的孔径，并开口于所述第一孔部的底壁。
  15. 根据权利要求14所述的半导体结构，其中，所述第二孔部的孔径为所述第一孔部 的孔径的30％～70％。
PCT/CN2021/108202 2021-01-05 2021-07-23 位线接触结构的形成方法及半导体结构 WO2022148004A1 (zh)

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