WO2022145454A1 - 半導体基板、半導体デバイス、電子機器 - Google Patents

半導体基板、半導体デバイス、電子機器 Download PDF

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Publication number
WO2022145454A1
WO2022145454A1 PCT/JP2021/048835 JP2021048835W WO2022145454A1 WO 2022145454 A1 WO2022145454 A1 WO 2022145454A1 JP 2021048835 W JP2021048835 W JP 2021048835W WO 2022145454 A1 WO2022145454 A1 WO 2022145454A1
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Prior art keywords
layer
mask
semiconductor
semiconductor substrate
opening
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PCT/JP2021/048835
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English (en)
French (fr)
Japanese (ja)
Inventor
剛 神川
克明 正木
敏洋 小林
雄一郎 林
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Kyocera Corp
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Kyocera Corp
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Priority to KR1020257013181A priority Critical patent/KR20250065711A/ko
Priority to JP2022573107A priority patent/JP7817190B2/ja
Priority to CN202180087640.9A priority patent/CN116783335A/zh
Priority to EP21915312.9A priority patent/EP4273306A4/en
Priority to US18/270,077 priority patent/US20240072198A1/en
Priority to KR1020237021620A priority patent/KR102800880B1/ko
Publication of WO2022145454A1 publication Critical patent/WO2022145454A1/ja
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    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/12—Pendeo epitaxial lateral overgrowth [ELOG], e.g. for growing GaN based blue laser diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3202—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth
    • H01S5/320275—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth semi-polar orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP

Definitions

  • the present invention relates to a semiconductor substrate, a semiconductor device, and an electronic device.
  • Patent Document 1 discloses a method of forming a GaN-based semiconductor layer on a GaN-based substrate or a dissimilar substrate (for example, a sapphire substrate) by using an ELO (Epitaxial Lateral Overgrowth) method.
  • the semiconductor substrate according to the present disclosure includes a main substrate having a lattice constant different from that of a GaN-based semiconductor, a mask layer located above the main substrate and having an opening and a mask portion, and a seed that overlaps the opening in a plan view.
  • a semiconductor layer including a GaN-based semiconductor arranged on the seed portion and the mask portion is provided, and the semiconductor layer is located between the opening portion and the center of the mask portion in a plan view.
  • the upper surface of the effective portion includes at least one low defect region having a size of 10 ⁇ m in the first direction along the width direction of the opening and 10 ⁇ m in the second direction orthogonal to the first direction. In the low defect region, linear defects by the CL method are not measured.
  • FIG. 1 is a plan view and a sectional view showing the configuration of a semiconductor substrate according to the present embodiment.
  • the semiconductor substrate 10 semiconductor wafer
  • the base layer 4 including the seed portion 3S and the base layer 4.
  • a semiconductor including a nitride semiconductor for example, a GaN-based semiconductor
  • a mask layer 6 having an opening KS and a mask portion 5 overlapping with the seed portion 3S in a plan view.
  • the base layer 4 may be the base portion 4
  • the mask layer 6 may be the mask 6 (mask pattern)
  • the semiconductor layer 8 may be the semiconductor portion 8.
  • the opening KS of the mask layer 4 may have a tapered shape (a shape in which the width becomes narrower toward the base layer 4 side).
  • the width of the opening KS and the width of the mask portion 5 can be expressed for the upper surface of the mask layer. However, it is not limited to this.
  • the GaN-based semiconductor is a semiconductor containing a gallium atom (Ga) and a nitrogen atom (N), and typical examples thereof include GaN, AlGaN, AlGaInN, and InGaN.
  • the semiconductor layer 8 may be a doped type (for example, an n-type including a donor) or a non-doped type.
  • the semiconductor substrate means a substrate including a nitride semiconductor (for example, a GaN-based semiconductor), and the material of the main substrate 1 may be a semiconductor or a non-semiconductor.
  • the main substrate 1 and the base layer 4 may be referred to as a base substrate, and the main substrate 1, the base layer 4 and the mask layer 6 may be referred to as a template substrate 7.
  • the semiconductor layer 8 is formed by the ELO (Epitaxial Lateral Overgrowth) method starting from the seed portion 3S exposed from the opening KS. Therefore, the semiconductor layer 8 may be referred to as an ELO semiconductor layer 8.
  • the thickness direction of the semiconductor layer 8 is the Z direction (the ⁇ 0001> direction of the GaN-based crystal).
  • the opening KS has a longitudinal shape, and its width direction is the X direction ( ⁇ 11-20> direction of the GaN-based crystal).
  • FIG. 2 is a cross-sectional view showing another configuration of the semiconductor substrate according to the present embodiment.
  • the semiconductor substrate 10 may have a configuration in which a main substrate 1, a base layer 4, a mask layer 6, a semiconductor layer 8, and a functional layer 9 are provided in this order.
  • the semiconductor substrate 10 a plurality of layers are laminated on the main substrate, and the stacking direction can be set to "upward". Further, viewing the semiconductor substrate 10 with a line of sight parallel to the normal direction of the semiconductor substrate 10 can be referred to as "planar view”.
  • the main substrate A different type of substrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1.
  • the dissimilar substrate include a silicon (Si) substrate, a sapphire (Al 2 O 3 ) substrate, a silicon carbide (SiC) substrate, a ScAlMgO 4 substrate, and the like.
  • the plane orientation of the main substrate 1 is, for example, the (111) plane of the silicon substrate, the (0001) plane of the sapphire substrate, and the 6H-SiC (0001) plane of the SiC substrate. These are examples, and any substrate and plane orientation in which the semiconductor layer 8 can be grown by the ELO method may be used.
  • the main substrate may be a self-standing substrate (for example, a wafer cut out from a bulk crystal).
  • a buffer layer 2 for example, an AlN layer
  • a seed layer 3 for example, a GaN-based semiconductor
  • the buffer layer 2 is a melting suppression layer capable of reducing the direct contact between the main substrate 1 and the seed layer 3 from melting with each other. It also has the effect of increasing the crystallinity of the seed layer 3.
  • the AlN layer is formed to a thickness of about 10 nm to about 5 ⁇ m by using, for example, the MOCVD method.
  • the main substrate 1 that does not melt with the seed layer 3 which is a GaN-based semiconductor it is possible to configure the buffer layer 2 without the buffer layer 2.
  • a silicon substrate or the like is used for the main substrate 1, it melts with a GaN-based semiconductor which is a seed layer. Therefore, for example, by providing a buffer layer 2 such as an AlN layer, melting is reduced.
  • the seed layer 3 for example, an AlGaN layer can be used.
  • the seed layer 3 includes a seed portion 3S that overlaps with the opening KS of the mask layer 6.
  • a graded layer whose Al composition approaches GaN can be used.
  • the graded layer is, for example, a laminated body provided with an Al 0.7 Ga 0.3 N layer, which is the first layer, and an Al 0.3 Ga 0.7 N layer, which is the second layer, in order from the AlN layer side. Is.
  • the graded layer can be easily formed by the MOCVD method, and may be composed of three or more layers. By using the graded layer for the seed layer 3, the stress from the main substrate 1 which is a different kind of substrate can be relaxed.
  • the seed layer 3 can be configured to include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the uppermost layer of the graded layer, which is the seed layer 3, may be a GaN layer.
  • the base layer 4 may be composed of only one of the buffer layer 2 and the seed layer 3.
  • a self-standing (for example, a single crystal wafer cut out from a bulk crystal) SiC substrate is used as the main substrate 1, and a mask layer 6 is formed on the SiC substrate without forming a base layer to form a template substrate. You can also do it.
  • a mask portion 5 and an opening KS are formed in the mask layer 6.
  • the opening KS has a function of a growth start opening that exposes the seed layer 3 and starts the growth of the semiconductor layer 8, and the mask portion 5 has a function of a selective growth mask that causes the semiconductor layer 8 to grow laterally. May be.
  • the opening KS is a portion (non-forming portion) of the mask layer 6 (mask pattern 6) without the mask portion 5, and does not have to be surrounded by the mask portion 5.
  • an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon nitride film (SiON), or a titanium nitride (TiNx) film can be used.
  • a silicon oxide film having a thickness of about 50 nm to 4 ⁇ m is formed on the entire surface of the base layer 4 by a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. Then, the resist is patterned using a photolithography method to form a resist having a striped opening.
  • a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) and buffered hydrofluoric acid (BHF) to form an opening KS, and the resist is removed by organic cleaning to obtain an opening KS and a mask.
  • the mask layer 6 having the portion 5 is formed.
  • resist is applied and patterned to remove the resist in the region to be the opening KS, and the opening KS is formed by using the dry etching method. Is also possible.
  • the opening KS has a longitudinal shape, and a plurality of opening KS are periodically arranged in the a-axis direction (first direction X) of the ELO semiconductor layer 8 with a first cycle.
  • the width of the opening KS shall be about 0.1 ⁇ m to 20 ⁇ m.
  • the ELO semiconductor layer 8 can be easily peeled off in the subsequent process. Further, the area of the effective portion with few surface defects can be increased.
  • a laminated film containing the above materials for example, a laminated film including a silicon oxide film and a silicon nitride film can also be used.
  • ELO semiconductor layer film formation As the semiconductor layer 8 (ELO semiconductor layer 8), a GaN-based semiconductor layer is formed by the ELO method.
  • the ELO semiconductor layer 8 may be made of GaN, and the seed portion 3S may contain GaN.
  • the template substrate 7 including the main substrate 1, the base layer 4, and the mask layer 6 is introduced into the MOCVD apparatus, and a GaN layer is formed on the template substrate 7.
  • growth pressure 50 kPa
  • TMG trimethylgallium
  • NH 3 15 slm
  • the semiconductor layer 8 In the film formation of the semiconductor layer 8, it is preferable to reduce the mutual reaction between the semiconductor layer 8 and the mask portion 5 and maintain a state in which the semiconductor layer 8 and the mask portion 5 are in contact with each other by van der Waals force. That is, the semiconductor layer 8 and the mask portion 5 are mainly in contact with each other by van der Waals force.
  • the adjacent ELO semiconductor layers 8 grown from the adjacent openings KS may be associated with each other, or may form a gap near the center of the mask portion 5 by not associating with each other.
  • the entire surface of the substrate can form a flat surface.
  • the stress (compressive stress or tensile stress) generated when the main substrate 1 whose main component is a material different from that of the nitride semiconductor is used can be more effectively relaxed in the gap. , The occurrence of defects and the occurrence of cracks can be effectively suppressed.
  • the semiconductor layer 8 has an effective portion YS (a portion constituting the element portion in a subsequent process) located between the opening KS and the center 5C of the mask portion in a plan view.
  • the portion located on the seed portion 3S (the portion having many through dislocations) becomes the ineffective portion NS. That is, the semiconductor layer 8 includes an effective portion YS having relatively few through dislocations and an ineffective portion NS having relatively many through dislocations.
  • the non-effective part NS is a dislocation inheritance part and has more dislocations than the effective part YS (dislocation non-inheritance part), but may be used as a part of the device.
  • the functional layer 9 includes an active layer
  • a portion (light emitting portion) in which electrons and holes are bonded can be provided so as to overlap the effective portion YS in a plan view.
  • the N-type electrode (cathode) or the like may be provided so as to overlap the ineffective portion NS in a plan view.
  • Penetrating dislocations are dislocations (defects) that extend from the lower surface or inside of the semiconductor layer 8 to its surface or surface along the thickness direction ( ⁇ 0001> direction, Z direction) of the ELO semiconductor layer 8. Penetration dislocations can be observed by performing CL (Cathodoluminescence) measurement on the surface of the semiconductor layer 8 (parallel to the c-plane).
  • CL Cathodoluminescence
  • the semiconductor layer 8 in FIG. 1 has an edge surface (side surface) 8E near the center of the mask portion 5 and does not associate with the semiconductor layer 8 grown from the adjacent seed portion 3S.
  • the side surfaces of the ELO semiconductor layer 8 are typically ⁇ 1-10 ⁇ > planes ( ⁇ is an arbitrary integer) and ⁇ 11-2 ⁇ > planes ( ⁇ is an arbitrary integer).
  • ⁇ is an arbitrary integer or is formed by a surface crystallographically equivalent to these. That is, the edge surface 8E of the semiconductor layer 8 may have an oblique surface (facet).
  • the semiconductor layers 8 that have grown laterally in the opposite directions from the two adjacent seed portions 3S do not contact (associate) on the mask portion 5 and have a gap (gap) GP, so that the semiconductor layer 8 has a gap (gap) GP.
  • Internal stress can be reduced.
  • cracks and defects generated in the semiconductor layer 8 can be reduced. This effect is particularly effective in the present embodiment in which the main substrate 1 is a different type of substrate.
  • the width of the gap GP is preferably 4 ⁇ m or less, more preferably 3 ⁇ m or less.
  • the semiconductor layer 8 may be an n-type GaN-based semiconductor (as a donor, for example, silicon).
  • a functional layer 9 including, for example, a p-type semiconductor layer is formed above the semiconductor layer 8 (see FIG. 2), when the semiconductor layer 8 has silicon or oxygen as an n-type dopant, a p-type dopant (magnesium, etc.)
  • this phenomenon can be significantly reduced by limiting the width of the gap GP to the above range.
  • FIG. 3 is a cross-sectional view showing another configuration of the semiconductor substrate according to the present embodiment.
  • edge growth 9G corner portion
  • the functional layer 9 includes an AlGaN layer.
  • the edge growth may have a width of 10 ⁇ m or more and a height of about 200 to 300 nm, which is an obstacle to the post-process, but the edge growth 9G is significantly reduced by suppressing the width of the gap GP to the above range. (For example, 100 nm or less) can be used.
  • the semiconductor layer 8 of FIG. 4 has a structure in which semiconductor layers grown laterally from two adjacent seed portions 3S meet in the vicinity of the center 5C of the mask portion and are integrated.
  • the hollow portion 8C is located near the center 5C of the mask portion, which is the meeting point. May be formed.
  • the shape of the hollow portion 8C is such that the mask portion 5 side is wide (for example, a weight shape or a drop shape in a cross-sectional view).
  • the semiconductor layer 8 has a portion (ineffective portion NS) that overlaps with the hollow portion 8C in a plan view. That is, the semiconductor layer 8 has an effective portion YS and an ineffective portion NS adjacent to the effective portion YS.
  • the temperature of the ELO semiconductor layer 8 associated at about 1000 ° C. is lowered to room temperature. At that time, cracks may occur in the ELO semiconductor layer 8 due to the difference in the coefficient of thermal expansion. Since the hollow portion 8C has the effect of significantly reducing the internal stress of the semiconductor layer 8, the occurrence of such cracks can be effectively reduced. Further, the surface of the semiconductor layer 8 may have a recess 8D in a portion corresponding to the upper part of the hollow portion 8C. This recess 8D also has the effect of relaxing the internal stress of the semiconductor layer 8.
  • the semiconductor substrate 10 of FIG. 2 includes a functional layer 9 on the semiconductor layer 8.
  • the functional layer 9 includes, for example, at least one of a GaN-based n-type semiconductor layer, a GaN-based non-doped semiconductor layer, a GaN-based p-type semiconductor layer, a conductive layer, and an insulating layer. Any film forming method may be used for the GaN-based semiconductor layer of the functional layer 9.
  • the functional layer 9 may be a compound semiconductor layer (compound semiconductor portion).
  • the compound semiconductor layer may be a nitride semiconductor layer (nitride semiconductor portion), and in this case, the nitride semiconductor layer may include a p-type layer and an active layer (for example, a light emitting layer), and the nitride semiconductor layer is It may include an n-type layer, an active layer and a p-type layer.
  • the functional layer 9 may constitute a semiconductor device (for example, LED, laser) together with the semiconductor layer 8, but is not limited thereto.
  • a semiconductor device for example, LED, laser
  • only a GaN-based n-type semiconductor layer may be provided.
  • FIG. 6 is a cross-sectional view showing a process of element separation according to the present embodiment.
  • FIG. 7 is a plan view showing a process of element separation according to the present embodiment. As shown in FIG. 6, in the semiconductor substrate 10, the region AK overlapping the opening KS in a plan view is removed until it reaches the base layer 4 by using vapor phase etching.
  • the base layer 4 is to be removed, and the base layer 4 and the mask portion 5 are contained in the trench TR (element separation groove) formed after the removal. Is exposed. It is desirable that the opening width of the trench TR is larger than the width of the opening KS of the mask layer.
  • the element portion DS can be separated in the semiconductor substrate 10 by the element separation step. At this stage, the element portion DS is van der Waals bonded to the mask portion 5 of the template substrate and is a part of the semiconductor substrate 10.
  • the trench TR can be formed in a grid shape (lattice pattern) in a plan view.
  • one element unit DS may be included in a region surrounded by adjacent horizontal trenches (stretched in the X direction) and adjacent vertical trenches (stretched in the Y direction).
  • Gas phase etching is realized by a general photolithography method. After the etching is completed, it is necessary to remove the photoresist that has become the mask for vapor phase etching, but if organic cleaning using weak ultrasonic waves is performed, there is little possibility that the element portion DS will peel off from the mask portion 5.
  • FIG. 8 is a cross-sectional view showing another example of the element separation process.
  • the region overlapping the opening KS and the region overlapping the gap portion GP in a plan view may be removed until the base layer 4 is reached by using vapor phase etching.
  • the meandering in the second direction (longitudinal direction of the opening KS, Y direction) of the semiconductor layer 8 is eliminated, and the element portion DS having a uniform shape can be obtained.
  • FIG. 9 is a cross-sectional view showing another example of the element separation process. As shown in FIG. 9, in the semiconductor substrate 10, the region overlapping the opening KS and the region overlapping the central portion 5 of the mask portion (ineffective portion NS) in a plan view are reached to the base layer 4 by using vapor phase etching. Can be removed.
  • FIG. 10 is a cross-sectional view showing a process of element peeling. Since the semiconductor layer 8 and the mask portion 5 are bonded by a van der Waals force (weak force), as shown in FIG. 10, they function by the attractive force (adhesive force, attractive force, electrostatic force, etc.) of the stamping device ST or the like. By pulling up the layer 9, the element portion DS can be easily peeled off from the template substrate to form the semiconductor device 20. Being able to directly peel off from the mask portion 5 using a viscoelastic elastomer stamp, an electrostatic adhesive stamp, or the like is a great advantage in terms of cost, throughput, and the like.
  • a van der Waals force weak force
  • the viscoelastic elastomer stamp, the electrostatic adhesive stamp, or the like is brought into contact with the semiconductor layer 8, vibration by ultrasonic waves or the like may be applied.
  • the semiconductor layer 8 can be more easily peeled off from the mask portion 5 by this vibration or the like.
  • FIG. 11 is a cross-sectional view showing another example of the element peeling process.
  • the mask portion 5 is wet-etched so that the element portion DS of the semiconductor layer 8 is connected only to the seed layer 3, and then the element portion DS is mechanically peeled from the template substrate 7 by tape TP or the like. You may. In this case, since it is not necessary to etch on the opening KS, a large semiconductor device 20 can be formed.
  • This peeling method has an advantage that the element separation step can be omitted when the semiconductor layer 8 is a separation type (when the mask portion has an edge surface).
  • the semiconductor layer 8 is an integral type (when the mask portion does not have an edge surface), it is sufficient to form a digging (up to the base layer) for the etchant inflow, which has an advantage that the element can be easily peeled off.
  • the element portion DS peeled off from the template substrate 7 functions as the semiconductor device 20.
  • the semiconductor device 20 include light emitting diodes (LEDs), semiconductor lasers, shotkey diodes, photodiodes, transistors (including power transistors and high electron mobility transistors) and the like.
  • FIG. 12 is a schematic diagram showing the configuration of the electronic device according to the present embodiment.
  • the electronic device 30 of FIG. 12 includes a semiconductor device 20 including a semiconductor layer 8 and a functional layer 9, a drive board 23 on which the semiconductor device 20 is mounted, and a control circuit 25 for controlling the drive board 23.
  • FIG. 13 is a schematic diagram showing another configuration of the electronic device according to the present embodiment.
  • the electronic device 30 of FIG. 13 includes a semiconductor substrate 10 including a semiconductor layer 8 and a functional layer 9, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 for controlling the drive substrate 23.
  • the main substrate 1 may be a substrate having light transmission (for example, a sapphire substrate).
  • Examples of electronic devices include display devices, laser emission devices (including fabric perow type and surface emission type), measuring devices, lighting devices, communication devices, information processing devices, and power control devices.
  • laser emission devices including fabric perow type and surface emission type
  • measuring devices including fabric perow type and surface emission type
  • lighting devices including fabric perow type and surface emission type
  • communication devices including communication devices, information processing devices, and power control devices.
  • voids may occur on the back surface of the ELO semiconductor layer 8.
  • This void causes a surface defect of the ELO semiconductor layer 8 (for example, the starting point of the defect when stress is applied to the semiconductor layer 8), and deteriorates the characteristics and reliability of the device formed on the ELO semiconductor layer 8. I will invite you.
  • the surface morphology of the mask portion 5 is improved by increasing the lateral film formation rate and reducing the interaction between the ELO semiconductor layer 8 and the mask portion 5, and as a result, the back surface of the ELO semiconductor layer 8 is used. We succeeded in reducing the adhesion between the gap and the mask portion 5.
  • the lateral film formation rate is increased, and the mask portion 5 is quickly covered with the lateral growth film (ELO semiconductor layer 8).
  • the lateral film formation rate is small, the mask portion 5 is exposed to hydrogen and nitrogen for a long time at a high temperature, evaporation and decomposition of the mask portion 5 proceed, deterioration of surface morphology, and pinholes. This is because there is a risk of occurrence, occurrence of pits, and the like.
  • the method for increasing the lateral film formation rate is as follows. First, a vertical growth layer that grows in the c-axis direction is formed on the seed portion exposed from the opening KS of the mask layer 6, and then a horizontal growth layer that grows in the a-axis direction is formed. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the film formation rate in the lateral direction can be increased.
  • FIG. 14 is a cross-sectional view showing an example of lateral growth of the semiconductor layer.
  • the initial growth layer SL serves as a starting point for lateral growth of the semiconductor layer 8.
  • the edge of the initial growth layer SL rides on the upper surface of the mask portion 5 immediately before (at the stage of being in contact with the upper end of the side surface of the mask portion 5) or on the upper surface of the mask portion 5.
  • the initial growth layer SL can be formed to have a thickness of 50 nm to 5.0 ⁇ m (for example, 80 nm to 2 ⁇ m). The thickness of the initial growth layer SL may be 500 nm or less.
  • the number of non-penetrating dislocations inside the effective portion YS is increased (the density of penetrating dislocations on the surface of the effective portion YS is reduced). Can be done. Further, the distribution of the impurity concentration (for example, silicon, oxygen) inside the effective portion YS can be controlled. By appropriately controlling the conditions during the film formation of the semiconductor layer 8, it is possible to control the semiconductor layer 8 to grow in the Z direction (c-axis direction) or in the X direction (a-axis direction). be.
  • the ratio (W1 / d1) of the size W1 in the X direction (first direction) to the thickness d1 can be set to, for example, 2.0 or more.
  • W1 / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. It has been found that by setting W1 / d1 to 1.5 or more, the division step as shown in FIG. 7 becomes easy. Further, the internal stress of the semiconductor layer 8 is reduced, and the warp of the substrate is reduced.
  • the semiconductor layer 8 shown in FIG. 14 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).
  • Non-penetrating dislocations are dislocations observed in CL in the cross section of a plane parallel to the c-axis (plane parallel to the thickness direction), and are mainly basal plane (c-plane) dislocations.
  • the plane parallel to the c-axis may be a plane parallel to the (1-100) plane (a plane whose normal is in the Y direction) or a plane parallel to the (11-20) plane (normal is in the X direction). (Surface) may be.
  • the non-penetrating dislocation density of the effective portion YS of the semiconductor layer 8 is larger than the penetrating dislocation density of the effective portion YS.
  • the effective portion YS of the semiconductor layer 8 can be expressed as a GaN-based crystal (GaN-based layer) in which the non-penetrating dislocation density is larger than the through-dislocation density.
  • the non-penetrating dislocation density in this case can be 10 times or more, for example, 20 times or more the penetrating dislocation density.
  • the through-dislocation density can be, for example, 5 ⁇ 106 [pieces / cm 2 ] or less.
  • the width (length in the X direction) of the effective portion (GaN-based crystal) can be, for example, 10 ⁇ m or more.
  • the effective portion (GaN-based crystal body) can have a longitudinal shape in which the size in the Y direction (m-axis direction) is larger than the size in the X direction (a-axis direction).
  • the non-penetrating dislocation density of the cross section parallel to the (11-20) plane is larger than the non-penetrating dislocation density of the cross section parallel to the (1-100) plane. You may.
  • the effective portion (GaN-based crystal) is formed by growth in the lateral direction (X direction), impurities (in the X direction) are found at the other end at the end of growth rather than at one end at the beginning of growth.
  • concentration of atoms for example, silicon and oxygen
  • the quality of the mask portion 5 is affected by the surface flatness, crystallinity, and material of the underlying layer on which the mask portion 5 is formed. If there is a defective portion in the base layer, the reaction between the mask portion 5 and the base layer proceeds from the defective portion, and the quality of the mask portion 5 deteriorates. As a result, the reaction between the mask portion 5 and the ELO semiconductor layer 8 formed on the mask portion 5 is promoted, and voids may be generated on the back surface (boundary surface with the mask portion 5) of the ELO semiconductor. In the ELO method, since the film formation proceeds from both sides of the mask portion 5 toward the center, voids are likely to occur in the portion near the center (the portion where the time until the film formation is long).
  • a temperature of 1150 ° C. or lower is preferable to a high temperature of more than 1200 ° C.
  • the ELO semiconductor layer 8 can be formed even at a low temperature of less than 1000 ° C., which is more preferable from the viewpoint of reducing mutual reaction. It was found that when trimethylgallium (TMG) is used as the gallium raw material in such a low temperature film formation, the raw material is not sufficiently decomposed and more gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor layer 8 than usual. rice field. It is considered that this is because in the ELO method, the film formation in the a-axis direction is fast and the film formation in the c-axis direction is slow, so that a large amount of film is taken in during the c-plane film formation.
  • TMG trimethylgallium
  • TEG triethyl gallium
  • the InGaN layer may be formed as the ELO semiconductor layer 8.
  • the transverse film formation of the InGaN layer is performed at a low temperature of, for example, below 1000 ° C. This is because the vapor pressure of indium increases at high temperatures and is not effectively incorporated into the membrane. By lowering the film formation temperature, there is an effect that the mutual reaction between the mask portion 5 and the InGaN layer is reduced. Further, the InGaN layer also has an effect that the reactivity with the mask portion 5 is lower than that of the GaN layer. When indium is incorporated into the InGaN layer at an In composition level of 1% or more, the reactivity with the mask portion 5 is further lowered, which is desirable.
  • TAG triethyl gallium
  • linear defects on the surface (surface layer) of the ELO semiconductor layer 8 can be reduced.
  • the m-plane of the ELO semiconductor layer 8 is vulnerable to stress, and defects are likely to occur. It is considered that this linear defect is caused by the sliding of the crystal along the m-plane. Dislocations extending in the m-axis direction (presumed to be mixed dislocations that combine blade-shaped dislocations and spiral dislocations) may be observed as linear defects in a specific cross section parallel to the c-plane, but from this specific cross section It is sufficient if the linear defects disappear (if not observed) in the cross section (parallel to the c-plane) cut on the surface layer.
  • adhesion on the back of the ELO semiconductor layer When a different type of substrate is used and the mask portion 5 is widened, adhesion with the mask portion 5 may occur on the back surface of the ELO semiconductor layer 8. When this adhesion is present, the stress generated by the difference in the coefficient of thermal expansion between the ELO semiconductor layer 8 and the dissimilar substrate becomes difficult to be relaxed, which causes surface defects. Further, when the ELO semiconductor layer 8 is peeled from the template substrate 7, the peeling yield is deteriorated.
  • the adhesion between the ELO semiconductor layer 8 and the mask portion 5 is reduced by reducing the mutual reaction between the ELO semiconductor layer 8 and the mask portion 5.
  • the material and thickness of the mask portion 5 are optimized, and the film density of the mask portion 5 is increased.
  • the film density of the mask portion 5 is low, the film evaporates quickly or the etching rate becomes high due to the high temperature and hydrogen atmosphere in the MOCVD apparatus.
  • the ELO semiconductor layer 8 that grows laterally covers the mask portion 5 the mask portion 5 and the ELO semiconductor layer 8 adhere to each other. It is considered that this is because a reaction layer in which the mask portion 5 and the ELO semiconductor layer 8 are mixed is generated, and the ELO semiconductor layer 8 is fixed to the mask portion 5.
  • an intermediate layer (a layer in which the mask portion 5 and the semiconductor layer 8 are reacted or mixed) is formed on the back surface of the ELO semiconductor layer 8.
  • This intermediate layer adheresion layer
  • AFM Atomic Force Microscope
  • Ra was about 13 nm in the case where the influence of adhesion was large.
  • any one of a titanium nitride film (TiN etc.), a silicon nitride film (SiN etc.), a silicon acid nitride film (SiON), and a refractory metal film examples thereof include a single-layer film composed of one or a multi-layer film composed of two or more.
  • the mask portion 5 may be a silicon nitride film or a silicon acid nitride film.
  • the silicon oxide film may be decomposed and evaporated in a small amount during the formation of the ELO semiconductor layer 8 and incorporated into the ELO semiconductor layer 8, but the silicon nitride film and the silicon acid nitride film are difficult to decompose and evaporate at high temperatures. There is a merit. Even when a silicon oxide film, which is common in the ELO method, is used for the mask layer, the film forming conditions of the mask layer and the ELO semiconductor layer 8 are optimized to optimize the film forming conditions between the mask portion 5 and the ELO semiconductor layer 8. The interaction can be effectively reduced.
  • the mask layer may be a single-layer film of a silicon nitride film or a silicon oxynitride film, or may be a multi-layer film in which a silicon oxide film and a silicon nitride film are formed in this order on the base layer, or on the base layer. It may be a multilayer film in which a silicon nitride film and a silicon oxide film are formed in this order, or a multilayer film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on an underlayer.
  • a high-quality mask layer may be formed by using a general silicon oxide film and using the re-deposition method as described above.
  • 15 to 18 are plan views and schematic views showing the evaluation of the present semiconductor substrate (the structure in which the ELO semiconductor layer has an edge surface on the mask).
  • the back surface of the semiconductor layer 8 (boundary surface 8R with the mask portion) can be evaluated in the state of the boundary surface in contact with the mask portion 5, or the semiconductor layer 8 is peeled from the mask portion 5 and the peeled surface is evaluated. You can also do it.
  • the semiconductor layer 8 can be peeled off by removing the mask portion 5 by wet etching or the like (note that if the semiconductor layer 8 is an integral type, pre-digging up to the base layer 4 may be performed).
  • the upper surface 8F of the effective portion YS is in the first direction X (a-axis direction) along the width direction of the opening KS.
  • At least one low defect region AL having a size of 10 ⁇ m and a size of 10 ⁇ m in the second direction Y (m-axis direction) orthogonal to the first direction is included, and in the low defect region AL, linear defects (caused by m-plane slip) are included.
  • a possible linear defect diagonal to the first direction X) was not measured (see FIG. 15, evaluation criterion 1).
  • the upper surface of the effective portion YS included a plurality of low defect regions AL arranged in the first direction X and a plurality of low defect regions AL arranged in the second direction Y (see FIG. 15, evaluation). Criterion 2). The size of the effective portion YS in the first direction was larger than the width of the opening KS (see FIG. 15, evaluation criterion 3).
  • the effective portion YS has a first region A1 having a size of 10 ⁇ m in the first direction X and a size of 10 ⁇ m in the second direction Y on the boundary surface 8R with the mask portion 5, and the first region having the same size as the above-mentioned size. It had a second region A2 located on the center side of the mask portion 5 with respect to A1 and having a distance PT from the center 5C of the mask portion 5 of 30% or less of the width of the mask portion 5.
  • the number of recesses having a major axis of 0.1 [ ⁇ m] or more in the first region A1 is the second.
  • the number of recesses having a major axis of 0.1 [ ⁇ m] or more in the region A2 was less than or equal to (see FIG. 16, evaluation standard 4). Further, the major axis of the concave portion existing in the first region A1 was 1 ⁇ m or less (hereinafter, evaluation standard 5).
  • the effective portion YS has a third region A3 having a size of 10 ⁇ m in the first direction X and 10 ⁇ m in the second direction Y on the boundary surface 8R with the mask portion 5, and a third region A3 having the same size as the said size and having a size of 10 ⁇ m. It had a fourth region A4 located on the center side of the mask portion 5 with respect to A3. Then, as a result of peeling the effective portion YS from the mask portion 5 and observing the first region A3 and the second region A4 with AFM, the adhesion area of the third region A3 was smaller than the adhesion area of the fourth region A4 (the adhesion area of the third region A3 was smaller than the adhesion area of the fourth region A4. See FIG.
  • the third region A3 was a non-adhesive region in which adhesion to the mask portion 5 was substantially not observed (hereinafter, evaluation standard 8).
  • the fourth region A4 was at a position where the distance PT from the center 5C of the mask portion was 30% or less of the width of the mask portion 5.
  • the effective portion YS includes a first portion P1 and a second portion P2 which is farther from the opening KS than the first portion P1 and has a distance KT from the opening KS of 10 ⁇ m or more, and masks the first portion P1.
  • the surface roughness (Ra) of the peeled surface F1 when peeled from 5 is the first surface roughness
  • the surface roughness (Ra) of the peeled surface F2 when the second portion P2 is peeled from the mask portion 5 is the second surface.
  • the first surface roughness was equal to or less than the second surface roughness (see FIG. 18, evaluation standard 9).
  • the arithmetic mean roughness (Ra) for the range of 5 ⁇ m ⁇ 5 ⁇ m of each peeled surface is extracted from a part of the roughness curve measured by AFM with a reference length, and the uneven state of the section is expressed by the average value. Can be done. Further, the value of the ratio of the second surface roughness to the first surface roughness was 1.0 to 10 (evaluation standard 10). Further, the peeled surface (including F1 and F2) when the effective portion YS is peeled from the mask portion 5 has a size of 10 ⁇ m in the first direction and 10 ⁇ m in the second direction, and has a major axis of 0.1 [ ⁇ m] or more.
  • the second surface roughness was less than 10 [nm] (evaluation standard 12).
  • the first portion P1 is adjacent to the opening KS, and the distance PT between the second portion P2 and the center 5C of the mask portion is 30% or less of the width of the mask portion 5 (evaluation criterion 13).
  • the area ratio of the recesses having a major axis of 0.1 ⁇ m or more included in the peeling surface F1 of the first portion P1 to the peeling surface is the first recess occupancy rate, and the major axis 0.1 ⁇ m or more included in the peeling surface F2 of the second portion.
  • the area ratio of the recesses to the peeled surface was defined as the second recess occupancy rate, and the first recess occupancy rate was equal to or less than the second recess occupancy rate (evaluation standard 14).
  • the concave portion (void region) can be measured by AFM in a range of 5 ⁇ m ⁇ 5 ⁇ m of each peeled surface, and its major axis, occupancy, and the like can be obtained.
  • the impurity concentration on the peeling surface F1 of the first portion P1 was higher than the impurity concentration on the peeling surface F2 of the second portion P2 (evaluation standard 15).
  • the through-dislocation density on the upper surface 8R of the effective portion YS was 5 ⁇ 10 6 [pieces / cm 2 ] or less (evaluation standard 16).
  • adhesion with the mask portion 5 is reduced to relieve stress, and the generation of voids causing surface defects (m-plane slip) is reduced. This is very important.
  • the crystallinity of the ELO semiconductor layer 8 that grows laterally from the opening KS of the mask 5 onto the mask 5 is extremely high.
  • the semiconductor substrate 10 by reducing the mutual reaction between the mask portion 5 and the semiconductor layer 8, it is possible to reduce the voids and adhesions generated on the back surface of the semiconductor layer 8 and effectively relieve the stress from the main substrate 1. is made of.
  • the defects generated in the effective portion YS do not penetrate to the surface of the semiconductor layer 8 but are confined inside the semiconductor layer 8.
  • 19 to 22 are plan views and schematic views showing the evaluation of a semiconductor substrate having a different configuration (an integrated type in which the ELO semiconductor layer has no edge surface on the mask). In this case as well, it was found that the evaluation criteria 1 to 16 were satisfied.
  • FIG. 23 is a CL (cathode luminescence) image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (the main substrate is a silicon substrate). No scotoma or dark line is observed in the effective part YS. Only in the ineffective portion NS, there are about 10 19 / cm 2 through dislocations due to the difference in lattice constant between the silicon substrate and GaN.
  • FIG. 24 is a CL (cathode luminescence) image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (the main substrate is a sapphire substrate). Since the ELO semiconductor layer 8 is mechanically peeled from the template substrate, the ineffective portion NS is slightly damaged, and the peeled surface is not flat, so that the CL image is slightly disturbed, but the effective portion YS. No dark spots, dark lines, etc., which are through-dislocations, are observed, or a low dislocation density can be realized.
  • CL cathode luminescence
  • FIG. 25 is a CL image of the back surface (peeled surface) of the ELO semiconductor layer of the semiconductor substrate 10. It can be seen that neither voids nor adhesions are observed in the effective portion YS.
  • FIG. 26 is a CL image of the surface of the GaN layer of the reference example.
  • sapphire is used as the main substrate, and a GaN layer is formed by the ELO method.
  • dark spots 10 18 to 10 19 / cm 2
  • dark lines which are high-density dislocations.
  • FIG. 27 is a CL image of the surface of the GaN layer of the reference example.
  • silicon is used as the main substrate, and a GaN layer is formed by the ELO method.
  • a dark spot of about 10 19 / cm 2 is observed on the opening, and a dark line is also observed on the mask.
  • FIG. 28 is a CL image of the back surface of the GaN layer of the reference example.
  • silicon is used as the main substrate, and a GaN layer is formed by the ELO method. A large number of voids are observed at the edges on the mask portion.
  • FIG. 29 is an optical microscope image of the back surface (peeling surface) of the GaN layer of the ELO method film formation of the reference example.
  • the adhesion NL (reaction layer) between the mask portion and the GaN layer can be seen.
  • the GaN layer and the mask portion are combined from the template substrate as shown in the peeled region NA in FIG. It will come off.
  • FIG. 31 is a cross-sectional view showing the configuration of the semiconductor substrate of the first embodiment.
  • the buffer layer 2 of the base layer 4 was an AlN layer (for example, 30 nm).
  • the first layer Al 0.6 Ga 0.4 N layer for example, 300 nm
  • the second layer GaN layer for example, 1 to 2 ⁇ m
  • a laminate in which a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) were formed in this order was used.
  • the thickness of the silicon oxide film is, for example, 0.3 ⁇ m, and the thickness of the silicon nitride film is, for example, 70 nm.
  • a plasma chemical vapor deposition (CVD) method was used to form the silicon oxide film and the silicon nitride film.
  • the semiconductor layer 8 was a GaN layer, and ELO film formation was performed using a MOCVD apparatus. First, the ELO semiconductor layer 8 selectively grows on the surface of the seed layer 3 (the GaN layer of the second layer) exposed to the opening KS, and subsequently grows laterally on the mask portion 5. At this time, the growth was stopped before the semiconductor layers growing laterally from both sides on the mask portion 5 were associated with each other. The width of the gap GP at this time was 2 ⁇ m.
  • the width WM of the mask portion 5 was 50 ⁇ m
  • the width of the opening KS was 5 ⁇ m
  • the width WL of the ELO semiconductor layer 8 was 53 ⁇ m
  • the width of the effective portion YS size in the X direction
  • the layer thickness of the ELO semiconductor layer 8 was 5 ⁇ m
  • the peeling of the semiconductor layer 8 at the time of evaluating the back surface of the semiconductor layer 8 can be performed as follows.
  • the semiconductor substrate 10 subjected to the element separation step (see FIGS. 8 and 9) is used as an etchant for phosphoric acid.
  • the mask layer 6 is dissolved in the etchant, and the semiconductor layer 8 can be peeled off from the template substrate 7.
  • the semiconductor substrate 10 is attached to an etchant of hydrofluoric acid to dissolve the mask layer 6, and then an adhesive tape (for example, a semiconductor wafer) is diced on the surface of the semiconductor layer 8.
  • the semiconductor substrate 10 with the adhesive tape attached may be lowered to a low temperature by sticking the adhesive dicing tape used in the case and using the Pelche element as it is.
  • the adhesive tape having a coefficient of thermal expansion larger than that of the semiconductor generally shrinks significantly, and stress is applied to the semiconductor layer 8. Since the semiconductor layer 8 is bonded to the template substrate 7 only in the opening KS and the mask portion 5 is removed, the stress from the adhesive tape is effectively applied to the bonded portion with the template substrate 7. , Mechanically, the joint can be cleaved or broken. That is, it is not necessary to remove the joint portion by dry etching.
  • FIG. 33 is a cross-sectional view showing the configuration of the semiconductor substrate of the second embodiment.
  • an integrated type in which the ELO semiconductor layer 8 does not have an edge surface on the mask portion 5 is adopted.
  • the width of the mask portion 5 is 50 ⁇ m, and the width of the opening KS is 5 ⁇ m.
  • the height of the hollow portion 8C is preferably 1 ⁇ m or more.
  • the width of the bottom surface of the hollow portion 8C is also preferably 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • FIG. 34 is a cross-sectional view showing the configuration of the semiconductor substrate of the third embodiment.
  • the width of the opening KS was 700 nm, which was 1 ⁇ m or less, and the width of the mask portion 5 was 100 ⁇ m.
  • the width of the effective portion YS can be widened, it is suitable for a high-power laser semiconductor device (ridge width is about 40 ⁇ m) or the like.
  • FIG. 34 shows a structure in which the semiconductor layer 8 has an edge surface on the mask portion 5, it may be an integrated type having no edge on the mask portion 5.
  • FIG. 35 is a cross-sectional view showing the configuration of the fourth embodiment.
  • the functional layer 9 constituting the LED is formed on the semiconductor layer 8.
  • the semiconductor layer 8 is n-type, for example, doped with silicon or the like.
  • the functional layer 9 includes an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor layer 36 in this order from the lower layer side.
  • the active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer.
  • the electron blocking layer 35 is, for example, an AlGaN layer.
  • the GaN-based p-type semiconductor layer 36 is, for example, a GaN layer.
  • the anode 38 is formed so as to be in contact with the GaN-based p-type semiconductor layer 36, and the cathode 39 is formed so as to be in contact with the semiconductor layer 8.
  • the voids on the back surface of the semiconductor layer cause surface defects (linear defects) and deteriorate the characteristics of the semiconductor device. Further, when the semiconductor device is a light emitting element, the voids on the back surface of the semiconductor layer reduce the in-plane uniformity of the emitted light.
  • the element portion (light emitting element portion) DS can be formed on the ELO semiconductor layer 8 and peeled off to obtain the semiconductor device 20 which is a light emitting element, so that these problems can be improved. .. Specifically, no defect was found in the light emitting region of the semiconductor device 20.
  • FIG. 36 is a cross-sectional view showing an application example of the fourth embodiment.
  • a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B can be obtained, and these are mounted on a drive board (TFT board) 23 to form a micro LED display 30D (electronic device).
  • TFT board drive board
  • a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B are mounted on a plurality of pixel circuits 27 of a drive board 23 via a conductive resin 24 (for example, an anisotropic conductive resin), and then the drive board is mounted.
  • the control circuit 25, the driver circuit 29, and the like are mounted on the 23. A part of the driver circuit 29 may be included in the drive board 23.
  • FIG. 37 is a cross-sectional view showing the configuration of the fifth embodiment.
  • the functional layer 9 constituting the semiconductor laser is formed on the semiconductor layer 8.
  • the functional layer 9 is, in order from the lower layer side, an n-type optical clad layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical clad layer 46, and a GaN system. It includes a p-type semiconductor layer 47.
  • An InGaN layer can be used for each of the guide layers 42 and 45.
  • a GaN layer or an AlGaN layer can be used for each of the clad layers 41 and 46.
  • the anode 48 is formed so as to be in contact with the GaN-based p-type semiconductor layer 47.
  • Example 5 as shown in FIG. 37, the cathode 49 is formed on the back surface of the semiconductor layer 8 after the element portion DS is peeled off. Therefore, the quality of the back surface of the semiconductor layer 8 affects the device characteristics.
  • FIG. 38 is a cross-sectional view showing the configuration of the sixth embodiment.
  • FIG. 39 is a cross-sectional view showing another configuration of the sixth embodiment.
  • a sapphire substrate having a surface unevenness processed is used as the main substrate 1.
  • the base layer 4 has a buffer layer 2 and a seed layer 3.
  • the semiconductor layer 8 may be in the form of having an edge surface on the mask 5 (FIG. 38) or an integrated type having no edge surface on the mask (FIG. 39).
  • a GaN layer having a (20-21) surface on the main substrate 1 can be formed as a base layer 4.
  • the ELO semiconductor layer 8 becomes a (20-21) surface which is a crystal main surface in the base layer 4, and an ELO semiconductor layer 8 having a semi-polar surface can be obtained.
  • the functional layer for the laser and the LED on the semi-polar surface, there is an advantage that the piezoelectric field is small and the probability of recombination of electrons and holes in the active layer is increased.
  • a GaN layer having a (11-22) surface on the main substrate 1 can be formed as a base layer 4.
  • the method for manufacturing the semiconductor substrate 10 includes at least a step of forming the semiconductor layer 8 on the template substrate 7 by using the ELO method. A step of forming the base layer 4 and the mask layer 6 on the main substrate 1 may be included.
  • the semiconductor substrate 10 can be manufactured, for example, by the semiconductor substrate manufacturing apparatus shown in FIG. 40.
  • the semiconductor substrate manufacturing apparatus 70 includes at least a semiconductor layer forming unit 71 that performs a step of forming the semiconductor layer 8 on the template substrate 7 by using the ELO method, and a control unit 72 that controls the semiconductor layer forming unit 71. ..
  • the semiconductor layer forming unit 71 may include a MOCVD device, and the control unit 72 may include a processor and a memory.
  • the control unit 72 may be configured to control the semiconductor layer forming unit 71 by executing, for example, a built-in memory, a communicable communication device, or a program stored on an accessible network, and this program and this program may be configured.
  • the stored recording medium and the like are also included in the present embodiment.
  • the semiconductor substrate manufacturing apparatus 70 includes a template substrate forming portion for forming a base layer 4 and a mask layer 6 on a main substrate 1, a functional layer forming portion for forming a functional layer 9 on a semiconductor layer 8, and the like. May include. Further, it is also possible to configure a semiconductor device manufacturing apparatus that performs a process of element peeling. The semiconductor device manufacturing apparatus may perform a process of element separation. The semiconductor device manufacturing apparatus may include the semiconductor substrate manufacturing apparatus 70.

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024085214A1 (ja) * 2022-10-19 2024-04-25 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置、半導体デバイスの製造方法
WO2024084664A1 (ja) * 2022-10-20 2024-04-25 京セラ株式会社 半導体基板、テンプレート基板、並びにテンプレート基板の製造方法および製造装置
WO2024122644A1 (ja) * 2022-12-09 2024-06-13 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置
WO2024162377A1 (ja) * 2023-01-31 2024-08-08 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置
WO2025115999A1 (ja) * 2023-12-01 2025-06-05 京セラ株式会社 半導体基板およびその製造方法、半導体基板の製造装置、並びに半導体デバイス

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110603651B (zh) * 2017-05-05 2023-07-18 加利福尼亚大学董事会 移除衬底的方法
WO2022270309A1 (ja) * 2021-06-21 2022-12-29 京セラ株式会社 半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器
JP2024525695A (ja) * 2021-07-13 2024-07-12 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア 高品質エピタキシャル結晶層上での小型発光ダイオードの作成方法
WO2023153358A1 (ja) * 2022-02-10 2023-08-17 京セラ株式会社 レーザ素子の製造方法および製造装置
JP7835616B2 (ja) * 2022-05-20 2026-03-25 京セラ株式会社 半導体基板、テンプレート基板、半導体基板の製造方法および製造装置、半導体デバイスの製造方法および製造装置、半導体デバイス
WO2024211817A1 (en) 2023-04-06 2024-10-10 Slt Technologies, Inc. High quality group-iii metal nitride crystals and methods of making
WO2025216274A1 (ja) * 2024-04-10 2025-10-16 京セラ株式会社 半導体基板およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010521064A (ja) * 2007-03-09 2010-06-17 クリー インコーポレイテッド 中間層構造を有する厚い窒化物半導体構造、及び厚い窒化物半導体構造を製造する方法
JP2012114263A (ja) * 2010-11-25 2012-06-14 Pawdec:Kk 半導体素子およびその製造方法
JP2013251304A (ja) 2012-05-30 2013-12-12 Furukawa Co Ltd 積層体および積層体の製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2311132C (en) * 1997-10-30 2004-12-07 Sumitomo Electric Industries, Ltd. Gan single crystalline substrate and method of producing the same
US6252261B1 (en) * 1998-09-30 2001-06-26 Nec Corporation GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor
JP2000349338A (ja) * 1998-09-30 2000-12-15 Nec Corp ＧａＮ結晶膜、ＩＩＩ族元素窒化物半導体ウェーハ及びその製造方法
US6812053B1 (en) * 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
JP4667556B2 (ja) * 2000-02-18 2011-04-13 古河電気工業株式会社 縦型ＧａＮ系電界効果トランジスタ、バイポーラトランジスタと縦型ＧａＮ系電界効果トランジスタの製造方法
JP4556300B2 (ja) * 2000-07-18 2010-10-06 ソニー株式会社 結晶成長方法
JP3801125B2 (ja) * 2001-10-09 2006-07-26 住友電気工業株式会社 単結晶窒化ガリウム基板と単結晶窒化ガリウムの結晶成長方法および単結晶窒化ガリウム基板の製造方法
US7498608B2 (en) * 2001-10-29 2009-03-03 Sharp Kabushiki Kaisha Nitride-composite semiconductor laser element, its manufacturing method, and semiconductor optical device
US7208393B2 (en) * 2002-04-15 2007-04-24 The Regents Of The University Of California Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy
FR2840452B1 (fr) * 2002-05-28 2005-10-14 Lumilog Procede de realisation par epitaxie d'un film de nitrure de gallium separe de son substrat
KR101086155B1 (ko) * 2002-12-16 2011-11-25 독립행정법인 과학기술진흥기구 수소화합물 기상 성장법에 의한 평면, 비극성 질화 갈륨의 성장
KR100513316B1 (ko) * 2003-01-21 2005-09-09 삼성전기주식회사 고효율 반도체 소자 제조방법
US7445673B2 (en) * 2004-05-18 2008-11-04 Lumilog Manufacturing gallium nitride substrates by lateral overgrowth through masks and devices fabricated thereof
US7956360B2 (en) * 2004-06-03 2011-06-07 The Regents Of The University Of California Growth of planar reduced dislocation density M-plane gallium nitride by hydride vapor phase epitaxy
JP4182935B2 (ja) * 2004-08-25 2008-11-19 住友電気工業株式会社 窒化ガリウムの結晶成長方法および窒化ガリウム基板の製造方法
TW200703463A (en) * 2005-05-31 2007-01-16 Univ California Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO)
JP4656410B2 (ja) * 2005-09-05 2011-03-23 住友電気工業株式会社 窒化物半導体デバイスの製造方法
TWI408264B (zh) * 2005-12-15 2013-09-11 聖戈班晶體探測器公司 低差排密度氮化鎵（ＧａＮ）之生長方法
JP4807081B2 (ja) * 2006-01-16 2011-11-02 ソニー株式会社 ＧａＮ系化合物半導体から成る下地層の形成方法、並びに、ＧａＮ系半導体発光素子の製造方法
TWI415295B (zh) * 2008-06-24 2013-11-11 榮創能源科技股份有限公司 半導體元件的製造方法及其結構
US9589792B2 (en) * 2012-11-26 2017-03-07 Soraa, Inc. High quality group-III metal nitride crystals, methods of making, and methods of use
JP2011066398A (ja) * 2009-08-20 2011-03-31 Pawdec:Kk 半導体素子およびその製造方法
US8110484B1 (en) * 2010-11-19 2012-02-07 Sumitomo Electric Industries, Ltd. Conductive nitride semiconductor substrate and method for producing the same
EP2701183A4 (en) * 2011-08-09 2014-07-30 Panasonic Corp STRUCTURE FOR BREEDING A NITRID SEMICONDUCTOR LAYER, STACKING STRUCTURE, NITRID BASE SEMICONDUCTOR ELEMENT, LIGHTING SOURCE AND MANUFACTURING METHOD THEREFOR
US9490119B2 (en) * 2014-05-21 2016-11-08 Palo Alto Research Center Incorporated Fabrication of thin-film devices using selective area epitaxy
CN110603651B (zh) * 2017-05-05 2023-07-18 加利福尼亚大学董事会 移除衬底的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010521064A (ja) * 2007-03-09 2010-06-17 クリー インコーポレイテッド 中間層構造を有する厚い窒化物半導体構造、及び厚い窒化物半導体構造を製造する方法
JP2012114263A (ja) * 2010-11-25 2012-06-14 Pawdec:Kk 半導体素子およびその製造方法
JP2013251304A (ja) 2012-05-30 2013-12-12 Furukawa Co Ltd 積層体および積層体の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4273306A4

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024085214A1 (ja) * 2022-10-19 2024-04-25 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置、半導体デバイスの製造方法
WO2024084634A1 (ja) * 2022-10-19 2024-04-25 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置
WO2024084664A1 (ja) * 2022-10-20 2024-04-25 京セラ株式会社 半導体基板、テンプレート基板、並びにテンプレート基板の製造方法および製造装置
WO2024085243A1 (ja) * 2022-10-20 2024-04-25 京セラ株式会社 半導体基板、テンプレート基板、並びにテンプレート基板の製造方法および製造装置
JPWO2024085243A1 (https=) * 2022-10-20 2024-04-25
TWI903259B (zh) * 2022-10-20 2025-11-01 日商京瓷股份有限公司 半導體基板、以及模片基板之製造方法及製造裝置
WO2024122644A1 (ja) * 2022-12-09 2024-06-13 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置
WO2024162377A1 (ja) * 2023-01-31 2024-08-08 京セラ株式会社 半導体基板、半導体基板の製造方法および製造装置
WO2025115999A1 (ja) * 2023-12-01 2025-06-05 京セラ株式会社 半導体基板およびその製造方法、半導体基板の製造装置、並びに半導体デバイス

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