WO2022142371A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2022142371A1
WO2022142371A1 PCT/CN2021/113021 CN2021113021W WO2022142371A1 WO 2022142371 A1 WO2022142371 A1 WO 2022142371A1 CN 2021113021 W CN2021113021 W CN 2021113021W WO 2022142371 A1 WO2022142371 A1 WO 2022142371A1
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trench
doped
layer
doped region
trenches
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PCT/CN2021/113021
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Chinese (zh)
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方冬
肖魁
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • Silicon carbide is a group IV-IV compound material, which has the characteristics of high hardness, high chemical stability, high thermal conductivity, wide band gap, high critical electric field strength, and high saturation migration rate. Silicon carbide power devices greatly improve the performance of semiconductor devices. SiC JBS has no minority carrier storage during operation, fast reverse recovery, and low switching loss.
  • the Schottky diode (SBD) and the PiN structure are combined, and the P-type region in the PiN structure is formed in the N-type active region, making the Schottky contact between the electrode and the active region.
  • the ohmic contact between the electrode and the PiN structure in the active region is formed in the same plane, so that the forward current passes from the electrode through the Schottky contact region to the current density of the N-type active region when forward bias is applied. Restricted, when reverse bias is applied, the leakage current is large and the withstand voltage is limited.
  • the present invention provides a manufacturing method of a semiconductor device.
  • the present invention provides a semiconductor device, comprising:
  • the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
  • the doped region including a first doped region at the bottom of the trench;
  • the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench
  • the doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
  • the doped region further includes a second doped region located below the surface of the doped layer, the depth of the second doped region is smaller than the depth of the trench, and the metal electrode further includes a second doped region located below the surface of the doped layer. A second portion above the doped layer, the second portion is in ohmic contact with the second doped region.
  • At least two trenches are provided in the doped layer.
  • the trenches include at least two strip-shaped trenches juxtaposed along a first direction, wherein the strip-shaped trenches extend from the active region in a second direction crossing the first direction.
  • the first end extends to a second end corresponding to the first end.
  • the grooves include concave grooves between the strip grooves.
  • At least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
  • the trench includes an annular concave trench and a concave trench provided in the doped layer surrounded by the annular concave trench.
  • the present invention also provides a method for manufacturing a semiconductor device, comprising:
  • a silicon carbide substrate including a doping layer of a first doping type
  • a doped region of a second doping type is formed in the doped layer, wherein the doped region includes a first doped region at the bottom of the trench, and at least a portion above the first doped region The doped region is not formed in the doped layer outside the sidewall of the trench;
  • the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are on the sidewall of the trench Schottky contacts are formed at least in part.
  • At least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches.
  • the method for forming a doped region of the second doping type at the bottom of the trench includes:
  • An ion implantation process is performed to convert the doped layer at a first depth below the bottom of the trench into the doped region.
  • the step of forming a doped region of the second doped type at the bottom of the trench also converts the doped layer at a second depth below the surface of the protrusion into the doped region. impurity region, the second depth is smaller than the depth of the concave trench.
  • the method of forming a metal electrode includes:
  • an etching process is performed to form holes, and the holes expose the trenches;
  • the holes are filled with metal.
  • a trench is formed in the active region, and a doping region opposite to the doping type of the active region is formed at the bottom of the trench in the active region, so that the electrode finally formed Schottky contacts are formed between the trench sidewalls and the active region.
  • the current flows into the active region through the metal electrode forming Schottky contact on the sidewall of the trench, and the electron concentration near the doping region of the second doping type increases, increasing the current path and improving the current density
  • the ratio of the active region to the doped region can be increased, and the current density can be further increased; by design, when the reverse current is loaded, the doped region pair can be formed between the trenches
  • the active region of the device is fully depleted, the leakage current is reduced, and the withstand voltage performance of the device is improved.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIGS. 7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 8 is an exemplary flowchart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • the present invention provides a semiconductor device, comprising:
  • the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
  • the doped region including a first doped region at the bottom of the trench;
  • the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench
  • the doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
  • a semiconductor device includes:
  • a silicon carbide substrate 100, the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, and a trench 102 is provided in the doping layer 101;
  • the doped region 103 including a first doped region 1031 located at the bottom of the trench 102;
  • Metal electrode 107 wherein said metal electrode 107 includes a first portion of said trench 102 embedded in said doped layer 101, said first portion being in ohmic contact with said first doped region 1031, said first portion Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 .
  • the semiconductor device includes a silicon carbide substrate 100 , and the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, exemplarily, the preparation material of the silicon carbide substrate 100 It can be 4H-SiC, the doping type is the first doping type, the doping concentration is 1 ⁇ 10 18 cm ⁇ 3 , and the thickness is 350 ⁇ m.
  • a first doping type exemplarily, the preparation material of the silicon carbide substrate 100 It can be 4H-SiC
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 18 cm ⁇ 3
  • the thickness is 350 ⁇ m.
  • the silicon carbide substrate 100 further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate 100, and the silicon carbide epitaxial layer is of the first doping type.
  • the thickness of the silicon carbide epitaxial layer is 6 ⁇ m
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 .
  • a silicon carbide power device is formed, wherein an active region and a termination region are formed on a silicon carbide substrate 100 .
  • the silicon carbide substrate 100 includes an active region A and a termination region B.
  • the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
  • the semiconductor device includes a doping layer 101 of a first doping type on a silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal Region B, exemplary, has a doping concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate 100 .
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type
  • the doping type is P-type, one of low-doped P-type, and high-doped P+ type
  • the second doping type is N-type, low-doped N-type, and one of high-doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and high-doped N+ type
  • the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
  • the first type is N-type
  • the second doping type is P-type
  • the semiconductor device according to the present invention is provided with trenches 102 in the doping layer 101 of the first doping type.
  • a trench 102 is provided in the active region A in the doped layer 101, the doped layer at the bottom of the trench 102 forms a doped region of the second doping type, and the trench 102 is filled with a metal electrode, when a forward current is loaded , the current can flow into the active region through the sidewall of the trench, increasing the current path and improving the current density; at the same time, due to the three-dimensional design of the trench structure, the ratio of the active region to the doped region can be increased, further improving the current density.
  • the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
  • the trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein. Meanwhile, in the drawings of the embodiments of the present invention, the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
  • the method of forming the trench 102 in the doped layer 101 includes:
  • a patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
  • An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
  • At least two trenches are formed in the doped layer.
  • protrusions are formed in the doped layer between adjacent two of the trenches.
  • the metal electrode is in Schottky contact with the sidewall of the protrusion (which is also the sidewall of the trench 102 ), and when a forward bias is applied, current flows through the metal The electrode flows into the protrusion through the sidewall in contact with the metal electrode Schottky, which further increases the current density of the active area (protrusion) between the trenches.
  • a reverse voltage is applied, the doping located at the bottom of the adjacent trench The active region between them is fully depleted, which further reduces the leakage current and improves the withstand voltage performance during the period.
  • the sidewalls of the trenches are vertical.
  • the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
  • the active region A covers a rectangular area of the surface of the doped layer 101 .
  • the two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
  • 2-6 are schematic diagrams of three-dimensional structures of forming a trench in a doped layer of a first doping type and subsequently forming a doped region of a second doping type at the bottom of the trench.
  • the grooves include at least two strip-shaped grooves arranged side by side along a first direction, wherein the strip-shaped grooves are in a second direction crossing the first direction Extends from a first end of the active region to a second end corresponding to the first end.
  • three strip-shaped trenches 102 are formed in the active region A of the doping layer 101 of the first doping type, and the three strip-shaped trenches 102 are arranged side by side and extend from one end of the active region A to the other. At the same time, the two outermost ends of the three strip-shaped trenches 102 cover the edge of the active region A.
  • the groove includes two strip-shaped grooves arranged side by side along the first direction and a concave groove between the two strip-shaped grooves.
  • two strip-shaped trenches 102 are formed at opposite edges of the active region A of the doping layer 101 of the first doping type, and the two strip-shaped trenches 102 are arranged side by side and in the A concave groove 102A is formed in the middle.
  • At least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
  • at least two rows of trenches are arranged in parallel along the first direction in the doped layer, and the trenches included in each of the at least two rows of trenches are arranged along the second direction.
  • the first direction and the second direction are directions parallel to the edge of the active region A, respectively.
  • two columns of trenches 102 are arranged in the length direction of the active region A of the doped layer 101 of the first doping type, and each column has three trenches 102 arranged in the width direction.
  • neither the first direction nor the second direction is parallel to the edge of the active region A.
  • each column is inclined at 45° to the edge corner, each column has two trenches 102.
  • the trench includes an annular trench and a concave trench provided in the doped layer surrounded by the annular trench.
  • annular trench 102 is formed in the active region A of the doping layer 101 of the first doping type, and a rectangular concave trench 102A is provided in the annular trench 102 .
  • the semiconductor device according to the present invention further includes a doped region 103 of a second doping type located in the doped layer 101 , and the doped region 103 includes a first doped region located at the bottom of the trench. Miscellaneous area 1031.
  • FIGS. 2 to 6 schematic diagrams of the three-dimensional structure of the doped regions of the second doping type formed at the bottom of the trenches are also shown. Wherein, a doped region 103 of a second doped type is formed in the doped layer 101 of the first doped type at the bottom of each trench 102 .
  • the first doping type is N-type
  • the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
  • the method for forming the first doped region 1031 includes:
  • a patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
  • An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
  • the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
  • the masks for forming the trenches 102 and the doping regions 103 of the second doping type are set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
  • the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 .
  • the depth of the impurity region 1032 is smaller than the depth of the trench 102 , so that the doped layer 101 on the outer side of at least part of the sidewall of the trench 102 is in contact with the metal electrode to form a Schottky contact.
  • a second doped region 1032 is provided under the surface of the protrusion 1011, so that after the metal electrode is formed subsequently, the metal electrode not only forms ohmic contact with the first doped region 1031 at the bottom of the trench 102, but also contacts with the surface of the protrusion 1011.
  • the second doped region 1032 forms an ohmic contact.
  • the second doped region 1032 is formed during the formation of the first doped region 1031 .
  • the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer formed on the silicon carbide substrate 100 also exposes at least the area between the trenches 102 .
  • the semiconductor device according to the present invention further includes a metal electrode 107 , wherein the metal electrode 107 includes a first portion of the trench 102 embedded in the doped layer 101 , the first portion is connected to the The first doped region 1031 is in ohmic contact, and the first portion is in Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 .
  • the metal electrode 107 forms an ohmic contact with the first doped region 1031 of the second doping type under the trench bottom, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench.
  • the current flows from the metal electrode 107 through the trench sidewall into the active region A in the doping layer 101 of the first doping type, increasing the current density.
  • the first doping region The 1031 fully depletes the active region formed between the trenches, reduces the leakage current, and improves the withstand voltage performance of the device.
  • the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 , and the metal electrode 107 is also connected to the second doped region. 1032 ohm contact.
  • the current flows through the metal electrode 107 and flows into the doped layer 101 between the trenches 102 through the sidewall of the trench 102 in Schottky contact with the metal electrode 107, increasing the current density in the active region,
  • a reverse voltage is applied, the first doped region 1031 located at the bottom of the trench 102 and the second doped region 1032 located below the top surface of the doped layer 101 are fully depleted of the active region between them, further reducing the leakage current, improving the withstand voltage performance during the period.
  • the semiconductor device further includes a backside electrode 108 on the backside of the silicon carbide substrate 100 .
  • FIG. 8 a method for manufacturing a semiconductor device according to the present invention will be exemplarily described below.
  • 7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • a silicon carbide substrate 100 is provided on which a doping layer 101 of a first doping type is formed.
  • the preparation material of the silicon carbide substrate 100 may be 4H-SiC, the doping type is the first doping type, the doping concentration is 1 ⁇ 10 18 cm ⁇ 3 , and the thickness is 350 ⁇ m.
  • the silicon carbide substrate further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate, and the silicon carbide epitaxial layer is of the first doping type.
  • the thickness of the silicon carbide epitaxial layer is 6 ⁇ m
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 .
  • a silicon carbide power device is formed in which active and termination regions are formed on a silicon carbide substrate.
  • the silicon carbide substrate 100 includes an active region A and a termination region B.
  • the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
  • a doping layer 101 of a first doping type is formed on the silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal region B, for example , with a doping concentration of 1 ⁇ 10 17 cm -3 .
  • the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate.
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type
  • the doping type is P-type, one of low-doped P-type, and high-doped P+ type
  • the second doping type is N-type, low-doped N-type, and one of high-doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and high-doped N+ type
  • the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
  • the first type is N-type
  • the second doping type is P-type
  • trenches 102 are formed in the doped layer 101 .
  • a trench 102 is formed in the active region A in the doped layer 101, and the trench 102 is used to form a trench 102 through the trench sidewall in the active region after the subsequent formation of the doped region of the second doping type.
  • the electrode contacted by the special base allows the current to flow into the active area through the sidewall of the trench when the forward current is loaded, which increases the current path and improves the current density; at the same time, due to the three-dimensional design of the trench structure, the active area can be improved.
  • the proportion of doped regions further increases the current density. When the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
  • trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein.
  • the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
  • the method of forming the trench 102 in the doped layer 101 includes:
  • a patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
  • An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
  • At least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches.
  • three trenches 102 are formed in the doped layer 101 , the doped layers between adjacent trenches 102 form protrusions 1011 , and doped regions of the second doping type and metal are subsequently formed
  • the metal electrode is in Schottky contact with the sidewall of the protrusion 1011 (also the sidewall of the trench 102), and when a forward bias is applied, current flows through the metal electrode through the sidewall in contact with the metal electrode Schottky
  • the protrusions further increase the current density of the active regions (protrusions) between the trenches.
  • a reverse voltage is applied, the doped regions at the bottom of the adjacent trenches are fully depleted of the active regions between them. The leakage current is further reduced, and the withstand voltage performance during the period is improved.
  • the sidewalls of the trenches are vertical.
  • the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
  • the above setting of the area of the sidewall of the trench and the area of the region of the trench is only exemplary, and those skilled in the art should understand that, according to the specific current-voltage design, different trench formation can be designed. area to form Schottky contacts of different areas.
  • the grooves of the present invention may have different shapes, which are the same as the grooves shown in the first embodiment with reference to FIGS. 2-6 , and are not limited to the grooves shown in FIGS. 2-6 . The example of the slot will not be repeated here.
  • the active region A covers a rectangular area of the surface of the doped layer 101 .
  • the two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
  • a doped region 103 of a second doping type is formed in the doped layer 101 , wherein the doped region 103 includes a first doped region 1031 located at the bottom of the trench.
  • the doped layer above the first doped region 1031 does not form a doped region; that is, no doped region is formed on the sidewall of the trench 102 and the surface of the protrusion 1011 .
  • the first doping type is N-type
  • the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
  • the method for forming the first doped region 1031 includes:
  • a patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
  • An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
  • the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
  • the mask for forming the trench 102 and the doping region for forming the second doping type is set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
  • the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer is formed on the silicon carbide substrate 100 .
  • the film layer also exposes at least the surface of the doped layer between the trenches 102, so that the doped region 103 of the second doping type is also formed in the doped layer where the trench 102 is not formed.
  • a first doped region 1031 located at the bottom of the trench 102 and a second doped region 1032 located below the surface of the protrusion 1011 are formed, wherein the first doped region 1031 is formed at the bottom of the trench 102
  • the second doped region 1032 has a second depth, which is smaller than the depth of the recessed trench 102 , so that at least part of the sidewall of the recessed trench 102 is not doped to form a second doping type doped region.
  • a second doped region 1032 is formed on the surface of the protruding portion 1011 , so that after the metal electrode is subsequently formed, in addition to forming ohmic contact with the first doped region 1031 at the bottom of the trench 102 , the metal electrode also forms an ohmic contact with the first doped region 1031 on the surface of the protruding portion 1011 .
  • the two doped regions 1032 form ohmic contacts.
  • the doped regions (first doped regions 1031 ) at the bottom of adjacent trenches and the doped regions below the surface of the protrusion between adjacent trenches (The second doped region 1032) fully depletes the active region between them, which further reduces the leakage current and improves the withstand voltage performance during the period.
  • a dielectric layer 104 is formed on the surface of the silicon carbide substrate 100 .
  • a dielectric layer 104 is formed on the surface of the silicon carbide substrate 100, and holes for forming metal electrodes are subsequently formed in the dielectric layer, wherein the areas other than the metal electrodes to be formed are covered by the dielectric layer, and finally required circuit connections are formed.
  • the method of forming the dielectric layer 104 includes:
  • a chemical mechanical polishing process is performed to planarize the dielectric material layer to form the dielectric layer 104 .
  • holes 106 are formed in the dielectric layer 104 , and the holes 106 expose the trenches 102 .
  • the finally formed metal electrode fills the trench 102, so that the formed metal electrode forms an ohmic contact with the first doped region 1031 located under the bottom of the trench 102, and is in ohmic contact with the trench 102.
  • the doped layers 101 on the sidewalls of 102 form Schottky contacts.
  • the doping layer 101 of the first doping type between adjacent trenches 102 forms a protrusion 1011 and is formed in the doping layer 101 below the surface of the protrusion 1011, the metal electrode An ohmic contact is also formed with the second doped region 1032 on the surface of the protrusion 1011 .
  • the method of forming the hole 106 includes:
  • a patterned mask layer 105 is formed on the dielectric layer 104, and the patterned mask layer 105 exposes the area where the holes are to be formed;
  • An etching process is performed using the patterned mask layer 105 as a mask to form holes 106 .
  • a metal layer is formed in the hole 106 to form the metal electrode 107 .
  • the metal electrode includes a portion filling the trench 102 and a portion above the doped layer 101 .
  • the method of forming the metal electrode 107 includes:
  • a chemical mechanical polishing process is performed to remove the metal material layer above the dielectric layer 104 to form a metal electrode.
  • a doped region 1031 forms an ohmic contact, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench.
  • the doped layer 101 is formed between two adjacent trenches 102
  • the protrusion 1011, and the first doping region 1031 and the second doping region 1032 of the second doping type are formed in the doped layer 101 of the first doping type below the bottom of the trench 102 and below the surface of the protrusion 1011, respectively , after the metal electrode 107 is formed, the metal electrode 107 is in Schottky contact with part of the sidewall of the protrusion 1011 (also part of the sidewall of the trench 102 ), and when a forward bias is applied, the current passes through the metal electrode and the metal electrode The sidewall of the Schottky contact flows into the protrusion, which further increases the current density of the active region.
  • a reverse voltage is applied, the doped region at the bottom of the adjacent trench is fully depleted of the active region between them, further increasing the current density of the active region.
  • the method further includes forming a back electrode on the back surface of the silicon carbide substrate.
  • a step of forming a backside electrode 108 on the backside of the silicon carbide substrate 100 is further included.
  • a flowchart of a method of fabricating a semiconductor device according to one embodiment of the present invention is shown.
  • a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
  • Step S1 providing a silicon carbide substrate, the silicon carbide substrate including a doping layer of the first doping type;
  • Step S2 forming a trench in the doped layer
  • Step S3 forming a doped region of a second doping type in the doped layer, wherein the doped region includes a first doped region located at the bottom of the trench and above the first doped region The doped region is not formed in the doped layer outside at least part of the sidewall of the trench;
  • Step S4 forming a metal electrode, the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are in the trench.
  • a Schottky contact is formed on at least a portion of the sidewall.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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Abstract

L'invention concerne un dispositif à semi-conducteur et son procédé de fabrication. Le dispositif à semi-conducteur comprend : un substrat en carbure de silicium, le substrat en carbure de silicium comprenant une couche dopée d'un premier type de dopage, une tranchée étant disposée dans la couche dopée ; une région dopée d'un second type de dopage qui est située sur la couche dopée, la région dopée comprenant une première région dopée située au fond de la tranchée ; et une électrode métallique, l'électrode métallique comprenant une première partie de la tranchée qui est incorporée dans la couche dopée, la première partie étant en contact ohmique avec la première région dopée, et la première partie et une paroi latérale de la tranchée ne formant pas un contact Schottky avec la couche dopée dans la région dopée. Selon le procédé de fabrication d'un dispositif à semi-conducteur et du dispositif à semi-conducteur de la présente invention, la densité de courant est augmentée, le courant de fuite est réduit, et les performances de tension de tenue du dispositif sont améliorées.
PCT/CN2021/113021 2020-12-30 2021-08-17 Dispositif à semi-conducteur et son procédé de fabrication WO2022142371A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116779648A (zh) * 2023-08-18 2023-09-19 深圳平创半导体有限公司 一种肖特基二极管版图结构及其制作方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
US6562706B1 (en) * 2001-12-03 2003-05-13 Industrial Technology Research Institute Structure and manufacturing method of SiC dual metal trench Schottky diode
CN102222701A (zh) * 2011-06-23 2011-10-19 哈尔滨工程大学 一种沟槽结构肖特基器件
CN103579365A (zh) * 2012-07-24 2014-02-12 杭州恩能科技有限公司 一种新型二极管器件
CN209981225U (zh) * 2018-12-20 2020-01-21 上海芯石半导体股份有限公司 一种具有复合沟槽结构的碳化硅肖特基器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6562706B1 (en) * 2001-12-03 2003-05-13 Industrial Technology Research Institute Structure and manufacturing method of SiC dual metal trench Schottky diode
CN102222701A (zh) * 2011-06-23 2011-10-19 哈尔滨工程大学 一种沟槽结构肖特基器件
CN103579365A (zh) * 2012-07-24 2014-02-12 杭州恩能科技有限公司 一种新型二极管器件
CN209981225U (zh) * 2018-12-20 2020-01-21 上海芯石半导体股份有限公司 一种具有复合沟槽结构的碳化硅肖特基器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116779648A (zh) * 2023-08-18 2023-09-19 深圳平创半导体有限公司 一种肖特基二极管版图结构及其制作方法

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