WO2022142371A1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
WO2022142371A1
WO2022142371A1 PCT/CN2021/113021 CN2021113021W WO2022142371A1 WO 2022142371 A1 WO2022142371 A1 WO 2022142371A1 CN 2021113021 W CN2021113021 W CN 2021113021W WO 2022142371 A1 WO2022142371 A1 WO 2022142371A1
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trench
doped
layer
doped region
trenches
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PCT/CN2021/113021
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French (fr)
Chinese (zh)
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方冬
肖魁
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无锡华润上华科技有限公司
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Publication of WO2022142371A1 publication Critical patent/WO2022142371A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • Silicon carbide is a group IV-IV compound material, which has the characteristics of high hardness, high chemical stability, high thermal conductivity, wide band gap, high critical electric field strength, and high saturation migration rate. Silicon carbide power devices greatly improve the performance of semiconductor devices. SiC JBS has no minority carrier storage during operation, fast reverse recovery, and low switching loss.
  • the Schottky diode (SBD) and the PiN structure are combined, and the P-type region in the PiN structure is formed in the N-type active region, making the Schottky contact between the electrode and the active region.
  • the ohmic contact between the electrode and the PiN structure in the active region is formed in the same plane, so that the forward current passes from the electrode through the Schottky contact region to the current density of the N-type active region when forward bias is applied. Restricted, when reverse bias is applied, the leakage current is large and the withstand voltage is limited.
  • the present invention provides a manufacturing method of a semiconductor device.
  • the present invention provides a semiconductor device, comprising:
  • the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
  • the doped region including a first doped region at the bottom of the trench;
  • the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench
  • the doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
  • the doped region further includes a second doped region located below the surface of the doped layer, the depth of the second doped region is smaller than the depth of the trench, and the metal electrode further includes a second doped region located below the surface of the doped layer. A second portion above the doped layer, the second portion is in ohmic contact with the second doped region.
  • At least two trenches are provided in the doped layer.
  • the trenches include at least two strip-shaped trenches juxtaposed along a first direction, wherein the strip-shaped trenches extend from the active region in a second direction crossing the first direction.
  • the first end extends to a second end corresponding to the first end.
  • the grooves include concave grooves between the strip grooves.
  • At least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
  • the trench includes an annular concave trench and a concave trench provided in the doped layer surrounded by the annular concave trench.
  • the present invention also provides a method for manufacturing a semiconductor device, comprising:
  • a silicon carbide substrate including a doping layer of a first doping type
  • a doped region of a second doping type is formed in the doped layer, wherein the doped region includes a first doped region at the bottom of the trench, and at least a portion above the first doped region The doped region is not formed in the doped layer outside the sidewall of the trench;
  • the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are on the sidewall of the trench Schottky contacts are formed at least in part.
  • At least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches.
  • the method for forming a doped region of the second doping type at the bottom of the trench includes:
  • An ion implantation process is performed to convert the doped layer at a first depth below the bottom of the trench into the doped region.
  • the step of forming a doped region of the second doped type at the bottom of the trench also converts the doped layer at a second depth below the surface of the protrusion into the doped region. impurity region, the second depth is smaller than the depth of the concave trench.
  • the method of forming a metal electrode includes:
  • an etching process is performed to form holes, and the holes expose the trenches;
  • the holes are filled with metal.
  • a trench is formed in the active region, and a doping region opposite to the doping type of the active region is formed at the bottom of the trench in the active region, so that the electrode finally formed Schottky contacts are formed between the trench sidewalls and the active region.
  • the current flows into the active region through the metal electrode forming Schottky contact on the sidewall of the trench, and the electron concentration near the doping region of the second doping type increases, increasing the current path and improving the current density
  • the ratio of the active region to the doped region can be increased, and the current density can be further increased; by design, when the reverse current is loaded, the doped region pair can be formed between the trenches
  • the active region of the device is fully depleted, the leakage current is reduced, and the withstand voltage performance of the device is improved.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
  • FIGS. 7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 8 is an exemplary flowchart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • the present invention provides a semiconductor device, comprising:
  • the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
  • the doped region including a first doped region at the bottom of the trench;
  • the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench
  • the doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
  • a semiconductor device includes:
  • a silicon carbide substrate 100, the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, and a trench 102 is provided in the doping layer 101;
  • the doped region 103 including a first doped region 1031 located at the bottom of the trench 102;
  • Metal electrode 107 wherein said metal electrode 107 includes a first portion of said trench 102 embedded in said doped layer 101, said first portion being in ohmic contact with said first doped region 1031, said first portion Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 .
  • the semiconductor device includes a silicon carbide substrate 100 , and the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, exemplarily, the preparation material of the silicon carbide substrate 100 It can be 4H-SiC, the doping type is the first doping type, the doping concentration is 1 ⁇ 10 18 cm ⁇ 3 , and the thickness is 350 ⁇ m.
  • a first doping type exemplarily, the preparation material of the silicon carbide substrate 100 It can be 4H-SiC
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 18 cm ⁇ 3
  • the thickness is 350 ⁇ m.
  • the silicon carbide substrate 100 further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate 100, and the silicon carbide epitaxial layer is of the first doping type.
  • the thickness of the silicon carbide epitaxial layer is 6 ⁇ m
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 .
  • a silicon carbide power device is formed, wherein an active region and a termination region are formed on a silicon carbide substrate 100 .
  • the silicon carbide substrate 100 includes an active region A and a termination region B.
  • the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
  • the semiconductor device includes a doping layer 101 of a first doping type on a silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal Region B, exemplary, has a doping concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate 100 .
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type
  • the doping type is P-type, one of low-doped P-type, and high-doped P+ type
  • the second doping type is N-type, low-doped N-type, and one of high-doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and high-doped N+ type
  • the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
  • the first type is N-type
  • the second doping type is P-type
  • the semiconductor device according to the present invention is provided with trenches 102 in the doping layer 101 of the first doping type.
  • a trench 102 is provided in the active region A in the doped layer 101, the doped layer at the bottom of the trench 102 forms a doped region of the second doping type, and the trench 102 is filled with a metal electrode, when a forward current is loaded , the current can flow into the active region through the sidewall of the trench, increasing the current path and improving the current density; at the same time, due to the three-dimensional design of the trench structure, the ratio of the active region to the doped region can be increased, further improving the current density.
  • the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
  • the trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein. Meanwhile, in the drawings of the embodiments of the present invention, the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
  • the method of forming the trench 102 in the doped layer 101 includes:
  • a patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
  • An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
  • At least two trenches are formed in the doped layer.
  • protrusions are formed in the doped layer between adjacent two of the trenches.
  • the metal electrode is in Schottky contact with the sidewall of the protrusion (which is also the sidewall of the trench 102 ), and when a forward bias is applied, current flows through the metal The electrode flows into the protrusion through the sidewall in contact with the metal electrode Schottky, which further increases the current density of the active area (protrusion) between the trenches.
  • a reverse voltage is applied, the doping located at the bottom of the adjacent trench The active region between them is fully depleted, which further reduces the leakage current and improves the withstand voltage performance during the period.
  • the sidewalls of the trenches are vertical.
  • the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
  • the active region A covers a rectangular area of the surface of the doped layer 101 .
  • the two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
  • 2-6 are schematic diagrams of three-dimensional structures of forming a trench in a doped layer of a first doping type and subsequently forming a doped region of a second doping type at the bottom of the trench.
  • the grooves include at least two strip-shaped grooves arranged side by side along a first direction, wherein the strip-shaped grooves are in a second direction crossing the first direction Extends from a first end of the active region to a second end corresponding to the first end.
  • three strip-shaped trenches 102 are formed in the active region A of the doping layer 101 of the first doping type, and the three strip-shaped trenches 102 are arranged side by side and extend from one end of the active region A to the other. At the same time, the two outermost ends of the three strip-shaped trenches 102 cover the edge of the active region A.
  • the groove includes two strip-shaped grooves arranged side by side along the first direction and a concave groove between the two strip-shaped grooves.
  • two strip-shaped trenches 102 are formed at opposite edges of the active region A of the doping layer 101 of the first doping type, and the two strip-shaped trenches 102 are arranged side by side and in the A concave groove 102A is formed in the middle.
  • At least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
  • at least two rows of trenches are arranged in parallel along the first direction in the doped layer, and the trenches included in each of the at least two rows of trenches are arranged along the second direction.
  • the first direction and the second direction are directions parallel to the edge of the active region A, respectively.
  • two columns of trenches 102 are arranged in the length direction of the active region A of the doped layer 101 of the first doping type, and each column has three trenches 102 arranged in the width direction.
  • neither the first direction nor the second direction is parallel to the edge of the active region A.
  • each column is inclined at 45° to the edge corner, each column has two trenches 102.
  • the trench includes an annular trench and a concave trench provided in the doped layer surrounded by the annular trench.
  • annular trench 102 is formed in the active region A of the doping layer 101 of the first doping type, and a rectangular concave trench 102A is provided in the annular trench 102 .
  • the semiconductor device according to the present invention further includes a doped region 103 of a second doping type located in the doped layer 101 , and the doped region 103 includes a first doped region located at the bottom of the trench. Miscellaneous area 1031.
  • FIGS. 2 to 6 schematic diagrams of the three-dimensional structure of the doped regions of the second doping type formed at the bottom of the trenches are also shown. Wherein, a doped region 103 of a second doped type is formed in the doped layer 101 of the first doped type at the bottom of each trench 102 .
  • the first doping type is N-type
  • the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
  • the method for forming the first doped region 1031 includes:
  • a patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
  • An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
  • the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
  • the masks for forming the trenches 102 and the doping regions 103 of the second doping type are set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
  • the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 .
  • the depth of the impurity region 1032 is smaller than the depth of the trench 102 , so that the doped layer 101 on the outer side of at least part of the sidewall of the trench 102 is in contact with the metal electrode to form a Schottky contact.
  • a second doped region 1032 is provided under the surface of the protrusion 1011, so that after the metal electrode is formed subsequently, the metal electrode not only forms ohmic contact with the first doped region 1031 at the bottom of the trench 102, but also contacts with the surface of the protrusion 1011.
  • the second doped region 1032 forms an ohmic contact.
  • the second doped region 1032 is formed during the formation of the first doped region 1031 .
  • the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer formed on the silicon carbide substrate 100 also exposes at least the area between the trenches 102 .
  • the semiconductor device according to the present invention further includes a metal electrode 107 , wherein the metal electrode 107 includes a first portion of the trench 102 embedded in the doped layer 101 , the first portion is connected to the The first doped region 1031 is in ohmic contact, and the first portion is in Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 .
  • the metal electrode 107 forms an ohmic contact with the first doped region 1031 of the second doping type under the trench bottom, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench.
  • the current flows from the metal electrode 107 through the trench sidewall into the active region A in the doping layer 101 of the first doping type, increasing the current density.
  • the first doping region The 1031 fully depletes the active region formed between the trenches, reduces the leakage current, and improves the withstand voltage performance of the device.
  • the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 , and the metal electrode 107 is also connected to the second doped region. 1032 ohm contact.
  • the current flows through the metal electrode 107 and flows into the doped layer 101 between the trenches 102 through the sidewall of the trench 102 in Schottky contact with the metal electrode 107, increasing the current density in the active region,
  • a reverse voltage is applied, the first doped region 1031 located at the bottom of the trench 102 and the second doped region 1032 located below the top surface of the doped layer 101 are fully depleted of the active region between them, further reducing the leakage current, improving the withstand voltage performance during the period.
  • the semiconductor device further includes a backside electrode 108 on the backside of the silicon carbide substrate 100 .
  • FIG. 8 a method for manufacturing a semiconductor device according to the present invention will be exemplarily described below.
  • 7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • a silicon carbide substrate 100 is provided on which a doping layer 101 of a first doping type is formed.
  • the preparation material of the silicon carbide substrate 100 may be 4H-SiC, the doping type is the first doping type, the doping concentration is 1 ⁇ 10 18 cm ⁇ 3 , and the thickness is 350 ⁇ m.
  • the silicon carbide substrate further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate, and the silicon carbide epitaxial layer is of the first doping type.
  • the thickness of the silicon carbide epitaxial layer is 6 ⁇ m
  • the doping type is the first doping type
  • the doping concentration is 1 ⁇ 10 16 cm ⁇ 3 .
  • a silicon carbide power device is formed in which active and termination regions are formed on a silicon carbide substrate.
  • the silicon carbide substrate 100 includes an active region A and a termination region B.
  • the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
  • a doping layer 101 of a first doping type is formed on the silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal region B, for example , with a doping concentration of 1 ⁇ 10 17 cm -3 .
  • the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate.
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type
  • the doping type is P-type, one of low-doped P-type, and high-doped P+ type
  • the second doping type is N-type, low-doped N-type, and one of high-doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and high-doped N+ type
  • the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
  • the first type is N-type
  • the second doping type is P-type
  • trenches 102 are formed in the doped layer 101 .
  • a trench 102 is formed in the active region A in the doped layer 101, and the trench 102 is used to form a trench 102 through the trench sidewall in the active region after the subsequent formation of the doped region of the second doping type.
  • the electrode contacted by the special base allows the current to flow into the active area through the sidewall of the trench when the forward current is loaded, which increases the current path and improves the current density; at the same time, due to the three-dimensional design of the trench structure, the active area can be improved.
  • the proportion of doped regions further increases the current density. When the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
  • trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein.
  • the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
  • the method of forming the trench 102 in the doped layer 101 includes:
  • a patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
  • An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
  • At least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches.
  • three trenches 102 are formed in the doped layer 101 , the doped layers between adjacent trenches 102 form protrusions 1011 , and doped regions of the second doping type and metal are subsequently formed
  • the metal electrode is in Schottky contact with the sidewall of the protrusion 1011 (also the sidewall of the trench 102), and when a forward bias is applied, current flows through the metal electrode through the sidewall in contact with the metal electrode Schottky
  • the protrusions further increase the current density of the active regions (protrusions) between the trenches.
  • a reverse voltage is applied, the doped regions at the bottom of the adjacent trenches are fully depleted of the active regions between them. The leakage current is further reduced, and the withstand voltage performance during the period is improved.
  • the sidewalls of the trenches are vertical.
  • the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
  • the above setting of the area of the sidewall of the trench and the area of the region of the trench is only exemplary, and those skilled in the art should understand that, according to the specific current-voltage design, different trench formation can be designed. area to form Schottky contacts of different areas.
  • the grooves of the present invention may have different shapes, which are the same as the grooves shown in the first embodiment with reference to FIGS. 2-6 , and are not limited to the grooves shown in FIGS. 2-6 . The example of the slot will not be repeated here.
  • the active region A covers a rectangular area of the surface of the doped layer 101 .
  • the two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
  • a doped region 103 of a second doping type is formed in the doped layer 101 , wherein the doped region 103 includes a first doped region 1031 located at the bottom of the trench.
  • the doped layer above the first doped region 1031 does not form a doped region; that is, no doped region is formed on the sidewall of the trench 102 and the surface of the protrusion 1011 .
  • the first doping type is N-type
  • the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
  • the method for forming the first doped region 1031 includes:
  • a patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
  • An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
  • the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
  • the mask for forming the trench 102 and the doping region for forming the second doping type is set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
  • the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer is formed on the silicon carbide substrate 100 .
  • the film layer also exposes at least the surface of the doped layer between the trenches 102, so that the doped region 103 of the second doping type is also formed in the doped layer where the trench 102 is not formed.
  • a first doped region 1031 located at the bottom of the trench 102 and a second doped region 1032 located below the surface of the protrusion 1011 are formed, wherein the first doped region 1031 is formed at the bottom of the trench 102
  • the second doped region 1032 has a second depth, which is smaller than the depth of the recessed trench 102 , so that at least part of the sidewall of the recessed trench 102 is not doped to form a second doping type doped region.
  • a second doped region 1032 is formed on the surface of the protruding portion 1011 , so that after the metal electrode is subsequently formed, in addition to forming ohmic contact with the first doped region 1031 at the bottom of the trench 102 , the metal electrode also forms an ohmic contact with the first doped region 1031 on the surface of the protruding portion 1011 .
  • the two doped regions 1032 form ohmic contacts.
  • the doped regions (first doped regions 1031 ) at the bottom of adjacent trenches and the doped regions below the surface of the protrusion between adjacent trenches (The second doped region 1032) fully depletes the active region between them, which further reduces the leakage current and improves the withstand voltage performance during the period.
  • a dielectric layer 104 is formed on the surface of the silicon carbide substrate 100 .
  • a dielectric layer 104 is formed on the surface of the silicon carbide substrate 100, and holes for forming metal electrodes are subsequently formed in the dielectric layer, wherein the areas other than the metal electrodes to be formed are covered by the dielectric layer, and finally required circuit connections are formed.
  • the method of forming the dielectric layer 104 includes:
  • a chemical mechanical polishing process is performed to planarize the dielectric material layer to form the dielectric layer 104 .
  • holes 106 are formed in the dielectric layer 104 , and the holes 106 expose the trenches 102 .
  • the finally formed metal electrode fills the trench 102, so that the formed metal electrode forms an ohmic contact with the first doped region 1031 located under the bottom of the trench 102, and is in ohmic contact with the trench 102.
  • the doped layers 101 on the sidewalls of 102 form Schottky contacts.
  • the doping layer 101 of the first doping type between adjacent trenches 102 forms a protrusion 1011 and is formed in the doping layer 101 below the surface of the protrusion 1011, the metal electrode An ohmic contact is also formed with the second doped region 1032 on the surface of the protrusion 1011 .
  • the method of forming the hole 106 includes:
  • a patterned mask layer 105 is formed on the dielectric layer 104, and the patterned mask layer 105 exposes the area where the holes are to be formed;
  • An etching process is performed using the patterned mask layer 105 as a mask to form holes 106 .
  • a metal layer is formed in the hole 106 to form the metal electrode 107 .
  • the metal electrode includes a portion filling the trench 102 and a portion above the doped layer 101 .
  • the method of forming the metal electrode 107 includes:
  • a chemical mechanical polishing process is performed to remove the metal material layer above the dielectric layer 104 to form a metal electrode.
  • a doped region 1031 forms an ohmic contact, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench.
  • the doped layer 101 is formed between two adjacent trenches 102
  • the protrusion 1011, and the first doping region 1031 and the second doping region 1032 of the second doping type are formed in the doped layer 101 of the first doping type below the bottom of the trench 102 and below the surface of the protrusion 1011, respectively , after the metal electrode 107 is formed, the metal electrode 107 is in Schottky contact with part of the sidewall of the protrusion 1011 (also part of the sidewall of the trench 102 ), and when a forward bias is applied, the current passes through the metal electrode and the metal electrode The sidewall of the Schottky contact flows into the protrusion, which further increases the current density of the active region.
  • a reverse voltage is applied, the doped region at the bottom of the adjacent trench is fully depleted of the active region between them, further increasing the current density of the active region.
  • the method further includes forming a back electrode on the back surface of the silicon carbide substrate.
  • a step of forming a backside electrode 108 on the backside of the silicon carbide substrate 100 is further included.
  • a flowchart of a method of fabricating a semiconductor device according to one embodiment of the present invention is shown.
  • a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
  • Step S1 providing a silicon carbide substrate, the silicon carbide substrate including a doping layer of the first doping type;
  • Step S2 forming a trench in the doped layer
  • Step S3 forming a doped region of a second doping type in the doped layer, wherein the doped region includes a first doped region located at the bottom of the trench and above the first doped region The doped region is not formed in the doped layer outside at least part of the sidewall of the trench;
  • Step S4 forming a metal electrode, the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are in the trench.
  • a Schottky contact is formed on at least a portion of the sidewall.

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Abstract

Disclosed are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a silicon carbide substrate, the silicon carbide substrate comprising a doped layer of a first doping type, a trench being provided in the doped layer; a doped region of a second doping type that is located on the doped layer, the doped region comprising a first doped region located at the bottom of the trench; and a metal electrode, the metal electrode comprising a first portion of the trench that is embedded in the doped layer, the first portion being in ohmic contact with the first doped region, and the first portion and a sidewall of the trench not forming Schottky contact with the doped layer in the doped region. According to the manufacturing method for a semiconductor device and the semiconductor device of the present invention, current density is increased, leakage current is reduced, and the voltage withstanding performance of the device is improved.

Description

一种半导体器件及其制造方法A kind of semiconductor device and its manufacturing method 技术领域technical field
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制造方法。The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
背景技术Background technique
碳化硅是Ⅳ-Ⅳ族化合物材料，具有高硬度、高化学稳定性、高热导率、宽禁带、高临界电场强度、高饱和迁移速率等特点。碳化硅功率器件大大提升半导体器件的性能，SiC JBS在工作过程中没有少数载流子储存，反向恢复快，开关损耗低。Silicon carbide is a group IV-IV compound material, which has the characteristics of high hardness, high chemical stability, high thermal conductivity, wide band gap, high critical electric field strength, and high saturation migration rate. Silicon carbide power devices greatly improve the performance of semiconductor devices. SiC JBS has no minority carrier storage during operation, fast reverse recovery, and low switching loss.
现有的SiC JBS中将肖特基二极管(SBD)和PiN结构结合在一起，PiN结构中的P型区域形成在N型有源区内，使电极与有源区之间的肖特基接触和电极与有源区内的PiN结构之间的欧姆接触形成在同一平面内，从而使得加正向偏压时正向电流由电极穿过肖特基接触区到达N型有源区的电流密度受到限制，加反向偏压时，漏电流较大，耐压受到限制。In the existing SiC JBS, the Schottky diode (SBD) and the PiN structure are combined, and the P-type region in the PiN structure is formed in the N-type active region, making the Schottky contact between the electrode and the active region. The ohmic contact between the electrode and the PiN structure in the active region is formed in the same plane, so that the forward current passes from the electrode through the Schottky contact region to the current density of the N-type active region when forward bias is applied. Restricted, when reverse bias is applied, the leakage current is large and the withstand voltage is limited.
为了解决现有技术中的问题，本发明提供了一种半导体器件的制造方法。In order to solve the problems in the prior art, the present invention provides a manufacturing method of a semiconductor device.
发明内容SUMMARY OF THE INVENTION
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.
为了解决现有技术中的问题，本发明提供了一种半导体器件，包括：In order to solve the problems in the prior art, the present invention provides a semiconductor device, comprising:
碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层，所述掺杂层中设置有沟槽；a silicon carbide substrate, the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
位于所述掺杂层中的第二掺杂类型的掺杂区，所述掺杂区包括位于所述沟槽底部的第一掺杂区；以及a doped region of a second doping type in the doped layer, the doped region including a first doped region at the bottom of the trench; and
金属电极，其中，所述金属电极包括嵌入所述掺杂层中的所述沟槽的第一部分，所述第一部分与所述第一掺杂区欧姆接触，所述第一部分与所述沟槽的侧壁上未形成所述掺杂区的所述掺杂层肖特基接触。a metal electrode, wherein the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench The doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
示例性地，所述掺杂区还包括位于所述掺杂层表面以下的第二掺杂区，所述第二掺杂区的深度小于所述沟槽的深度，所述金属电极还包括位于所述掺杂层上方的第二部分，所述第二部分与所述第二掺杂区欧姆接触。Exemplarily, the doped region further includes a second doped region located below the surface of the doped layer, the depth of the second doped region is smaller than the depth of the trench, and the metal electrode further includes a second doped region located below the surface of the doped layer. A second portion above the doped layer, the second portion is in ohmic contact with the second doped region.
示例性地，所述掺杂层中设置有至少两个沟槽。Exemplarily, at least two trenches are provided in the doped layer.
示例性地，所述沟槽包括沿着第一方向并列设置的至少两个条状沟槽，其中所述条状沟槽在与所述第一方向交叉的第二方向上从有源区的第一端延伸到与所述第一端相对应的第二端。Exemplarily, the trenches include at least two strip-shaped trenches juxtaposed along a first direction, wherein the strip-shaped trenches extend from the active region in a second direction crossing the first direction. The first end extends to a second end corresponding to the first end.
示例性地，所述沟槽包括位于所述条状沟槽之间的凹型沟槽。Exemplarily, the grooves include concave grooves between the strip grooves.
示例性地，所述掺杂层中设置有至少两列沟槽，其中，所述至少两列沟槽中的每一列至少包括两个所述沟槽。Exemplarily, at least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
示例性地，所述沟槽包括环形凹型沟槽以及在所述环形凹型沟槽所环绕的所述掺杂层中设置的凹型沟槽。Exemplarily, the trench includes an annular concave trench and a concave trench provided in the doped layer surrounded by the annular concave trench.
本发明还提供一种半导体器件的制造方法，包括：The present invention also provides a method for manufacturing a semiconductor device, comprising:
提供碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层；providing a silicon carbide substrate including a doping layer of a first doping type;
在所述掺杂层中形成沟槽；forming trenches in the doped layer;
在所述掺杂层中形成第二掺杂类型的掺杂区，其中所述掺杂区包括位于所述沟槽底部的第一掺杂区，并且所述第一掺杂区以上的至少部分所述沟槽的侧壁外侧的所述掺杂层中未形成所述掺杂区；A doped region of a second doping type is formed in the doped layer, wherein the doped region includes a first doped region at the bottom of the trench, and at least a portion above the first doped region The doped region is not formed in the doped layer outside the sidewall of the trench;
形成金属电极，所述金属电极至少填充所述沟槽，其中，所述金属电极与所述掺杂区形成欧姆接触，所述金属电极与所述掺杂层在所述沟槽的侧壁的至少部分上形成肖特基接触。forming a metal electrode, the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are on the sidewall of the trench Schottky contacts are formed at least in part.
示例性地，在所述掺杂层中形成至少两个沟槽，在相邻两个所述沟槽之间的所述掺杂层形成突出部。Exemplarily, at least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches.
示例性地，在所述沟槽的底部形成第二掺杂类型的掺杂区的方法包括：Exemplarily, the method for forming a doped region of the second doping type at the bottom of the trench includes:
执行离子注入工艺，以将所述沟槽底部以下的第一深度的所述掺杂层转化为所述掺杂区。An ion implantation process is performed to convert the doped layer at a first depth below the bottom of the trench into the doped region.
示例性地，所述在所述沟槽的底部形成第二掺杂类型的掺杂区的步骤，还将所述突出部的表面以下的第二深度的所述掺杂层转化为所述掺杂区，所述第二深度小于所述凹型沟槽的深度。Exemplarily, the step of forming a doped region of the second doped type at the bottom of the trench also converts the doped layer at a second depth below the surface of the protrusion into the doped region. impurity region, the second depth is smaller than the depth of the concave trench.
示例性地，所述形成金属电极的方法包括：Exemplarily, the method of forming a metal electrode includes:
执行沉积工艺，以形成覆盖所述碳化硅衬底并填充所述沟槽的介质层；performing a deposition process to form a dielectric layer covering the silicon carbide substrate and filling the trenches;
执行光刻工艺，以形成覆盖在所述介质层的表面的图案化的掩膜层；performing a photolithography process to form a patterned mask layer covering the surface of the dielectric layer;
以所述图案化的掩膜层为掩膜，执行刻蚀工艺，以形成孔，所述孔露出所述沟槽；Using the patterned mask layer as a mask, an etching process is performed to form holes, and the holes expose the trenches;
在所述孔中填充金属。The holes are filled with metal.
根据本发明的半导体器件及其制造方法，在有源区内形成沟槽，将与有源区的掺杂类 型相反的掺杂区形成在有源区内的沟槽底部，使最终形成的电极通过沟槽侧壁与有源区之间形成肖特基接触。在加载正向电流时，电流通过沟槽侧壁形成肖特基接触的金属电极流入有源区，第二掺杂类型的掺杂区附近的电子浓度增加，增加了电流路径，提高了电流密度；同时，由于沟槽结构的三维设计，可以提高有源区对掺杂区的比例，进一步提高电流密度；可以通过设计，在加载反向电流时，使掺杂区对形成在沟槽之间的有源区充分耗尽，减小漏电流，提高了器件的耐压性能。According to the semiconductor device and the manufacturing method thereof of the present invention, a trench is formed in the active region, and a doping region opposite to the doping type of the active region is formed at the bottom of the trench in the active region, so that the electrode finally formed Schottky contacts are formed between the trench sidewalls and the active region. When a forward current is loaded, the current flows into the active region through the metal electrode forming Schottky contact on the sidewall of the trench, and the electron concentration near the doping region of the second doping type increases, increasing the current path and improving the current density At the same time, due to the three-dimensional design of the trench structure, the ratio of the active region to the doped region can be increased, and the current density can be further increased; by design, when the reverse current is loaded, the doped region pair can be formed between the trenches The active region of the device is fully depleted, the leakage current is reduced, and the withstand voltage performance of the device is improved.
附图说明Description of drawings
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.
附图中：In the attached picture:
图1为根据本发明的一个实施例的一种半导体器件的结构示意图；1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
图2为根据本发明的一个实施例的一种半导体器件中在有源区中形成沟槽的半导体器件的结构示意图。2 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
图3为根据本发明的一个实施例的一种半导体器件中在有源区中形成沟槽的半导体器件的结构示意图。3 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
图4为根据本发明的一个实施例的一种半导体器件中在有源区中形成沟槽的半导体器件的结构示意图。4 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
图5为根据本发明的一个实施例的一种半导体器件中在有源区中形成沟槽的半导体器件的结构示意图。5 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
图6为根据本发明的一个实施例的一种半导体器件中在有源区中形成沟槽的半导体器件的结构示意图。6 is a schematic structural diagram of a semiconductor device in which trenches are formed in an active region in a semiconductor device according to an embodiment of the present invention.
图7A-图7H为根据本发明的一个实施例的一种半导体器件的制造方法中形成的半导体器件的结构示意图；7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
图8为根据本发明的一个实施例的一种半导体器件的制造方法的示例性流程图。FIG. 8 is an exemplary flowchart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
具体实施方式Detailed ways
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.
现在，将参照附图更详细地描述根据本发明的示例性实施例。然而，这些示例性实施例可以多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施例。应当理解的是，提供这些实施例是为了使得本发明的公开彻底且完整，并且将这些示例性实施例的构思充分传达给本领域普通技术人员。在附图中，为了清楚起见，夸大了层和区域的厚度，并且使用相同的附图标记表示相同的元件，因而将省略对它们的描述。Now, exemplary embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same reference numerals are used to denote the same elements, and thus their descriptions will be omitted.
实施例一Example 1
为了解决现有技术中的问题，本发明提供了一种半导体器件，包括：In order to solve the problems in the prior art, the present invention provides a semiconductor device, comprising:
碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层，所述掺杂层中设置有沟槽；a silicon carbide substrate, the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
位于所述掺杂层中的第二掺杂类型的掺杂区，所述掺杂区包括位于所述沟槽底部的第一掺杂区；以及a doped region of a second doping type in the doped layer, the doped region including a first doped region at the bottom of the trench; and
金属电极，其中，所述金属电极包括嵌入所述掺杂层中的所述沟槽的第一部分，所述第一部分与所述第一掺杂区欧姆接触，所述第一部分与所述沟槽的侧壁上未形成所述掺杂区的所述掺杂层肖特基接触。a metal electrode, wherein the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench The doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
参看图1，示出了根据本发明的一个实施例的半导体器件的结构示意图。如图1所示，半导体器件包括：Referring to FIG. 1 , a schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown. As shown in Figure 1, a semiconductor device includes:
碳化硅衬底100，所述碳化硅衬底100包括第一掺杂类型的掺杂层101，所述掺杂层101中设置有沟槽102；A silicon carbide substrate 100, the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, and a trench 102 is provided in the doping layer 101;
位于所述掺杂层101中的第二掺杂类型的掺杂区103，所述掺杂区103包括位于所述沟槽102底部的第一掺杂区1031；以及a doped region 103 of the second doping type located in the doped layer 101, the doped region 103 including a first doped region 1031 located at the bottom of the trench 102; and
金属电极107，其中，所述金属电极107包括嵌入所述掺杂层101中的所述沟槽102的第一部分，所述第一部分与所述第一掺杂区1031欧姆接触，所述第一部分与所述沟槽102的侧壁上未形成所述掺杂区103的所述掺杂层101肖特基接触。 Metal electrode 107, wherein said metal electrode 107 includes a first portion of said trench 102 embedded in said doped layer 101, said first portion being in ohmic contact with said first doped region 1031, said first portion Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 .
如图1所示，根据本发明的半导体器件包括碳化硅衬底100，所述碳化硅衬底100包括第一掺杂类型的掺杂层101，示例性的，碳化硅衬底100的制备材料可为4H-SiC，掺杂类型为第一掺杂类型，掺杂浓度为1×10 18cm -3，厚度为350μm。 As shown in FIG. 1 , the semiconductor device according to the present invention includes a silicon carbide substrate 100 , and the silicon carbide substrate 100 includes a doping layer 101 of a first doping type, exemplarily, the preparation material of the silicon carbide substrate 100 It can be 4H-SiC, the doping type is the first doping type, the doping concentration is 1×10 18 cm −3 , and the thickness is 350 μm.
在根据本发明的一个示例中，所述碳化硅衬底100还包括形成在所述碳化硅衬底100上的碳化硅外延层，所述碳化硅外延层为第一掺杂类型。示例性的，所述碳化硅外延层的厚度为6μm，掺杂类型为第一掺杂类型，掺杂浓度为1×10 16cm -3。 In an example according to the present invention, the silicon carbide substrate 100 further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate 100, and the silicon carbide epitaxial layer is of the first doping type. Exemplarily, the thickness of the silicon carbide epitaxial layer is 6 μm, the doping type is the first doping type, and the doping concentration is 1×10 16 cm −3 .
在根据本发明的一个示例中，形成碳化硅功率器件，其中，碳化硅衬底100上形成有源区和终端区。如图1所示，碳化硅衬底100包括有源区A和终端区B。In one example according to the present invention, a silicon carbide power device is formed, wherein an active region and a termination region are formed on a silicon carbide substrate 100 . As shown in FIG. 1 , the silicon carbide substrate 100 includes an active region A and a termination region B.
需要理解的是，本发明的实施例中，在附图中示出形成在终端区B之间的有源区A仅为一个区域仅仅是示例性的，本领域技术人员应当理解，在实际半导体器件制造中，终端区B之间可以多包括任意个重复设置的有源区A。It should be understood that, in the embodiments of the present invention, the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
继续参看图1，根据本发明的半导体器件在碳化硅衬底100上包括第一掺杂类型的掺杂层101，所述第一掺杂类型掺杂层包括覆盖所述有源区A和终端区B，示例性的，掺杂浓度为1×10 17cm -3。 Continuing to refer to FIG. 1 , the semiconductor device according to the present invention includes a doping layer 101 of a first doping type on a silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal Region B, exemplary, has a doping concentration of 1×10 17 cm −3 .
示例性的，形成所述掺杂层的方法包括执行离子注入工艺，以在所述碳化硅衬底100上形成所述第一掺杂类型的掺杂层101。Exemplarily, the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate 100 .
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。It should be noted that in this specification, the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type The doping type is P-type, one of low-doped P-type, and high-doped P+ type, and the second doping type is N-type, low-doped N-type, and one of high-doped N+ type. Or conversely, the first doping type is one of N-type, low-doped N-type, and high-doped N+ type, and the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
在本实施例中，所述第一类型为N型，第二掺杂类型为P型。In this embodiment, the first type is N-type, and the second doping type is P-type.
继续参看图1，根据本发明的半导体器件在第一掺杂类型的所述掺杂层101中设置有沟槽102。Continuing to refer to FIG. 1 , the semiconductor device according to the present invention is provided with trenches 102 in the doping layer 101 of the first doping type.
在掺杂层101中的有源区A中设置沟槽102，沟槽102底部的掺杂层形成第二掺杂类型的掺杂区，沟槽102中填充金属电极，在加载正向电流时，电流可以通过沟槽侧壁流入有源区，增加了电流路径，提高了电流密度；同时，由于沟槽结构的三维设计，可以提高有源区对掺杂区的比例，进一步提高电流密度。加载反向电流时，可以设计使掺杂区对有源区充分耗尽，从而减小漏电流，提高器件的耐压性能。A trench 102 is provided in the active region A in the doped layer 101, the doped layer at the bottom of the trench 102 forms a doped region of the second doping type, and the trench 102 is filled with a metal electrode, when a forward current is loaded , the current can flow into the active region through the sidewall of the trench, increasing the current path and improving the current density; at the same time, due to the three-dimensional design of the trench structure, the ratio of the active region to the doped region can be increased, further improving the current density. When the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
需要理解的是，本发明的实施例的附图中将沟槽102示出为形成在有源区A中仅仅是示例性的，本领域技术人员应当理解，沟槽102可以仅形成在有源区A中，可以在有源区A和终端区B中均形成沟槽，在此并不限定。同时，本发明的实施例的附图中将沟槽102形成在有源区A的边缘仅仅是示例性的，本领域技术人员应当理解，沟槽102可以在有源区的任意位置，在此并不限定。It should be understood that, the trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein. Meanwhile, in the drawings of the embodiments of the present invention, the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
示例性的，在掺杂层101中形成沟槽102的方法包括：Exemplarily, the method of forming the trench 102 in the doped layer 101 includes:
在掺杂层101表面形成图案化的光刻胶层，所述图案化的光刻胶层露出拟形成沟槽102的区域；A patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
以所述图案化的光刻胶层为掩膜执行刻蚀工艺，以在掺杂层101中形成沟槽102。An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
在根据本发明的一个示例中，在所述掺杂层中形成至少两个沟槽。当在掺杂层中设置 至少两个沟槽时，在相邻两个所述沟槽之间的所述掺杂层形成突出部。在后续形成第二掺杂类型的掺杂区和金属电极之后，金属电极与突出部的侧壁(也是沟槽102的侧壁)肖特基接触，当加正向偏压时，电流通过金属电极通过与金属电极肖特基接触的侧壁流入突出部，进一步增加沟槽之间的有源区(突出部)的电流密度，当加反向电压时，位于相邻沟槽底部的掺杂区对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。In an example according to the present invention, at least two trenches are formed in the doped layer. When at least two trenches are provided in the doped layer, protrusions are formed in the doped layer between adjacent two of the trenches. After the doped region of the second doping type and the metal electrode are subsequently formed, the metal electrode is in Schottky contact with the sidewall of the protrusion (which is also the sidewall of the trench 102 ), and when a forward bias is applied, current flows through the metal The electrode flows into the protrusion through the sidewall in contact with the metal electrode Schottky, which further increases the current density of the active area (protrusion) between the trenches. When a reverse voltage is applied, the doping located at the bottom of the adjacent trench The active region between them is fully depleted, which further reduces the leakage current and improves the withstand voltage performance during the period.
示例性地，所述沟槽的侧壁垂直。Exemplarily, the sidewalls of the trenches are vertical.
进一步，示例性的，在所述有源区中，形成所述沟槽的区域的面积小于未形成所述沟槽的区域的面积。Further, exemplarily, in the active region, the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
需要理解的是，上述形成沟槽的侧壁和沟槽的区域的面积的设置仅仅是示例性的，本领域技术人员应当理解，根据具体的电流-电压设计，可以设计不同的形成沟槽的区域的面积，以形成不同面积的肖特基接触。It should be understood that the above setting of the area of the sidewall of the trench and the area of the region of the trench is only exemplary, and those skilled in the art should understand that, according to the specific current-voltage design, different trench formation can be designed. area to form Schottky contacts of different areas.
在本发明的一个实施例中，有源区A覆盖掺杂层101的表面的矩形区域。在掺杂层101中的两个沟槽102相对有源区的边缘平行设置。In one embodiment of the present invention, the active region A covers a rectangular area of the surface of the doped layer 101 . The two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
下面参看图2-图6，对根据本发明的实施例的一种半导体器件中在第一掺杂类型的掺杂层101中设置沟槽的示例进行示例性说明。其中，图2-图6示出为在第一掺杂类型的掺杂层中形成沟槽和后续在沟槽底部形成了第二掺杂类型的掺杂区的三维结构示意图。2 to 6 , an example of arranging a trench in the doping layer 101 of the first doping type in a semiconductor device according to an embodiment of the present invention will be exemplarily described. 2-6 are schematic diagrams of three-dimensional structures of forming a trench in a doped layer of a first doping type and subsequently forming a doped region of a second doping type at the bottom of the trench.
在本发明的一个实施例中，所述沟槽包括沿着第一方向并列设置的至少两个条状沟槽，其中所述条状沟槽在与所述第一方向交叉的第二方向上从有源区的第一端延伸到与所述第一端相对应的第二端。In one embodiment of the present invention, the grooves include at least two strip-shaped grooves arranged side by side along a first direction, wherein the strip-shaped grooves are in a second direction crossing the first direction Extends from a first end of the active region to a second end corresponding to the first end.
参看图2，在第一掺杂类型的掺杂层101的有源区A中形成三个条状沟槽102，三个条状沟槽102并列设置并且从有源区A的一端延伸向另一端，同时三个条状沟槽102位于最外侧的两端覆盖有源区A的边缘。2, three strip-shaped trenches 102 are formed in the active region A of the doping layer 101 of the first doping type, and the three strip-shaped trenches 102 are arranged side by side and extend from one end of the active region A to the other. At the same time, the two outermost ends of the three strip-shaped trenches 102 cover the edge of the active region A.
在本发明的另一个实施例中，所述沟槽包括沿着第一方向并列设置的两个条状沟槽以及在所述两个条状沟槽之间的凹型沟槽。In another embodiment of the present invention, the groove includes two strip-shaped grooves arranged side by side along the first direction and a concave groove between the two strip-shaped grooves.
参看图3，在第一掺杂类型的掺杂层101的有源区A的相对的边缘形成有两个条状沟槽102，两个条状沟槽102并列设置并且在两条状沟槽中间形成有凹型沟槽102A。Referring to FIG. 3 , two strip-shaped trenches 102 are formed at opposite edges of the active region A of the doping layer 101 of the first doping type, and the two strip-shaped trenches 102 are arranged side by side and in the A concave groove 102A is formed in the middle.
在本发明的另一个实施例中，所述掺杂层中设置有至少两列沟槽，其中，所述至少两列沟槽中的每一列至少包括两个所述沟槽。示例性的，所述掺杂层中沿着第一方向并列设置有至少两列沟槽，并且所述至少两列沟槽中的每一列中包含的沟槽沿着第二方向排列设置。In another embodiment of the present invention, at least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches. Exemplarily, at least two rows of trenches are arranged in parallel along the first direction in the doped layer, and the trenches included in each of the at least two rows of trenches are arranged along the second direction.
在一个示例中，第一方向和第二方向为分别平行于有源区A边缘的方向。In one example, the first direction and the second direction are directions parallel to the edge of the active region A, respectively.
参看图4，在第一掺杂类型的掺杂层101的有源区A的长度方向上设置有两列沟槽102，其中每一列在宽度方向上具有三个沟槽102排列设置。Referring to FIG. 4 , two columns of trenches 102 are arranged in the length direction of the active region A of the doped layer 101 of the first doping type, and each column has three trenches 102 arranged in the width direction.
在一个示例中，第一方向和第二方向均不平行于有源区A的边缘。In one example, neither the first direction nor the second direction is parallel to the edge of the active region A.
参看图5，在第一掺杂类型的掺杂层101的在第一掺杂类型的掺杂层101的有源区A中设置有两列沟槽102，其中每一列与边缘呈45°倾斜角，每一列具有两个沟槽102。Referring to FIG. 5 , two columns of trenches 102 are provided in the active region A of the doped layer 101 of the first doped type, wherein each column is inclined at 45° to the edge corner, each column has two trenches 102.
在本发明的另一个实施例中，所述沟槽包括环形沟槽以及在所述环形沟槽所环绕的所述掺杂层中设置的凹型沟槽。In another embodiment of the present invention, the trench includes an annular trench and a concave trench provided in the doped layer surrounded by the annular trench.
参看图6，示出了在第一掺杂类型的掺杂层101的有源区A中形成环形沟槽102，并且在环形沟槽102中设置有矩形凹型沟槽102A。Referring to FIG. 6 , it is shown that an annular trench 102 is formed in the active region A of the doping layer 101 of the first doping type, and a rectangular concave trench 102A is provided in the annular trench 102 .
需要理解的是，上述凹型沟槽设置的各种形式(图2-图6)仅仅是示例性的，本领域技术人员可以根据实际需要，在有源区的任何位置，以及设置任何形式的沟槽均能实现本发明的技术效果。It should be understood that the various forms of the above-mentioned concave trench arrangement (FIG. 2-FIG. 6) are only exemplary, and those skilled in the art can arrange trenches of any form at any position of the active region according to actual needs The grooves can achieve the technical effect of the present invention.
继续参看图1，根据本发明的半导体器件还包括位于所述掺杂层101中的第二掺杂类型的掺杂区103，所述掺杂区103包括位于所述沟槽底部的第一掺杂区1031。Continuing to refer to FIG. 1 , the semiconductor device according to the present invention further includes a doped region 103 of a second doping type located in the doped layer 101 , and the doped region 103 includes a first doped region located at the bottom of the trench. Miscellaneous area 1031.
在图2-图6中，也示出了在沟槽底部形成第二掺杂类型的掺杂区的三维结构示意图。其中，在每一沟槽102的底部的第一掺杂类型的掺杂层101中均形成有第二掺杂类型的掺杂区103。In FIGS. 2 to 6 , schematic diagrams of the three-dimensional structure of the doped regions of the second doping type formed at the bottom of the trenches are also shown. Wherein, a doped region 103 of a second doped type is formed in the doped layer 101 of the first doped type at the bottom of each trench 102 .
在本实施例中，第一掺杂类型为N型，第二掺杂类型为P型，因此，在此步骤形成P型的掺杂区。In this embodiment, the first doping type is N-type, and the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
示例性的，形成第一掺杂区1031的方法包括：Exemplarily, the method for forming the first doped region 1031 includes:
在所述碳化硅衬底100上形成图案化的掩膜层，所述图案化的掩膜层露出沟槽102的区域，A patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
以图案化的掩膜层为掩膜执行离子注入工艺，以形成位于沟槽102底部的第一掺杂区1031。An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
在根据本发明的一个实施例中，上述图案化的掩膜层也可以是在形成沟槽102的刻蚀工艺中形成的掩膜层。In an embodiment according to the present invention, the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
将形成沟槽102和形成第二掺杂类型的掺杂区103的掩膜设置为同一掩膜层，有效减少工艺步骤，节省生产成本。The masks for forming the trenches 102 and the doping regions 103 of the second doping type are set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
示例性的，在根据本发明的一个实施例中，如图1所示，所述掺杂区103还包括位于所述掺杂层101表面以下的第二掺杂区1032，所述第二掺杂区1032的深度小于所述沟槽102的深度，使得沟槽102的至少部分侧壁的外侧的掺杂层101与金属电极接触而形成肖 特基接触。Exemplarily, in an embodiment according to the present invention, as shown in FIG. 1 , the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 . The depth of the impurity region 1032 is smaller than the depth of the trench 102 , so that the doped layer 101 on the outer side of at least part of the sidewall of the trench 102 is in contact with the metal electrode to form a Schottky contact.
在突出部1011表面下方设置第二掺杂区1032，使后续在形成金属电极之后，金属电极除了与沟槽102的底部的第一掺杂区1031形成欧姆接触以外，还与突出部1011表面的第二掺杂区1032形成欧姆接触，当加反向电压时，位于相邻沟槽底部的掺杂区(第一掺杂区1031)以及相邻沟槽之间的突出部表面以下的掺杂区(第二掺杂区1032)对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。A second doped region 1032 is provided under the surface of the protrusion 1011, so that after the metal electrode is formed subsequently, the metal electrode not only forms ohmic contact with the first doped region 1031 at the bottom of the trench 102, but also contacts with the surface of the protrusion 1011. The second doped region 1032 forms an ohmic contact. When a reverse voltage is applied, the doped region (the first doped region 1031 ) located at the bottom of the adjacent trenches and the doping under the surface of the protrusion between the adjacent trenches The active region between them (the second doped region 1032 ) is fully depleted, which further reduces the leakage current and improves the withstand voltage performance during the period.
在根据本发明的一个实施例中，在形成第一掺杂区1031的过程中形成第二掺杂区1032。具体的，不执行在所述碳化硅衬底100上形成图案化的掩膜层的步骤，或者在所述碳化硅衬底100上形成图案化的掩膜层还至少露出沟槽102之间的掺杂层的表面，从而在未形成沟槽102的掺杂层中也形成第二掺杂类型的掺杂区103。In one embodiment according to the present invention, the second doped region 1032 is formed during the formation of the first doped region 1031 . Specifically, the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer formed on the silicon carbide substrate 100 also exposes at least the area between the trenches 102 . The surface of the doped layer, so that the doped region 103 of the second doping type is also formed in the doped layer where the trench 102 is not formed.
继续参看图1，根据本发明的半导体器件还包括金属电极107，其中，所述金属电极107包括嵌入所述掺杂层101中的所述沟槽102的第一部分，所述第一部分与所述第一掺杂区1031欧姆接触，所述第一部分与所述沟槽102的侧壁上未形成所述掺杂区103的所述掺杂层101肖特基接触。金属电极107与位于沟槽底部下方的第二掺杂类型的第一掺杂区1031形成欧姆接触，而与沟槽侧壁的第一掺杂类型的掺杂层101形成肖特基接触。在加载正向电流时，电流从金属电极107通过沟槽侧壁流入第一掺杂类型的掺杂层101中的有源区A，提高电流密度，加载反向电流时，第一掺杂区1031充分对形成在沟槽之间的有源区充分耗尽，减小漏电流，提高了器件的耐压性能。Continuing to refer to FIG. 1 , the semiconductor device according to the present invention further includes a metal electrode 107 , wherein the metal electrode 107 includes a first portion of the trench 102 embedded in the doped layer 101 , the first portion is connected to the The first doped region 1031 is in ohmic contact, and the first portion is in Schottky contact with the doped layer 101 on which the doped region 103 is not formed on the sidewall of the trench 102 . The metal electrode 107 forms an ohmic contact with the first doped region 1031 of the second doping type under the trench bottom, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench. When a forward current is loaded, the current flows from the metal electrode 107 through the trench sidewall into the active region A in the doping layer 101 of the first doping type, increasing the current density. When a reverse current is loaded, the first doping region The 1031 fully depletes the active region formed between the trenches, reduces the leakage current, and improves the withstand voltage performance of the device.
在根据本发明的一个示例中，如图1所示，所述掺杂区103还包括位于所述掺杂层101表面以下的第二掺杂区1032，金属电极107还与第二掺杂区1032欧姆接触。当加正向偏压时，电流通过金属电极107并通过与金属电极107肖特基接触的沟槽102的侧壁流入沟槽102之间的掺杂层101，增加有源区的电流密度，当加反向电压时，位于沟槽102底部的第一掺杂区1031和位于掺杂层101顶部表面以下的第二掺杂区1032对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。In an example according to the present invention, as shown in FIG. 1 , the doped region 103 further includes a second doped region 1032 located below the surface of the doped layer 101 , and the metal electrode 107 is also connected to the second doped region. 1032 ohm contact. When a forward bias is applied, the current flows through the metal electrode 107 and flows into the doped layer 101 between the trenches 102 through the sidewall of the trench 102 in Schottky contact with the metal electrode 107, increasing the current density in the active region, When a reverse voltage is applied, the first doped region 1031 located at the bottom of the trench 102 and the second doped region 1032 located below the top surface of the doped layer 101 are fully depleted of the active region between them, further reducing the leakage current, improving the withstand voltage performance during the period.
在根据本发明的一个示例中，如图1所示，半导体器件还包括在所述碳化硅衬底100的背面的背面电极108。In an example according to the present invention, as shown in FIG. 1 , the semiconductor device further includes a backside electrode 108 on the backside of the silicon carbide substrate 100 .
实施例二Embodiment 2
下面参看图7A-图7H和图8对根据本发明的一种半导体器件的制造方法进行示例性说明。其中，图7A-图7H为根据本发明的一个实施例的一种半导体器件的制造方法中形成的半导体器件的结构示意图；图2为根据本发明的一个实施例的一种半导体器件的制造 方法的示例性流程图。7A-7H and FIG. 8, a method for manufacturing a semiconductor device according to the present invention will be exemplarily described below. 7A-7H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 2 is a method for manufacturing a semiconductor device according to an embodiment of the present invention. An exemplary flowchart of .
首先，参看图7A，提供碳化硅衬底100，所述碳化硅衬底100上形成有第一掺杂类型的掺杂层101。First, referring to FIG. 7A , a silicon carbide substrate 100 is provided on which a doping layer 101 of a first doping type is formed.
示例性的，碳化硅衬底100的制备材料可为4H-SiC，掺杂类型为第一掺杂类型，掺杂浓度为1×10 18cm -3，厚度为350μm。 Exemplarily, the preparation material of the silicon carbide substrate 100 may be 4H-SiC, the doping type is the first doping type, the doping concentration is 1×10 18 cm −3 , and the thickness is 350 μm.
在根据本发明的一个示例中，所述碳化硅衬底还包括形成在所述碳化硅衬底上的碳化硅外延层，所述碳化硅外延层为第一掺杂类型。示例性的，所述碳化硅外延层的厚度为6μm，掺杂类型为第一掺杂类型，掺杂浓度为1×10 16cm -3。 In an example according to the present invention, the silicon carbide substrate further includes a silicon carbide epitaxial layer formed on the silicon carbide substrate, and the silicon carbide epitaxial layer is of the first doping type. Exemplarily, the thickness of the silicon carbide epitaxial layer is 6 μm, the doping type is the first doping type, and the doping concentration is 1×10 16 cm −3 .
在根据本发明的一个示例中，形成碳化硅功率器件，其中，碳化硅衬底上形成有源区和终端区。如图7A所示，碳化硅衬底100包括有源区A和终端区B。In one example according to the present invention, a silicon carbide power device is formed in which active and termination regions are formed on a silicon carbide substrate. As shown in FIG. 7A , the silicon carbide substrate 100 includes an active region A and a termination region B.
需要理解的是，本发明的实施例中，在附图中示出形成在终端区B之间的有源区A仅为一个区域仅仅是示例性的，本领域技术人员应当理解，在实际半导体器件制造中，终端区B之间可以多包括任意个重复设置的有源区A。It should be understood that, in the embodiments of the present invention, the active region A formed between the terminal regions B shown in the drawings is only an example, and those skilled in the art should understand that in an actual semiconductor During device manufacture, any number of active regions A repeatedly arranged between the termination regions B may be included.
继续参看图7A，在碳化硅衬底100上形成有第一掺杂类型的掺杂层101，所述第一掺杂类型掺杂层包括覆盖所述有源区A和终端区B，示例性的，掺杂浓度为1×10 17cm -3。 Continuing to refer to FIG. 7A , a doping layer 101 of a first doping type is formed on the silicon carbide substrate 100 , and the doping layer of the first doping type includes covering the active region A and the terminal region B, for example , with a doping concentration of 1×10 17 cm -3 .
示例性的，形成所述掺杂层的方法包括执行离子注入工艺，以在所述碳化硅衬底上形成所述第一掺杂类型的掺杂层101。Exemplarily, the method of forming the doping layer includes performing an ion implantation process to form the doping layer 101 of the first doping type on the silicon carbide substrate.
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。It should be noted that in this specification, the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping type The doping type is P-type, one of low-doped P-type, and high-doped P+ type, and the second doping type is N-type, low-doped N-type, and one of high-doped N+ type. Or conversely, the first doping type is one of N-type, low-doped N-type, and high-doped N+ type, and the second doping type is P-type, low-doped P-type, and high-doped P+ type one of them.
在本实施例中，所述第一类型为N型，第二掺杂类型为P型。In this embodiment, the first type is N-type, and the second doping type is P-type.
接着，如图7B所示，在所述掺杂层101中形成沟槽102。Next, as shown in FIG. 7B , trenches 102 are formed in the doped layer 101 .
在掺杂层101中的有源区A中形成沟槽102，沟槽102用于在后续形成第二掺杂类型的掺杂区后，形成通过在有源区内的沟槽侧壁进行肖特基接触的电极，使得加载正向电流时，电流可以通过沟槽侧壁流入有源区，增加了电流路径，提高了电流密度；同时，由于沟槽结构的三维设计，可以提高有源区对掺杂区的比例，进一步提高电流密度。加载反向电流时，可以设计使掺杂区对有源区充分耗尽，从而减小漏电流，提高器件的耐压性能。A trench 102 is formed in the active region A in the doped layer 101, and the trench 102 is used to form a trench 102 through the trench sidewall in the active region after the subsequent formation of the doped region of the second doping type. The electrode contacted by the special base allows the current to flow into the active area through the sidewall of the trench when the forward current is loaded, which increases the current path and improves the current density; at the same time, due to the three-dimensional design of the trench structure, the active area can be improved. The proportion of doped regions further increases the current density. When the reverse current is loaded, the active region can be fully depleted by the doped region, thereby reducing the leakage current and improving the withstand voltage performance of the device.
需要理解的是，本发明的实施例的附图中将沟槽102示出为形成在有源区A中仅仅是示例性的，本领域技术人员应当理解，沟槽102可以仅形成在有源区A中，可以在有源区 A和终端区B中均形成沟槽，在此并不限定。It should be understood that the trenches 102 are shown as being formed in the active region A in the drawings of the embodiments of the present invention, and those skilled in the art should understand that the trenches 102 may only be formed in the active region A. In the region A, trenches may be formed in both the active region A and the termination region B, which are not limited herein.
同时，本发明的实施例的附图中将沟槽102形成在有源区A的边缘仅仅是示例性的，本领域技术人员应当理解，沟槽102可以在有源区的任意位置，在此并不限定。Meanwhile, in the drawings of the embodiments of the present invention, the trench 102 is formed at the edge of the active region A is only exemplary, and those skilled in the art should understand that the trench 102 may be at any position in the active region, and here Not limited.
示例性的，在掺杂层101中形成沟槽102的方法包括：Exemplarily, the method of forming the trench 102 in the doped layer 101 includes:
在掺杂层101表面形成图案化的光刻胶层，所述图案化的光刻胶层露出拟形成沟槽102的区域；A patterned photoresist layer is formed on the surface of the doped layer 101, and the patterned photoresist layer exposes the area where the trench 102 is to be formed;
以所述图案化的光刻胶层为掩膜执行刻蚀工艺，以在掺杂层101中形成沟槽102。An etching process is performed using the patterned photoresist layer as a mask to form trenches 102 in the doped layer 101 .
在根据本发明的一个示例中，在所述掺杂层中形成至少两个沟槽，在相邻两个所述沟槽之间的所述掺杂层形成突出部。如图7B所示，在掺杂层101中形成三个沟槽102，相邻的沟槽102之间的掺杂层形成突出部1011，在后续形成第二掺杂类型的掺杂区和金属电极之后，金属电极与突出部1011的侧壁(也是沟槽102的侧壁)肖特基接触，当加正向偏压时，电流通过金属电极通过与金属电极肖特基接触的侧壁流入突出部，进一步增加沟槽之间的有源区(突出部)的电流密度，当加反向电压时，位于相邻沟槽底部的掺杂区对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。In an example according to the present invention, at least two trenches are formed in the doped layer, and protrusions are formed on the doped layer between two adjacent trenches. As shown in FIG. 7B , three trenches 102 are formed in the doped layer 101 , the doped layers between adjacent trenches 102 form protrusions 1011 , and doped regions of the second doping type and metal are subsequently formed After the electrode, the metal electrode is in Schottky contact with the sidewall of the protrusion 1011 (also the sidewall of the trench 102), and when a forward bias is applied, current flows through the metal electrode through the sidewall in contact with the metal electrode Schottky The protrusions further increase the current density of the active regions (protrusions) between the trenches. When a reverse voltage is applied, the doped regions at the bottom of the adjacent trenches are fully depleted of the active regions between them. The leakage current is further reduced, and the withstand voltage performance during the period is improved.
示例性地，所述沟槽的侧壁垂直。Exemplarily, the sidewalls of the trenches are vertical.
进一步，示例性的，在所述有源区中，形成所述沟槽的区域的面积小于未形成所述沟槽的区域的面积。Further, exemplarily, in the active region, the area of the area where the trench is formed is smaller than the area of the area where the trench is not formed.
需要理解的是，上述形成沟槽的侧壁和沟槽的区域的面积的设置仅仅是示例性的，本领域技术人员应当理解，根据具体的电流-电压设计，可以设计不同的形成沟槽的区域的面积，以形成不同面积的肖特基接触。同时应当理解的是，本发明的沟槽可以具有不同的形状，其与实施例一中参考图2-图6示出的沟槽的示例一样，也不限于图2-图6示出的沟槽的示例，在此不再赘述。It should be understood that the above setting of the area of the sidewall of the trench and the area of the region of the trench is only exemplary, and those skilled in the art should understand that, according to the specific current-voltage design, different trench formation can be designed. area to form Schottky contacts of different areas. At the same time, it should be understood that the grooves of the present invention may have different shapes, which are the same as the grooves shown in the first embodiment with reference to FIGS. 2-6 , and are not limited to the grooves shown in FIGS. 2-6 . The example of the slot will not be repeated here.
在本发明的一个实施例中，有源区A覆盖掺杂层101的表面的矩形区域。在掺杂层101中的两个沟槽102相对有源区的边缘平行设置。In one embodiment of the present invention, the active region A covers a rectangular area of the surface of the doped layer 101 . The two trenches 102 in the doped layer 101 are arranged parallel to the edges of the active region.
继续参看图7C，在所述掺杂层101中形成第二掺杂类型的掺杂区103，其中，掺杂区103包括位于沟槽底部的第一掺杂区1031。第一掺杂区1031以上的掺杂层未形成掺杂区；即，所述沟槽102的侧壁和突出部1011的表面未形成掺杂区。Continuing to refer to FIG. 7C , a doped region 103 of a second doping type is formed in the doped layer 101 , wherein the doped region 103 includes a first doped region 1031 located at the bottom of the trench. The doped layer above the first doped region 1031 does not form a doped region; that is, no doped region is formed on the sidewall of the trench 102 and the surface of the protrusion 1011 .
在本实施例中，第一掺杂类型为N型，第二掺杂类型为P型，因此，在此步骤形成P型的掺杂区。In this embodiment, the first doping type is N-type, and the second doping type is P-type. Therefore, a P-type doped region is formed in this step.
示例性的，形成第一掺杂区1031的方法包括：Exemplarily, the method for forming the first doped region 1031 includes:
在所述碳化硅衬底100上形成图案化的掩膜层，所述图案化的掩膜层露出沟槽102的 区域，A patterned mask layer is formed on the silicon carbide substrate 100, and the patterned mask layer exposes the region of the trench 102,
以图案化的掩膜层为掩膜执行离子注入工艺，以形成位于沟槽102底部的第一掺杂区1031。An ion implantation process is performed using the patterned mask layer as a mask to form a first doped region 1031 at the bottom of the trench 102 .
在根据本发明的一个实施例中，上述图案化的掩膜层也可以是在形成沟槽102的刻蚀工艺中形成的掩膜层。In an embodiment according to the present invention, the above-mentioned patterned mask layer may also be a mask layer formed in the etching process for forming the trench 102 .
将形成沟槽102和形成第二掺杂类型的掺杂区的掩膜设置为同一掩膜层，有效减少工艺步骤，节省生产成本。The mask for forming the trench 102 and the doping region for forming the second doping type is set to be the same mask layer, which effectively reduces the process steps and saves the production cost.
示例性的，在根据本发明的一个实施例中，不执行在所述碳化硅衬底100上形成图案化的掩膜层的步骤，或者在所述碳化硅衬底100上形成图案化的掩膜层还至少露出沟槽102之间的掺杂层的表面，从而在未形成沟槽102的掺杂层中也形成第二掺杂类型的掺杂区103。Exemplarily, in an embodiment according to the present invention, the step of forming a patterned mask layer on the silicon carbide substrate 100 is not performed, or the patterned mask layer is formed on the silicon carbide substrate 100 . The film layer also exposes at least the surface of the doped layer between the trenches 102, so that the doped region 103 of the second doping type is also formed in the doped layer where the trench 102 is not formed.
如图7D所示，在形成第二掺杂类型的掺杂区103时，形成位于沟槽102底部的第一掺杂区1031和位于突出部1011表面以下的第二掺杂区1032，其中第二掺杂区1032具有第二深度，第二深度小于凹型沟槽102的深度，以使凹型沟槽102至少部分侧壁未被掺杂形成第二掺杂类型的掺杂区。As shown in FIG. 7D , when forming the doped region 103 of the second doping type, a first doped region 1031 located at the bottom of the trench 102 and a second doped region 1032 located below the surface of the protrusion 1011 are formed, wherein the first doped region 1031 is formed at the bottom of the trench 102 The second doped region 1032 has a second depth, which is smaller than the depth of the recessed trench 102 , so that at least part of the sidewall of the recessed trench 102 is not doped to form a second doping type doped region.
在突出部1011表面形成第二掺杂区1032，使后续在形成金属电极之后，金属电极除了与沟槽102的底部的第一掺杂区1031形成欧姆接触以外，还与突出部1011表面的第二掺杂区1032形成欧姆接触，当加反向电压时，位于相邻沟槽底部的掺杂区(第一掺杂区1031)以及相邻沟槽之间的突出部表面以下的掺杂区(第二掺杂区1032)对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。A second doped region 1032 is formed on the surface of the protruding portion 1011 , so that after the metal electrode is subsequently formed, in addition to forming ohmic contact with the first doped region 1031 at the bottom of the trench 102 , the metal electrode also forms an ohmic contact with the first doped region 1031 on the surface of the protruding portion 1011 . The two doped regions 1032 form ohmic contacts. When reverse voltage is applied, the doped regions (first doped regions 1031 ) at the bottom of adjacent trenches and the doped regions below the surface of the protrusion between adjacent trenches (The second doped region 1032) fully depletes the active region between them, which further reduces the leakage current and improves the withstand voltage performance during the period.
继续参看图7E，接着，在碳化硅衬底100表面形成介质层104。Continuing to refer to FIG. 7E , next, a dielectric layer 104 is formed on the surface of the silicon carbide substrate 100 .
在碳化硅衬底100表面形成介质层104，后续在介质层中形成用以形成金属电极的孔，其中，在拟形成金属电极以外的区域，被介质层覆盖，最终形成所需的电路连接。A dielectric layer 104 is formed on the surface of the silicon carbide substrate 100, and holes for forming metal electrodes are subsequently formed in the dielectric layer, wherein the areas other than the metal electrodes to be formed are covered by the dielectric layer, and finally required circuit connections are formed.
示例性的，形成介质层104的方法包括：Exemplarily, the method of forming the dielectric layer 104 includes:
执行沉积工艺，以形成覆盖所述掺杂层101表面并填充沟槽102的介质材料层；performing a deposition process to form a dielectric material layer covering the surface of the doped layer 101 and filling the trench 102;
执行化学机械研磨工艺，以对所述介质材料层进行平坦化，形成介质层104。A chemical mechanical polishing process is performed to planarize the dielectric material layer to form the dielectric layer 104 .
接着参看图7F，在所述介质层104中形成孔106，所述孔106露出所述沟槽102。Next, referring to FIG. 7F , holes 106 are formed in the dielectric layer 104 , and the holes 106 expose the trenches 102 .
由于拟形成金属电极的孔106露出沟槽102，最终形成的金属电极填充沟槽102，从而使形成的金属电极与位于沟槽102底部下方的第一掺杂区1031形成欧姆接触，与沟槽102侧壁上的掺杂层101形成肖特基接触。Since the hole 106 where the metal electrode is to be formed exposes the trench 102, the finally formed metal electrode fills the trench 102, so that the formed metal electrode forms an ohmic contact with the first doped region 1031 located under the bottom of the trench 102, and is in ohmic contact with the trench 102. The doped layers 101 on the sidewalls of 102 form Schottky contacts.
形成多个沟槽102，相邻的沟槽102之间第一掺杂类型的掺杂层101形成突出部1011 并在突出部1011表面以下的掺杂层101中形成的实施例中，金属电极还与突出部1011表面的第二掺杂区1032形成欧姆接触。In an embodiment in which a plurality of trenches 102 are formed, the doping layer 101 of the first doping type between adjacent trenches 102 forms a protrusion 1011 and is formed in the doping layer 101 below the surface of the protrusion 1011, the metal electrode An ohmic contact is also formed with the second doped region 1032 on the surface of the protrusion 1011 .
示例性的，形成所述孔106的方法包括：Exemplarily, the method of forming the hole 106 includes:
在所述介质层104上形成图案化的掩膜层105，所述图案化的掩膜层105露出拟形成孔的区域；A patterned mask layer 105 is formed on the dielectric layer 104, and the patterned mask layer 105 exposes the area where the holes are to be formed;
以所述图案化的掩膜层105为掩膜执行刻蚀工艺，以形成孔106。An etching process is performed using the patterned mask layer 105 as a mask to form holes 106 .
接着继续参看图7G，在所述孔106中形成金属层，以形成金属电极107。金属电极包括填充沟槽102的部分和位于掺杂层101以上的部分。Continuing to refer to FIG. 7G , a metal layer is formed in the hole 106 to form the metal electrode 107 . The metal electrode includes a portion filling the trench 102 and a portion above the doped layer 101 .
示例性的，形成金属电极107的方法包括：Exemplarily, the method of forming the metal electrode 107 includes:
在执行金属蒸发或者溅射工艺，以在碳化硅衬底100的表面形成覆盖介质层104和填充孔106的金属材料层；performing a metal evaporation or sputtering process to form a metal material layer covering the dielectric layer 104 and filling the holes 106 on the surface of the silicon carbide substrate 100;
执行化学机械研磨工艺，以去除介质层104以上的金属材料层，从而形成金属电极。A chemical mechanical polishing process is performed to remove the metal material layer above the dielectric layer 104 to form a metal electrode.
由于在第一掺杂类型的掺杂层101中形成有沟槽，在形成金属电极107后，金属电极107填充沟槽，从而金属电极107与位于沟槽底部下方的第二掺杂类型的第一掺杂区1031形成欧姆接触，而与沟槽侧壁的第一掺杂类型的掺杂层101形成肖特基接触。在加载正向电流时，电流从金属电极107通过沟槽侧壁流入第一掺杂类型的掺杂层101中的有源区A，提高电流密度，加载反向电流时，第一掺杂区1031充分对形成在沟槽之间的有源区充分耗尽，减小漏电流，提高了器件的耐压性能。Since a trench is formed in the doping layer 101 of the first doping type, after the metal electrode 107 is formed, the metal electrode 107 fills the trench, so that the metal electrode 107 is connected to the first doping type of the second doping type located under the bottom of the trench. A doped region 1031 forms an ohmic contact, and forms a Schottky contact with the doped layer 101 of the first doping type on the sidewall of the trench. When a forward current is loaded, the current flows from the metal electrode 107 through the trench sidewall into the active region A in the doping layer 101 of the first doping type, increasing the current density. When a reverse current is loaded, the first doping region The 1031 fully depletes the active region formed between the trenches, reduces the leakage current, and improves the withstand voltage performance of the device.
在根据本发明的一个示例中，如图7H所示，在所述掺杂层101中形成至少两个沟槽102，在相邻两个所述沟槽102之间的所述掺杂层形成突出部1011，并且沟槽102底部以下和在突出部1011表面以下的第一掺杂类型的掺杂层101中分别形成第二掺杂类型的第一掺杂区1031和第二掺杂区1032，在形成金属电极107之后，金属电极107与突出部1011的部分侧壁(也是沟槽102的部分侧壁)肖特基接触，当加正向偏压时，电流通过金属电极通过与金属电极肖特基接触的侧壁流入突出部，进一步增加有源区的电流密度，当加反向电压时，位于相邻沟槽底部的掺杂区对其之间的有源区充分耗尽，进一步减小漏电流，提高期间的耐压性能。In an example according to the present invention, as shown in FIG. 7H , at least two trenches 102 are formed in the doped layer 101 , and the doped layer is formed between two adjacent trenches 102 The protrusion 1011, and the first doping region 1031 and the second doping region 1032 of the second doping type are formed in the doped layer 101 of the first doping type below the bottom of the trench 102 and below the surface of the protrusion 1011, respectively , after the metal electrode 107 is formed, the metal electrode 107 is in Schottky contact with part of the sidewall of the protrusion 1011 (also part of the sidewall of the trench 102 ), and when a forward bias is applied, the current passes through the metal electrode and the metal electrode The sidewall of the Schottky contact flows into the protrusion, which further increases the current density of the active region. When a reverse voltage is applied, the doped region at the bottom of the adjacent trench is fully depleted of the active region between them, further increasing the current density of the active region. The leakage current is reduced and the withstand voltage performance during the period is improved.
在根据本发明的一个示例中，在形成金属电极之后，还包括在所述碳化硅衬底的背面形成背面电极。继续参看图7G和图7H，在形成金属电极107之后，还包括在碳化硅衬底100的背面形成背面电极108的步骤。In an example according to the present invention, after forming the metal electrode, the method further includes forming a back electrode on the back surface of the silicon carbide substrate. Continuing to refer to FIGS. 7G and 7H , after forming the metal electrode 107 , a step of forming a backside electrode 108 on the backside of the silicon carbide substrate 100 is further included.
参看图8，示出了根据本发明的一个实施例的半导体器件制造方法的流程图。其中，根据本发明的一个实施例的半导体器件制造方法包括：Referring to FIG. 8, a flowchart of a method of fabricating a semiconductor device according to one embodiment of the present invention is shown. Wherein, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
步骤S1：提供碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层；Step S1: providing a silicon carbide substrate, the silicon carbide substrate including a doping layer of the first doping type;
步骤S2：在所述掺杂层中形成沟槽；Step S2: forming a trench in the doped layer;
步骤S3：在所述掺杂层中形成第二掺杂类型的掺杂区，其中所述掺杂区包括位于所述沟槽底部的第一掺杂区，并且所述第一掺杂区以上的至少部分所述沟槽的侧壁外侧的所述掺杂层中未形成所述掺杂区；Step S3: forming a doped region of a second doping type in the doped layer, wherein the doped region includes a first doped region located at the bottom of the trench and above the first doped region The doped region is not formed in the doped layer outside at least part of the sidewall of the trench;
步骤S4：形成金属电极，所述金属电极至少填充所述沟槽，其中，所述金属电极与所述掺杂区形成欧姆接触，所述金属电极与所述掺杂层在所述沟槽的侧壁的至少部分上形成肖特基接触。Step S4 : forming a metal electrode, the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are in the trench. A Schottky contact is formed on at least a portion of the sidewall.
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (15)

  1. 一种半导体器件，其特征在于，包括：A semiconductor device, comprising:
    碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层，所述掺杂层中设置有沟槽；a silicon carbide substrate, the silicon carbide substrate includes a doping layer of a first doping type, and a groove is provided in the doping layer;
    位于所述掺杂层中的第二掺杂类型的掺杂区，所述掺杂区包括位于所述沟槽底部的第一掺杂区；以及a doped region of a second doping type in the doped layer, the doped region including a first doped region located at the bottom of the trench; and
    金属电极，其中，所述金属电极包括嵌入所述掺杂层中的所述沟槽的第一部分，所述第一部分与所述第一掺杂区欧姆接触，所述第一部分与所述沟槽的侧壁上未形成所述掺杂区的所述掺杂层肖特基接触。a metal electrode, wherein the metal electrode includes a first portion of the trench embedded in the doped layer, the first portion is in ohmic contact with the first doped region, and the first portion is in contact with the trench The doped layer Schottky contact of the doped region is not formed on the sidewall of the doped region.
  2. 根据权利要求1所述的半导体器件，其特征在于，所述掺杂区还包括位于所述掺杂层表面以下的第二掺杂区，所述第二掺杂区的深度小于所述沟槽的深度。The semiconductor device according to claim 1, wherein the doped region further comprises a second doped region below the surface of the doped layer, and the depth of the second doped region is smaller than that of the trench depth.
  3. 根据权利要求2所述的半导体器件，其特征在于，所述金属电极还包括位于所述掺杂层上方的第二部分，所述金属电极的第二部分与所述第二掺杂区欧姆接触。The semiconductor device according to claim 2, wherein the metal electrode further comprises a second portion located above the doped layer, and the second portion of the metal electrode is in ohmic contact with the second doped region .
  4. 根据权利要求1所述的半导体器件，其特征在于，所述掺杂层中设置有至少两个沟槽。The semiconductor device according to claim 1, wherein at least two trenches are provided in the doped layer.
  5. 根据权利要求4所述的半导体器件，其特征在于，所述沟槽包括沿着第一方向并列设置的至少两个条状沟槽，其中所述条状沟槽在与所述第一方向交叉的第二方向上从有源区的第一端延伸到与所述第一端相对应的第二端。5. The semiconductor device of claim 4, wherein the trenches comprise at least two strip-shaped trenches arranged side by side along a first direction, wherein the strip-shaped trenches intersect the first direction The second direction extends from the first end of the active region to the second end corresponding to the first end.
  6. 根据权利要求5所述的半导体器件，其特征在于，所述沟槽包括位于所述条状沟槽之间的凹型沟槽。6. The semiconductor device of claim 5, wherein the trenches comprise concave trenches between the strip trenches.
  7. 根据权利要求5所述的半导体器件，其特征在于，所述掺杂层中设置有至少两列沟槽，其中，所述至少两列沟槽中的每一列至少包括两个所述沟槽。6. The semiconductor device of claim 5, wherein at least two columns of trenches are provided in the doped layer, wherein each column of the at least two columns of trenches includes at least two of the trenches.
  8. 根据权利要求5所述的半导体器件，其特征在于，所述沟槽包括环形凹型沟槽以及在所述环形凹型沟槽所环绕的所述掺杂层中设置的凹型沟槽。6. The semiconductor device of claim 5, wherein the trench comprises an annular concave trench and a concave trench provided in the doped layer surrounded by the annular concave trench.
  9. 根据权利要求1所述的半导体器件，其特征在于，所述碳化硅衬底还包括形成在所述碳化硅衬底上的碳化硅外延层，所述碳化硅外延层为第一掺杂类型。The semiconductor device according to claim 1, wherein the silicon carbide substrate further comprises a silicon carbide epitaxial layer formed on the silicon carbide substrate, and the silicon carbide epitaxial layer is of the first doping type.
  10. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括位于所述碳化硅衬底背面的背面电极。The semiconductor device of claim 1, wherein the semiconductor device further comprises a back electrode on the back surface of the silicon carbide substrate.
  11. 一种半导体器件的制造方法，其特征在于，包括：A method of manufacturing a semiconductor device, comprising:
    提供碳化硅衬底，所述碳化硅衬底包括第一掺杂类型的掺杂层；providing a silicon carbide substrate including a doping layer of a first doping type;
    在所述掺杂层中形成沟槽；forming trenches in the doped layer;
    在所述掺杂层中形成第二掺杂类型的掺杂区，其中所述掺杂区包括位于所述沟槽底部的第一掺杂区，并且所述第一掺杂区以上的至少部分所述沟槽的侧壁外侧的所述掺杂层中 未形成所述掺杂区；A doped region of a second doping type is formed in the doped layer, wherein the doped region includes a first doped region at the bottom of the trench, and at least a portion above the first doped region The doped region is not formed in the doped layer outside the sidewall of the trench;
    形成金属电极，所述金属电极至少填充所述沟槽，其中，所述金属电极与所述掺杂区形成欧姆接触，所述金属电极与所述掺杂层在所述沟槽的侧壁的至少部分上形成肖特基接触。forming a metal electrode, the metal electrode at least fills the trench, wherein the metal electrode forms an ohmic contact with the doped region, and the metal electrode and the doped layer are on the sidewall of the trench Schottky contacts are formed at least in part.
  12. 根据权利要求11所述的制造方法，其特征在于，在所述掺杂层中形成至少两个沟槽，位于相邻两个所述沟槽之间的所述掺杂层形成突出部。The manufacturing method according to claim 11, wherein at least two trenches are formed in the doped layer, and the doped layer located between two adjacent trenches forms a protrusion.
  13. 根据权利要求12所述的制造方法，其特征在于，在所述沟槽的底部形成第二掺杂类型的掺杂区的方法包括：The manufacturing method according to claim 12, wherein the method for forming a doped region of the second doping type at the bottom of the trench comprises:
    执行离子注入工艺，以将所述沟槽底部以下的第一深度的所述掺杂层转化为所述掺杂区。An ion implantation process is performed to convert the doped layer at a first depth below the bottom of the trench into the doped region.
  14. 根据权利要求13所述的制造方法，其特征在于，所述在所述沟槽的底部形成第二掺杂类型的掺杂区的步骤，还包括将所述突出部的表面以下的第二深度的所述掺杂层转化为所述掺杂区，所述第二深度小于所述沟槽的深度。14. The manufacturing method of claim 13, wherein the step of forming a doped region of the second doping type at the bottom of the trench further comprises a second depth below the surface of the protruding portion The doped layer is converted into the doped region, and the second depth is less than the depth of the trench.
  15. 根据权利要求11所述的制造方法，其特征在于，所述形成金属电极的方法包括：The manufacturing method according to claim 11, wherein the method for forming a metal electrode comprises:
    执行沉积工艺，以形成覆盖所述碳化硅衬底并填充所述沟槽的介质层；performing a deposition process to form a dielectric layer covering the silicon carbide substrate and filling the trenches;
    执行光刻工艺，以形成覆盖在所述介质层的表面的图案化的掩膜层；performing a photolithography process to form a patterned mask layer covering the surface of the dielectric layer;
    以所述图案化的掩膜层为掩膜，执行刻蚀工艺，以形成孔，所述孔露出所述沟槽；Using the patterned mask layer as a mask, an etching process is performed to form holes, and the holes expose the trenches;
    在所述孔中填充金属。The holes are filled with metal.
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