WO2022142227A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2022142227A1
WO2022142227A1 PCT/CN2021/103871 CN2021103871W WO2022142227A1 WO 2022142227 A1 WO2022142227 A1 WO 2022142227A1 CN 2021103871 W CN2021103871 W CN 2021103871W WO 2022142227 A1 WO2022142227 A1 WO 2022142227A1
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Prior art keywords
etched
region
etching
area
etched area
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PCT/CN2021/103871
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English (en)
French (fr)
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黄鑫
李弘祥
王士欣
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长鑫存储技术有限公司
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Priority to US17/612,209 priority Critical patent/US20240049456A1/en
Publication of WO2022142227A1 publication Critical patent/WO2022142227A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a preparation method thereof.
  • the fabrication process of semiconductor structures generally includes multiple processes, such as photolithography, deposition, curing, annealing, and the like.
  • photolithography it is often necessary to etch different materials at the same time to form the desired pattern in the semiconductor structure.
  • a height difference is easily formed at the interface of different materials, which affects the yield of the semiconductor structure.
  • dynamic random access memory usually includes a substrate, an active area and a shallow trench isolation area are arranged in the substrate, and a word line is arranged in the active area. , referred to as WL).
  • a bit line contact window (Bit Line Contact, BLC for short) is also formed in the substrate, and at least part of the active region is exposed in the bit line contact window.
  • BLC Bit Line Contact
  • the above-mentioned height difference will also increase, resulting in an increased risk of the bit line contact window extending to the word line, which in turn leads to formation on the bit line.
  • the risk of short circuits between bit lines and word lines in the contact windows increases, reducing the DRAM yield.
  • embodiments of the present application provide a semiconductor structure and a method for fabricating the same, which are used to reduce the height difference at the junction of different materials when etching different materials at the same time, so as to improve the yield of the semiconductor structure.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including providing a substrate, wherein the substrate includes a first to-be-etched region and a second to-be-etched region located outside the first to-be-etched region, The etching rate of the first to-be-etched area is different from that of the second to-be-etched area; the first to-be-etched area and the second to-be-etched area are simultaneously performed at least twice Etching until the etching depth of the first to-be-etched area and the second to-be-etched area with a lower etching rate is equal to the target etching depth; during the at least two etchings , backfilling the sacrificial material in the first to-be-etched area and the second to-be-etched area after the previous etching is completed, and removing part of the sacrificial material during the subsequent etching.
  • a substrate is first provided, the substrate includes a first to-be-etched area and a second to-be-etched area with different etching rates, and the first to-be-etched area is located in the second to-be-etched area Then, at least two etchings are performed on the first to-be-etched area and the second to-be-etched area at the same time, and the first to-be-etched area and the second to-be-etched area have a lower etching rate Etch to the target etching depth; in at least two etching processes, backfill sacrificial material in the first to-be-etched area and the second to-be-etched area after the previous etching is completed to reduce the first to-be-etched area The difference between the etching depth of the second to-be-etched area and the second to-be-etched area, part of the sacrificial material is removed in the subsequent etching, so as to continue to etch the first and second to-
  • the difference between the etching depths of the first to-be-etched area and the second to-be-etched area can be partially eliminated after backfilling, and the A difference between the final etch depths of the to-be-etched area and the second to-be-etched area, thereby reducing the possibility of the first to-be-etched area or the second to-be-etched area being etched through, thereby improving the finished product of the semiconductor structure Rate.
  • the etching rate of the sacrificial material satisfies the following relational expression:
  • s 1 is the etching rate of the first region to be etched
  • s 2 is the etching rate of the second region to be etched
  • v is the etching rate of the sacrificial material.
  • the etching rate of the first to-be-etched region is lower than the etching rate of the second to-be-etched region, and the sacrificial material is partially removed during the subsequent etching
  • the step includes: removing the sacrificial material located in the first region to be etched and a part of the sacrificial material located in the second region to be etched during the subsequent etching.
  • the etching depth of the first to-be-etched area is equal to the the target etching depth.
  • the step of removing part of the sacrificial material in the subsequent etching includes: etching the sacrificial material located in the first to-be-etched area and the second to-be-etched area , until the sacrificial material in the first to-be-etched area is removed; at the same time, the substrate in the first to-be-etched area and the sacrificial material in the second to-be-etched area are etched, Alternatively, the substrate in the first region to be etched and the sacrificial material and the substrate in the second region to be etched are simultaneously etched.
  • the etching depth of the first to-be-etched region is greater than or equal to 1/2 of the target etching depth, and less than or equal to the target etching depth. 3/4 of the etch depth.
  • the sacrificial material is the same as the material of the second region to be etched.
  • the etching depth h of the second to-be-etched region satisfies the following relational expression:
  • a is the target etching depth
  • k is the first etching ratio
  • 0 ⁇ k ⁇ 1 m is the etching rate of the second to-be-etched area and the first to-be-etched area of the etching rate Etch rate ratio.
  • the preparation method before the step of performing the first etching on the first to-be-etched area and the second to-be-etched area at the same time, the preparation method further includes: on the substrate A mask layer is formed thereon; a mask opening penetrating the mask layer is formed in the mask layer, and the mask opening is opposite to the first to-be-etched area and the second to-be-etched area .
  • an initial target opening connected to the mask opening is formed after the previous etching is completed, and a sacrificial material is backfilled in the first to-be-etched area and the second to-be-etched area , the sacrificial material fills the mask opening and the initial target opening, and covers the mask layer.
  • the method for preparing a semiconductor structure as described above, after backfilling the sacrificial material in the first to-be-etched area and the second to-be-etched area, further includes: performing a planarization process on the sacrificial material, and after the planarization process The surface of the sacrificial material is flush with the surface of the mask layer.
  • the first to-be-etched region and the second to-be-etched region are simultaneously etched at least twice to form a bit line contact window, the first to-be-etched region is a part of the active region, and the second to-be-etched region is a part of the shallow trench isolation region.
  • an embodiment of the present application further provides a semiconductor structure, including a substrate, wherein a target opening is formed in the substrate, and the target opening passes through a first to-be-etched region and a second to-be-etched area of the substrate at the same time.
  • the etching area is formed by at least two etchings, and the etching rate of the first to-be-etched area is different from the etching rate of the second to-be-etched area; and during the at least two etchings, The sacrificial material is backfilled in the first to-be-etched area and the second to-be-etched area after the previous etching is completed, and part of the sacrificial material is removed during the subsequent etching.
  • the semiconductor structure provided by the embodiment of the present application includes a substrate, and the target opening in the substrate is formed by simultaneously etching the first to-be-etched region and the second to-be-etched region of the substrate at least twice.
  • the etching rate of the second to-be-etched area is different. After the previous etching is completed, the etching depth of the first to-be-etched area is different from that of the second to-be-etched area.
  • the sacrificial material is backfilled with the second to-be-etched area to reduce the difference between the etching depths of the first to-be-etched area and the second to-be-etched area, and part of the sacrificial material is removed in the subsequent etching to continue to
  • the first to-be-etched area and the second to-be-etched area of different etching rates are etched.
  • the difference between the etching depths of the first to-be-etched area and the second to-be-etched area can be partially eliminated after backfilling, which can reduce
  • the difference between the final etching depths of the first to-be-etched area and the second to-be-etched area can reduce the possibility of the first to-be-etched area or the second to-be-etched area being etched through, thereby improving the semiconductor structure Yield.
  • the target opening is formed by simultaneously etching the first to-be-etched region and the second to-be-etched region twice, and the first to-be-etched region is etched
  • the rate is lower than the etching rate of the second area to be etched;
  • the etching depth of the first area to be etched is equal to the target etching depth a, and the etching depth h of the second area to be etched satisfies the following relationship Mode:
  • k is the first etching ratio
  • m is the ratio of the etching rate of the second to-be-etched area to the first to-be-etched area of the etching rate.
  • the target opening is a bit line contact window
  • the first region to be etched is a part of the active region
  • the second region to be etched is a part of the shallow trench isolation region.
  • a mask layer is further formed on the substrate, and the mask layer is formed with mask openings corresponding to the bit line contact windows;
  • the material of the shallow trench isolation region is oxide Silicon
  • the material of the active region is silicon
  • the material of the mask layer is silicon nitride.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a substrate according to an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of an embodiment of the present application after forming an initial target opening
  • FIG. 4 is a schematic structural diagram after backfilling the sacrificial material according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an embodiment of the present application after removing part of the sacrificial material
  • FIG. 6 is a schematic structural diagram of forming a target opening according to an embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of forming a target opening according to an embodiment of the present application.
  • FIG. 8 is another structural schematic diagram of forming a target opening according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a target opening according to an embodiment of the present application.
  • FIG. 10 is a graph showing the relationship between the difference h of the etching depths of the first to-be-etched region and the second to-be-etched region and the first etching ratio k according to an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of a mask layer and a substrate according to an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a mask opening and an initial target opening according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of the mask opening and the initial target opening after backfilling the sacrificial material according to an embodiment of the present application;
  • FIG. 14 is a schematic structural diagram of an embodiment of the present application after a planarization process
  • FIG. 15 is a schematic structural diagram of the mask opening, the first to-be-etched region and the second to-be-etched region of the partial sacrificial material according to an embodiment of the present application;
  • 16 is a schematic structural diagram of a mask opening and a target opening according to an embodiment of the present application.
  • FIG. 17 is a top view of an active region and a shallow trench isolation region according to an embodiment of the present application.
  • an embodiment of the present application provides a method for preparing a semiconductor structure, which simultaneously performs at least two etchings on the first to-be-etched region and the second to-be-etched region with different etching rates, and In at least two etching processes, the sacrificial material is backfilled in the first to-be-etched area and the second to-be-etched area after the previous etching is completed, and part of the sacrificial material is removed during the subsequent etching.
  • the etching depths of the first to-be-etched area and the second to-be-etched area can be partially eliminated after backfilling, thereby reducing the difference between the final etching depths of the first to-be-etched area and the second to-be-etched area, and further The possibility of the first to-be-etched region or the second to-be-etched region being etched through can be reduced, thereby ultimately improving the yield of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • the method for fabricating a semiconductor structure includes the following steps:
  • the substrate includes a first to-be-etched area and a second to-be-etched area located outside the first to-be-etched area, the etching rate of the first to-be-etched area and the etching rate of the second to-be-etched area Rates are different.
  • the substrate includes a first region to be etched and a second region to be etched.
  • the first region to be etched is shown at A in FIG. 2
  • the second region to be etched is shown at B in FIG. 2 .
  • the second to-be-etched region surrounds and adjoins the first to-be-etched region, so that the first to-be-etched region and the second to-be-etched region can be etched simultaneously.
  • the etching rates of the first to-be-etched area and the second to-be-etched area are different, that is, the etching rate of the first to-be-etched area may be higher or lower than that of the second to-be-etched area. It can be understood that the first to-be-etched area and the second to-be-etched area may be made of different materials, and the etching rates of the material located in the first to-be-etched area and the material located in the second to-be-etched area are different.
  • the etching rate of the first to-be-etched area is lower than that of the second to-be-etched area.
  • the material of the first to-be-etched area may be silicon, and the second to-be-etched area may be made of silicon.
  • the material in the region may be silicon oxide.
  • the first to-be-etched area and the second to-be-etched area are etched at least twice at the same time, and finally the desired target opening 12 is formed.
  • the bottom surface of the target opening 12 has a height difference, and the height difference is determined by the A portion of the bottom surface of the first region to be etched and a portion of the bottom surface of the second region to be etched are formed.
  • the minimum depth of the target opening 12 is the target etching depth, that is, the etching depth of the first to-be-etched region and the second to-be-etched region with a lower etching rate after at least two etchings.
  • the sacrificial material 20 is backfilled in the first to-be-etched area and the second to-be-etched area after the previous etching is completed, and is removed during the subsequent etching Part of the sacrificial material 20 is used to continuously etch the first to-be-etched region and the second to-be-etched region with different etching rates at the same time.
  • the sacrificial material 20 can be formed in the first to-be-etched area and the second to-be-etched area by chemical vapor deposition or physical vapor deposition, and the etching rate of the sacrificial material 20 is at the etch rate of the first to-be-etched area and the second to-be-etched area. between the etch rates of the etched regions.
  • the etching rate of the sacrificial material 20 satisfies the following relationship:
  • s 1 is the etching rate of the first region to be etched
  • s 2 is the etching rate of the second region to be etched
  • v is the etching rate of the sacrificial material 20 .
  • the sacrificial material 20 and the material of the substrate 10 in the second to-be-etched region may be the same or different.
  • the material of the substrate 10 in the first to-be-etched area can be silicon
  • the material of the substrate 10 in the second to-be-etched area can be silicon oxide
  • the sacrificial material 20 can be silicon oxide, silicon nitride, silicon oxynitride, etc. one or more.
  • the first to-be-etched area and the second to-be-etched area are etched twice at the same time, the first to-be-etched area and the second to-be-etched area are etched between the two etching processes. area to be backfilled.
  • the backfill times are less than the etching times and greater than one.
  • first to-be-etched area and the second to-be-etched area are etched three or more times at the same time, the first to-be-etched area and the second to-be-etched area can be etched between any two adjacent etching processes.
  • the second to-be-etched area is backfilled.
  • the first etching, the second etching or the third etching may be performed only after the first etching, the second etching or the third etching.
  • the initial target openings 11 are formed in the first to-be-etched area and the second to-be-etched area, and the backfilled sacrificial material 20 fills the initial target openings 11 . It can be understood that the initial target opening 11 is different after each etching is completed, that is, the initial target opening 11 is constantly changing with the etching process.
  • the sacrificial material 20 of the first to-be-etched area and the second to-be-etched area are simultaneously etched, so as to Remove the sacrificial material located in the first to-be-etched area or in the second to-be-etched area; then simultaneously etch the first to-be-etched area and the second to-be-etched area, at this time, the to-be-etched area located in the first to-be-etched area
  • the etched material is different from the material to be etched in the second to-be-etched area, that is, the first to-be-etched area and the second to-be-etched area have different etching rates. It should be noted that, the above-mentioned two simultaneous etching processes of the first to-be-etched region and the second to-be-etched region can be completed in the same step.
  • the etching rate of the first region to be etched is lower than the etching rate of the second region to be etched, and the first region to be etched and the second region to be etched are simultaneously etched twice Then, the etching depth of the first to-be-etched region is equal to the target etching depth.
  • the etching depth of the first region to be etched may be greater than or equal to 1/2 of the target etching depth, and less than or equal to 3/4 of the target etching depth.
  • the etching rate of the first to-be-etched area is lower than that of the second to-be-etched area, the first to-be-etched area is etched slowly corresponding to the second to-be-etched area, and the first to-be-etched area is etched slowly.
  • the etching depth is smaller than the etching depth of the second to-be-etched region. As shown in FIG. 3 , the depth of the initial target opening 11 at the first region to be etched is smaller than the depth of the initial target opening 11 at the second region to be etched.
  • the sacrificial material 20 is backfilled in the first to-be-etched area and the second to-be-etched area, and the backfilled sacrificial material 20 fills the initial target opening 11 , as shown in FIG. 4 , The sacrificial material 20 is flush with the substrate 10 .
  • the etch rate of the sacrificial material 20 is between the etch rate of the first region to be etched and the etch rate of the second region to be etched.
  • the sacrificial material 20 is the same as the material of the substrate 10 in the second to-be-etched area, that is, the sacrificial material 20 is the same as the one of the first to-be-etched area and the second to-be-etched area with a higher etching rate Materials are the same.
  • the sacrificial material 20 located in the first to-be-etched area and the second to-be-etched area is etched to remove until completely
  • the sacrificial material 20 in the first to-be-etched area is removed.
  • a part of the sacrificial material 20 is removed from the second to-be-etched area, and a part of the sacrificial material 20 remains.
  • the sacrificial material 20 When the sacrificial material 20 is removed, there is no difference in etching depth between the first to-be-etched region and the second to-be-etched region. When the sacrificial material 20 in the first to-be-etched area is completely removed, the second to-be-etched area of the sacrificial material 20 removes a portion corresponding to the first to-be-etched area, so that the substrate 10 of the first to-be-etched area and the The sacrificial material 20 of the second region to be etched is flush.
  • the substrate 10 located in the first region to be etched and the sacrificial material 20 located in the second region to be etched are simultaneously etched, or the substrate 10 located in the first region to be etched and the second region to be etched are simultaneously etched sacrificial material 20 and the substrate 10 in the region until the etching depth of the first region to be etched is equal to the target etching depth.
  • the etching depth of the first region to be etched is equal to the target etching depth
  • part of the sacrificial material 20 is removed from the second region to be etched, and the target opening 12 is located in the second region to be etched.
  • the depth of the region to be etched is smaller than the depth of the initial target opening 11 in the second region to be etched, and a portion of the sacrificial material 20 remains in the second region to be etched. That is, the substrate 10 in the second to-be-etched area and a portion of the sacrificial material 20 in the second to-be-etched area are etched simultaneously to form the desired target opening 12 .
  • the second to-be-etched area removes all the sacrificial material 20 , the target opening 12 and the initial The depths of the target openings 11 in the second region to be etched are the same. That is, the substrate 10 located in the second to-be-etched area and all the sacrificial materials 20 located in the second to-be-etched area are etched simultaneously to form the desired target opening 12 .
  • the second to-be-etched region removes all the sacrificial material 20 and partially removes the substrate 10 .
  • the position of the double-dotted line is the depth of the initial target opening 11 in the second to-be-etched area, and the depth of the target opening 12 in the second to-be-etched area is greater than the initial target opening 11 in the second to-be-etched area depth within the etch zone. That is, the substrate 10 located in the second to-be-etched area and the entire sacrificial material 20 and a part of the substrate 10 located in the second to-be-etched area are etched simultaneously to form the desired target opening 12 .
  • the sacrificial material 20 is the same as the material of the second to-be-etched area.
  • the second to-be-etched area satisfies the following relation:
  • k is the ratio of the first etching, 0 ⁇ k ⁇ 1
  • m is the ratio of the etching rate of the second to-be-etched area to the first to-be-etched area of the etching rate.
  • the difference y between the etching depths of the first to-be-etched region and the second to-be-etched region is:
  • the ratio m of the etching rate of the second to-be-etched area to the first to-be-etched area is 1.5
  • the first etching ratio k is 3/4
  • the target etching depth a is At 40 nm
  • the target opening 12 is formed by one etching
  • the etching depth of the first to-be-etched area is 40 nm
  • the etching depth of the second to-be-etched area is 60 nm
  • the first to-be-etched area and the second to-be-etched area are The difference of the etching depth is 20nm.
  • the etching depth of the first to-be-etched area is 40 nm
  • the second to-be-etched area of the etching depth is 45 nm
  • the first to-be-etched area and the second to-be-etched area are The difference between the etching depths is 5 nm, and the difference between the etching depths of the first to-be-etched region and the second to-be-etched region decreases.
  • a substrate 10 is first provided, the substrate 10 includes a first to-be-etched area and a second to-be-etched area with different etching rates, and the first to-be-etched area is located in the second to-be-etched area.
  • the outer side of the etched area then at least two etchings are performed on the first to-be-etched area and the second to-be-etched area at the same time, and the first to-be-etched area and the second to-be-etched area have a lower etching rate.
  • One is etched to the target etching depth; in at least two etching processes, the sacrificial material 20 is backfilled in the first to-be-etched area and the second to-be-etched area after the previous etching is completed, so as to reduce the amount of the first to-be-etched area.
  • the difference between the etch depths of the etched area and the second to-be-etched area, part of the sacrificial material 20 is removed in the subsequent etching, so as to continue to etch the first and second to-be-etched areas with different etching rates
  • the etched area is etched.
  • the height difference between the first to-be-etched area and the second to-be-etched area can be partially eliminated after backfilling, and the first to-be-etched area can be reduced.
  • the final height difference between the etched area and the second to-be-etched area can reduce the possibility of the first to-be-etched area or the second to-be-etched area being etched through, thereby improving the yield of the semiconductor structure.
  • the preparation method before the first etching is performed on the first to-be-etched area and the second to-be-etched area at the same time, the preparation method further includes:
  • the mask layer 30 is formed on the substrate 10 .
  • a mask layer 30 may be deposited and formed on the substrate 10 , and the mask layer 30 covers the first region to be etched and the second region to be etched.
  • the material of the mask layer 30 may be silicon nitride material.
  • a mask opening 31 penetrating the mask layer 30 is formed in the mask layer 30 , and the mask opening 31 is opposite to the first to-be-etched region and the second to-be-etched region.
  • the mask opening 31 penetrates through the mask layer 30 to expose the substrate 10 , and the mask opening 31 is opposite to the first region to be etched and a portion of the second region to be etched.
  • the region of the substrate 10 located in the mask opening 31 is etched.
  • initial target openings 11 are formed in the substrate 10 after the first etching, and the initial target openings 11 communicate with the mask openings 31 .
  • an initial target opening 11 that communicates with the mask opening 31 is formed after the previous etching is completed.
  • the sacrificial material 20 is backfilled in the first to-be-etched region and the second to-be-etched region, the sacrificial material 20 fills the mask The opening 31 and the initial target opening 11 cover the mask layer 30 .
  • the preparation method further includes: performing a planarization process on the sacrificial material 20; The surface of the membrane layer 30 is flush.
  • CMP chemical mechanical polishing
  • the sacrificial material 20 in the mask opening 31 is removed, and the first to-be-etched area is removed All of the sacrificial material 20 in the to-be-etched area, part of the sacrificial material 20 is removed in the second to-be-etched area, and a part of the sacrificial material 20 remains.
  • the etching rates of the first to-be-etched area and the second to-be-etched area are different, and when the etching depth of the first to-be-etched area is equal to the target etching depth, the second etching is completed, and the first The to-be-etched region and the second to-be-etched region form the target opening 12 shown in FIG. 16 .
  • the above-mentioned target opening 12 may be a bit line contact window, that is, the preparation method of the embodiment of the present application may be applied to the formation process of the bit line contact window of the memory, that is, the The etched area and the second to-be-etched area are etched at least twice to form a bit line contact window, the first to-be-etched area is a part of the active area, and the second to-be-etched area is a part of the shallow trench isolation area. trench isolation, referred to as STI).
  • STI trench isolation
  • the semiconductor structure in the embodiment of the present application includes a substrate 10 , and the substrate 10 includes a first region to be etched and a second region to be etched.
  • the first region to be etched is shown at A in FIG. 16
  • the second region to be etched is shown at B in FIG. 16 .
  • the second to-be-etched region surrounds and adjoins the first to-be-etched region, so that the first to-be-etched region and the second to-be-etched region can be etched simultaneously.
  • the etching rates of the first to-be-etched area and the second to-be-etched area are different, that is, the etching rate of the first to-be-etched area may be higher or lower than that of the second to-be-etched area. It can be understood that, the first to-be-etched area and the second to-be-etched area may be made of different materials, and the etching rates of the material located in the first to-be-etched area and the material located in the second to-be-etched area are different.
  • target openings 12 are also formed in the substrate 10 , and the target openings 12 are formed by simultaneously etching the first to-be-etched region and the second to-be-etched region of the substrate 10 at least twice. During the etching process, after the previous etching is completed, the sacrificial material 20 is backfilled in the first to-be-etched area and the second to-be-etched area, and part of the sacrificial material 20 is removed during the subsequent etching.
  • the first to-be-etched area and the second to-be-etched area form the initial target opening 11, and the sacrificial material 20 can be formed on the first to-be-etched area and the second to-be-etched area by chemical vapor deposition or physical vapor deposition.
  • the etching rate of the sacrificial material 20 is between the etching rate of the first region to be etched and the etching rate of the second region to be etched.
  • the sacrificial material 20 in the first and second to-be-etched areas is removed until the substrate 10 is exposed in the first or second to-be-etched area, and then the remaining sacrificial materials 20 are removed.
  • the material 20 and the substrate 10 are simultaneously etched to form the target opening 12 .
  • the etching rate of the first to-be-etched region is lower than the etching rate of the second to-be-etched region, and simultaneously the first and second to-be-etched regions of the substrate 10 are subjected to two The secondary etch forms the target opening 12, and the sacrificial material 20 is the same material as the second region to be etched.
  • the etching depth of the first to-be-etched area is equal to the target etching depth a, and the second to-be-etched area of the etching depth h satisfies the following relationship:
  • k is the ratio of the first etching, 0 ⁇ k ⁇ 1
  • m is the ratio of the etching rate of the second to-be-etched area to the first to-be-etched area of the etching rate.
  • the target opening 12 can be the bit line contact window 12
  • the first region to be etched can be a part of the active region 101 , the material of which is silicon
  • the second region to be etched can be part of the active region 101 .
  • the shallow trench isolation region 102 may be made of silicon oxide, and the active region 101 and the shallow trench isolation region 102 constitute the substrate 10 .
  • FIG. 16 may be a cross-sectional view taken along the direction I-I in FIG. 17 .
  • a bit line contact structure can be formed in the bit line contact window 12, and the bit line contact structure can be used to connect a bit line (Bit Line, BL for short).
  • a mask layer 30 may also be formed on the substrate 10 , the mask layer 30 is formed with mask openings 31 corresponding to the bit line contact windows, and the material of the mask layer 30 may be silicon nitride.
  • the sacrificial material 20 fills the mask opening 31 and the initial target opening 11, and covers the mask layer 30.
  • the sacrificial material 20 may be planarized, so that the sacrificial material 20 and the The mask layer 30 is flush to facilitate subsequent etching.
  • the semiconductor structure provided by this embodiment of the present application includes a substrate 10, and the target opening 12 in the substrate 10 is formed by simultaneously etching the first to-be-etched region and the second to-be-etched region of the substrate 10 at least twice.
  • the etching rates of the etched area and the second to-be-etched area are different. After the previous etching is completed, the etching depth of the first to-be-etched area is different from that of the second to-be-etched area.
  • the to-be-etched area and the second to-be-etched area are backfilled with the sacrificial material 20 to reduce the difference between the etching depths of the first to-be-etched area and the second to-be-etched area, and part of the sacrificial material is removed in the subsequent etching 20, to continue etching the first to-be-etched region and the second to-be-etched region with different etching rates.
  • the height difference between the first to-be-etched area and the second to-be-etched area can be partially eliminated after backfilling, and the first to-be-etched area can be reduced.
  • the final height difference between the etched area and the second to-be-etched area can reduce the possibility of the first to-be-etched area or the second to-be-etched area being etched through, thereby improving the yield of the semiconductor structure.
  • references to the terms “one embodiment,” “some embodiments,” “exemplary embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments
  • a particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请提供一种半导体结构及其制备方法，涉及半导体技术领域，用于解决半导体结构成品率低的技术问题。该半导体结构的制备方法包括：基底包括第一待刻蚀区和位于第一待刻蚀区外侧的第二待刻蚀区，第一待刻蚀区的刻蚀速率与第二待刻蚀区的刻蚀速率不同；同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，直至第一待刻蚀区和第二待刻蚀区中刻蚀速率较小的一个的刻蚀深度等于目标刻蚀深度；在至少两次刻蚀的过程中，在前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分牺牲材料。通过在至少两次刻蚀过程之间回填牺牲材料，以减少第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值，提高半导体结构的成品率。

Description

半导体结构及其制备方法
本申请要求于2021年01月04日提交中国专利局、申请号为202110004899.4、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
半导体结构的制备过程通常包括多个制程，例如光刻、沉积、固化、退火等。光刻时，通常需要同时刻蚀不同的材料，以在半导体结构中形成所需图案。然而，刻蚀后所形成的图案中，不同的材料的交界处易形成高度差，影响半导体结构的成品率。
以动态随机存储器(Dynamic Random Access Memory，简称DRAM)的制备为例，动态随机存储器通常包括基底，基底中设置有有源区和浅沟槽隔离区，有源区内设置有字线(Word Line，简称WL)。基底中还形成有位线接触窗(Bit Line Contact，简称BLC)，位线接触窗中暴露至少部分有源区。形成位线接触窗时，通常需要对浅沟槽隔离区和有源区同时进行刻蚀，所形成的位线接触窗的底部存在高度差。随刻蚀深度的增加或者位线接触窗相对有源区的偏移量增加，上述高度差也会随之增大，导致位线接触窗延伸至字线的风险增加，进而导致形成在位线接触窗中的位线与字线之间的短路的风险增加，降低了动态随机存储器的成品率。
发明内容
有鉴于此，本申请实施例提供一种半导体结构及其制备方法，用于减少同时刻蚀不同的材料时，不同的材料的交界处的高度差，以提高半导体结构的成品率。
为了实现上述目的，本申请实施例提供如下技术方案：
第一方面，本申请实施例提供一种半导体结构的制备方法，包括提供基底，所述基底包括第一待刻蚀区和位于所述第一待刻蚀区外侧的第二待刻蚀区，所述第一待刻蚀区的刻蚀速率与所述第二待刻蚀区的刻蚀速率不同；同时对所述第一待刻蚀区和所述第二待刻蚀区进行至少两次刻蚀，直至所述第一待刻蚀区和所述第二待刻蚀区中刻蚀速率较小的一个的刻蚀深度等于目标刻蚀深度；在所述至少两次刻蚀的过程中，在前一次刻蚀完成后在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分所述牺牲材料。
本申请实施例提供的半导体结构的制备方法具有如下优点：
本申请实施例提供的半导体结构的制备方法中，先提供基底，基底包括刻蚀速率不同的第一待刻蚀区和第二待刻蚀区，第一待刻蚀区位于第二待刻蚀区的外侧；然后同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，将第一待刻蚀区和第二待刻蚀区中刻蚀速率较小的一个刻蚀至目标刻蚀深度；在至少两次刻蚀过程中，在前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料，以减小第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值，在后一次刻蚀时去除部分牺牲材料，以继续对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行刻蚀。相较于相关技术中一次刻蚀到目标刻蚀深度，本申请实施例中，第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值经回填后可以消除部分，降低第一待刻蚀区和第二待刻蚀区的最终刻蚀深度的差值，从而可以减小第一待刻蚀区或者第二待刻蚀区刻穿的可能性，进而提高半导体结构的成品率。
如上所述的半导体结构的制备方法，所述牺牲材料的刻蚀速率满足以下关系式：
min(s 1，s 2)＜v≤max(s 1，s 2)；
其中，s 1为所述第一待刻蚀区的刻蚀速率，s 2为所述第二待刻蚀区的刻蚀速率，v为所述牺牲材料的刻蚀速率。
如上所述的半导体结构的制备方法，所述第一待刻蚀区的刻蚀速率小于所述第二待刻蚀区的刻蚀速率，所述在后一次刻蚀时去除部分所述牺牲材料的步骤包括：在后一次刻蚀时去除位于所述第一待刻蚀区的所述牺牲材料和位于所述第二待刻蚀区的部分所述牺牲材料。
如上所述的半导体结构的制备方法，同时对所述第一待刻蚀区和所述 第二待刻蚀区进行两次刻蚀后，所述第一待刻蚀区的刻蚀深度等于所述目标刻蚀深度。
如上所述的半导体结构的制备方法，后一次刻蚀时去除部分所述牺牲材料的步骤包括：刻蚀位于所述第一待刻蚀区和所述第二待刻蚀区的所述牺牲材料，直至去除所述第一待刻蚀区内的所述牺牲材料；同时刻蚀位于所述第一待刻蚀区的所述基底和位于所述第二待刻蚀区的所述牺牲材料，或者，同时刻蚀位于所述第一待刻蚀区的所述基底以及位于所述第二待刻蚀区的所述牺牲材料和所述基底。
如上所述的半导体结构的制备方法，第一次刻蚀后所述第一待刻蚀区的刻蚀深度大于或者等于所述目标刻蚀深度的1/2，且小于或者等于所述目标刻蚀深度的3/4。
如上所述的半导体结构的制备方法，所述牺牲材料与所述第二待刻蚀区的材料相同。
如上所述的半导体结构的制备方法，当所述第一待刻蚀区的刻蚀深度等于所述目标刻蚀深度时，所述第二待刻蚀区的刻蚀深度h满足如下关系式：
h＝a×k+[a×(1-k)]×m；
其中，a为所述目标刻蚀深度，k为第一次刻蚀比例，0<k<1，m为所述第二待刻蚀区的刻蚀速率与所述第一待刻蚀区的刻蚀速率的比值。
如上所述的半导体结构的制备方法，同时对所述第一待刻蚀区和所述第二待刻蚀区进行第一次刻蚀的步骤之前，所述制备方法还包括：在所述基底上形成掩膜层；在所述掩膜层中形成有贯穿所述掩膜层的掩膜开口，所述掩膜开口与所述第一待刻蚀区和所述第二待刻蚀区相对。
如上所述的半导体结构的制备方法，前一次刻蚀完成后形成与所述掩膜开口连通的初始目标开口，在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料时，所述牺牲材料填满所述掩膜开口和所述初始目标开口，且覆盖所述掩膜层。
如上所述的半导体结构的制备方法，在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料之后，还包括：对所述牺牲材料进行平坦化处理，平坦化处理后的所述牺牲材料的表面与所述掩膜层的表面齐平。
如上所述的半导体结构的制备方法，同时对所述第一待刻蚀区和所述 第二待刻蚀区进行至少两次刻蚀后形成位线接触窗，所述第一待刻蚀区为部分有源区，所述第二待刻蚀区为部分浅沟槽隔离区。
如上所述的半导体结构的制备方法，采用化学气相沉积或物理气相沉积形成所述牺牲材料。
第二方面，本申请实施例还提供了一种半导体结构，包括基底，所述基底中形成有目标开口，所述目标开口通过同时对所述基底的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀形成，所述第一待刻蚀区的刻蚀速率与所述第二待刻蚀区的刻蚀速率不同；且在所述至少两次刻蚀的过程中，在前一次刻蚀完成后在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分所述牺牲材料。
本申请实施例提供的半导体结构具有如下优点：
本申请实施例提供的半导体结构包括基底，基底中的目标开口通过同时对基底的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀形成，由于第一待刻蚀区和第二待刻蚀区的刻蚀速率不同，前一次刻蚀完成后，第一待刻蚀区的刻蚀深度和第二待刻蚀区的刻蚀深度不同，通过在第一待刻蚀区和第二待刻蚀区回填牺牲材料，以减小第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值，在后一次刻蚀时去除部分牺牲材料，以继续对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行刻蚀。相较于相关技术中一次刻蚀到目标刻蚀深度，本申请实施例中，第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值经回填后可以消除部分，可以降低第一待刻蚀区和第二待刻蚀区的最终刻蚀深度的差值，从而可以减小第一待刻蚀区或者第二待刻蚀区刻穿的可能性，进而提高半导体结构的成品率。
如上所述的半导体结构，所述目标开口通过同时对所述第一待刻蚀区和所述第二待刻蚀区进行两次刻蚀形成，且所述第一待刻蚀区的刻蚀速率小于所述第二待刻蚀区的刻蚀速率；所述第一待刻蚀区的刻蚀深度等于目标刻蚀深度a，所述第二待刻蚀区的刻蚀深度h满足如下关系式：
a＜h≤a×k+[a×(1-k)]×m；
其中，k为第一次刻蚀比例，0<k<1，m为所述第二待刻蚀区的刻蚀速率与所述第一待刻蚀区的刻蚀速率的比值。
如上所述的半导体结构，所述目标开口为位线接触窗，所述第一待刻蚀区为部分有源区，所述第二待刻蚀区为部分浅沟槽隔离区。
如上所述的半导体结构，所述基底上还形成有掩膜层，所述掩膜层形成有与所述位线接触窗相对应的掩膜开口；所述浅沟槽隔离区的材质为氧化硅，所述有源区的材质为硅，所述掩膜层的材质为氮化硅。
附图说明
图1为本申请实施例的半导体结构的制备方法的流程图；
图2为本申请实施例的基底的结构示意图；
图3为本申请实施例的形成初始目标开口后的结构示意图；
图4为本申请实施例的回填牺牲材料后的结构示意图；
图5为本申请实施例的去除部分牺牲材料后的结构示意图；
图6为本申请实施例的形成目标开口的一种结构示意图；
图7为本申请实施例的形成目标开口的另一种结构示意图；
图8为本申请实施例的形成目标开口的又一种结构示意图；
图9为本申请实施例的目标开口的结构示意图；
图10为本申请实施例的第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值h与第一次刻蚀比例k的关系图；
图11为本申请实施例的掩膜层和基底的结构示意图；
图12为本申请实施例的掩膜开口和初始目标开口的结构示意图；
图13为本申请实施例的在掩膜开口和初始目标开口回填牺牲材料后的结构示意图；
图14为本申请实施例的平坦化处理后的结构示意图；
图15为本申请实施例的去除掩膜开口、第一待刻蚀区和第二待刻蚀区的部分牺牲材料后的结构示意图；
图16为本申请实施例的掩膜开口和目标开口的结构示意图；
图17为本申请实施例的有源区和浅沟槽隔离区的俯视图。
具体实施方式
为了提高半导体结构的成品率，本申请实施例提供一种半导体结构的制备方法，同时对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，并在至少两次刻蚀过程中，在前一次刻蚀完成后在第一待 刻蚀区和第二待刻蚀区回填牺牲材料，在后一次刻蚀时去除部分牺牲材料。第一待刻蚀区和第二待刻蚀区的刻蚀深度经回填后可以消除部分，从而降低了第一待刻蚀区和第二待刻蚀区的最终刻蚀深度的差值，进而可以减小第一待刻蚀区或者第二待刻蚀区刻穿的可能性，最终提高半导体结构的成品率。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例一
参照图1，图1为本申请实施例的半导体结构的制备方法的流程图，该半导体结构的制备方法包括以下步骤：
S101、提供基底，基底包括第一待刻蚀区和位于第一待刻蚀区外侧的第二待刻蚀区，第一待刻蚀区的刻蚀速率与第二待刻蚀区的刻蚀速率不同。
基底包括第一待刻蚀区和第二待刻蚀区。在一种可能的示例中，参照图2，第一待刻蚀区如图2中A处所示，第二待刻蚀区如图2中B处所示。第二待刻蚀区围绕第一待刻蚀区且与第一待刻蚀区邻接，从而能够同时刻蚀第一待刻蚀区和第二待刻蚀区。
第一待刻蚀区和第二待刻蚀区的刻蚀速率不同，即第一待刻蚀区的刻蚀速率可以大于或者小于第二待刻蚀区的刻蚀速率。可以理解的是，第一待刻蚀区和第二待刻蚀区内可以为不同的材质，位于第一待刻蚀区的材质和位于第二待刻蚀区的材质的刻蚀速率不同。
本申请实施例中，第一待刻蚀区的刻蚀速率小于第二待刻蚀区的刻蚀速率，示例性的，第一待刻蚀区内的材质可以为硅，第二待刻蚀区内的材质可以为氧化硅。
S102、同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，直至第一待刻蚀区和第二待刻蚀区中刻蚀速率较小的一个的刻蚀深度等于目标刻蚀深度；在至少两次刻蚀的过程中，在前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分牺牲材料。
本步骤中，同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，最终形成所需的目标开口12，目标开口12的底面具有高度差，该高度差由分别位于第一待刻蚀区的部分底面和第二待刻蚀区的部分底面形成。目标开口12的最小深度为目标刻蚀深度，即为第一待刻蚀区和第二待刻蚀区中刻蚀速率较小的一个经过至少两次刻蚀后的刻蚀深度。
为了减小上述高度差，在至少两次刻蚀的过程中，前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料20，并在后一次刻蚀时去除部分牺牲材料20，使得同时对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区继续进行刻蚀。
牺牲材料20可以通过化学气相沉积或物理气相沉积形成在第一待刻蚀区和第二待刻蚀区，牺牲材料20的刻蚀速率位于第一待刻蚀区的刻蚀速率和第二待刻蚀区的刻蚀速率之间。示例性的，牺牲材料20的刻蚀速率满足以下关系式：
min(s 1，s 2)＜v≤max(s 1，s 2)；
其中，s 1为第一待刻蚀区的刻蚀速率，s 2为第二待刻蚀区的刻蚀速率，v为牺牲材料20的刻蚀速率。
牺牲材料20与第二待刻蚀区内的基底10材料可以相同也可以不相同。例如，第一待刻蚀区内的基底10材料可以为硅，第二待刻蚀区内的基底10材料可以为氧化硅，牺牲材料20可以为氧化硅、氮化硅、氮氧化硅等其中一种或多种。
本申请实施例中，当同时对第一待刻蚀区和第二待刻蚀区进行两次刻蚀时，这两次刻蚀过程之间对第一待刻蚀区和第二待刻蚀区进行回填。当同时对第一待刻蚀区和第二待刻蚀区进行三次及以上刻蚀时，回填次数小于刻蚀次数，且大于一次。
需要说明的是，当同时对第一待刻蚀区和第二待刻蚀区进行三次及以上刻蚀时，可以在任意两次相邻的刻蚀过程之间对第一待刻蚀区和第二待刻蚀区进行回填。
示例性的，当同时对第一待刻蚀区和第二待刻蚀区进行四次刻蚀时，可以只在第一次刻蚀、第二次刻蚀或者第三次刻蚀之后对第一待刻蚀区和第二待刻蚀区进行回填，即回填次数为一次；也可以在第一次刻蚀和第二次刻蚀之后、第一次刻蚀和第三次刻蚀之后，或者第二次刻蚀和第三次刻 蚀之后对第一待刻蚀区和第二待刻蚀区进行回填，即回填次数为两次；还可以在第一次刻蚀、第二次刻蚀和第三次刻蚀之后都对第一待刻蚀区和第二待刻蚀区进行回填，即回填次数为三次。
需要说明的是，前一次刻蚀完成后，在第一待刻蚀区和第二待刻蚀区中形成初始目标开口11，回填的牺牲材料20填充满初始目标开口11。可以理解的是，初始目标开口11在每次刻蚀完成后均不相同，即初始目标开口11随着刻蚀过程不断变化。
在后一次刻蚀时，同时对第一待刻蚀区和第二待刻蚀区进行刻蚀时，先同时刻蚀第一待刻蚀区和第二待刻蚀区的牺牲材料20，以去除位于第一待刻蚀区或位于第二待刻蚀区的牺牲材料；然后同时刻蚀第一待刻蚀区和第二待刻蚀区，此时，位于第一待刻蚀区的待刻蚀材料与位于第二待刻蚀区的待刻蚀材料不同，即此时第一待刻蚀区和第二待刻蚀区具有不同的刻蚀速率。需要说明的是，上述同时两次同时对第一待刻蚀区和第二待刻蚀区的刻蚀过程可以在同一步骤中完成。
在一些可能的示例中，第一待刻蚀区的刻蚀速率小于第二待刻蚀区的刻蚀速率，且同时对第一待刻蚀区和第二待刻蚀区进行两次刻蚀后，第一待刻蚀区的刻蚀深度等于目标刻蚀深度。
参照图3，同时对第一待刻蚀区和第二待刻蚀区进行第一次刻蚀后，形成初始目标开口11。示例性的，第一待刻蚀区的刻蚀深度可以大于或者等于目标刻蚀深度的1/2，且小于或者等于目标刻蚀深度的3/4。
由于第一待刻蚀区的刻蚀速率小于第二待刻蚀区的刻蚀速率，第一待刻蚀区相对应第二待刻蚀区刻蚀较慢，第一待刻蚀区的刻蚀深度小于第二待刻蚀区的刻蚀深度。如图3所示，初始目标开口11位于第一待刻蚀区处的深度小于初始目标开口11位于第二待刻蚀区处的深度。
参照图4，在第一次刻蚀完成后，在第一待刻蚀区和第二待刻蚀区回填牺牲材料20，回填的牺牲材料20填充满初始目标开口11，如图4所示，牺牲材料20与基底10齐平。
牺牲材料20的刻蚀速率在第一待刻蚀区的刻蚀速率和第二待刻蚀区的刻蚀速率之间。本申请实施例中，牺牲材料20与第二待刻蚀区内的基底10材料相同，即牺牲材料20与第一待刻蚀区和第二待刻蚀区中刻蚀速率较大的一个的材料相同。如此设置，当经过第二次刻蚀后，未完全去除牺 牲材料20时，剩余的牺牲材料20无需额外去除，提高了半导体结构的制备效率。
回填牺牲材料20后，去除位于第一待刻蚀区的牺牲材料20和位于第二待刻蚀区的部分牺牲材料20，并同时对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行第二次刻蚀。第二次刻蚀完成后，基底10中形成所需的目标开口12。
在同时对第一待刻蚀区和第二待刻蚀区进行第二次刻蚀时，首先，刻蚀去除位于第一待刻蚀区和第二待刻蚀区的牺牲材料20，直至完全去除第一待刻蚀区内的牺牲材料20，如图5所示，第二待刻蚀区内去除部分牺牲材料20，保留有部分牺牲材料20。
在去除牺牲材料20时，第一待刻蚀区和第二待刻蚀区内不会出现刻蚀深度差。当完全去除位于第一待刻蚀区的牺牲材料20时，第二待刻蚀区的牺牲材料20去除与第一待刻蚀区相对应的部分，使得第一待刻蚀区的基底10和第二待刻蚀区的牺牲材料20齐平。
然后，同时刻蚀位于第一待刻蚀区的基底10和位于第二待刻蚀区的牺牲材料20，或者，同时刻蚀位于第一待刻蚀区的基底10和位于第二待刻蚀区的牺牲材料20和基底10，直至第一待刻蚀区的刻蚀深度等于目标刻蚀深度。
在一种可能的示例中，如图6所示，当第一待刻蚀区的刻蚀深度等于目标刻蚀深度时，第二待刻蚀区去除部分牺牲材料20，目标开口12在第二待刻蚀区内的深度小于初始目标开口11在第二待刻蚀区内的深度，第二待刻蚀区保留有部分牺牲材料20。也就是说，同时刻蚀位于第二待刻蚀区的基底10和位于第二待刻蚀区的部分牺牲材料20，形成所需目标开口12。
在另一种可能的示例中，如图7所示，当第一待刻蚀区的刻蚀深度等于目标刻蚀深度时，第二待刻蚀区去除全部牺牲材料20，目标开口12和初始目标开口11在第二待刻蚀区内的深度相同。也就是说，同时刻蚀位于第二待刻蚀区的基底10和位于第二待刻蚀区的全部牺牲材料20，形成所需目标开口12。
在又一种可能的示例中，如图8所示，当第一待刻蚀区的刻蚀深度等于目标刻蚀深度时，第二待刻蚀区去除全部牺牲材料20且去除部分基底10。如图8所示，双点划线位置为初始目标开口11在第二待刻蚀区内的深 度，目标开口12在第二待刻蚀区内的深度大于初始目标开口11在第二待刻蚀区内的深度。也就是说，同时刻蚀位于第二待刻蚀区的基底10和位于第二待刻蚀区的全部牺牲材料20和部分基底10，形成所需目标开口12。
本申请实施例中，牺牲材料20与第二待刻蚀区的材料相同，如图9所示，当第一待刻蚀区的刻蚀深度等于目标刻蚀深度a时，第二待刻蚀区的刻蚀深度h满足如下关系式：
h＝a×k+[a×(1-k)]×m；
其中，k为第一次刻蚀比例，0<k<1，m为第二待刻蚀区的刻蚀速率与第一待刻蚀区的刻蚀速率的比值。
第一待刻蚀区和第二待刻蚀区的刻蚀深度之间的差值y为：
y＝h-a＝a×(m-1)+a×k×(1-m)；
以k为自变量，y为因变量作图，如图10所示。从图中可以看到，随着k值的逐渐增大，y值逐渐减小，k与y之间线性负相关。也就是说，在第一次刻蚀时，第一待刻蚀区的刻蚀深度越接近目标刻蚀深度时，第一待刻蚀区和第二待刻蚀区所形成的高度差越小。然而，第一待刻蚀区的刻蚀深度越大，回填难度也越大，因此，需根据实际工艺和实际工况选择合适的k值。
示例性的，当第二待刻蚀区的刻蚀速率与第一待刻蚀区的刻蚀速率的比值m为1.5，第一次刻蚀比例k为3/4，目标刻蚀深度a为40nm时，一次刻蚀形成目标开口12，第一待刻蚀区的刻蚀深度为40nm，第二待刻蚀区的刻蚀深度为60nm，第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值为20nm。本申请实施例形成目标开口12后，第一待刻蚀区的刻蚀深度为40nm，第二待刻蚀区的刻蚀深度为45nm，第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值为5nm，第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值减小。
本申请实施例提供的半导体结构的制备方法中，先提供基底10，基底10包括刻蚀速率不同的第一待刻蚀区和第二待刻蚀区，第一待刻蚀区位于第二待刻蚀区的外侧；然后同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀，将第一待刻蚀区和第二待刻蚀区中刻蚀速率较小的一个刻蚀至目标刻蚀深度；在至少两次刻蚀过程中，在前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料20，以减小第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值，在后一次刻蚀时去除部分牺牲材料20，以继续对具 有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行刻蚀。相较于相关技术中一次刻蚀到目标刻蚀深度，本申请实施例中，第一待刻蚀区和第二待刻蚀区的高度差经回填后可以消除部分，可以降低第一待刻蚀区和第二待刻蚀区的最终高度差值，从而可以减小第一待刻蚀区或者第二待刻蚀区刻穿的可能性，进而提高半导体结构的成品率。
本申请实施例中，同时对第一待刻蚀区和第二待刻蚀区进行第一次刻蚀之前，制备方法还包括：
首先，在基底10上形成掩膜层30。如图11所示，基底10上可以沉积形成有掩膜层30，掩膜层30覆盖第一待刻蚀区和第二待刻蚀区。掩膜层30的材质可以为氮化硅材质。
其次，在掩膜层30中形成有贯穿掩膜层30的掩膜开口31，掩膜开口31与第一待刻蚀区和第二待刻蚀区相对。掩膜开口31贯穿掩膜层30，以暴露基底10，掩膜开口31与第一待刻蚀区和部分第二待刻蚀区相对。
本申请实施例中，同时对第一待刻蚀区和第二待刻蚀区进行两次刻蚀时，刻蚀基底10位于掩膜开口31内的区域。参照图12，第一次刻蚀后在基底10中形成初始目标开口11，初始目标开口11与掩膜开口31相连通。
参照图13，前一次刻蚀完成后形成与掩膜开口31连通的初始目标开口11，在第一待刻蚀区和第二待刻蚀区回填牺牲材料20时，牺牲材料20填满掩膜开口31和初始目标开口11，且覆盖掩膜层30。
参照图14，在第一待刻蚀区和第二待刻蚀区回填牺牲材料20之后，制备方法还包括：对牺牲材料20进行平坦化处理，平坦化处理后的牺牲材料20的表面与掩膜层30的表面齐平。
示例性的，采用化学机械研磨(Chemical Mechanical Polish，简称CMP)对牺牲材料20的上表面进行平坦化处理，以使牺牲材料20的上表面与掩膜层30的上表面齐平。如此设置，当对牺牲材料20进行刻蚀时，牺牲材料20的刻蚀深度一致性较好，可以减少或者避免牺牲材料20的底面不平或者倾斜。
回填牺牲材料20后，同时对第一待刻蚀区和第二待刻蚀区进行第二次刻蚀时，如图15所示，去除掩膜开口31中的牺牲材料20，并去除第一待刻蚀区内的全部牺牲材料20，第二待刻蚀区内去除部分牺牲材料20，保留有部分牺牲材料20。
继续刻蚀时，第一待刻蚀区和第二待刻蚀区的刻蚀速率不同，第一待刻蚀区的刻蚀深度等于目标刻蚀深度时，第二次刻蚀完成，第一待刻蚀区和第二待刻蚀区形成图16所示的目标开口12。
在一种可能的示例中，上述目标开口12可以为位线接触窗，也就是说，本申请实施例的制备方法可以应用于存储器的位线接触窗的形成过程中，即同时对第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀后形成位线接触窗，第一待刻蚀区为部分有源区，第二待刻蚀区为部分浅沟槽隔离区(Shallow trench isolation，简称STI)。
实施例二
参照图16，本申请实施例中的半导体结构包括基底10，基底10包括第一待刻蚀区和第二待刻蚀区。在一种可能的示例中，第一待刻蚀区如图16中A处所示，第二待刻蚀区如图16中B处所示。第二待刻蚀区围绕第一待刻蚀区且与第一待刻蚀区邻接，从而能够同时刻蚀第一待刻蚀区和第二待刻蚀区。
第一待刻蚀区和第二待刻蚀区的刻蚀速率不同，即第一待刻蚀区的刻蚀速率可以大于或者小于第二待刻蚀区的刻蚀速率。可以理解的是，第一待刻蚀区和第二待刻蚀区内可以为不同的材质，位于第一待刻蚀区的材质和位于第二待刻蚀区的材质的刻蚀速率不同。
继续参照图16，基底10中还形成有目标开口12，目标开口12通过同时对基底10的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀形成，在至少两次刻蚀的过程中，前一次刻蚀完成后在第一待刻蚀区和第二待刻蚀区回填牺牲材料20，并在后一次刻蚀时去除部分牺牲材料20。
在前一次刻蚀完成后，第一待刻蚀区和第二待刻蚀区形成初始目标开口11，牺牲材料20可以通过化学气相沉积或物理气相沉积形成在第一待刻蚀区和第二待刻蚀区，牺牲材料20的刻蚀速率位于第一待刻蚀区的刻蚀速率和第二待刻蚀区的刻蚀速率之间。
在后一次刻蚀时，去除第一待刻蚀区和第二待刻蚀区的牺牲材料20，直至第一待刻蚀区或者第二待刻蚀区中暴露基底10，然后对剩余的牺牲材料20和基底10同时进行刻蚀，形成目标开口12。
在一种可能的示例中，第一待刻蚀区的刻蚀速率小于第二待刻蚀区的 刻蚀速率，同时对基底10的第一待刻蚀区和第二待刻蚀区进行两次刻蚀形成目标开口12，牺牲材料20与第二待刻蚀区的材料相同。
如图16所示，第一待刻蚀区的刻蚀深度等于目标刻蚀深度a，第二待刻蚀区的刻蚀深度h满足如下关系式：
a＜h≤a×k+[a×(1-k)]×m；
其中，k为第一次刻蚀比例，0<k<1，m为第二待刻蚀区的刻蚀速率与第一待刻蚀区的刻蚀速率的比值。
需要说明的是，如图17所示，目标开口12可以为位线接触窗12，第一待刻蚀区可以为部分有源区101，其材质为硅，第二待刻蚀区可以为部分浅沟槽隔离区102，其材质可以为氧化硅，有源区101和浅沟槽隔离区102构成基底10。图16可以为图17中I-I方向的剖面图。形成位线接触窗口12之后，可在位线接触窗口内12形成位线接触结构，位线接触结构可用于连接位线(Bit Line，简称BL)。
需要说明的是，基底10上还可以形成有掩膜层30，掩膜层30形成有与位线接触窗相对应的掩膜开口31，掩膜层30的材质可以为氮化硅。
回填牺牲材料20时，牺牲材料20填满掩膜开口31和初始目标开口11，且覆盖掩膜层30，回填牺牲材料20后，可以对牺牲材料20进行平坦化处理，以使牺牲材料20与掩膜层30平齐，便于后续刻蚀。
本申请实施例提供的半导体结构包括基底10，基底10中的目标开口12通过同时对基底10的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀形成，由于第一待刻蚀区和第二待刻蚀区的刻蚀速率不同，前一次刻蚀完成后，第一待刻蚀区的刻蚀深度和第二待刻蚀区的刻蚀深度不同，通过在第一待刻蚀区和第二待刻蚀区回填牺牲材料20，以减小第一待刻蚀区和第二待刻蚀区的刻蚀深度的差值，在后一次刻蚀时去除部分牺牲材料20，以继续对具有不同刻蚀速率的第一待刻蚀区和第二待刻蚀区进行刻蚀。相较于相关技术中一次刻蚀到目标刻蚀深度，本申请实施例中，第一待刻蚀区和第二待刻蚀区的高度差经回填后可以消除部分，可以降低第一待刻蚀区和第二待刻蚀区的最终高度差值，从而可以减小第一待刻蚀区或者第二待刻蚀区刻穿的可能性，进而提高半导体结构的成品率。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相 互参见即可。
本领域技术人员应理解的是，在本申请的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的系统或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本申请的限制。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种半导体结构的制备方法，其特征在于，包括：
    提供基底，所述基底包括第一待刻蚀区和位于所述第一待刻蚀区外侧的第二待刻蚀区，所述第一待刻蚀区的刻蚀速率与所述第二待刻蚀区的刻蚀速率不同；
    同时对所述第一待刻蚀区和所述第二待刻蚀区进行至少两次刻蚀，直至所述第一待刻蚀区和所述第二待刻蚀区中刻蚀速率较小的一个的刻蚀深度等于目标刻蚀深度；在所述至少两次刻蚀的过程中，在前一次刻蚀完成后在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分所述牺牲材料。
  2. 根据权利要求1所述的制备方法，其特征在于，所述牺牲材料的刻蚀速率满足以下关系式：
    min(s 1，s 2)＜v≤max(s 1，s 2)；
    其中，s 1为所述第一待刻蚀区的刻蚀速率，s 2为所述第二待刻蚀区的刻蚀速率，v为所述牺牲材料的刻蚀速率。
  3. 根据权利要求1所述的制备方法，其特征在于，所述第一待刻蚀区的刻蚀速率小于所述第二待刻蚀区的刻蚀速率，所述在后一次刻蚀时去除部分所述牺牲材料的步骤包括：
    在后一次刻蚀时去除位于所述第一待刻蚀区的所述牺牲材料和位于所述第二待刻蚀区的部分所述牺牲材料。
  4. 根据权利要求3所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行两次刻蚀后，所述第一待刻蚀区的刻蚀深度等于所述目标刻蚀深度。
  5. 根据权利要求4所述的制备方法，其特征在于，后一次刻蚀时去除部分所述牺牲材料的步骤包括：
    同时刻蚀位于所述第一待刻蚀区和所述第二待刻蚀区的所述牺牲材料，直至去除所述第一待刻蚀区内的所述牺牲材料；
    同时刻蚀位于所述第一待刻蚀区的所述基底和位于所述第二待刻蚀区的所述牺牲材料，或者，同时刻蚀位于所述第一待刻蚀区的所述基底以及位于所述第二待刻蚀区的所述牺牲材料和所述基底，直至所述第一待刻蚀 区的刻蚀深度等于所述目标刻蚀深度。
  6. 根据权利要求4所述的制备方法，其特征在于，第一次刻蚀后所述第一待刻蚀区的刻蚀深度大于或者等于所述目标刻蚀深度的1/2，且小于或者等于所述目标刻蚀深度的3/4。
  7. 根据权利要求4所述的制备方法，其特征在于，所述牺牲材料与所述第二待刻蚀区的材料相同。
  8. 根据权利要求7所述的制备方法，其特征在于，当所述第一待刻蚀区的刻蚀深度等于所述目标刻蚀深度时，所述第二待刻蚀区的刻蚀深度h满足如下关系式：
    h＝a×k+[a×(1-k)]×m；
    其中，a为所述目标刻蚀深度，k为第一次刻蚀比例，0<k<1，m为所述第二待刻蚀区的刻蚀速率与所述第一待刻蚀区的刻蚀速率的比值。
  9. 根据权利要求1所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行第一次刻蚀的步骤之前，所述制备方法还包括：
    在所述基底上形成掩膜层；
    在所述掩膜层中形成有贯穿所述掩膜层的掩膜开口，所述掩膜开口与所述第一待刻蚀区和所述第二待刻蚀区相对。
  10. 根据权利要求2所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行第一次刻蚀的步骤之前，所述制备方法还包括：
    在所述基底上形成掩膜层；
    在所述掩膜层中形成有贯穿所述掩膜层的掩膜开口，所述掩膜开口与所述第一待刻蚀区和所述第二待刻蚀区相对。
  11. 根据权利要求3所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行第一次刻蚀的步骤之前，所述制备方法还包括：
    在所述基底上形成掩膜层；
    在所述掩膜层中形成有贯穿所述掩膜层的掩膜开口，所述掩膜开口与所述第一待刻蚀区和所述第二待刻蚀区相对。
  12. 根据权利要求9所述的制备方法，其特征在于，前一次刻蚀完成 后形成与所述掩膜开口连通的初始目标开口，在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料时，所述牺牲材料填满所述掩膜开口和所述初始目标开口，且覆盖所述掩膜层。
  13. 根据权利要求12所述的制备方法，其特征在于，在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料之后，还包括：
    对所述牺牲材料进行平坦化处理，平坦化处理后的所述牺牲材料的表面与所述掩膜层的表面齐平。
  14. 根据权利要求1所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行至少两次刻蚀后形成位线接触窗，所述第一待刻蚀区为部分有源区，所述第二待刻蚀区为部分浅沟槽隔离区。
  15. 根据权利要求2所述的制备方法，其特征在于，同时对所述第一待刻蚀区和所述第二待刻蚀区进行至少两次刻蚀后形成位线接触窗，所述第一待刻蚀区为部分有源区，所述第二待刻蚀区为部分浅沟槽隔离区。
  16. 根据权利要求1所述的制备方法，其特征在于，采用化学气相沉积或物理气相沉积形成所述牺牲材料。
  17. 一种半导体结构，其特征在于，包括：基底，所述基底中形成有目标开口，所述目标开口通过同时对所述基底的第一待刻蚀区和第二待刻蚀区进行至少两次刻蚀形成，所述第一待刻蚀区的刻蚀速率与所述第二待刻蚀区的刻蚀速率不同；且在所述至少两次刻蚀的过程中，在前一次刻蚀完成后在所述第一待刻蚀区和所述第二待刻蚀区回填牺牲材料，并在后一次刻蚀时去除部分所述牺牲材料。
  18. 根据权利要求17所述的半导体结构，其特征在于，所述目标开口通过同时对所述第一待刻蚀区和所述第二待刻蚀区进行两次刻蚀形成，且所述第一待刻蚀区的刻蚀速率小于所述第二待刻蚀区的刻蚀速率；
    所述第一待刻蚀区的刻蚀深度等于目标刻蚀深度a，所述第二待刻蚀区的刻蚀深度h满足如下关系式：
    a＜h≤a×k+[a×(1-k)]×m；
    其中，k为第一次刻蚀比例，0<k<1，m为所述第二待刻蚀区的刻蚀速率与所述第一待刻蚀区的刻蚀速率的比值。
  19. 根据权利要求17所述的半导体结构，其特征在于，所述目标开口为位线接触窗，所述第一待刻蚀区为部分有源区，所述第二待刻蚀区为部 分浅沟槽隔离区。
  20. 根据权利要求19所述的半导体结构，其特征在于，所述基底上还形成有掩膜层，所述掩膜层形成有与所述位线接触窗相对应的掩膜开口；
    所述浅沟槽隔离区的材质为氧化硅，所述有源区的材质为硅，所述掩膜层的材质为氮化硅。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262127B2 (en) * 2005-01-21 2007-08-28 Sony Corporation Method for Cu metallization of highly reliable dual damascene structures
CN101197308A (zh) * 2006-12-04 2008-06-11 中芯国际集成电路制造(上海)有限公司 半导体器件中金属布线结构的制作方法
CN108807282A (zh) * 2017-04-28 2018-11-13 长鑫存储技术有限公司 存储器的形成方法
CN112018034A (zh) * 2019-05-31 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112864156A (zh) * 2021-01-04 2021-05-28 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW434838B (en) * 1999-10-11 2001-05-16 Mosel Vitelic Inc Manufacturing process of trench capacitor with bumps
DE102005030588B4 (de) * 2005-06-30 2008-10-16 Advanced Micro Devices, Inc., Sunnyvale Technik zum Reduzieren des Ätzschadens während der Herstellung von Kontaktdurchführungen und Gräben in Zwischenschichtdielektrika
US8313663B2 (en) * 2008-09-24 2012-11-20 Tel Epion Inc. Surface profile adjustment using gas cluster ion beam processing
CN110416151A (zh) * 2019-06-06 2019-11-05 德淮半导体有限公司 半导体器件及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262127B2 (en) * 2005-01-21 2007-08-28 Sony Corporation Method for Cu metallization of highly reliable dual damascene structures
CN101197308A (zh) * 2006-12-04 2008-06-11 中芯国际集成电路制造(上海)有限公司 半导体器件中金属布线结构的制作方法
CN108807282A (zh) * 2017-04-28 2018-11-13 长鑫存储技术有限公司 存储器的形成方法
CN112018034A (zh) * 2019-05-31 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112864156A (zh) * 2021-01-04 2021-05-28 长鑫存储技术有限公司 半导体结构及其制备方法

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