WO2022141241A1 - 薄膜晶体管及阵列基板 - Google Patents

薄膜晶体管及阵列基板 Download PDF

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Publication number
WO2022141241A1
WO2022141241A1 PCT/CN2020/141591 CN2020141591W WO2022141241A1 WO 2022141241 A1 WO2022141241 A1 WO 2022141241A1 CN 2020141591 W CN2020141591 W CN 2020141591W WO 2022141241 A1 WO2022141241 A1 WO 2022141241A1
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layer
metal
thin film
film transistor
ions
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PCT/CN2020/141591
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English (en)
French (fr)
Inventor
胡小波
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Tcl华星光电技术有限公司
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Priority to US17/266,655 priority Critical patent/US20240047548A1/en
Publication of WO2022141241A1 publication Critical patent/WO2022141241A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • the present application relates to the technical field of display panels, and in particular, to a thin film transistor and an array substrate.
  • the molybdenum oxide film layer has a low reflectivity, with a minimum of 5%, which is much smaller than that of the copper film. Therefore, in the prior art, a low-reflection molybdenum oxide film layer is generally designed on the metal wire to reduce the product reflectivity. Because the molybdenum oxide film layer It is relatively loose and has poor adhesion with dielectric layers such as silicon oxide, silicon nitride and silicon oxynitride, especially after high temperature process, silicon oxide, silicon nitride and silicon oxynitride above the molybdenum oxide film layer Such dielectric layers are prone to bulge, which in turn causes the film layer to fall off and affects the yield of the product.
  • dielectric layers such as silicon oxide, silicon nitride and silicon oxynitride
  • the present application provides a thin film transistor and an array substrate, which are used to solve the problem of poor adhesion between the thin film transistor in the prior art due to the poor adhesion between the molybdenum oxide film layer and the dielectric layers such as silicon oxide, silicon nitride and silicon oxynitride.
  • the present application provides a thin film transistor with a substrate, the thin film transistor includes: a gate, the gate is disposed on one side of the substrate; a gate insulating layer, the gate insulating layer Covering the gate and the substrate; an active layer, the active layer is arranged on the side of the gate insulating layer away from the gate; a source and a drain, the source and the drain are arranged on the side of the active layer away from the gate insulating layer; a passivation layer covering the active layer, the source and the drain; wherein the gate, the At least one of the source electrode and the drain electrode is a composite film layer, and the composite film layer includes a first metal layer, a second metal layer, a low inverse function layer and an alloy layer which are stacked in sequence.
  • the alloy layer is formed by implanting metal ions into the low inverse function layer.
  • the implantation depth of the metal ions is smaller than the thickness of the low inverse functional layer.
  • the first metal layer and the second metal layer are stacks composed of at least one or more of molybdenum, copper, aluminum, and silver;
  • the low inverse functional layer is a metal oxide layer
  • the alloy layer is a metal oxide layer implanted with metal ions.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a copper layer
  • the low inverse function layer is a molybdenum oxide layer
  • the alloy layer is an implanted layer Molybdenum oxide layer with metal ions.
  • the relative atomic mass ratio of the metal ions to the molybdenum atoms in the alloy layer ranges from 0.005 to 0.5.
  • the metal ions are at least one of tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions.
  • materials of the gate insulating layer and the passivation layer include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the present application also provides a thin film transistor including a gate electrode, a source electrode, and a drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode is a composite film layer, and the
  • the composite film layer includes a metal layer, a low inverse function layer and an alloy layer which are stacked in sequence.
  • the metal layer includes a first metal layer and a second metal layer; the first metal layer is formed on a base substrate; the second metal layer is disposed on between the first metal layer and the low inverse function layer.
  • the alloy layer is formed by implanting metal ions into the low inverse function layer.
  • the implantation depth of the metal ions is smaller than the thickness of the low inverse functional layer.
  • the implantation depth of the metal ions is equal to the thickness of the low inverse function layer.
  • the metal ions are at least one of tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions.
  • the metal layer is a stack composed of at least one or more of molybdenum, copper, aluminum, and silver; the low-reverse functional layer is a metal oxide layer; The alloy layer is a metal oxide layer implanted with metal ions.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a copper layer
  • the low inverse function layer is a molybdenum oxide layer
  • the alloy layer is an implanted layer Molybdenum oxide layer with metal ions.
  • the relative atomic mass ratio of the metal ions to the molybdenum atoms in the alloy layer ranges from 0.005 to 0.5.
  • the present application further provides an array substrate, where the array substrate includes the thin film transistor described in any one of the above embodiments.
  • the gate electrode, the source electrode, and the drain electrode is configured as a composite film layer, and the composite film layer includes a first metal layer, a second metal layer and a low-reverse function layer;
  • the first metal layer is formed on a base substrate, and together with the second metal layer serves as a main electrode layer, the setting of the first metal layer
  • the adhesion between the second electrode layer and the base substrate can be improved;
  • the low inverse function layer is located on the side of the first metal layer away from the base substrate, and the low inverse function layer is located on the side of the first metal layer away from the base substrate.
  • the layer is a metal oxide layer, which can greatly reduce the reflectivity of the second metal layer.
  • the composite film layer further comprises the alloy layer on the side of the low inverse function layer away from the first metal layer, the hardness of the alloy layer is higher than that of the metal oxide layer, covering The stability of the metal oxide layer can be enhanced on the surface of the metal oxide layer. Since the alloy layer is implanted with metal ions into the metal oxide layer, the density of the alloy layer is higher, and the density of the alloy layer is higher than that of oxidation.
  • dielectric layers such as silicon, silicon nitride and silicon oxynitride are stronger than that of metal oxide layers, and it is not easy to appear bulging in a high temperature environment, thereby preventing the oxidation of the surface of the composite film layer
  • Dielectric layers such as silicon, silicon nitride, and silicon oxynitride are peeled off to improve product yield.
  • FIG. 1 is a schematic structural diagram of one embodiment of a thin film transistor of the present application
  • FIG. 2 is a schematic structural diagram of an embodiment of the composite film layer of the thin film transistor of the present application
  • FIG. 3 is a schematic structural diagram of another embodiment of the composite film layer of the thin film transistor of the present application.
  • 4A to 4C are schematic diagrams of the preparation structure of the composite film layer of the thin film transistor of the present application in one of the embodiments;
  • FIG. 5 is a schematic diagram of the preparation process of the composite film layer of the thin film transistor of the present application in one of the embodiments;
  • FIG. 6 is a schematic structural diagram of one embodiment of the array substrate of the present application.
  • FIG. 7 is a schematic structural diagram of one embodiment of the display panel of the present application.
  • the present application provides a thin film transistor, which includes a gate electrode, a source electrode, and a drain electrode, at least one of the gate electrode, the source electrode, and the drain electrode is a composite film layer, and the composite film layer is The outermost layer of the film layer is an alloy layer.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application
  • FIG. 2 is a structural schematic diagram of a composite film layer provided by an embodiment of the present application.
  • the thin film transistor 10 includes: a substrate 11; a gate electrode 12 disposed on the substrate 11; a gate insulating layer 13 covering the gate electrode 12 and the substrate 11; The active layer 14 on the gate insulating layer; the source electrode 15 and the drain electrode 16 disposed on the active layer 14 and connected to the active layer 14; covering the active layer 14, the The source electrode 15 and the passivation layer 17 of the drain electrode 16 .
  • a pixel electrode layer 202 is further disposed on the passivation layer 17 , and the pixel electrode layer 202 is connected to the source electrode 15 or the drain electrode 16 through a via hole.
  • At least one of the gate electrode 12 , the source electrode 15 and the drain electrode 16 is a composite film layer 100 .
  • the number of the composite film layer 100 in the gate electrode 12 , the source electrode 15 and the drain electrode 16 is not limited. All of the source electrode 15 and the drain electrode 16 are the composite film layer 100 .
  • the outermost layer of the composite film layer 100 is an alloy layer.
  • the composite film layer 100 includes a metal layer 120 disposed on a base substrate 110 , a low-reverse functional layer 130 covering the metal layer 120 , and a low-reverse functional layer 130 located away from the metal. Alloy layer 140 on one side of layer 120 .
  • the alloy layer 140 is located at the outermost layer of the composite film layer 100 .
  • the metal layer 120 includes a stack composed of at least one or more of molybdenum, copper, aluminum and silver;
  • the low inverse function layer 130 is a metal oxide layer;
  • the alloy layer 140 is a metal ion 141
  • the metal oxide layer is implanted.
  • the metal ions 141 are at least one of tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions.
  • the alloy layer 140 may be formed by implanting a variety of different metal ions 141 into the metal oxide layer at the same time.
  • the alloy layer 140 is an alloy composed of metal oxide and tantalum ions.
  • the alloy layer 140 is an alloy material composed of metal oxides and nickel ions
  • the alloy layer 140 is an alloy material composed of metal oxides, tantalum ions, and niobium ions.
  • the outermost layer of the composite film layer 100 is an alloy layer
  • the metal layer 120 includes a first metal layer 121 and a second metal layer 121 .
  • the composite film layer 100 includes a first metal layer 121 disposed on a base substrate 110 , a second metal layer 121 covering the first metal layer 121 , and a metal layer 121 covering the second metal layer 121 .
  • the low inverse function layer 130 and the alloy layer 140 located on the side of the low inverse function layer 130 away from the first metal layer 121 .
  • the alloy layer 140 is located at the outermost layer of the composite film layer 100 .
  • the first metal layer 121 includes a stack of at least one or more of molybdenum, copper, aluminum and silver; the second metal layer 121 includes at least one of molybdenum, copper, aluminum and silver
  • the low inverse function layer 130 is a metal oxide layer; the alloy layer 140 is a metal ion 141 implanted into the metal oxide layer.
  • the metal ions 141 are at least one of tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions.
  • the alloy layer 140 may be formed by implanting a variety of different metal ions 141 into the metal oxide layer at the same time.
  • the alloy layer 140 is an alloy composed of metal oxide and tantalum ions.
  • the alloy layer 140 is an alloy material composed of metal oxides and nickel ions, and the alloy layer 140 is an alloy material composed of metal oxides, tantalum ions, and niobium ions.
  • the first metal layer 121 is a molybdenum layer
  • the second metal layer 121 is a copper layer
  • the low inverse function layer 130 is a molybdenum oxide layer
  • the alloy layer 140 is implanted with tantalum ion the molybdenum oxide layer.
  • the first metal layer 121 and the second metal layer 121 both include a stack of at least one or more of molybdenum, copper, aluminum, and silver.
  • the first metal layer 121 is in contact with the base substrate 110 , so preferably, the adhesion between the material of the first metal layer 121 and the base substrate 110 is higher than that of the second metal layer 121 The adhesion of the material to the base substrate 110 .
  • the implantation depth of the metal ions 141 is less than or equal to the thickness of the metal oxide layer.
  • the film structure of the composite film layer 100 includes a first layer disposed on a base substrate 110 .
  • the low inverse functional layer 130 is completely replaced by the alloy layer 140 .
  • the implantation depth of the metal ions 141 is smaller than the thickness of the metal oxide layer, that is, the low inverse function layer 130 and the alloy layer 140 coexist.
  • the relative atomic mass ratio of the metal ions 141 to the molybdenum atoms in the alloy layer 140 ranges from 0.005 to 0.5.
  • the relative atomic mass ratio of the metal ions 141 to molybdenum atoms is in the range of 0.005 between 0.5, specifically means that the sum of the relative atomic mass ratios of various metal ions 141 to molybdenum atoms is between 0.005 and 0.5.
  • the alloy layer 140 is an alloy material composed of molybdenum oxide, tantalum ions, and niobium ions, and the relative atomic mass ratio of the metal ions 141 to molybdenum atoms refers to the relative atomic mass ratios of tantalum ions, niobium ions and molybdenum atoms, respectively.
  • the alloy layer 140 is an alloy material composed of molybdenum oxide and tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions, then the relative atomic mass ratio of the metal ions 141 to molybdenum atoms It refers to the sum of the relative atomic mass ratios of tantalum ions, niobium ions, titanium ions, nickel ions, and tungsten ions to molybdenum atoms, respectively.
  • the relative atomic mass ratio of the metal ions 141 to the molybdenum atoms in the alloy layer 140 is not limited by the type of the metal ions 141 .
  • the base substrate 110 is the substrate 10; when the source electrode 15 or the drain electrode 16 is the composite film layer At 100, the base substrate 110 is the active layer 14 .
  • the base substrate 110 in the composite film layer 100 is substantially the first metal in the gate electrode 12 , the source electrode 15 and the drain electrode 16
  • the layer 121 is far from the film layer on the side of the second metal layer 121 , that is, the base substrate 110 is not an essential structure of the composite film layer 100 .
  • the thin film transistor 10 in this application may be a bottom gate structure, such as a back channel etch structure and an etch stop structure; the thin film transistor 10 may also be a top gate structure, and the thin film
  • the structure of the transistor is not limited to FIG. 1 , as long as at least one of the gate electrode 12 , the source electrode 15 , and the drain electrode 16 in the present application is a composite film layer 100 .
  • film layer materials of the thin film transistor 10 in this application can be made of conventional materials in the art, for example: the substrate 11 is a polyimide substrate or a glass substrate; the gate insulating layer 13 and the passivation layer
  • the material of 17 includes at least one of silicon oxide, silicon nitride and silicon oxynitride; the active layer 14 is made of amorphous silicon or polysilicon material; the pixel electrode layer is made of indium tin oxide alloy material. Specific materials can be selected according to actual conditions, which are not limited in this application.
  • FIGS. 4A to 4C are schematic diagrams of a preparation structure of the composite film layer provided by the embodiment of the application
  • FIG. 5 is a schematic diagram of a preparation process of the composite film layer provided by the embodiment of the application.
  • the present application also provides a method for preparing the composite film layer 100, comprising the following steps:
  • step S1 depositing a metal material on a base substrate 110 to form the metal layer 120 ;
  • step S2 depositing a metal oxide material on the metal layer 120 to form a low inverse function layer 130 ;
  • step S3 implanting metal ions 141 on the low inverse function layer 130 to form the alloy layer 140 .
  • the composite film layer 100 can be the gate electrode, source electrode and drain electrode of any type of thin film transistor in the art; the thin film transistor can be applied to a TFT- LCD, OLED, Display devices such as mini-LED and micro-LED are not limited.
  • At least one of the gate electrode 12 , the source electrode 15 , and the drain electrode 16 is a composite film layer 100 , and the composite film layer 100 includes a first metal layer 121, a second metal layer 121 and a low inverse function layer 130; the first metal layer 121 is formed on a base substrate 110, and together with the second metal layer 121 serves as a main electrode layer, the first metal layer 121
  • the arrangement of the layer 121 can improve the adhesion between the second metal layer 121 and the base substrate 110 ;
  • One side, and the low inverse function layer 130 is a metal oxide layer, which can greatly reduce the reflectivity of the second metal layer 121 .
  • the composite film layer 100 further includes the alloy layer 140 located on the side of the low inverse function layer 130 away from the first metal layer 121 , and the hardness of the alloy layer 140 is relatively higher than that of the metal oxide.
  • the metal oxide layer is higher, and covering the surface of the metal oxide layer can enhance the stability of the metal oxide layer. Since the alloy layer 140 injects metal ions 141 into the metal oxide layer, the alloy layer The density of 140 is higher, and the adhesion between dielectric layers such as silicon oxide, silicon nitride and silicon oxynitride is stronger than that of metal oxide layers.
  • the problem of peeling off of dielectric layers such as silicon oxide, silicon nitride, and silicon oxynitride on the surface of the composite film layer 100 improves product yield.
  • the present application also provides an array substrate, which adopts a plurality of thin film transistors 10 as described above, and is used in a pixel unit driving circuit.
  • the array substrate 200 includes a glass substrate 201, a thin film transistor layer 10 formed on the glass substrate 201, a pixel electrode layer 202 disposed on the thin film transistor, and so on.
  • the thin film transistor layer 10 adopts the structure of the thin film transistor 10 described above.
  • the present application further provides a display panel 300, the display panel 300 includes the array substrate 200, and the array substrate is a TFT array substrate, which uses the above-mentioned thin film transistors.
  • the display panel 300 includes the array substrate 200 , a liquid crystal layer 301 , and a color filter substrate 302 .
  • the thin film transistor 10 provided by the embodiments of the present application has been described in detail above, and the principles and implementations of the present application are described with specific examples herein.
  • the descriptions of the above embodiments are only used to help understand the technology of the present application. scheme and its core idea; those of ordinary skill in the art should understand that: it is still possible to modify the technical solutions recorded in the foregoing embodiments, or to perform equivalent replacements for some of the technical features; and these modifications or replacements do not make The essence of the corresponding technical solutions deviates from the scope of the technical solutions of the embodiments of the present application.

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Abstract

本申请公开了一种薄膜晶体管及其制备方法、阵列基板，所述薄膜晶体管包括栅极、源极、以及漏极，其中，所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层包括依次层叠设置的金属层、低反功能层以及合金层。所述合金层覆盖于所述低反功能层表面可以增强所述低反功能层的稳定性，由于所述合金层是与氧化硅、氮化硅以及氮氧化硅等介电层之间的附着力相较于低反功能层更强，在高温环境下，也不易出现鼓包现象，进而可以防止所述复合膜层表面的氧化硅、氮化硅以及氮氧化硅等介电层的脱落问题，提高产品良率。

Description

薄膜晶体管及阵列基板 技术领域
本申请涉及显示面板的技术领域，特别是涉及一种薄膜晶体管及阵列基板。
 背景技术
随着显示技术的蓬勃发展，大尺寸显示屏幕成为目前最具吸引力的开发及市场宠儿。大尺寸TFT产品都采用铜制程，尤其是目前热点的8K产品，其铜制程的数量非常多，占整个像素区的面积可达到20%；铜膜在可见光的反射率大于70%，铜膜在上方没有遮挡，可见光到达铜膜表面会引起反射，从而导致产品的反射率偏高，影响视觉效果，无法满足高阶产品需求。
氧化钼膜层具有较低的反射率，最低达到5%，远小于铜膜，故现有技术一般在金属线上方设计低反的氧化钼膜层，来降低产品反射率，由于氧化钼膜层较为疏松，并且与氧化硅、氮化硅以及氮氧化硅等介电层之间的附着力较差，尤其是经过高温制程后，氧化钼膜层上方的氧化硅、氮化硅以及氮氧化硅等介电层易出现鼓包的现象，进而导致膜层脱落，影响产品的良率。
因此，针对现有技术中存在的上述缺陷，急需进行改进。
 技术问题
本申请提供一种薄膜晶体管及阵列基板，用于解决现有技术中薄膜晶体管由于氧化钼膜层与氧化硅、氮化硅以及氮氧化硅等介电层之间的附着力较差，从而引起膜层脱落的问题。
 技术解决方案
为了解决上述问题，本申请提供一种薄膜晶体管，具有一基板，所述薄膜晶体管包括：栅极，所述栅极设置于所述基板的一侧；栅极绝缘层，所述栅极绝缘层覆盖所述栅极与所述基板；有源层，所述有源层设置于所述栅极绝缘层远离所述栅极的一侧；源极与漏极，所述源极与漏极设置于所述有源层远离所述栅极绝缘层的一侧；钝化层，所述钝化层覆盖所述有源层、所述源极以及所述漏极；其中所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层包括依次层叠设置的第一金属层、第二金属层、低反功能层以及合金层。
可选的，在本申请的一些实施例中，所述合金层为金属离子注入所述低反功能层而形成。
可选的，在本申请的一些实施例中，所述金属离子的注入深度小于所述低反功能层的厚度。
可选的，在本申请的一些实施例中，所述第一金属层以及所述第二金属层为钼、铜、铝以及银中的至少一种或多种组成的叠层；
可选的，在本申请的一些实施例中，所述低反功能层为金属氧化物层；
可选的，在本申请的一些实施例中，所述合金层为注入有金属离子的金属氧化物层。
可选的，在本申请的一些实施例中，所述第一金属层为钼层；所述第二金属层为铜层；所述低反功能层为氧化钼层；所述合金层为注入有金属离子的氧化钼层。
可选的，在本申请的一些实施例中，所述合金层中所述金属离子与钼原子的相对原子质量比的范围在0.005至0.5之间。
可选的，在本申请的一些实施例中，所述金属离子为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。
可选的，在本申请的一些实施例中，所述栅极绝缘层以及所述钝化层的材料包括氧化硅、氮化硅以及氮氧化硅中的至少一种。
本申请还提供一种薄膜晶体管，包括栅极、源极、以及漏极，其中所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层包括依次层叠设置的金属层、低反功能层以及合金层。
可选的，在本申请的一些实施例中，所述金属层包括第一金属层以及第二金属层；所述第一金属层形成于一衬底基板上；所述第二金属层设置于所述第一金属层与所述低反功能层之间。
可选的，在本申请的一些实施例中，所述合金层为金属离子注入所述低反功能层而形成。
可选的，在本申请的一些实施例中，所述金属离子的注入深度小于所述低反功能层的厚度。
可选的，在本申请的一些实施例中，所述金属离子的注入深度等于所述低反功能层的厚度。
可选的，在本申请的一些实施例中，所述金属离子为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。
可选的，在本申请的一些实施例中，所述金属层为钼、铜、铝以及银中的至少一种或多种组成的叠层；所述低反功能层为金属氧化物层；所述合金层为注入有金属离子的金属氧化物层。
可选的，在本申请的一些实施例中，所述第一金属层为钼层；所述第二金属层为铜层；所述低反功能层为氧化钼层；所述合金层为注入有金属离子的氧化钼层。
可选的，在本申请的一些实施例中，所述合金层中所述金属离子与钼原子的相对原子质量比的范围在0.005至0.5之间。
相应的，本申请还提供一种阵列基板，所述阵列基板包括上述任一实施例中所述的薄膜晶体管。
 有益效果
相较于现有技术，本申请薄膜晶体管及阵列基板通过将所述栅极、所述源极、以及所述漏极中的至少其中之一设置为一复合膜层，所述复合膜层包括第一金属层、第二金属层以及低反功能层；所述第一金属层形成于一衬底基板上，与所述第二金属层共同作为主要电极层，所述第一金属层的设置可以提高所述第二电极层与所述衬底基板之间的附着力；所述低反功能层位于所述第一金属层的远离所述衬底基板的一侧，且所述低反功能层为一金属氧化物层，可以大幅度降低所述第二金属层的反射率。
进一步地，所述复合膜层还包括位于所述低反功能层的远离所述第一金属层一侧的所述合金层，所述合金层的硬度相对所述金属氧化物层更高，覆盖于所述金属氧化物层表面可以增强所述金属氧化物层的稳定性，由于所述合金层是将金属离子的注入所述金属氧化物层，因此所述合金层的密度更高，与氧化硅、氮化硅以及氮氧化硅等介电层之间的附着力相较于金属氧化物层更强，在高温环境下，也不易出现鼓包现象，进而可以防止所述复合膜层表面的氧化硅、氮化硅以及氮氧化硅等介电层的脱落问题，提高产品良率。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请薄膜晶体管的其中一实施例的结构示意图；
图2为本申请薄膜晶体管的复合膜层的一实施例例的结构示意图；
图3为本申请薄膜晶体管的复合膜层的另一实施例例的结构示意图；
图4A至4C为本申请薄膜晶体管的复合膜层在其中一实施例中的制备结构示意图；
图5为本申请薄膜晶体管的复合膜层的在其中一实施例中的制备流程示意图；
图6为本申请阵列基板的其中一实施例的结构示意图；
图7为本申请显示面板的其中一实施例的结构示意图。
上述附图中的主要附图标记说明如下：
10、薄膜晶体管；        11、基板；           12、栅极；
13、栅极绝缘层；        14、有源层；         15、源极；
16、漏极；              17、钝化层；         100、复合膜层；
110、衬底基板；         120、金属层；        121、第一金属层；
122、第二金属层；       130、低反功能层；    140、合金层；
141、金属离子；         200、阵列基板；      201、玻璃基板；
202、像素电极层；       300、显示面板；      301、液晶层；
302、彩膜基板。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供一种薄膜晶体管，其包括栅极、源极、以及漏极，所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层最外层为一合金层。
具体实施例请结合参阅图1至图2，图1为本申请实施例提供的薄膜晶体管的一种结构示意图；图2为本申请实施例提供的复合膜层的一种结构示意图。
在本实施例中，所述薄膜晶体管10包括：一基板11；设置于所述基板11上的栅极12；覆盖所述栅极12与所述基板11的栅极绝缘层13；设置于所述栅极绝缘层上的有源层14；设置于所述有源层14上，并与所述有源层14连接的源极15以及漏极16；覆盖所述有源层14、所述源极15以及所述漏极16的钝化层17。在本申请所述的阵列基板中，所述钝化层17上还设置有像素电极层202，所述像素电极层202通过一过孔与所述源极15或所述漏极16连接。
所述栅极12、所述源极15、以及所述漏极16中的至少其中之一为一复合膜层100。本领域技术人员可以理解的是，所述栅极12、所述源极15、以及所述漏极16中为所述复合膜层100的个数不作限定，优选地，所述栅极12、所述源极15、以及所述漏极16全部为所述复合膜层100。
如图2所示，在本申请中，所述复合膜层100最外层为一合金层。具体地讲，所述复合膜层100包括设置于一衬底基板110上的金属层120、覆盖所述金属层120的低反功能层130，以及位于所述低反功能层130远离所述金属层120一侧的合金层140。所述合金层140位于所述复合膜层100的最外层。其中，所述金属层120包括钼、铜、铝以及银中的至少一种或多种组成的叠层；所述低反功能层130为金属氧化物层；所述合金层140为金属离子141注入所述金属氧化物层。其中，所述金属离子141为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。本领域技术人员可以理解的是，可以是多种不同的金属离子141同时注入所述金属氧化物层形成所述合金层140，例如：所述合金层140为金属氧化物与钽离子组成的合金材料、所述合金层140为金属氧化物与镍离子组成的合金材料、所述合金层140为金属氧化物与钽离子、铌离子共同组成的合金材料等。
如图3所示，在本申请一实施例中，所述复合膜层100最外层为一合金层，所述金属层120包括第一金属层121以及第二金属层121。具体地讲，所述复合膜层100包括设置于一衬底基板110上的第一金属层121、覆盖所述第一金属层121的第二金属层121、覆盖所述第二金属层121的低反功能层130，以及位于所述低反功能层130远离所述第一金属层121一侧的合金层140。所述合金层140位于所述复合膜层100的最外层。其中，所述第一金属层121包括钼、铜、铝以及银中的至少一种或多种组成的叠层；所述第二金属层121包括钼、铜、铝以及银中的至少一种或多种组成的叠层；所述低反功能层130为金属氧化物层；所述合金层140为金属离子141注入所述金属氧化物层。其中，所述金属离子141为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。本领域技术人员可以理解的是，可以是多种不同的金属离子141同时注入所述金属氧化物层形成所述合金层140，例如：所述合金层140为金属氧化物与钽离子组成的合金材料、所述合金层140为金属氧化物与镍离子组成的合金材料、所述合金层140为金属氧化物与钽离子、铌离子共同组成的合金材料等。优选地，所述第一金属层121为钼层，所述第二金属层121为铜层，所述所述低反功能层130为氧化钼层，所述所述合金层140为注入有钽离子所述氧化钼层。
本申请中所述第一金属层121以及所述第二金属层121均包括钼、铜、铝以及银中的至少一种或多种组成的叠层。其中所述第一金属层121与所述衬底基板110接触，故优选地，所述第一金属层121的材料与所述衬底基板110的附着力高于所述第二金属层121的材料与所述衬底基板110的附着力。
在本申请的一些实施例中，所述金属离子141的注入深度小于等于所述金属氧化物层的厚度。本领域技术人员可以理解的是，当所述金属离子141的注入深度等于所述金属氧化物层的厚度时，所述复合膜层100的膜层结构包括设置于一衬底基板110上的第一金属层121、覆盖所述第一金属层121的第二金属层121、覆盖所述第二金属层的合金层140。此时所述低反功能层130全部被所述合金层140替代。优选地，所述金属离子141的注入深度小于所述金属氧化物层的厚度，即所述低反功能层130与所述合金层140同时存在。
在本申请中，所述合金层140中所述金属离子141与钼原子的相对原子质量比的范围在0.005至0.5之间。本领域技术人员可以理解的是，当多种不同的金属离子141同时注入所述金属氧化物层形成所述合金层140时，所述金属离子141与钼原子的相对原子质量比的范围在0.005至0.5之间，具体指的是多种不同的金属离子141分别与钼原子的相对原子质量比之和在0.005至0.5之间。例如：所述合金层140为氧化钼与钽离子、铌离子共同组成的合金材料，则所述金属离子141与钼原子的相对原子质量比指的是钽离子、铌离子分别与钼原子的相对原子质量比之和；所述合金层140为氧化钼与钽离子、铌离子、钛离子、镍离子、以及钨离子共同组成的合金材料，则所述金属离子141与钼原子的相对原子质量比指的是钽离子、铌离子、钛离子、镍离子、以及钨离子分别与钼原子的相对原子质量比之和。所述合金层140中所述金属离子141与钼原子的相对原子质量比并不受所述金属离子141的种类的限制。
在本申请中，当所述栅极12为所述复合膜层100时，所述衬底基板110为所述基板10；当所述源极15或所述漏极16为所述复合膜层100时，所述衬底基板110为所述有源层14。本领域技术人员可以理解的是，所述复合膜层100中的所述衬底基板110实质上为所述栅极12、所述源极15以及所述漏极16中的所述第一金属层121远离所述第二金属层121一侧所接触的膜层，即所述衬底基板110并非所述复合膜层100的必要结构。
需要注意的是，本申请中所述薄膜晶体管10可以是底栅结构，例如：背沟道刻蚀型结构以及刻蚀阻挡型结构；所述薄膜晶体管10还可以是顶栅结构，所述薄膜晶体管的结构并不以图1为限，只要满足本申请中所述栅极12、所述源极15、以及所述漏极16中的至少其中之一为一复合膜层100即可。
本申请中所述薄膜晶体管10的其他膜层材料可以是本领域常规材料构成，例如：所述基板11为聚酰亚胺基板或玻璃基板；所述栅极绝缘层13以及所述钝化层17的材料包括氧化硅、氮化硅以及氮氧化硅中的至少一种；所述有源层14为非晶硅或多晶硅材料制成；所述像素电极层为氧化铟锡合金材料。具体地材料可以根据实际进行选择，本申请不作限定。
请结合参阅图4A至4C以及图5，图4A至4C为本申请实施例提供的复合膜层的一种制备结构示意图；图5为本申请实施例提供的复合膜层的一种制备流程示意图。本申请还提供一种所述复合膜层100的制备方法，包括如下步骤：
如图4A以及图5所示，步骤S1：在一衬底基板110上沉积金属材料，以形成所述金属层120；
如图4B以及图5所示，步骤S2：在所述金属层120上沉积金属氧化物材料，以形成低反功能层130；
如图4C以及图5所示，步骤S3：在所述低反功能层130上注入金属离子141，以形成所述合金层140。
在本申请中，所述复合膜层100可以是本领域任意类型薄膜晶体管中的栅极、源极以及漏极；所述薄膜晶体管可以应用于是TFT - LCD、OLED、 mini-LED、micro-LED等显示装置中，并不做限定。
在本申请所述薄膜晶体管中，所述栅极12、所述源极15、以及所述漏极16中的至少其中之一为一复合膜层100，所述复合膜层100包括第一金属层121、第二金属层121以及低反功能层130；所述第一金属层121形成于一衬底基板110上，与所述第二金属层121共同作为主要电极层，所述第一金属层121的设置可以提高所述第二金属层121与所述衬底基板110之间的附着力；所述低反功能层130位于所述第一金属层121的远离所述衬底基板110的一侧，且所述低反功能层130为一金属氧化物层，可以大幅度降低所述第二金属层121的反射率。
进一步地，所述复合膜层100还包括位于所述低反功能层130的远离所述第一金属层121一侧的所述合金层140，所述合金层140的硬度相对所述金属氧化物层更高，覆盖于所述金属氧化物层表面可以增强所述金属氧化物层的稳定性，由于所述合金层140是将金属离子141的注入所述金属氧化物层，因此所述合金层140的密度更高，与氧化硅、氮化硅以及氮氧化硅等介电层之间的附着力相较于金属氧化物层更强，在高温环境下，也不易出现鼓包现象，进而可以防止所述复合膜层100表面的氧化硅、氮化硅以及氮氧化硅等介电层的脱落问题，提高产品良率。
本申请还提供一种阵列基板，其采用了多个如上所述的薄膜晶体管10，用于像素单元驱动电路中。在如图6所示的实施例中，所述阵列基板200包括一玻璃基板201、形成于所述玻璃基板201上的薄膜晶体管层10，设置于所述薄膜晶体管上的像素电极层202，所述薄膜晶体管层10采用上述薄膜晶体管10的结构。
本申请还提供一种显示面板300，所述显示面板300包括所述阵列基板200，所述阵列基板为TFT阵列基板，其采用了如上所述的薄膜晶体管。在如图7所示的实施例中，所述显示面板300包括所述阵列基板200、液晶层301、以及彩膜基板302。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种薄膜晶体管10进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种薄膜晶体管，具有一基板，其特征在于：所述薄膜晶体管包括：
    栅极，所述栅极设置于所述基板的一侧；
    栅极绝缘层，所述栅极绝缘层覆盖所述栅极与所述基板；
    有源层，所述有源层设置于所述栅极绝缘层远离所述栅极的一侧；
    源极与漏极，所述源极与漏极设置于所述有源层远离所述栅极绝缘层的一侧；
    钝化层，所述钝化层覆盖所述有源层、所述源极以及所述漏极；
    其中，所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层包括依次层叠设置的第一金属层、第二金属层、低反功能层以及合金层。
  2. 如权利要求1所述的薄膜晶体管，其特征在于：所述合金层为金属离子注入所述低反功能层而形成。
  3. 如权利要求2所述的薄膜晶体管，其特征在于：所述金属离子的注入深度小于所述低反功能层的厚度。
  4. 如权利要求1所述的薄膜晶体管，其特征在于：所述第一金属层以及所述第二金属层为钼、铜、铝以及银中的至少一种或多种组成的叠层。
  5. 如权利要求1所述的薄膜晶体管，其特征在于：所述低反功能层为金属氧化物层。
  6. 如权利要求1所述的薄膜晶体管，其特征在于：所述合金层为注入有金属离子的金属氧化物层。
  7. 如权利要求1所述的薄膜晶体管，其特征在于：所述第一金属层为钼层；所述第二金属层为铜层；所述低反功能层为氧化钼层；所述合金层为注入有金属离子的氧化钼层。
  8. 如权利要求7所述的薄膜晶体管，其特征在于，所述合金层中所述金属离子与钼原子的相对原子质量比的范围在0.005至0.5之间。
  9. 如权利要求7所述的薄膜晶体管，其特性在于：所述金属离子为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。
  10. 如权利要求1所述的薄膜晶体管，其特性在于：所述栅极绝缘层以及所述钝化层的材料包括氧化硅、氮化硅以及氮氧化硅中的至少一种。
  11. 一种薄膜晶体管，包括栅极、源极、以及漏极，其特征在于：所述栅极、所述源极、以及所述漏极中的至少其中之一为一复合膜层，所述复合膜层包括依次层叠设置的金属层、低反功能层以及合金层。
  12. 如权利要求11所述的薄膜晶体管，其特征在于：所述金属层包括第一金属层以及第二金属层；
    所述第一金属层形成于一衬底基板上；
    所述第二金属层设置于所述第一金属层与所述低反功能层之间。
  13. 如权利要求11所述的薄膜晶体管，其特征在于：所述合金层为金属离子注入所述低反功能层而形成。
  14. 如权利要求13所述的薄膜晶体管，其特征在于：所述金属离子的注入深度小于所述低反功能层的厚度。
  15. 如权利要求13所述的薄膜晶体管，其特征在于：所述金属离子的注入深度等于所述低反功能层的厚度。
  16. 如权利要求13所述的薄膜晶体管，其特性在于：所述金属离子为钽离子、铌离子、钛离子、镍离子、以及钨离子中的至少一种。
  17. 如权利要求11所述的薄膜晶体管，其特征在于：所述金属层为钼、铜、铝以及银中的至少一种或多种组成的叠层；所述低反功能层为金属氧化物层；所述合金层为注入有金属离子的金属氧化物层。
  18. 如权利要求17所述的薄膜晶体管，其特征在于：所述第一金属层为钼层；所述第二金属层为铜层；所述低反功能层为氧化钼层；所述合金层为注入有金属离子的氧化钼层。
  19. 如权利要求18所述的薄膜晶体管，其特征在于：所述合金层中所述金属离子与钼原子的相对原子质量比的范围在0.005至0.5之间。
  20. 一种阵列基板，其特性在于，所述阵列基板包括如权利要求11所述的薄膜晶体管。
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