WO2022134821A1 - 显示面板、显示装置及制作显示面板的方法 - Google Patents

显示面板、显示装置及制作显示面板的方法 Download PDF

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Publication number
WO2022134821A1
WO2022134821A1 PCT/CN2021/125885 CN2021125885W WO2022134821A1 WO 2022134821 A1 WO2022134821 A1 WO 2022134821A1 CN 2021125885 W CN2021125885 W CN 2021125885W WO 2022134821 A1 WO2022134821 A1 WO 2022134821A1
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WIPO (PCT)
Prior art keywords
signal
area
display panel
dummy
traces
Prior art date
Application number
PCT/CN2021/125885
Other languages
English (en)
French (fr)
Inventor
张元其
文平
张顺
曾扬
王威
王裕
罗昶
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2217903.0A priority Critical patent/GB2611199A/en
Priority to US17/904,968 priority patent/US11893178B2/en
Publication of WO2022134821A1 publication Critical patent/WO2022134821A1/zh
Priority to US18/488,295 priority patent/US20240045541A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/04—Signs, boards or panels, illuminated from behind the insignia
    • G09F13/0404—Signs, boards or panels, illuminated from behind the insignia the light source being enclosed in a box forming the character of the sign
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F19/00—Advertising or display means not otherwise provided for
    • G09F19/22—Advertising or display means on roads, walls or similar surfaces, e.g. illuminated
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/20—Illuminated signs; Luminous advertising with luminescent surfaces or parts
    • G09F13/22—Illuminated signs; Luminous advertising with luminescent surfaces or parts electroluminescent
    • G09F2013/222—Illuminated signs; Luminous advertising with luminescent surfaces or parts electroluminescent with LEDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a display device including the display panel, and a method for manufacturing the display panel.
  • a display device applying touch technology usually includes a touch IC chip (also called a touch controller), which is used to send control signals to the touch electrodes in the display device or receive sensing signals from the touch electrodes to determine the user touch position.
  • a touch IC chip also called a touch controller
  • Embodiments of the present disclosure provide a display panel including: a base substrate including a display area and a non-display area around the display area; a touch panel on the base substrate a control electrode layer, the touch electrode layer is located in the display area; and a plurality of signal wires electrically connected to the touch electrode layer, the plurality of signal wires are distributed in the non-display area and in the first area adjacent to the display area.
  • the display panel further includes a plurality of outer dummy traces in a second area of the non-display area, the second area is located between the first area and an outer boundary of the non-display area, the The plurality of outer dummy traces and the plurality of signal traces are separated from each other.
  • the display panel further includes a first signal shielding line and a second signal shielding line located in the non-display area, and at least a part of the first signal shielding line is located in the second area and all the between the outer boundaries of the non-display area, the second signal shielding line is located between the first signal shielding line and the first area, and the plurality of outer dummy traces include the first signal shielding line At least one first dummy trace between the wire and the second signal shield wire.
  • the first signal shielding wire includes a ground wire
  • the second signal shielding wire is configured to receive a fixed potential or a square wave signal.
  • the touch electrode layer includes a plurality of first touch electrodes arranged in parallel and a plurality of second touch electrodes arranged in parallel, the plurality of first touch electrodes and the plurality of first touch electrodes
  • the two touch electrodes cross each other
  • the plurality of signal wires include a plurality of first signal wires connected to the corresponding first touch electrodes and a plurality of second signal wires connected to the corresponding second touch electrodes
  • the second signal shielding line includes a first segment and a second segment.
  • At least part of the extension pattern of the first segment is consistent with the extension pattern of the outermost first signal trace far from the display area among the plurality of first signal traces, and at least part of the extension of the second segment The pattern is consistent with the extension pattern of the outermost second signal wirings far from the display area among the plurality of second signal wirings.
  • the spacing between the first segment and the outermost first signal trace is equal to the distance between the outermost first signal trace and its adjacent first signal trace
  • the distance between the second segment and the outermost second signal wiring is equal to the distance between the outermost second signal wiring and its adjacent second signal wiring.
  • the base substrate includes a bending region within the non-display region, the base substrate forms a first portion and a second portion via the bending region, and the first portion includes In the display area, the first area and the second area, the plurality of outer dummy wirings further include at least one second dummy wiring in the second area and adjacent to the bending area Wire.
  • the plurality of signal traces, the first signal shielding wire and the second signal shielding wire extend to the bending region, and the at least one second dummy trace is distributed in between the first signal shielding line and the outer boundary of the non-display area.
  • the display panel further includes at least one intermediate dummy trace between at least a part of the signal traces in the plurality of signal traces, and the at least one intermediate dummy trace is connected to the Multiple signal traces are separated from each other.
  • the touch electrode layer includes a plurality of first touch electrodes arranged in parallel and a plurality of second touch electrodes arranged in parallel, the plurality of first touch electrodes and the plurality of touch electrodes
  • the second touch electrodes cross each other, and the plurality of signal wires include a plurality of first signal wires connected to the corresponding first touch electrodes and a plurality of second signal wires connected to the corresponding second touch electrodes wiring
  • the base substrate includes a bending area in the non-display area, the base substrate forms a first part and a second part through the bending area, and the first part includes the display area, and a middle non-display area of the non-display area between the bending area and the display area
  • the plurality of first signal lines and the plurality of second signal lines extend to the middle a non-display area
  • the at least one middle dummy line includes at least one third dummy between the plurality of first signal lines and the plurality of second signal lines and in the middle non-display
  • the display panel further includes a touch controller disposed on the second portion of the base substrate, and the plurality of signal traces are electrically connected to the touch controller Touch the controller.
  • each of the at least one first dummy traces is spaced apart from each other and evenly distributed between the first signal shielding wire and the second signal shielding wire
  • Each of the at least one second dummy traces is spaced apart from each other and evenly distributed between the first signal shielding wire and the outer boundary of the non-display area.
  • At least one of the outer dummy trace, the signal trace, and the middle dummy trace includes a first metal line and a second metal line disposed above the first metal line
  • the display panel further includes an insulating layer between the first metal line and the second metal line, the insulating layer includes a via hole, and the first metal line is electrically connected to the the second metal wire.
  • the material of the first metal wire and the second metal wire includes at least one of titanium, silver, and indium tin oxide.
  • the display panel further includes an encapsulation dam on the base substrate, the encapsulation dam is located between the first signal shielding line and an outer boundary of the non-display area, so The packaging dam extends in the non-display area around the first signal shielding wire, and a fixed first distance is maintained between the packaging dam and the first signal shielding wire, and the first signal shielding wire is connected to the first signal shielding wire.
  • a second distance exists between the outer dummy lines adjacent to the first signal shielding line among the plurality of outer dummy lines, and the ratio of the first distance to the second distance is greater than 1 and less than 6.
  • the base substrate includes a rounded portion
  • the second region includes a curved region within the rounded portion and a flat region outside the rounded portion
  • the curved The area includes a first void
  • the straight area includes a second void
  • the first void is formed by an end of an outer dummy trace in the curved area and a connection with the one of the plurality of outer dummy traces.
  • the outer dummy traces adjacent to the outer dummy traces are jointly formed, and the second gap is formed by the end of the other outer dummy trace in the straight area and the other outer dummy trace in the plurality of outer dummy traces.
  • An outer dummy trace adjacent to one outer dummy trace is formed together, and the area of the first void is larger than the area of the second void.
  • the average width of the signal traces far from the display area among the plurality of signal traces is greater than the average width of the signal traces close to the display area.
  • the display panel further includes at least one crack detection line disposed on the base substrate, the at least one crack detection line being located at an outer boundary of the non-display area and the first signal shield
  • the extension pattern of the at least one crack detection line is consistent with the extension pattern of the first signal shielding line.
  • the second distance between adjacent outer dummy traces of the first signal shielding wire is 2 to 3 times the third distance.
  • the display panel further includes a pixel structure layer between the touch electrode layer and the base substrate, and the pixel structure layer includes an anode, a cathode, and an organic light-emitting layer therebetween.
  • Another embodiment of the present disclosure provides a display device including the display panel as described in any of the foregoing embodiments.
  • the outer dummy traces, the middle dummy traces, or both of the dummy traces described in the embodiments of the present disclosure in the non-display area of the display panel, it is possible to facilitate the etching of the metal film layer in the process of manufacturing the display panel.
  • the etching uniformity in the etching process is beneficial to improve the touch performance of the fabricated display panel or display device.
  • FIG. 1 schematically shows a distribution diagram of signal wirings and external dummy wirings in a display panel according to an embodiment of the present disclosure
  • FIG. 2 schematically shows a distribution diagram of signal wirings and external dummy wirings in a display panel according to another embodiment of the present disclosure
  • FIG. 3 schematically shows a distribution diagram of signal shielding wires, signal wires and external dummy wires in a display panel according to another embodiment of the present disclosure
  • FIG. 4 schematically shows the state after the base substrate in FIG. 3 is bent
  • FIG. 5 schematically shows a distribution diagram of signal shielding wires, signal wires, outer dummy wires, and middle dummy wires in a display panel according to yet another embodiment of the present disclosure
  • FIG. 6 schematically shows a distribution diagram of signal shielding wires, signal wires, outer dummy wires, and middle dummy wires in a display panel according to yet another embodiment of the present disclosure
  • FIG. 7 schematically shows the overall outline of the area where various types of wirings are located around the display area of the display panel according to another embodiment of the present disclosure
  • Fig. 8-Fig. 10 schematically show a partial enlarged view of the area indicated by Q1 in Fig. 7;
  • Fig. 11 schematically shows an enlarged view of the area indicated by Q2 in Fig. 7;
  • Fig. 12 schematically shows a partial cross-sectional view along the line D1-D2 in Fig. 11;
  • FIG. 13 schematically shows a partial cross-sectional view of a single pixel region of a display panel according to another embodiment of the present disclosure
  • FIG. 14 schematically illustrates a process of fabricating a touch electrode layer in a display panel and various types of wirings in a non-display area according to yet another embodiment of the present disclosure.
  • some metal traces are usually arranged, and these metal traces electrically connect the touch controller and the touch electrodes in the touch display device. These metal traces are drawn from the terminals of the touch controller, extend to the touch electrode layer through the non-display area of the display device, and are respectively connected with the corresponding touch electrodes.
  • the inventors of the present application found that the process of fabricating these metal traces often leads to a decrease in the touch performance of the display device. Specifically, the metal traces located at the periphery of the display area of the display device are not uniformly distributed in the non-display area.
  • metal traces may be distributed outside two or three of the four edges of the display area, and there is no metal trace on the periphery of one edge of the display area.
  • a part of the non-display area surrounding the rectangular display area is a blank area where no metal wires exist. The inventor realized that in the process of fabricating these metal traces in the non-display area, it is difficult to ensure the etching uniformity of the metal film layer, and this uneven etching of the metal film layer affects the display device. A factor in touch performance.
  • an embodiment of the present disclosure provides a display panel to improve the touch performance of a touch display device.
  • a display panel provided according to an embodiment of the present disclosure includes a base substrate, a touch electrode layer, a plurality of signal wirings, and a plurality of external dummy wirings.
  • the base substrate of the display panel includes a display area A and a non-display area around the display area A (for example, NA1 and NA2 shown in FIG. 1 ), and the touch electrode layer is disposed on the base substrate , and is located in display area A.
  • the display panel also includes a plurality of signal wires and a plurality of external dummy wires, the plurality of signal wires are electrically connected to the touch electrode layer and distributed in the first area NA1 of the non-display area, and the first area NA1 is connected to the touch electrode layer.
  • Display area A is adjacent.
  • the plurality of outer dummy wires are located in the second area NA2 of the non-display area, and the second area NA2 is located between the first area NA1 and the outer boundary OB of the non-display area.
  • the outer dummy traces in the second area NA2 and the signal traces in the first area NA1 are separated from each other.
  • the “dummy traces” mentioned in this article refer to wires that do not play a role in signal transmission during the operation of the display panel or the display device, and these dummy wires may not be connected to any other electrical components of the display panel or the display device, During the operation of the display device, no electrical signal is received, or some or all of these dummy traces are only electrically connected to a fixed potential (eg, ground potential).
  • a fixed potential eg, ground potential
  • the plurality of mutually independent dummy traces may present any pattern, and the embodiments of the present disclosure do not impose any restrictions on the pattern of each dummy trace in various types of dummy traces and the overall pattern of the plurality of dummy traces.
  • outer dummy traces are relative to the “middle dummy traces” described in other embodiments below, and are intended to be used to distinguish the differences in the positions of the two dummy traces. , but without any limitations on any properties or characteristics (eg, structure, pattern, material, etc.) of the dummy traces.
  • the second area where the outer dummy traces are located is between the first area where the signal traces are located in the non-display area and the outer boundary of the non-display area, and the middle dummy traces are laid out between the signal traces Between lines, the details will be described in further embodiments below.
  • FIG. 1 shows an example in which the outer dummy traces are arranged in a corner area between the outer boundary OB of the non-display area and the first area NA1 where a plurality of signal traces are located
  • FIG. 2 schematically shows the outer dummy traces Another example of the arrangement of lines.
  • there are three second areas NA2 between the first area NA1 of the non-display area and the outer boundary OB of the non-display area one of the second areas NA2 is above the display area A, and the other two are The area NA2 is below the display area A.
  • the first area NA1 and the second area NA2 together may form an annular area surrounding the display area A.
  • the process of forming the signal traces in the non-display area usually involves an etching process on the metal film layer.
  • a plurality of signal traces in the non-display area can be fabricated simultaneously.
  • External dummy traces These outer dummy traces together with the signal traces make the material of the finally formed metal traces more uniformly distributed on the periphery of the display area.
  • the etching uniformity is improved, which is beneficial to improve the touch performance of the fabricated display panel or display device.
  • the embodiments of the present disclosure do not impose any limitations on the materials for making the signal traces and the external dummy traces.
  • the materials for making the signal traces and the external dummy traces may be any metal, metal oxide, or metal alloy material with electrical conductivity, Including, but not limited to, for example, indium tin oxide (ITO), silver (Ag), aluminum (Al), titanium (Ti), and the like.
  • ITO indium tin oxide
  • silver Ag
  • aluminum Al
  • titanium Ti
  • signal shielding wires are further provided in the non-display area of the display panel, so as to reduce the interference of the signal wires by external signals.
  • the display panel includes a first signal shielding line P1 and a second signal shielding line P2 located in the non-display area, and at least a part of the first signal shielding line P1 is located in the second area NA2 (where the first outer dummy lines are arranged Between the line DT1) and the outer boundary OB of the non-display area, the second signal shielding line P2 is between the first signal shielding line P1 and the first area (where the signal traces T1, T2 are arranged).
  • the plurality of outer dummy wires arranged in the non-display area include at least one first dummy wire DT1 between the first signal shielding wire P1 and the second signal shielding wire P2.
  • the first signal shielding line P1 and the second signal shielding line P2 extend substantially around the display area A, and each of the first signal shielding line P1 and the second signal shielding line P2 may be uninterrupted
  • the continuous traces can also be arranged to include several segments spaced apart from each other.
  • the first signal shielding wire P1 may include a ground wire
  • the second signal shielding wire P2 may be configured to receive a fixed potential or a square wave signal.
  • the second signal shielding wire P2 extends along the outer edge of the first area NA1 where the signal trace is located, and the first signal wire P1 basically surrounds the second signal shielding wire P2, so that the first area
  • the internal signal traces T1 and T2 play the role of double signal shielding.
  • a plurality of first dummy traces DT1 are formed in a large gap area between the first signal shielding wire P1 and the second signal shielding wire P2, so that the signal traces and the first signal shielding wire can be fabricated.
  • the uniformity of the etching of the metal film layer in the process of P1 and the second signal shielding line P2 promotes the improvement of the touch performance of the final touch display panel or display device.
  • the base substrate is a flexible base substrate, or the base substrate includes a flexible region such that the base substrate is bendable.
  • FIG. 4 schematically shows the base substrate 100 after being bent, and FIG. 3 shows a state when the base substrate is not bent.
  • the base substrate 100 includes a bending area BA in the non-display area, the base substrate 100 forms a first part 1A and a second part 2A through the bending area BA, and the first part 1A includes the display area A and the first area of the non-display area NA1 and the second area NA2, the plurality of outer dummy wires further include at least one second dummy wire DT2 located in the second area NA2 and adjacent to the bending area BA.
  • the bending axis may be parallel to one side of the base substrate, and the base substrate 100 may be bent around the bending axis AX such that the second part 2A faces the back of the first part 1A
  • the first portion 1A and the second portion 2A may form any angle, which is not limited by the embodiments of the present disclosure.
  • various IC devices including the touch controller C may be arranged in the second portion 2A, whereby these IC devices may be hidden to the back of the first portion 1A in the final formed display device , can achieve full screen display.
  • the plurality of signal traces are electrically connected to the touch controller C, as shown in FIG. 3 .
  • a plurality of signal traces T1, T2, a first signal shielding wire P1 and a second signal shielding wire P2 extend to the bending area BA, and a plurality of outer dummy traces (the second The dummy traces DT2) are respectively distributed between the first signal shielding line P1 and the outer boundary OB of the non-display area.
  • a plurality of second dummy traces DT2 are located between the display area A and the bending area BA.
  • the plurality of second dummy traces DT2 here can realize similar functions as the first dummy traces DT1 in the foregoing embodiments, that is, can facilitate the fabrication of signal traces, the first signal shielding wire P1 and the second signal shielding wire P2
  • the uniformity of the etching of the metal film layer during the process is beneficial to improve the touch performance of the touch display panel or the display device.
  • these second dummy traces DT2 can also reduce the film layer of the side edge area of the display panel The risk of detachment from the base substrate is improved, and the structural stability of the display panel is improved.
  • the signal wiring T1 and the signal wiring T2 mentioned in the embodiments of the present disclosure represent signal wirings connected to different touch electrodes in the touch electrode layer.
  • the signal trace T1 can be connected to the transmitting electrode in the touch electrode layer
  • the signal trace T2 can be connected to the receiving electrode in the touch electrode layer
  • the transmitting electrode and the receiving electrode can generate mutual capacitance.
  • the touch controller can transmit control signals to the transmitting electrodes and receive sensing signals from the receiving electrodes, whereby the user's touch position can be determined based on the change of mutual capacitance.
  • the touch electrodes in the touch electrode layer can also be based on the structure of the self-capacitance sensing principle. The specific arrangement and structure of the touch electrodes in the touch electrode layer are not the focus and key of the present disclosure, and will not be described in detail here.
  • each of the first dummy traces in the plurality of first dummy traces is independent from each other, and each second dummy trace in the plurality of second dummy traces is also independent from each other. Yes, they can be uniformly distributed in the corresponding area of the non-display area, so as to further facilitate the uniformity of the etching of the metal film layer.
  • the first dummy traces DT1 are spaced apart from each other and evenly distributed between the first signal shielding wire P1 and the second signal shielding wire P2, and the second dummy traces DT2 are spaced apart from each other, and Evenly distributed between the first signal shielding line P1 and the outer boundary OB of the non-display area.
  • a region F on the base substrate where the encapsulation dam is located.
  • the second dummy trace DT2 may be located between the bending area BA and the area F where the packaging dam is located.
  • the distance between each of the first dummy traces DT1 in the plurality of first dummy traces DT1 is equal to the distance between the second signal shielding wire P2 and the second signal traces T2 that is closest to the first dummy trace DT1.
  • the width of the first dummy wire closest to the first signal shielding wire P1 among the plurality of first dummy wires DT1 is equal to the width of the first signal shielding wire P1
  • the width of the first dummy wire DT1 is the closest to the first signal shielding wire P1.
  • the width of the first dummy trace close to the second signal shielding wire P2 is equal to the width of the second signal shielding wire P2.
  • the difference between the spacing between the first dummy traces DT1 and the spacing between the second signal shielding wire P2 and the second signal trace T2 closest to the second signal shielding wire P2 may be in each Within %5 of the spacing between the first dummy traces DT1.
  • the touch electrode layer includes a plurality of first touch electrodes arranged in parallel and a plurality of second touch electrodes arranged in parallel, the plurality of first touch electrodes and the plurality of first touch electrodes The two touch electrodes cross each other.
  • the plurality of signal traces include a plurality of first signal traces T1 respectively connected to the corresponding first touch electrodes and a plurality of second signal traces respectively connected to the corresponding second touch electrodes Line T2, the second signal shielding line P2 includes a first segment P21 and a second segment P22.
  • the extension pattern of the first segment P21 is consistent with the extension pattern of the outermost first signal line T1 far away from the display area A among the plurality of first signal lines
  • the extension pattern of the second segment P22 is consistent with the extension pattern of the plurality of first signal lines.
  • the extension patterns of the outermost second signal traces in the second signal traces T2 away from the display area are consistent.
  • the spacing between the first segment P21 and the outermost first signal trace is equal to the spacing between the outermost first signal trace and its adjacent first signal trace
  • the second The spacing between the segment P22 and the outermost second signal trace is equal to the spacing between the outermost second signal trace and its adjacent second signal trace.
  • first segment P21 and the second segment P22 are separated from each other.
  • first segment P21 and the second segment P22 may be connected to each other to form an integral second signal shield Wire.
  • each touch electrode in the touch electrode layer is shown as being connected to only one signal trace, for example, the signal trace T1 in FIG. 3 may be connected to the touch trace.
  • the transmitting electrodes in the electrode layer are connected, and the signal trace T2 may be connected with the receiving electrodes in the touch electrode layer, but this does not constitute any limitation of the embodiments of the present disclosure.
  • each touch electrode may be connected to two signal traces. For example, as shown in FIG. 5 , two ends (upper end and lower end) of each transmitting electrode in the touch electrode layer are respectively connected to the signal wiring T11 and the signal wiring T12 , and each receiving electrode is connected to the signal wiring T2 .
  • each receiving electrode may be connected to two signal wires, or each transmitting electrode and each receiving electrode may be connected to two signal wires.
  • the embodiments of the present disclosure do not impose any specific limitations on the layout of the touch electrodes and the signal traces in the touch electrode layer, and the connection between the touch electrodes and the signal traces, which are disclosed in the embodiments of the present disclosure.
  • the technical measures for improving the touch performance of the touch display device by using dummy traces are not limited by the connection method between the touch electrodes and the signal traces.
  • the display panel further includes at least one intermediate dummy trace between the plurality of signal traces, the intermediate dummy traces and the plurality of signal traces being separated from each other.
  • the intermediate dummy traces mentioned in this article can be arranged between the above-mentioned multiple first signal traces, or between the above-mentioned multiple signal traces, or, can also be arranged between the first signal trace and the first signal traces. between the two signal traces. Referring next to FIG. 5 , a plurality of intermediate dummy traces DT3 are formed between the signal trace T2 and the signal trace T12.
  • another dummy trace (that is, the middle dummy trace) can be formed between the two. line DT3).
  • intermediate dummy traces may be arranged in the gaps between other signal traces.
  • intermediate dummy traces may be formed in the gaps between different signal traces connected to touch electrodes of the same type.
  • the middle dummy trace DT3 is shown to exist between the signal trace T1 connected to the transmitting electrode, between the signal trace T2 connected to the receiving electrode, and the signal trace T1 and the signal trace between lines T2.
  • intermediate dummy traces may be arranged between any two of the plurality of signal traces.
  • These intermediate dummy traces DT3 can achieve at least partially similar functions to the first dummy traces DT1 and the second dummy traces DT2 in the foregoing embodiments, that is, they can facilitate the etching of the metal film during the fabrication of the signal traces. Uniformity, thereby helping to improve the touch performance of the touch display panel or the display device.
  • the base substrate includes a bending area in the non-display area, and the base substrate forms the first part and the second part through the bending area, as shown in FIGS. 3 and 4 . Show.
  • the first part includes the display area and a middle non-display area of the non-display area between the bending area and the display area (as shown in FIG. 3 , between the display area A and the bending area BA
  • the non-display area in between may be referred to as a middle non-display area
  • a plurality of first signal traces and a plurality of second signal traces may extend to the bending area.
  • the at least one intermediate dummy trace includes at least one intermediate dummy trace that is located between a plurality of first signal traces T1 and a plurality of second signal traces T2 and is located in a non-display area in the middle A third dummy trace DT3.
  • the third dummy trace DT3 in this embodiment can play a similar role as the second dummy trace DT2 in the previous embodiment, and can facilitate the fabrication of the signal trace, the first signal shielding wire P1 and the second signal shielding wire P2
  • the uniformity of the etching of the metal film layer during the process is beneficial to improve the touch performance of the touch display panel or the display device.
  • these third dummy traces DT3 can also reduce the risk of the film layer near the bending area of the display panel being detached from the base substrate, thereby improving the structural stability of the display panel .
  • the material of the second signal shielding wire may be arranged between the plurality of first signal traces T1 and the adjacent third dummy traces DT3, or the material of the second signal shielding wire may be arranged between the plurality of first signal traces T1 and the adjacent third dummy traces DT3.
  • the material of the second signal shielding line is arranged between a signal trace T2 and the adjacent third dummy trace DT3.
  • the second signal shielding wire can extend to a plurality of first signal shielding lines in the middle non-display area. Both sides of the signal trace T1 or the plurality of second signal traces T2.
  • each of the signal traces, dummy traces, and signal shielding wires may include more than two metal wires, which may be electrically connected to each other but distributed in different layers to have It is beneficial to reduce the overall resistance of the trace.
  • each of the signal traces T1, T2 and each of the dummy traces DT1, DT2, DT3 includes a first metal wire and a second metal wire arranged above the first metal wire
  • the display panel further includes a An insulating layer between a metal wire and a second metal wire, the insulating layer includes a via hole, and the first metal wire is electrically connected to the second metal wire through the via hole in the insulating layer.
  • FIG. 7 illustrates the overall outline of the area around the display area of the display panel where various traces are located.
  • FIG. 8 is an enlarged schematic view of the Q1 region of FIG. 7 .
  • the first signal shielding wire P1 (the ground wire GND in this example) is arranged outside the signal wires T1 and T2, and the two second signal shielding wires P2 are respectively adjacent to the first signal wire.
  • T1 and the second signal trace T2 to reduce or avoid external signals from interfering with the first signal trace T1 and the second signal trace T2.
  • a plurality of outer dummy traces are arranged between the first signal shielding wire P1 and the second signal shielding wire P2. Also illustrated in FIG.
  • encapsulation dams Dam1, Dam2 which are also located in and around the non-display area, and may be between the first signal shielding line and the outer boundary of the non-display area.
  • the example of FIG. 7 shows two encapsulation dams Dam1 , Dam2 , however, in other examples, the number of encapsulation dams may be one or more than two.
  • the individual encapsulation dams may have the same or different film layer structures.
  • the encapsulation dam may include a protective portion and a blocking portion that are stacked in sequence.
  • the encapsulation dam may further include a support over the barrier.
  • At least one of the protection part, the blocking part and the supporting part may be in the same layer as a film layer in the display area of the display panel.
  • the blocking portion of the encapsulation dam may be in the same layer as the pixel defining layer.
  • the packaging dam extends in the non-display area around the first signal shielding wire, and a fixed first distance is maintained between the packaging dam and the first signal shielding wire, and the first signal shielding wire is connected to the multiple signal shielding wires.
  • a second distance exists between the outer dummy lines adjacent to the first signal shielding line among the outer dummy lines, and the ratio of the first distance to the second distance is greater than 1 and less than 6.
  • the distance a between the first signal shielding line P1 and the packaging dam Dam1 at a certain area of the upper right corner of the display panel is equal to the distance a between the first signal shielding line P1 and the packaging dam Dam1 at the top of the display panel Distance b between flat areas.
  • the first distance between the first signal shielding wire and the package dam is greater than the second distance between the first signal shielding wire and the outer dummy trace adjacent to the first signal shielding wire.
  • the above-mentioned ratio between the first distance and the second distance may be in the range of 1-6. As shown in FIG.
  • the distance a or b between the first signal shielding line P1 and the package dam Dam1 may be 40 ⁇ m-170 ⁇ m, and the first signal shielding line P1 and the outer dummy adjacent to the first signal shielding line P1 are separated from each other.
  • the second distance d between the lines may be 30 ⁇ m-40 ⁇ m.
  • the distance a or b between the first signal shielding line P1 and the package dam Dam1 may be 75 ⁇ m-120 ⁇ m or 75 ⁇ m-130 ⁇ m.
  • the width of the first signal shielding line P1 is greater than the width of the second signal shielding line P2.
  • the width of the first signal shielding line P1 may be 3-5 times the width of the second signal shielding line P2.
  • the second signal shielding line P2 has a width of 3 ⁇ m-5 ⁇ m, and the first signal shielding line has a width of about 15 ⁇ m.
  • the touch electrode layer includes a plurality of first touch electrodes arranged in parallel and a plurality of second touch electrodes arranged in parallel, and the first touch electrodes and the second touch electrodes intersect with each other.
  • Each of the first touch electrodes and each of the second touch electrodes may include a plurality of touch electrode blocks spaced apart from each other, and two adjacent touch electrode blocks among the plurality of touch electrode blocks are connected to each other through a bridge layer.
  • FIG. 9 illustrates a plurality of touch electrode blocks, and a row or a column of touch electrode blocks are electrically connected to each other through a bridging layer (not shown in FIG. 7 ) to form a first touch electrode or a second touch electrode.
  • the first touch electrodes or the second touch electrodes mentioned here may be the aforementioned transmitting electrodes or receiving electrodes.
  • the first touch electrodes and the second touch electrodes formed by the touch electrode block E are respectively connected to the first signal trace T1 or the second signal trace T2 .
  • the touch electrode block E and the above-mentioned second metal wire can be made of the same material and made in the same process.
  • the layer formed by the touch electrode block E and the second metal wire is identified as Metal2 Layer in FIG. 9 .
  • the base substrate further includes at least one crack detection line disposed on the base substrate.
  • the crack detection line PCD is located between the outer boundary of the non-display area and the first signal shielding line P1
  • the crack detection line PCD may surround the first signal shielding line P1
  • its extension pattern may be consistent with the first signal shielding line P1
  • the extension patterns of the lines P1 are the same.
  • the process of fabricating the display panel may involve cutting the base substrate or a similar mechanical process, for example, cutting out a plurality of display panel units based on the fabricated motherboard, or cutting off unnecessary outer edge portions of the display panel. In the process of mechanical cutting, the display panel or the substrate substrate may have cracks at the incision.
  • the crack detection line PCD can at least prevent the crack from damaging the display panel. In other words, with the crack detection line, the crack can stop at the crack detection line, and Does not extend any further in the direction of the display area.
  • the crack detection line PCD may be fabricated in the same process as the above-mentioned touch electrode block E and the second metal line, that is, the layer where the crack detection line is located is also identified as Metal2 Layer in FIG. 9 .
  • the third distance between the crack detection line and the first signal shielding line P1 is smaller than the above-mentioned second distance d (ie, the first signal shielding line P1 and the first signal shielding line P1 are in phase with the first signal shielding line P1 ). the second distance between adjacent outer dummy traces).
  • the second distance between the first signal shielding line P1 and the outer dummy wiring adjacent to the first signal shielding line P1 is 2-3 times the above-mentioned third distance.
  • the second distance d may be 30 ⁇ m-40 ⁇ m
  • the third distance between the crack detection line PCD and the first signal shielding line P1 is about 14 ⁇ m.
  • the display panel includes two crack detection lines, as shown in FIG. 9 .
  • the extension patterns of the two crack detection lines are the same, which can be consistent with the first signal shielding line P1, and the distance between the two crack detection lines is kept substantially constant.
  • each crack detection line may have a width of 4 ⁇ m, and a spacing of about 15 ⁇ m may be maintained between the two crack detection lines.
  • the base substrate includes a rounded portion
  • the second region includes a curved region within the rounded portion and a flat region outside the rounded portion
  • the curved region includes a first A void
  • the flat region includes a second void.
  • the first gap is jointly formed by an end of an outer dummy wire located in the bending region among the plurality of outer dummy wires and an outer dummy wire adjacent to the outer dummy wire, and the second outer dummy wire is formed.
  • the gap is jointly formed by the end of another outer dummy trace in the straight area and the outer dummy trace adjacent to the other outer dummy trace, and the third outer dummy trace is formed.
  • the area of a void is larger than the area of the second void.
  • FIG. 9 schematically shows the gaps S1 and S2 enclosed by the ends of the two outer dummy wires and the other outer dummy wires, respectively.
  • the gaps S1 and S2 schematically shown in FIG. 9 may correspond to the first gap S1 and the second gap S2 described above, respectively.
  • the first gap S1 is formed by the end of an outer dummy trace DTa in which the plurality of outer dummy traces Dummy Trace is located in the bending area and the outer dummy trace adjacent to the one outer dummy trace DTa
  • the second The gap S2 is formed by the end of another outer dummy trace DTb in the straight area in the plurality of outer dummy traces Dummy Trace and the outer dummy trace adjacent to the other outer dummy trace.
  • the area of one gap S1 is larger than that of the second gap S2.
  • the gaps between the outer dummy lines can effectively prevent or reduce the influence of static electricity that may accumulate at the ends of the outer dummy lines on other outer dummy lines.
  • the end of the first outer dummy trace DTa in the bending area is roughly in the shape of a cone, so that the area of the first gap S1 is large, which is convenient for the manufacture of the dummy trace outside the bending area, and can also Prevent or reduce adverse effects caused by static electricity that may collect at the ends of the outer dummy traces.
  • FIG. 10 shows the first metal line mentioned in the above example, and the first metal line may be located under the second metal line.
  • the layer where the first metal line is located is identified as Metal1 Layer.
  • the above-mentioned bridging layer (not shown in FIG. 10 ) can be made of the same material as the first metal wire in the same process. From this, it can be understood that FIG. 9 also shows the layout of parts in Metal2 Layer.
  • the material used to make the first metal wire and the second metal wire includes at least one of titanium, silver, and indium tin oxide.
  • at least one of the first metal line and the second metal line includes an aluminum layer and titanium layers flanking the aluminum layer.
  • at least one of the first metal line and the second metal line includes a silver layer and indium tin oxide layers on both sides of the silver layer.
  • the first metal wire may include a Ti/Al/Ti three-layer metal structure or an ITO/Ag/ITO three-layer metal structure
  • the second metal wire may also include a Ti/Al/Ti three-layer metal structure or ITO /Ag/ITO three-layer metal structure.
  • FIG. 11 illustrates a partial enlarged schematic diagram of the two Q2 regions shown in FIG. 7 , that is, FIG. 11 can be regarded as an enlarged schematic diagram after the two Q2 regions in FIG. 7 are merged. 7, 11 and 4, the non-display area shown in FIG. 11 is still located in the first part 1A of the base substrate, and the bent part BA of the base substrate is not shown in FIG. In the straight state, the curved portion may be located just below the area shown in FIG. 11 . As shown in FIG.
  • a plurality of outer dummy traces DT2 are distributed in the second area, and are located on both sides of the plurality of signal traces, and are located in the second area.
  • the outer side of a signal shielding line P1 eg, a GND line
  • adding the second dummy wiring DT2 in the process of manufacturing the display panel can promote the uniformity of the etching of the metal film layer, which is beneficial to improve the touch performance of the touch display panel or the display device.
  • the second dummy trace DT2 is close to the bending area, which can also reduce the risk of the film layer in the area where it is located and the adjacent area being detached from the base substrate during the bending process of the base substrate, thereby improving the structural stability of the display panel.
  • each trace including the signal trace includes a double-layer metal wire to reduce the resistance of the signal trace and facilitate various traces and touch electrode layers. production process.
  • the first metal lines of the signal lines in different regions may be made of different materials, or the first metal lines of the signal lines in different regions may be completed in different fabrication processes.
  • the base substrate forms a first part and a second part via a bending area, and the first part includes a middle non-display area of the non-display area between the bending area and the display area
  • FIG. 11 can be regarded as an example of a partial schematic diagram of the middle non-display area. As shown in FIG.
  • SD may represent a structure in the same layer as the source or drain of the thin film transistor in the display area of the display panel but isolated from each other, that is, the source-drain signal line mentioned herein.
  • the source-drain signal line SD and a part of the external dummy lines eg, the second dummy line DT2 shown in FIG. 11
  • the source-drain signal line SD may have a partial overlapping area with at least a part of the signal lines, and be insulated from each other.
  • the display panel further includes a transit electrode for electrically connecting the pixel electrode (eg, the anode of the organic light emitting device of the OLED display panel) and the source or drain of the thin film transistor, in this case 11
  • SD in FIG. 11 may represent a structure that is on the same layer as the transition electrode and separated from each other, that is, the transition electrode signal line mentioned herein.
  • the transition electrode signal line and at least a part of the outer dummy wiring have at least a partial overlapping area and are insulated from each other.
  • the transition electrode signal line SD and at least a part of the signal wiring have at least a partial overlapping area, and are insulated from each other.
  • FIG. 11 shows a transit electrode for electrically connecting the pixel electrode (eg, the anode of the organic light emitting device of the OLED display panel) and the source or drain of the thin film transistor, in this case 11
  • SD in FIG. 11 may represent a structure that is on the same layer as the transition electrode and separated from each other, that is, the
  • the source-drain signal line SD or the transition electrode signal line SD is further provided with a plurality of openings for releasing the gas of the underlying film layer.
  • At least one opening and at least a part of the outer dummy traces have at least a partial overlapping area. Further, there is at least a partial overlap area between the at least one opening and at least a part of the signal traces.
  • the display panel may include pixel electrodes and thin film transistors for driving the pixels of the display panel to emit light, and the above-mentioned source-drain signal lines formed in the same process as the source and drain of the thin film transistors in the pixel driving circuit of the display panel may serve as signals Traces.
  • FIGS. 11 and 12 FIG. 12 schematically shows a cross-sectional view along the D1-D2 direction of the region of the middle non-display area adjacent to the bending area in FIG.
  • M2 represents the second metal wire
  • SD represents the second metal wire serving as the first metal wire.
  • the above-mentioned other conductive structures in the display panel can be used as the above-mentioned various types of wirings. Therefore, the second metal line and the first metal line may not extend to the bending area.
  • the other conductive structures can be electrically connected with the second metal lines in the second portion when the other conductive structures extend in the bending region to, for example, the above-mentioned second portion. That is, in the second part, various types of traces including signal traces may have a structure similar to that of the signal traces in the Q1 region in FIG. 7 , that is, including the first metal wire and the second metal wire.
  • the display panel further includes a transfer electrode for electrically connecting the pixel electrode and the source electrode or the drain electrode of the thin film transistor, and a transfer electrode formed in the same manufacturing process as the transfer electrode.
  • the transfer electrode signal line similarly, the transfer electrode signal line can be used as various traces in the bending area. Therefore, in the middle non-display area near the bending area, the transfer electrode signal line passes through the upper part of the The via hole of the second insulating layer is electrically connected to the second metal line, which can also be schematically shown in FIG. 12 .
  • the transition electrode signal lines can be used as various wirings, and at this time, neither the second metal wire nor the first metal wire extends to the bending area.
  • the transfer electrode signal line When the transfer electrode signal line extends in the bending region to reach, for example, the above-mentioned second part, it can be electrically connected with the second metal line in the second part.
  • various types of traces including signal traces may have a similar structure to the signal traces in the Q1 region in FIG. Two metal wires.
  • FIG. 13 schematically shows a partial cross-sectional view of a display panel including transition electrodes.
  • the display panel includes a base substrate 100 and a pixel driving circuit and a light emitting device located on the base substrate.
  • the pixel driving circuit may include a thin film transistor and a capacitor, the capacitor includes a first capacitance electrode 112 and a second capacitance electrode 113 , and the thin film transistor includes an active layer 108 , a gate electrode 109 , a source electrode 110 and a drain electrode 111 .
  • the light emitting device includes an anode 1141 , a light emitting functional layer 1142 and a cathode 1143 . As shown in FIG.
  • the display panel further includes a transfer electrode 121 between the source electrode 110 and the anode electrode 1141 , and the transfer electrode 121 penetrates the insulating layer to electrically connect the pixel electrode (eg, the anode electrode 1141 ) and the source electrode 110 .
  • the above-mentioned transfer electrode signal line can be formed in the process of manufacturing the transfer electrode 121 , and the transfer electrode signal line can be used as the above-mentioned first metal line in the middle non-display area.
  • a display panel may include a pixel driving circuit, the pixel driving circuit includes a capacitor, and the capacitor includes capacitive electrodes, such as the first capacitive electrode 112 and the second capacitive electrode 113 in FIG. 13 , the display panel may further It includes a capacitive signal line formed in the same manufacturing process as the capacitive electrode (eg, the second capacitive electrode 113 ) and located in the non-display area.
  • the other conductive structures mentioned above may include conductive structures or capacitive signal lines formed in the same layer as the gate, or may be a combination of the various conductive structures mentioned above, for example, a capacitor
  • the signal line and the transfer electrode signal line can be used as the signal line in the bending area together, or the transfer electrode signal line can only play an electrical connection role in the area near the bending area in the middle non-display area, not as a signal line.
  • Various types of traces including signal traces in the bending area can be designed according to requirements, which are not limited here. As mentioned above, the bending area is located below the area where the lines D1-D2 shown in FIG. 11 are located, and will not be shown here.
  • source-drain signal line does not refer to the source-drain transfer electrode or the capacitor itself, but refer to the process of making the source-drain, transfer, respectively. Electrodes and signal lines formed together with source and drain electrodes, transfer electrodes or capacitor electrodes on the non-display area of the base substrate in the process of capacitors, therefore, they have the same characteristics as source and drain electrodes, transfer electrodes or capacitor electrodes. material, but not connected to source-drain, via electrodes, or capacitor electrodes.
  • the above-mentioned first metal line in the middle non-display area may include at least one of a transfer electrode signal line, a source-drain signal line, and a capacitor signal line.
  • a transfer electrode signal line any two or more of the transition electrode signal line, the source-drain signal line, and the capacitance signal line can simultaneously serve as the first metal line.
  • the first metal lines in the middle non-display area may include source-drain signal lines and transfer electrode signal lines, or may include transfer electrode signal lines and capacitor signal lines.
  • the width of each signal trace T1 and T2 extending from the touch controller to the touch electrode layer of the display area is not constant.
  • the width of each signal trace close to the touch controller is not constant.
  • the width of the section is smaller than the width of the section away from the touch controller because the space for routing signal traces is smaller near the touch controller than in the area away from the touch controller.
  • the signal traces can be gradually wider from the touch controller to the touch electrode layer, which can reduce the overall resistance of the signal traces.
  • the widths of different signal traces among the plurality of signal traces also vary. For example, the further the signal traces are arranged from the display area, the wider they are.
  • the average width of the signal lines far from the display area among the plurality of signal lines is greater than the average width of the signal lines close to the display area.
  • the relatively abundant wiring space in the area relatively far from the display area can be fully utilized to reduce the resistance of a single signal trace; on the other hand, it is also beneficial to reduce the overall resistance difference between different signal traces , because the wider average width of the outermost signal trace away from the display area can make up for the increase in resistance caused by the longer extension of the signal trace to a certain extent.
  • the width of the portion of each signal trace remote from the touch controller may vary from 3 microns to 50 microns.
  • the width of the signal trace is too large, the effect of reducing the overall resistance of the signal trace is gradually reduced, and it is easy to form a large capacitance with other components of the display device (for example, the cathode in the OLED display panel), which is not conducive to Touch performance of the display device.
  • the display device for example, the cathode in the OLED display panel
  • the display panels mentioned in the above embodiments may be various types of display panels, including but not limited to, for example, organic light emitting diode (OLED) display panels, liquid crystal display (LCD) panels, and the like.
  • OLED organic light emitting diode
  • LCD liquid crystal display
  • the above-mentioned touch electrode layer can be formed above the light-emitting layer. That is to say, the display panel also includes a pixel structure layer between the touch electrode layer and the base substrate, and the pixel structure layer includes an anode, a cathode, and an organic light-emitting layer therebetween.
  • the present disclosure provides a display device including the display panel described in the above embodiments.
  • the present disclosure does not limit the type or use of the display device.
  • the display device can be any electronic device or component with a display function. Examples of the display device include but are not limited to mobile electronic devices, navigators, watches, printers, computers. , PDAs, TVs, etc.
  • Another embodiment of the present disclosure also provides a method of fabricating a display panel, the method may include the following steps: B1. Provide a base substrate, the base substrate including a display area and a non-display around the display area B2, forming a touch electrode layer in the display area of the base substrate; B3, forming a plurality of signal traces in the first area adjacent to the non-display area and the display area, so The plurality of signal traces are electrically connected to the touch electrode layer; B4, a plurality of external dummy traces are formed in the second area of the non-display area, and the second area is located between the first area and all the Between the outer boundaries of the non-display area, the plurality of outer dummy wires and the plurality of signal wires are separated from each other.
  • steps B1-B4 listed in the above embodiment do not mean that these steps must be completed in sequence or in different processes, but only mean that the method for manufacturing a display panel described in this embodiment involves the above steps B1-B4.
  • the above-mentioned steps B2, B3 and B4 may be performed in the same process, that is, the touch electrode layer, the signal traces, and the outer dummy traces may be completed in the same fabrication process.
  • the touch electrode layer includes a plurality of first touch electrodes arranged in parallel and a plurality of second touch electrodes arranged in parallel, the plurality of first touch electrodes and The plurality of second touch electrodes cross each other.
  • Each of the first touch electrodes and each of the second touch electrodes includes a plurality of touch electrode blocks spaced apart from each other, and two adjacent touch electrode blocks of the plurality of touch electrode blocks are connected to each other via a bridge layer , wherein each signal line and each outer dummy line include a first metal line and a second metal line that are electrically connected to each other.
  • fabricating the touch electrode layer, the plurality of signal wires and the plurality of outer dummy wires includes: forming a first insulating layer on the base substrate; forming a first metal layer on the layer, and patterning the first metal layer to form the bridge layer and the first metal line; forming a patterned first metal layer on the bridge layer and the first metal line Two insulating layers; a patterned second metal layer is fabricated on the patterned second insulating layer to form the plurality of touch electrode blocks and the second metal lines, and the second metal lines pass through the Vias in the patterned second insulating layer are connected to the first metal lines.
  • the method for manufacturing the display panel further includes: based on the first metal layer and the second signal shielding line A metal layer, in which the first signal shielding wire and the second signal shielding wire are formed during the process of fabricating the plurality of signal wires and the plurality of external dummy wires. That is to say, the first signal shielding wire, the second signal shielding wire, the external dummy wire, the signal wire, and the touch electrode layer can all be fabricated in the same preparation process.
  • these intermediate dummy traces may be formed together in the process of preparing the outer dummy traces, the signal traces, and the touch electrode layer.
  • At least one of the first signal shielding wire, the second signal shielding wire, the outer dummy wire, the signal wire, and the middle dummy wire includes a double-layer wire (ie, the above-mentioned first metal wire and second metal wire).
  • a double-layer wire ie, the above-mentioned first metal wire and second metal wire.
  • a first insulating layer IN1 is formed on the base substrate, and the material for forming the first insulating layer IN1 includes but is not limited to SiNx.
  • a patterned first metal layer M1 is formed on the first insulating layer IN1 with a conductive material, and the material of the first metal layer M1 includes but is not limited to titanium, aluminum, silver, indium tin oxide, and any of them combination of materials, etc.
  • the pattern of the first metal layer M1 may include the pattern of the first metal line and the pattern of the bridge layer described in the above embodiments.
  • step S4 the second insulating layer IN2 is formed and patterned, so that some via holes exposing the first metal layer M1 are formed in the second insulating layer IN2 .
  • step S5 a second metal layer M2 is formed on the patterned second insulating layer IN2, and the second metal layer M2 is patterned.
  • the pattern of the second metal layer M2 may include the pattern of the second metal line and the pattern of the touch electrode block described in the above embodiments.
  • step S6 a protective layer PL is formed on the patterned second metal layer M2, and the material of the protective layer PL includes but is not limited to polyimide.

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Abstract

本公开的实施例公开了一种显示面板和包括该显示面板的显示装置。显示面板包括：衬底基板，所述衬底基板包括显示区和处于所述显示区周围的非显示区；位于所述衬底基板上的触控电极层，所述触控电极层处于所述衬底基板的所述显示区内；以及与所述触控电极层电连接的多条信号走线，所述多条信号走线分布在所述非显示区的与所述显示区相邻的第一区域内。该显示面板还包括处于所述非显示区的第二区域内的多条外虚设走线，所述第二区域位于所述第一区域和所述非显示区的外边界之间，所述多条外虚设走线与所述多条信号走线彼此分离。

Description

显示面板、显示装置及制作显示面板的方法 技术领域
本公开涉及显示技术领域，特别地，涉及一种显示面板、包括该显示面板的显示装置、以及制作该显示面板的方法。
背景技术
当前，触控技术已经普遍地应用到各种类型的显示装置中，例如，OLED触控显示装置、LCD触控显示装置，极大地提升了用户使用显示装置的体验。应用触控技术的显示装置通常包括触控IC芯片(也称为触摸控制器)，用于向显示装置中的触控电极发送控制信号或者接收来自于触控电极的感测信号，以确定用户的触摸位置。但是，对于现有的触控显示装置，触控性能仍有较大的改进空间。
发明内容
本公开的实施例提供了一种显示面板，该显示面板包括：衬底基板，所述衬底基板包括显示区和处于所述显示区周围的非显示区；位于所述衬底基板上的触控电极层，所述触控电极层处于所述显示区内；以及与所述触控电极层电连接的多条信号走线，所述多条信号走线分布在所述非显示区中与所述显示区相邻的第一区域内。所述显示面板还包括处于所述非显示区的第二区域内的多条外虚设走线，所述第二区域位于所述第一区域和所述非显示区的外边界之间，所述多条外虚设走线与所述多条信号走线彼此分离。
根据本公开的一些实施例，显示面板还包括位于所述非显示区内的第一信号屏蔽线和第二信号屏蔽线，所述第一信号屏蔽线的至少一部分处于所述第二区域和所述非显示区的外边界之间，所述第二信号屏蔽线处于所述第一信号屏蔽线和所述第一区域之间，所述多条外虚设走线包括处于所述第一信号屏蔽线和第二信号屏蔽线之间的至少一条第一虚设走线。
根据本公开的一些实施例，所述第一信号屏蔽线包括接地线，第二信号屏蔽线被配置成接收固定电位或方波信号。
根据本公开的一些实施例，触控电极层包括并行排列的多个第一 触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉，所述多条信号走线包括与相应的第一触控电极连接的多条第一信号走线和与相应的第二触控电极连接的多条第二信号走线，所述第二信号屏蔽线包括第一分段和第二分段。至少部分所述第一分段的延伸图案与所述多条第一信号走线中远离所述显示区的最外侧第一信号走线的延伸图案一致，至少部分所述第二分段的延伸图案与所述多条第二信号走线中远离所述显示区的最外侧第二信号走线延伸图案的一致。
根据本公开的一些实施例，所述第一分段与所述最外侧第一信号走线之间的间距等于所述最外侧第一信号走线与其相邻的第一信号走线之间的间距，所述第二分段与所述最外侧第二信号走线之间的间距等于所述最外侧第二信号走线与其相邻的第二信号走线之间的间距。
根据本公开的一些实施例，所述衬底基板包括处于所述非显示区内的弯折区，所述衬底基板经由所述弯折区形成第一部分和第二部分，所述第一部分包括所述显示区、所述第一区域和所述第二区域，所述多条外虚设走线还包括处于所述第二区域内并与所述弯折区相邻的至少一条第二虚设走线。
根据本公开的一些实施例，所述多条信号走线、所述第一信号屏蔽线和所述第二信号屏蔽线延伸至所述弯折区，所述至少一条第二虚设走线分布在所述第一信号屏蔽线和所述非显示区的外边界之间。
根据本公开的一些实施例，所述显示面板还包括处于所述多条信号走线中的至少一部分信号走线之间的至少一条中间虚设走线，所述至少一条中间虚设走线与所述多条信号走线彼此分离。
根据本公开的一些实施例，所述触控电极层包括并行排列的多个第一触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉，所述多条信号走线包括与相应的第一触控电极连接的多条第一信号走线和与相应的第二触控电极连接的多条第二信号走线，所述衬底基板包括处于所述非显示区内的弯折区，所述衬底基板经由所述弯折区形成第一部分和第二部分，所述第一部分包括所述显示区、以及所述非显示区的处于所述弯折区和所述显示区之间的中间非显示区，所述多条第一信号走线和所述多条第二信号走线延伸至所述中间非显示区，所述至少一条中间虚设走线包 括处于所述多条第一信号走线和所述多条第二信号走线之间、并处于所述中间非显示区的至少一条第三虚设走线。
根据本公开的一些实施例，所述显示面板还包括触摸控制器，所述触摸控制器布置在所述衬底基板的所述第二部分上，所述多条信号走线电连接至所述触摸控制器。
根据本公开的一些实施例，所述至少一条第一虚设走线中的各条第一虚设走线彼此间隔、且均匀地分布在所述第一信号屏蔽线和第二信号屏蔽线之间，所述至少一条第二虚设走线中的各条第二虚设走线彼此间隔、且均匀地分布在所述第一信号屏蔽线和非显示区的外边界之间。
根据本公开的一些实施例，所述外虚设走线、所述信号走线、以及所述中间虚设走线中的至少一个包括第一金属线和布置在第一金属线上方的第二金属线，所述显示面板还包括处于第一金属线和第二金属线之间的绝缘层，所述绝缘层包括过孔，所述第一金属线经由所述绝缘层中的过孔电连接至所述第二金属线。
根据本公开的一些实施例，所述第一金属线和第二金属线的材料包括钛、银和氧化铟锡中的至少一种。
根据本公开的一些实施例，所述显示面板还包括位于所述衬底基板上的封装坝，所述封装坝处于所述第一信号屏蔽线和所述非显示区的外边界之间，所述封装坝围绕所述第一信号屏蔽线在所述非显示区内延伸，且所述封装坝和所述第一信号屏蔽线之间保持固定的第一距离，所述第一信号屏蔽线与所述多条外虚设走线中同所述第一信号屏蔽线相邻的外虚设走线之间存在第二距离，所述第一距离和所述第二距离的比值大于1小于6。
根据本公开的一些实施例，所述衬底基板包括圆角部分，所述第二区域包括处于所述圆角部分内的弯曲区域和处于所述圆角部分外部的平直区域，所述弯曲区域包括第一空隙，所述平直区域包括第二空隙，所述第一空隙由所述多条外虚设走线中处于所述弯曲区域内的一条外虚设走线的端部和与该一条外虚设走线相邻的外虚设走线共同形成，所述第二空隙由所述多条外虚设走线中处于所述平直区域内的另一条外虚设走线的端部和与该另一条外虚设走线相邻的外虚设走线共同形成，所述第一空隙的面积大于所述第二空隙的面积。
根据本公开的一些实施例，所述多条信号走线中远离所述显示区的信号走线的平均宽度大于靠近所述显示区的信号走线的平均宽度。
根据本公开的一些实施例，所述显示面板还包括布置在所述衬底基板上的至少一条裂纹检测线，所述至少一条裂纹检测线位于非显示区的外边界和所述第一信号屏蔽线，所述至少一条裂纹检测线的延伸图案与所述第一信号屏蔽线的延伸图案一致。
根据本公开的一些实施例，所述至少一条裂纹检测线和所述第一信号屏蔽线之间存在第三距离，所述第一信号屏蔽线与所述多条外虚设走线中同所述第一信号屏蔽线相邻的外虚设走线之间的第二距离是所述第三距离的2至3倍。
根据本公开的一些实施例，显示面板还包括处于所述触控电极层和衬底基板之间的像素结构层，所述像素结构层包括阳极、阴极以及二者之间的有机发光层。
本公开的另一实施例提供了一种显示装置，包括如前述的任一实施例所述的显示面板。
通过在显示面板的非显示区布置本公开实施例所述的外虚设走线、中间虚设走线或者同同时布置这两种虚设走线，可以促进在制作显示面板过程中针对金属膜层的刻蚀工艺中的刻蚀均一性，从而有利于提升所制作的显示面板或显示装置的触控性能。
附图说明
图1示意性地示出了根据本公开的一个实施例的显示面板中的信号走线和外虚设走线的分布图；
图2示意性地示出了根据本公开的另一实施例的显示面板中的信号走线和外虚设走线的分布图；
图3示意性地示出了根据本公开的另一实施例的显示面板中的信号屏蔽线、信号走线和外虚设走线的分布图；
图4示意性地示出了图3中的衬底基板弯折之后的状态；
图5示意性地示出了根据本公开的又一实施例的显示面板中的信号屏蔽线、信号走线、外虚设走线和中间虚设走线的分布图；
图6示意性地示出了根据本公开的又一实施例的显示面板中的信号屏蔽线、信号走线、外虚设走线和中间虚设走线的分布图；
图7示意性地示出了根据本公开的另一实施例的显示面板的显示区周围的各类走线所在区域的总体轮廓；
图8-图10示意性地示出了图7中Q1所示区域的局部放大图；
图11示意性地示出了图7中Q2所示区域的放大图；
图12示意性地示出了图11中沿着线D1-D2的局部截面图；
图13示意性地示出了根据本公开的另一实施例的显示面板的单个像素区域的局部截面图；
图14示意性地说明根据本公开的又一实施例的制作显示面板中的触控电极层和非显示区中的各类走线的过程。
具体实施方式
下面，通过具体的示例详细说明本公开的一些实施例。应当理解到，下面描述的这些示例性实施例仅仅是为了解释和阐明本公开一些实施例的实现方式，并不表示真实显示面板或显示装置的结构，特别地，各个附图中所示的各类走线不代表实际产品中的走线的具体图案，而仅示意性地示出这些走线所处的位置以及与与显示面板的其他走线或区域的相对位置关系。而且，基于本文的描述的实施例和这些实施例所揭示的原理，本领域技术人员可以以其它不同的实施方式实施本公开的技术方案，从而获得与这里描述的实施例不同的另外的实施例，这些另外的实施例同样属于本专利申请的保护范围。因此，本文所描述的示例性实施例不构成对本专利申请保护范围的限制。
在触控显示装置的非显示区，通常布置有一些金属走线，这些金属走线将触摸控制器与触控显示装置中的触控电极电连接。这些金属走线从触摸控制器的端子引出，经由显示装置的非显示区延伸至触控电极层，分别与相应的触控电极连接。本申请的发明人发现，制作这些金属走线的过程往往会导致显示装置的触控性能的降低。具体地，处于显示装置的显示区外围的这些金属走线并不是均匀地分布在非显示区内。例如，对于具有矩形显示区的显示装置而言，金属走线可能分布在该显示区的四个边缘中的两个或三个边缘的外侧，而显示区的一个边缘的外围没有金属走线，或者，环绕该矩形显示区的非显示区的部分区域为不存在金属走线的空白区。发明人认识到，在制作非显示区的这些金属走线的过程中，难以保证针对金属膜层的刻蚀均一性， 而且，这种对金属膜层的不均一的刻蚀是影响显示装置的触控性能的一个因素。
鉴于上述的技术认知，本公开的一个实施例提出了一种显示面板，以促进触控显示装置的触控性能的提升。根据本公开实施例提供的显示面板包括衬底基板、触控电极层、多条信号走线以及多条外虚设走线。如图1所示，显示面板的衬底基板包括显示区A和处于显示区A周围的非显示区(例如，图1中示出的NA1、NA2)，触控电极层设置于衬底基板上、且位于显示区A内。显示面板还包括多条信号走线和多条外虚设走线，所述多条信号走线与触控电极层电连接、且分布在非显示区的第一区域NA1内，第一区域NA1与显示区A相邻。所述多条外虚设走线处于所述非显示区的第二区域NA2内，第二区域NA2处于第一区域NA1和非显示区的外边界OB之间。另外，如图1所示，第二区域NA2内的外虚设走线与第一区域NA1内的信号走线彼此分离。
本文提到的“虚设走线”(包括上面实施例提及的“外虚设走线”以及下文中将提到的“第一虚设走线”、“第二虚设走线”、“中间虚设走线”、“第三虚设走线”)指的是在显示面板或显示装置的运行中不起信号传输作用的走线，这些虚设走线可不与显示面板或显示装置的任何其它电气元件连接，在显示装置的运行过程中不接收任何的电信号，或者，这些虚设走线中的一部分或者全部仅与固定电位(例如，接地电位)电连接。另外，互相独立的多条虚设走线可以呈现任何样式的图案，本公开的实施例对各类虚设走线中的每条虚设走线的图案以及多条虚设走线的整体图案不作任何限制。
上述实施例中提到的“外虚设走线”是相对于下文其它实施例中描述的“中间虚设走线”而言的，意在用于区分这两种虚设走线所处位置方面的差异，但并存在针对虚设走线的任何属性或特征(例如，结构、图案、材料等)方面的任何限制。如上面的实施例所描述的，外虚设走线所在的第二区域处于非显示区中信号走线所在的第一区域和非显示区的外边界之间，而中间虚设走线布局在信号走线之间，具体将在下文的另外的实施例中描述。
图1示出了外虚设走线布置在非显示区的外边界OB和多条信号走线所在的第一区域NA1之间的一个角落区域的示例，图2示意性地示 出了外虚设走线的布置的另一示例。如图2所示，非显示区的第一区域NA1和非显示区的外边界OB之间存在三个第二区域NA2，其中一个第二区域NA2处于显示区A的上方，另外两个第二区域NA2处于显示区A的下方。根据本公开的一些实施例，第一区域NA1和第二区域NA2一起可形成围绕显示区A的环形区域。
形成非显示区内的信号走线的过程通常涉及对金属膜层的刻蚀工艺，对于本公开实施例提供的显示面板，在制作非显示区域的信号走线的同时，可同时制作出多条外虚设走线。这些外虚设走线与信号走线一起，使得最终形成的金属走线的材料更均匀地分布在显示区外围，相应地，在制作信号走线和外虚设走线的过程中，金属膜层的蚀刻均一性得以提升，从而有利于提升所制作的显示面板或显示装置的触控性能。本公开的实施例不对制作信号走线和外虚设走线的材料作任何限制，制作信号走线和外虚设走线的材料可以是具有导电性能的任何金属、金属氧化物、或金属合金材料，包括但不限于例如氧化铟锡(ITO)、银(Ag)、铝(Al)、钛(Ti)等。
根据本公开的一些实施例，显示面板的非显示区内还设置有信号屏蔽线，以减少信号走线受到外界信号的干扰。如图3所示，显示面板包括处于非显示区的第一信号屏蔽线P1和第二信号屏蔽线P2，第一信号屏蔽线P1的至少一部分处于第二区域NA2(布置有第一外虚设走线DT1)和非显示区的外边界OB之间，第二信号屏蔽线P2处于第一信号屏蔽线P1和第一区域(布置有信号走线T1、T2)之间。根据本公开的一些实施例，布置在非显示区的所述多条外虚设走线包括处于第一信号屏蔽线P1和第二信号屏蔽线P2之间的至少一条第一虚设走线DT1。在图3的实施例中，第一信号屏蔽线P1和第二信号屏蔽线P2基本上围绕显示区A延伸，第一信号屏蔽线P1和第二信号屏蔽线P2中的每个可以是无中断的连续走线，也可以被布置成包括若干个彼此间隔的分段。
在一些实施例中，第一信号屏蔽线P1可包括接地线，第二信号屏蔽线P2可被配置成接收固定电位或方波信号。如图3所示，第二信号屏蔽线P2沿着信号走线所在的第一区域NA1的外边缘延伸，第一信号线P1基本上包围第二信号屏蔽线P2，由此可以对第一区域内的信号走线T1、T2起到双重信号屏蔽的作用。如图3所示，在第一信号屏蔽 线P1和第二信号屏蔽线P2之间的较大的空隙区域形成多条第一虚设走线DT1，可以实现制作信号走线、第一信号屏蔽线P1和第二信号屏蔽线P2的过程中对金属膜层刻蚀的均一性，促进最终的触控显示面板或显示装置的触控性能的提升。
参考图4并结合参考图3，根据本公开的一些实施例，衬底基板是柔性衬底基板，或者衬底基板包括柔性区域，使得衬底基板是可弯曲的。图4示意性地示出了被弯折后的衬底基板100，图3示出了衬底基板未被弯折时的状态。衬底基板100包括处于非显示区内的弯折区BA，衬底基板100经由弯折区BA形成第一部分1A和第二部分2A，第一部分1A包括显示区A、非显示区的第一区域NA1和第二区域NA2，所述多条外虚设走线还包括处于第二区域NA2内并与所述弯折区BA相邻的至少一条第二虚设走线DT2。图4中的AX表示弯折区BA的弯曲轴，该弯曲轴可平行于衬底基板的一个侧边，衬底基板100可围绕弯曲轴AX弯曲，使得第二部分2A朝第一部分1A的背面弯曲，第一部分1A和第二部分2A可形成任何的角度，本公开的实施例对此不作任何的限制。在一些实施例中，可以将包括触摸控制器C在内的各种IC器件布置在第二部分2A，由此，在最终形成的显示装置中，这些IC器件可以被隐藏到第一部分1A的背面，可以实现全屏显示。在该情形中，所述多条信号走线电连接至触摸控制器C，如图3所示。
如图3所示，在一些实施例中，多条信号走线T1、T2、第一信号屏蔽线P1和第二信号屏蔽线P2延伸至弯折区BA，多条外虚设走线(第二虚设走线DT2)分别分布在第一信号屏蔽线P1和所述非显示区的外边界OB之间。在图3的示例中，多条第二虚设走线DT2位于显示区A和弯折区BA之间。这里的多条第二虚设走线DT2可实现与前述实施例中的第一虚设走线DT1类似的功能，即，可以促进制作信号走线、第一信号屏蔽线P1和第二信号屏蔽线P2的过程中对金属膜层刻蚀的均一性，有利于提升触控显示面板或显示装置的触控性能。此外，由于第二虚设走线DT2所在的区域靠近弯折区BA，同时且处于衬底基板的侧边缘区域，因此，这些第二虚设走线DT2还可以降低显示面板的侧边缘区域的膜层脱离衬底基板的风险，提升显示面板的结构的稳定性。
本公开实施例中提到的信号走线T1和信号走线T2表示与触控电 极层中的不同触控电极相连接的信号走线。例如，信号走线T1可以触控电极层中的发射电极相连，信号走线T2可以与触控电极层中的接收电极相连，发射电极和接收电极可以产生互电容，在触控显示装置运行过程中，触摸控制器可以向发射电极传送控制信号，并从接收电极接收感测信号，由此，可基于互电容的变化而确定用户的触摸位置。当然，触控电极层中的触控电极也可以基于自电容感测原理的结构，触控电极层的触控电极的具体排列和结构不是本公开的重点和关键，在此不再详述。
根据本公开的实施，多条第一虚设走线中的各条第一虚设走线之间是彼此独立的，多条第二虚设走线中的各条第二虚设走线之间也是彼此独立的，它们可以均匀地分布在非显示区的相应的区域内，以进一步有利于对金属膜层刻蚀的均一性。如图3所示，各条第一虚设走线DT1彼此间隔、且均匀地分布在第一信号屏蔽线P1和第二信号屏蔽线P2之间，各条第二虚设走线DT2彼此间隔、且均匀地分布在第一信号屏蔽线P1和非显示区的外边界OB之间内。图3中还示意性地示出了衬底基板上的封装坝所在的区域F。在该实施例中，第二虚设走线DT2可处于弯折区BA和封装坝所在的区域F之间。
在图3的实施例中，多条第一虚设走线DT1中的各条第一虚设走线DT1之间的间距等于第二信号屏蔽线P2与多条第二信号走线T2中最靠近第二信号屏蔽线P2的第二信号走线T2之间的间距。进一步地，多条第一虚设走线DT1中最靠近第一信号屏蔽线P1的第一虚设走线的宽度等于所述第一信号屏蔽线P1的宽度，多条第一虚设走线DT1中最靠近所述第二信号屏蔽线P2的第一虚设走线的宽度等于第二信号屏蔽线P2的宽度。由此，可以有利于实现多条第一虚设走线DT1、第一信号屏蔽线P1、第二信号屏蔽线P2以及多条第二信号走线T2的整体分布的均一性，进一步促进对金属膜层的蚀刻均一性。能够理解到的是，本文提到的“等于”或“相等”并不限于或者追求绝对意义上的相等或等于，而是表示让两个参数的值尽可能地接近或相等。例如，各条第一虚设走线DT1之间的间距、第二信号屏蔽线P2与最靠近第二信号屏蔽线P2的第二信号走线T2之间的间距二者之间的差可能在各条第一虚设走线DT1之间的间距的％5以内。
根据本公开的一些实施例，触控电极层包括并行排列的多个第一 触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉。接着参照图3，所述多条信号走线包括分别与相应的第一触控电极连接的多条第一信号走线T1和分别与相应的第二触控电极连接的多条第二信号走线T2，所述第二信号屏蔽线P2包括第一分段P21和第二分段P22。第一分段P21的延伸图案与所述多条第一信号走线中远离显示区A的最外侧第一信号走线T1的延伸图案一致，第二分段P22的延伸图案与所述多条第二信号走线T2中远离所述显示区的最外侧第二信号走线延伸图案的一致。进一步地，在一些实施例中，第一分段P21与最外侧第一信号走线之间的间距等于最外侧第一信号走线与其相邻的第一信号走线之间的间距，第二分段P22与最外侧第二信号走线之间的间距等于所述最外侧第二信号走线与其相邻的第二信号走线之间的间距。类似地，第二信号屏蔽线的这种布置有利于促进对金属膜层的蚀刻均一性。在图3的示例中，第一分段P21和第二分段P22是彼此分离的，在其它实施例中，第一分段P21和第二分段P22可以互相连接形成一体的第二信号屏蔽线。
尽管图1至图3的示例性实施例中，触控电极层中的每个触控电极被示出为仅与一条信号走线相连，例如，图3中的信号走线T1可以与触控电极层中的发射电极相连，信号走线T2可以与触控电极层中的接收电极相连，但是这并不构成本公开实施例的任何限制。在另外的实施例中，每个触控电极可以与两条信号走线相连。例如，如图5所示，触控电极层中的每个发射电极的两端(上端和下端)分别与信号走线T11和信号走线T12相连，每个接收电极与信号走线T2相连。当然，在其它的实施例中，每个接收电极可以与两条信号走线相连，或者，每个发射电极和每个接收电极均与两条信号走线相连。总之，本公开的实施例并不对触控电极层中的触控电极和信号走线的布局、以及触控电极和信号走线之间的连接方式作出任何具体的限制，本公开实施例所揭示的利用虚设走线改善触控显示装置的触控性能的技术措施不受触控电极和信号走线之间的连接方式的限制。
根据本公开的一些实施例，显示面板还包括处于所述多条信号走线之间的至少一条中间虚设走线，这些中间虚设走线与所述多条信号走线彼此分离。本文提到的中间虚设走线可以布置在上述的多条第一信号走线之间，也可以布置在上述的多条信号走线之间，或者，还可 以布置在第一信号走线和第二信号走线之间。接着参照图5，多条中间虚设走线DT3被形成在信号走线T2和信号走线T12之间。也就是说，在与发射电极相连的信号走线T12和与接收电极相连的信号走线T2存在较大间隙的情形中，可以在二者之间形成另外的虚设走线(即，中间虚设走线DT3)。同样地，可以在其它的信号走线之间的间隙中布置中间虚设走线，例如，可以在与同类型的触控电极相连的不同信号走线之间的间隙中形成中间虚设走线。如图6所示，中间虚设走线DT3被示出为可存在于与发射电极相连的信号走线T1之间、与接收电极相连的信号走线T2之间、以及信号走线T1和信号走线T2之间。也就是说，根据本公开的另外的实施例，可以在多条信号走线中的任何两条信号走线之间布置中间虚设走线。这些中间虚设走线DT3可实现与前述实施例中的第一虚设走线DT1、第二虚设走线DT2至少部分类似的功能，即，可以促进制作信号走线过程中对金属膜层刻蚀的均一性，从而有利于提升触控显示面板或显示装置的触控性能。如前所述，根据本公开的一些实施例，衬底基板包括处于非显示区内的弯折区，衬底基板经由所述弯折区形成第一部分和第二部分，如图3和4所示。第一部分包括所述显示区、以及所述非显示区的处于所述弯折区和所述显示区之间的中间非显示区(如图3中所示，显示区A和弯折区BA之间的非显示区可被称作中间非显示区)，多条第一信号走线和多条第二信号走线可延伸至所述弯折区。如图3所示，在一些实施例中，所述至少一条中间虚设走线包括处于多条第一信号走线T1和多条第二信号走线T2之间、并处于中间非显示区的至少一条第三虚设走线DT3。该实施例中的第三虚设走线DT3可起到与前述实施例中的第二虚设走线DT2类似的作用，可以促进制作信号走线、第一信号屏蔽线P1和第二信号屏蔽线P2的过程中对金属膜层刻蚀的均一性，有利于提升触控显示面板或显示装置的触控性能。此外，由于第三虚设走线DT3靠近弯折区BA，这些第三虚设走线DT3还可以降低显示面板的弯折区附近的膜层脱离衬底基板的风险，提升显示面板的结构的稳定性。进一步地，根据本公开的另外的实施例，可以在多条第一信号走线T1和与其相邻的第三虚设走线DT3之间布置第二信号屏蔽线的材料，也可以在多条第一信号走线T2和与其相邻的第三虚设走线DT3之间布置第二信号屏蔽线的材料，换句话说，在第二信号屏蔽线可以延伸至中间 非显示区中的多条第一信号走线T1或多条第二信号走线T2的两侧。
根据本公开的实施例，信号走线、虚设走线、以及信号屏蔽线中的每个可以包括两条以上的金属线，这些金属线可彼此电连接、但分布在不同的层中，以有利于走线的整体电阻的降低。在一个示例中，每条信号走线T1、T2和每条虚设走线DT1、DT2、DT3均包括第一金属线和布置在第一金属线上方的第二金属线，显示面板还包括处于第一金属线和第二金属线之间的绝缘层，该绝缘层包括过孔，第一金属线经由所述绝缘层中的过孔电连接至第二金属线。
下面，结合图7至图11进一步说明本公开实施例中的信号走线、外虚设走线、第一信号屏蔽线和第二信号屏蔽线的示例。
图7图示了显示面板的显示区周围的各种走线所在区域的整体轮廓。图8为图7的Q1区域的放大示意图。如图8所示，第一信号屏蔽线P1(在该示例中为接地线GND)布置在信号走线T1、T2的外侧，两段第二信号屏蔽线P2分别紧挨着第一信号走线T1和第二信号走线T2，以减少或避免外界信号干扰第一信号走线T1和第二信号走线T2。多条外虚设走线(在图8中被标识为Dummy Trace)布置在第一信号屏蔽线P1和第二信号屏蔽线P2之间。图8中还图示了封装坝Dam1、Dam2，封装坝同样位于非显示区并围绕显示区而设置，封装坝可处于所述第一信号屏蔽线和所述非显示区的外边界之间。图7的示例示出了两个封装坝Dam1、Dam2，但是，在另外的示例中，封装坝的数量可以为一个或者两个以上。各个封装坝可以具有相同或者不同的膜层结构。在一个示例中，封装坝可包括依次层叠设置的保护部和阻隔部。在另一示例中，封装坝还可包括位于阻隔部上方的支撑部。保护部、阻隔部和支撑部中的至少一个可以与显示面板显示区中的一个膜层处于同层。例如，在OLED显示面板中，封装坝的阻隔部可以与像素界定层处于同一层。
根据本公开的一些实施例，封装坝围绕第一信号屏蔽线在非显示区内延伸，且封装坝和第一信号屏蔽线之间保持固定的第一距离，第一信号屏蔽线与所述多条外虚设走线中同所述第一信号屏蔽线相邻的外虚设走线之间存在第二距离，第一距离和第二距离的比值大于1小于6。例如，结合图7参考图8，第一信号屏蔽线P1和封装坝Dam1在显示面板的右上方圆角某一区域之间的距离a等于第一信号屏蔽线 P1和封装坝Dam1在显示面板的顶部平直区域之间的距离b。根据本公开的一些实施例，第一信号屏蔽线和封装坝之间的第一距离大于第一信号屏蔽线和与该第一信号屏蔽线相邻的外虚设走线之间的第二距离。在一个示例中，上述的第一距离和第二距离之间的比值可以在1至6的范围内。如图8所示，第一信号屏蔽线P1和封装坝Dam1之间的距离a或b可为40μm-170μm，第一信号屏蔽线P1和与该第一信号屏蔽线P1相邻的外虚设走线之间的第二距离d可为30μm-40μm。在另外的示例中，第一信号屏蔽线P1和封装坝Dam1之间的距离a或b可为75μm-120μm或75μm-130μm。
根据本公开的一些实施例，第一信号屏蔽线P1的宽度大于第二信号屏蔽线P2的宽度。第一信号屏蔽线P1的宽度可以是第二信号屏蔽线P2的宽度的3-5倍。在图8的示例中，第二信号屏蔽线P2具有3μm-5μm的宽度，而第一信号屏蔽线具有大约15μm的宽度。
在图9中，不仅示出了多条信号走线T1、T2、外虚设走线Dummy Trace、第一信号屏蔽线P1、第二信号屏蔽线P2，还图示了包括多个触控电极块E的触控电极。根据本公开的一些实施例，触控电极层包括并行排列的多个第一触控电极和并行排列的多个第二触控电极，第一触控电极和第二触控电极相互交叉。每个第一触控电极和每个第二触控电极可包括彼此间隔的多个触控电极块，多个触控电极块中相邻的两个触控电极块经由桥接层而彼此连接。图9图示了多个触控电极块，一行或一列触控电极块经由桥接层(图7中未示出)彼此电连接而形成第一触控电极或第二触控电极。这里提到的第一触控电极或第二触控电极可以是前述的发射电极或者接收电极。如图9所示，由触控电极块E形成的第一触控电极和第二触控电极分别与第一信号走线T1或第二信号走线T2连接。在一些实施例中，触控电极块E可与上述的第二金属线由相同的材料、并在同一工艺中制成。触控电极块E和第二金属线所作的层在图9中被标识为Metal2 Layer。
根据本公开的一些实施例，衬底基板还包括布置在衬底基板上的至少一条裂纹检测线。在图9的示例中，裂纹检测线PCD位于非显示区的外边界和第一信号屏蔽线P1之间，裂纹检测线PCD可以围绕第一信号屏蔽线P1，其延伸图案可以与第一信号屏蔽线P1的延伸图案一致。在制作显示面板的过程中，可能涉及对衬底基板进行切割或类似 的机械工艺，例如，基于制作好的母板切割出多个显示面板单元，或者切除显示面板的不必要的外缘部分。在机械切割的过程中，显示面板或衬底基板在切口处可能产生裂纹，裂纹检测线PCD至少可以防止裂纹损害显示面板，或者说，有了裂纹检测线，裂纹可以停止于裂纹检测线，而不会再朝显示区的方向进一步延伸。在一些实施例中，裂纹检测线PCD可以与上述的触控电极块E和第二金属线在同一工艺中制作，即，裂纹检测线所在的层在图9中也被标识为Metal2 Layer。
根据本公开的一些实施例，裂纹检测线和第一信号屏蔽线P1之间的第三距离小于上述的第二距离d(即，第一信号屏蔽线P1和与该第一信号屏蔽线P1相邻的外虚设走线之间的第二距离)。在一个示例中，第一信号屏蔽线P1和与该第一信号屏蔽线P1相邻的外虚设走线之间的第二距离是上述的第三距离的2-3倍。如前所述，在第二距离d可为30μm-40μm，裂纹检测线PCD和第一信号屏蔽线P1之间的第三距离约为14μm。
进一步地，根据本公开的一些实施例，显示面板包括两条裂纹检测线，如图9所示。这两条裂纹检测线的延伸图案相同，可以与第一信号屏蔽线P1一致，且这两条裂纹检测线之间的间距保持大致恒定。在一些实施例中，每条裂纹检测线可具有4μm的宽度，两条裂纹检测线之间可保持15μm左右的间距。
根据本公开的一些实施例，衬底基板包括圆角部分，第二区域包括处于所述圆角部分内的弯曲区域和处于所述圆角部分外部的平直区域，所述弯曲区域包括第一空隙，所述平直区域包括第二空隙。第一空隙由所述多条外虚设走线中处于所述弯曲区域内的一条外虚设走线的端部和与该一条外虚设走线相邻的外虚设走线共同形成，所述第二空隙由所述多条外虚设走线中处于所述平直区域内的另一条外虚设走线的端部和与该另一条外虚设走线相邻的外虚设走线共同形成，所述第一空隙的面积大于所述第二空隙的面积。
继续参照图7和图9，非显示区的多条外虚设走线中的一些外虚设走线可围成小的空隙，这些小的空隙可与某条或某些外虚设走线的端部有关。图9示意性地示出了两条外虚设走线的端部分别与其他的外虚设走线围成的空隙S1、S2。图9中示意性地示出的空隙S1和S2可分别对应于上述的第一空隙S1和第二空隙S2。第一空隙S1由所述多 条外虚设走线Dummy Trace处于弯曲区域内的一条外虚设走线DTa的端部和与该一条外虚设走线DTa相邻的外虚设走线共同形成，第二空隙S2由多条外虚设走线Dummy Trace中处于所述平直区域内的另一条外虚设走线DTb的端部和与该另一条外虚设走线相邻的外虚设走线共同形成，第一空隙S1的面积大于第二空隙S2的面积。外虚设走线之间的诸如上述的第一空隙和第二空隙之类的空隙可以有效地防止或降低可能聚集在外虚设走线的端部处的静电对其他外虚设走线的影响。如图9所示，处于弯曲区域的第一外虚设走线DTa的端部大致呈锥体形状，使得第一空隙S1的面积较大，便利于弯曲区域外虚设走线的制作，同时也能防止或降低可能聚集在外虚设走线的端部处的静电导致的不利影响。
图10示出了上述示例中提及的第一金属线，第一金属线可以处于第二金属线的下方，在图10中，第一金属线所在的层被标识为Metal1 Layer。上述的桥接层(图10中未示出)可以用与第一金属线相同的材料、在同一工艺中制成。由此，能够理解到的是，图9同样表示了Metal2 Layer中的部分的走线布局。
根据本公开的一些实施例，用于制作第一金属线和第二金属线的材料包括钛、银和氧化铟锡中的至少一种。在一个示例中，第一金属线和第二金属线中的至少一个包括铝层以及位于所述铝层两侧的钛层。或者，第一金属线和第二金属线中的至少一个包括银层以及位于所述银层两侧的氧化铟锡层。由此，第一金属线可包括Ti/Al/Ti三层金属结构或者ITO/Ag/ITO三层金属结构，同样地，第二金属线也可包括Ti/Al/Ti三层金属结构或者ITO/Ag/ITO三层金属结构。
图11图示了图7所示的两个Q2区域的局部放大示意图，即，图11可以被视为图7中的两个Q2区域合并后放大示意图。结合图7、图11和图4，图11所示的非显示区仍位于衬底基板的第一部分1A，衬底基板的弯曲部分BA在图11中没有被示出，如果衬底基板处于平直状态，弯曲部分可以位于图11所示的区域的正下方。如图11所示，多个外虚设走线DT2(即，前述实施例中提到的第二虚设走线)分布在第二区域内，并且位于多条信号走线的两侧，且位于第一信号屏蔽线P1(例如，GND线)的外侧，如图11中的矩形虚线框所示。如前所述，在制作显示面板的过程中增加第二虚设走线DT2的制作可以促 进对金属膜层刻蚀的均一性，有利于提升触控显示面板或显示装置的触控性能，同时，第二虚设走线DT2靠近弯曲区，还可以降低其所在区域及相邻区域的膜层在衬底基板弯曲过程中脱离衬底基板的风险，提升显示面板的结构的稳定性。
如前所述，在本公开的一些实施例中，包括信号走线在内的各个走线包括双层金属线，以降低信号走线的电阻，同时便利于各种走线与触控电极层的制作过程。在一些实施例中，不同区域的信号走线的第一金属线可以采用不同的材料制成，或者，不同区域的信号走线中的第一金属线可以在不同的制备工艺中完成。例如，对于可弯折的显示面板，衬底基板经由弯折区形成第一部分和第二部分，所述第一部分包括所述非显示区的处于弯折区和显示区之间的中间非显示区，图11可被视为中间非显示区的局部示意图的一个示例。如图11所示，SD可表示与显示面板显示区中薄膜晶体管的源极或漏极同层但是相互隔离的结构，即，本文所提到的源漏信号线。在一些实施例中，源漏信号线SD与一部分外虚设走线(例如，图11中示出的第二虚设走线DT2)至少存在部分重叠面积，且相互绝缘。进一步地，源漏信号线SD可以与至少一部分信号走线存在部分重叠面积，且相互绝缘。
根据本公开的另外的实施例，显示面板还包括用于将像素电极(例如，OLED显示面板的有机发光器件的阳极)和薄膜晶体管的源极或漏极电连接的转接电极，在该情形中，图11中的SD可以表示与转接电极同层且相互隔开的结构，即，本文中提到的转接电极信号线。在一些实施例中，转接电极信号线与至少一部分外虚设走线至少存在部分重叠面积，且相互绝缘。进一步地，转接电极信号线SD与至少一部分信号走线至少存在部分重叠面积，且相互绝缘。在一些实施例中，如图11所示，源漏信号线SD或者转接电极信号线SD还设置有多个开孔，用于释放下层膜层的气体。至少一个开孔与至少一部分外虚设走线至少存在部分重叠面积。进一步地，至少一个开孔与至少一部分信号走线至少存在部分重叠面积。
根据本公开的一些实施例，在上述的弯折区内，包括信号走线在内的各类走线中的至少一类走线可以借助于显示面板的其它导电结构实现。例如，显示面板可包括像素电极和用于驱动显示面板的像素发光的薄膜晶体管，显示面板的像素驱动电路中的与薄膜晶体管的源漏 极在同一工艺中形成的上述源漏信号线可以充当信号走线。参见图11和12，图12示意性地示出了图11中的中间非显示区临近弯折区的区域沿着D1-D2方向的截面图，其中M2表示第二金属线，SD表示充当第一金属线的源漏信号线。根据本公开的一些实施例，在弯折区内，可以利用显示面板中的上述的其它导电结构作为上述的各类走线，因此，第二金属线和第一金属线可不延伸至弯折区，所述其它导电结构在弯折区内延伸到达例如上述的第二部分时，其可与第二部分中的第二金属线电连接。也就是说，在第二部分中，包括信号走线在内的各类走线可以具有图7中的Q1区域中的信号走线类似的结构，即，包括彼此电连接的第一金属线和第二金属线。
如前所述，在一些实施例中，显示面板还包括用于将像素电极和薄膜晶体管的源极或漏极电连接的转接电极、以及与所述转接电极在同一制作工艺中形成的转接电极信号线，同样地，可以利用转接电极信号线充当弯折区内的各类走线，因此，在中间非显示区靠近弯折区的区域，转接电极信号线通过贯穿其上方的第二绝缘层的过孔而与第二金属线电连接，这同样地可由图12示意性地示出。在弯折区内，可利用转接电极信号线充当各类走线，此时，第二金属线和第一金属线都不延伸至弯折区。转接电极信号线在弯折区内延伸到达例如上述的第二部分时，其可与第二部分中的第二金属线电连接。同样地，在第二部分中，包括信号走线在内的各类走线可以具有图7中的Q1区域中的信号走线类似的结构，即，包括彼此电连接的第一金属线和第二金属线。
图13示意性地示出了包括转接电极的显示面板的局部截面图。如图13所示，显示面板包括衬底基板100和位于衬底基板上的像素驱动电路和发光器件。像素驱动电路可包括薄膜晶体管和电容器，电容器包括第一电容电极112和第二电容电极113，薄膜晶体管包括有源层108、栅极109、源极110和漏极111。发光器件包括阳极1141、发光功能层1142和阴极1143。如图13所示，显示面板还包括处于源极110和阳极1141之间的转接电极121，转接电极121穿透绝缘层将像素电极(例如，阳极1141)与源极110电连接。对于图13所示的显示面板，可以在制作转接电极121的过程中，形成上述的转接电极信号线，该转接电极信号线可作为上述的中间非显示区内的第一金属线。根据本 公开的又一实施例，显示面板可包括像素驱动电路，像素驱动电路包括电容器，电容器包括电容电极，例如图13中的第一电容电极112和第二电容电极113，所述显示面板还包括与电容电极(例如，第二电容电极113)在同一制作工艺中形成、处于所述非显示区的电容信号线。
根据本公开的另外的实施例，上述提及的其它导电结构可以包括与栅极同层形成的导电结构或电容信号线，也可以是上述提及到的各种导电结构的组合，例如，电容信号线和转接电极信号线可以一起作为弯折区的信号走线，或者，转接电极信号线可以只在中间非显示区临近弯折区的区域起电连接作用，而不作为信号走线。弯折区内包括信号走线的各类走线可以根据需求进行设计，在此不做限制。如前所述，弯折区位于图11所示的线D1-D2所在区域的下方，这里不再示出。
本文提到的“源漏信号线”、“转接电极信号线”、“电容信号线”并不是指源漏极转接电极、或者电容器自身，而是分别指在制作源漏极、转接电极、以及电容器的过程中在衬底基板的非显示区上与源漏极、转接电极或者电容器电极一同形成的信号线，因此，它们与源漏极、转接电极或电容电极具有相同的材料，但不与源漏极、转接电极或电容电极连接。
进一步地，根据本公开的另外的实施例，上述的中间非显示区内的第一金属线可包括转接电极信号线、源漏信号线以及电容信号线中的至少一者。或者说，转接电极信号线、源漏信号线以及电容信号线中的任何两个或更多可同时充当第一金属线。例如，中间非显示区内的第一金属线可包括源漏信号线和转接电极信号线，或者可包括转接电极信号线和电容信号线。
在一些实施例中，从触摸控制器延伸至显示区的触控电极层的每条信号走线T1、T2的宽度并不是保持不变的，例如，每条信号走线的靠近触摸控制器的部分的宽度要小于远离触摸控制器的部分的宽度，这是因为触摸控制器附近的用于布局信号走线的空间要小于远离触摸控制器的区域中的布线空间。例如，可以让信号走线从触摸控制器到触控电极层逐渐变宽，这样可以减小信号走线的整体电阻。在一些实施例中，多条信号走线中的不同信号走线的宽度也存在差异。例如，可以将这些信号走线布置成越是远离显示区，宽度越大。也就是说，所述多条信号走线中远离显示区的信号走线的平均宽度大于靠近显示 区的信号走线的平均宽度。这样，一方面，可以充分利用距离显示区相对较远区域的相对富裕的布线空间，降低单个信号走线的电阻，另一方面，还有利于缩小不同的信号走线之间的整体电阻的差异，因为远离显示区而处于最外侧的信号走线的较宽的平均宽度可以在一定程度上弥补由于该信号走线延伸长度较长导致的电阻增加。在一个示例中，各条信号走线远离触摸控制器的部分的宽度可在3微米到50微米之间变化。如果信号走线的宽度过大，信号走线的整体电阻的降低的效果也逐渐减小，而且容易与显示装置的其他部件(例如，OLED显示面板中的阴极)形成较大的电容，不利于显示装置的触控性能。对于本公开的实施例，通过设置一定数量的虚设走线，有利于实现制作信号走线的过程中对金属膜层进行均一性的刻蚀，提升触控显示面板或显示装置的触控性能，同时，也允许实现信号走线的合理的较大的宽度，尽可能缩小不同的信号走线之间的电阻差异。
上述实施例中提到的显示面板可以是各种类型的显示面板，包括但不限于例如有机发光二极管(OLED)显示面板、液晶显示(LCD)面板等。在OLED显示面板的情形中，上述的触控电极层可以制作在发光层的上方。也就是说，显示面板此时还包括处于触控电极层和衬底基板之间的像素结构层，所述像素结构层包括阳极、阴极以及二者之间的有机发光层。
本公开的另一实施例提供了一种显示装置，该显示装置包括上述实施例所述的显示面板。本公开并不对显示装置的类型或用途进行任何的限定，该显示装置可以是任何具有显示功能的电子设备或部件，显示装置的示例包括但不限于移动电子设备、导航仪、手表、打印机、计算机、掌上电脑、电视机等等。
本公开的另外的实施例还提供了一种制作显示面板的方法，该方法可包括如下步骤：B1、提供衬底基板，所述衬底基板包括显示区和处于所述显示区周围的非显示区；B2、在所述衬底基板的所述显示区内形成触控电极层；B3、在所述非显示区与所述显示区相邻的第一区域内形成多条信号走线，所述多条信号走线与所述触控电极层电连接；B4、在所述非显示区的第二区域内形成多条外虚设走线，所述第二区域处于所述第一区域和所述非显示区的外边界之间，所述多条外虚设走线与所述多条信号走线彼此分离。
上述实施例列出的各个步骤B1-B4并不意味着这些步骤必须先后依次完成或者在不同的工艺制程中完成，而是仅仅意味着该实施例所述的制作显示面板的方法涉及上述的步骤B1-B4。例如，根据本公开的一些实施例，上述的步骤B2、B3和B4可以在同一工艺中进行，即，触控电极层、信号走线、外虚设走线可以在同一制备工艺中完成。
如前所述，根据本公开的一些实施例，触控电极层包括并行排列的多个第一触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉。每个第一触控电极和每个第二触控电极包括彼此间隔的多个触控电极块，所述多个触控电极块中相邻的两个触控电极块经由桥接层而彼此连接，其中每条信号走线和每条外虚设走线包括彼此电连接的第一金属线和第二金属线。在该情形中，制作所述触控电极层、所述多条信号走线以及所述多条外虚设走线包括：在所述衬底基板上形成第一绝缘层；在所述第一绝缘层上形成第一金属层，并使所述第一金属层图案化以形成所述桥接层和所述第一金属线；在所述桥接层、所述第一金属线上形成图案化的第二绝缘层；在所述图案化的第二绝缘层上制作图案化的第二金属层，以形成所述多个触控电极块和所述第二金属线，所述第二金属线经由所述图案化的第二绝缘层中的过孔连接至所述第一金属线。
在显示面板还包括上述的处于所述非显示区的第一信号屏蔽线和第二信号屏蔽线的实施例中，制作显示面板的方法还包括：基于所述第一金属层和所述第二金属层，在制作所述多条信号走线以及多条外虚设走线的过程中形成所述第一信号屏蔽线和第二信号屏蔽线。也就是说，第一信号屏蔽线、第二信号屏蔽线、外虚设走线、信号走线、触控电极层均可在同一制备工艺中制作完成。
进一步地，在显示面板还包括前述实施例中描述的中间虚设走线的情形中，可以在制备外虚设走线、信号走线、触控电极层的过程中一同形成这些中间虚设走线。
根据本公开的一些实施例，第一信号屏蔽线、第二信号屏蔽线、外虚设走线、信号走线中以及中间虚设走线中的至少一个包括双层走线(即，上述的第一金属线和第二金属线)。为了简便起见，下面结合图14的示例概括性地说明出制备上述的第一信号屏蔽线、第二信号屏蔽线、外虚设走线和信号走线的过程。如图14所示，在步骤S1中， 提供衬底基板，该衬底基板上可制备有显示面板一些必要的部件，例如，对于OLED显示面板，衬底基板上可制备有像素驱动电路、像素结构层(例如，包括阳极、有机发光层、阴极)。在步骤S2中，在衬底基板上形成第一绝缘层IN1，形成第一绝缘层IN1的材料包括但不限于SiNx。在步骤S3中，在第一绝缘层IN1上用导电材料形成图案化的第一金属层M1，第一金属层M1的材料包括但不限于钛、铝、银、氧化铟锡、以及它们中任何材料的组合等等。第一金属层M1的图案可包括上述实施例中所述的第一金属线的图案和桥接层的图案。在步骤S4中，形成第二绝缘层IN2并对其进行图案化处理，使得第二绝缘层IN2中形成一些露出第一金属层M1的过孔。在步骤S5中，在图案化的第二绝缘层IN2上形成第二金属层M2，并对第二金属层M2进行图案化处理。第二金属层M2的图案可包括上述实施例中所述的第二金属线的图案和触控电极块的图案。在步骤S6中，在图案化的第二金属层M2上形成保护层PL，保护层PL的材料包括但不限于聚酰亚胺。
以上具体描述了本公开的一些示例性实施例，但是本领域技术人员在实践所要求保护的公开时根据对附图、公开内容已经权利要求的研究，能够理解和实现所公开实施例的其他变型。在权利要求中，词语“包括”不排除其它元件的存在。虽然一些特征被记载在不同的从属权利要求中，但是本公开也意图涵盖将这些特征组合在一起的实施例。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板，所述衬底基板包括显示区和处于所述显示区周围的非显示区；
    位于所述衬底基板上的触控电极层，所述触控电极层处于所述显示区内；以及
    与所述触控电极层电连接的多条信号走线，所述多条信号走线分布在所述非显示区中与所述显示区相邻的第一区域内，
    其中所述显示面板还包括处于所述非显示区的第二区域内的多条外虚设走线，所述第二区域位于所述第一区域和所述非显示区的外边界之间，
    其中所述多条外虚设走线与所述多条信号走线彼此分离。
  2. 如权利要求1所述的显示面板，其中所述显示面板还包括位于所述非显示区内的第一信号屏蔽线和第二信号屏蔽线，所述第一信号屏蔽线的至少一部分处于所述第二区域和所述非显示区的外边界之间，所述第二信号屏蔽线处于所述第一信号屏蔽线和所述第一区域之间，其中所述多条外虚设走线包括处于所述第一信号屏蔽线和第二信号屏蔽线之间的至少一条第一虚设走线。
  3. 如权利要求2所述显示面板，其中所述第一信号屏蔽线包括接地线，第二信号屏蔽线被配置成接收固定电位或方波信号。
  4. 如权利要求2所述的显示面板，其中所述触控电极层包括并行排列的多个第一触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉，其中所述多条信号走线包括与相应的第一触控电极连接的多条第一信号走线和与相应的第二触控电极连接的多条第二信号走线，所述第二信号屏蔽线包括第一分段和第二分段，
    其中至少部分所述第一分段的延伸图案与所述多条第一信号走线中远离所述显示区的最外侧第一信号走线的延伸图案一致，至少部分所述第二分段的延伸图案与所述多条第二信号走线中远离所述显示区的最外侧第二信号走线延伸图案的一致。
  5. 如权利要求4所述的显示面板，其中所述第一分段与所述最外 侧第一信号走线之间的间距等于所述最外侧第一信号走线与其相邻的第一信号走线之间的间距，所述第二分段与所述最外侧第二信号走线之间的间距等于所述最外侧第二信号走线与其相邻的第二信号走线之间的间距。
  6. 如权利要求2所述的显示面板，其中所述衬底基板包括处于所述非显示区内的弯折区，所述衬底基板经由所述弯折区形成的第一部分和第二部分，其中所述第一部分包括所述显示区、所述第一区域和所述第二区域，其中所述多条外虚设走线还包括处于所述第二区域内并与所述弯折区相邻的至少一条第二虚设走线。
  7. 如权利要求6所述的显示面板，其中所述多条信号走线、所述第一信号屏蔽线和所述第二信号屏蔽线延伸至所述弯折区，其中所述至少一条第二虚设走线分布在所述第一信号屏蔽线和所述非显示区的外边界之间。
  8. 如权利要求1所述的显示面板，其中所述显示面板还包括处于所述多条信号走线中的至少一部分信号走线之间的至少一条中间虚设走线，所述至少一条中间虚设走线与所述多条信号走线彼此分离。
  9. 如权利要求8所述的显示面板，其中所述触控电极层包括并行排列的多个第一触控电极和并行排列的多个第二触控电极，所述多个第一触控电极和所述多个第二触控电极相互交叉，其中所述多条信号走线包括与相应的第一触控电极连接的多条第一信号走线和与相应的第二触控电极连接的多条第二信号走线，
    其中所述衬底基板包括处于所述非显示区内的弯折区，所述衬底基板经由所述弯折区形成第一部分和第二部分，其中所述第一部分包括所述显示区、以及所述非显示区的处于所述弯折区和所述显示区之间的中间非显示区，
    其中所述多条第一信号走线和所述多条第二信号走线延伸至所述中间非显示区，所述至少一条中间虚设走线包括处于所述多条第一信号走线和所述多条第二信号走线之间、并处于所述中间非显示区的至少一条第三虚设走线。
  10. 如权利要求6所述的显示面板，其中所述显示面板还包括触摸控制器，所述触摸控制器布置在所述衬底基板的所述第二部分上，所述多条信号走线电连接至所述触摸控制器。
  11. 如权利要求7所述的显示面板，其中所述至少一条第一虚设走线中的各条第一虚设走线彼此间隔、且均匀地分布在所述第一信号屏蔽线和第二信号屏蔽线之间，所述至少一条第二虚设走线中的各条第二虚设走线彼此间隔、且均匀地分布在所述第一信号屏蔽线和非显示区的外边界之间。
  12. 如权利要求9所述的显示面板，其中所述外虚设走线、所述信号走线、以及所述中间虚设走线中的至少一个包括第一金属线和布置在第一金属线上方的第二金属线，所述显示面板还包括处于第一金属线和第二金属线之间的绝缘层，所述绝缘层包括过孔，所述第一金属线经由所述绝缘层中的过孔电连接至所述第二金属线。
  13. 如权利要求12所述的显示面板，其中所述第一金属线和第二金属线的材料包括钛、银和氧化铟锡中的至少一种。
  14. 如权利要求2所述的显示面板，其中所述显示面板还包括位于所述衬底基板上的封装坝，所述封装坝处于所述第一信号屏蔽线和所述非显示区的外边界之间，
    其中所述封装坝围绕所述第一信号屏蔽线在所述非显示区内延伸，且所述封装坝和所述第一信号屏蔽线之间保持固定的第一距离，所述第一信号屏蔽线与所述多条外虚设走线中同所述第一信号屏蔽线相邻的外虚设走线之间存在第二距离，
    其中所述第一距离和所述第二距离的比值大于1小于6。
  15. 根据权利要求1-14中任一项所述的显示面板，其中所述衬底基板包括圆角部分，所述第二区域包括处于所述圆角部分内的弯曲区域和处于所述圆角部分外部的平直区域，所述弯曲区域包括第一空隙，所述平直区域包括第二空隙，
    其中所述第一空隙由所述多条外虚设走线中处于所述弯曲区域内的一条外虚设走线的端部和与该一条外虚设走线相邻的外虚设走线共同形成，所述第二空隙由所述多条外虚设走线中处于所述平直区域内的另一条外虚设走线的端部和与该另一条外虚设走线相邻的外虚设走线共同形成，
    其中所述第一空隙的面积大于所述第二空隙的面积。
  16. 如权利要求1-14中任一项所述的显示面板，其中所述多条信号走线中远离所述显示区的信号走线的平均宽度大于靠近所述显示区 的信号走线的平均宽度。
  17. 如权利要求2-14中任一项所述的显示面板，其中所述显示面板还包括布置在所述衬底基板上的至少一条裂纹检测线，所述至少一条裂纹检测线位于非显示区的外边界和所述第一信号屏蔽线，所述至少一条裂纹检测线的延伸图案与所述第一信号屏蔽线的延伸图案一致。
  18. 如权利要求17所述的显示面板，其中所述至少一条裂纹检测线和所述第一信号屏蔽线之间存在第三距离，其中所述第一信号屏蔽线与所述多条外虚设走线中同所述第一信号屏蔽线相邻的外虚设走线之间的第二距离是所述第三距离的2至3倍。
  19. 如权利要求1-14和18中任一项所述的显示面板，所述显示面板还包括处于所述触控电极层和衬底基板之间的像素结构层，所述像素结构层包括阳极、阴极以及二者之间的有机发光层。
  20. 一种显示装置，包括如权利要求1-19中任一项所述的显示面板。
PCT/CN2021/125885 2020-12-25 2021-10-22 显示面板、显示装置及制作显示面板的方法 WO2022134821A1 (zh)

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