WO2022120822A1 - 半导体器件及其制备方法、电子设备 - Google Patents

半导体器件及其制备方法、电子设备 Download PDF

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WO2022120822A1
WO2022120822A1 PCT/CN2020/135857 CN2020135857W WO2022120822A1 WO 2022120822 A1 WO2022120822 A1 WO 2022120822A1 CN 2020135857 W CN2020135857 W CN 2020135857W WO 2022120822 A1 WO2022120822 A1 WO 2022120822A1
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substrate
layer
transistor
semiconductor device
metal
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PCT/CN2020/135857
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English (en)
French (fr)
Inventor
赫然
焦慧芳
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华为技术有限公司
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Priority to CN202080107725.4A priority Critical patent/CN116635995A/zh
Priority to PCT/CN2020/135857 priority patent/WO2022120822A1/zh
Publication of WO2022120822A1 publication Critical patent/WO2022120822A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a semiconductor device, a preparation method thereof, and an electronic device.
  • Nitride and its alloys based on group III-V elements such as gallium nitride (GaN), as third-generation semiconductor materials, have excellent properties such as high breakdown field strength, high thermal stability, and high electron saturation drift velocity.
  • group III-V elements such as gallium nitride (GaN)
  • GaN gallium nitride
  • semiconductor devices made of wide bandgap semiconductors such as gallium nitride as semiconductor materials, such as heterojunction field effect transistors (Heterojunction Field Effect Transistors, referred to as HFET) or high electron mobility transistors (High Electron Mobility Transistor, referred to as HEMT)
  • HFET Heterojunction Field Effect Transistors
  • HEMT High Electron Mobility Transistor
  • the device has the characteristics of heat resistance, high frequency, high power and radiation resistance, and can be widely used in wireless communication and other fields.
  • GaN-based High Electron Mobility Transistors may also be referred to as GaN-based two-dimensional electron gas field effect transistors or GaN-based modulation-doped FETs, which may rely on nitride
  • the gallium wafer was prepared.
  • GaN wafers are expensive.
  • the area utilization rate of the GaN wafers is low, the production cost of the semiconductor devices will easily be high. Not too high.
  • the GaN semiconductor layer includes an active area (active area) and a passive area (passive area), wherein the active area refers to the area within the GaN semiconductor layer for forming a conductive channel, and the passive area
  • the region is the region outside the active region.
  • metal wires or bonding pads for interconnecting with an external power source or an external signal source are correspondingly formed in the passive region. Therefore, the portion of the GaN semiconductor layer in the passive region does not actually function as a semiconductor. That is, only the portion of the GaN semiconductor layer located in the active region is an effective portion that can work. Therefore, the area ratio of the active region in the entire GaN semiconductor layer is the area utilization ratio of the GaN semiconductor layer. In some cases, the area of the active region in the entire GaN semiconductor layer is less than 50%, that is, the area utilization rate of the GaN semiconductor layer is less than 50%, thereby causing serious cost waste.
  • Embodiments of the present disclosure provide a semiconductor device, a method for fabricating the same, and an electronic device, which are used to solve the problem of low area utilization of a wide-bandgap semiconductor wafer such as gallium nitride during the batch fabrication of semiconductor devices, so as to reduce the production of semiconductor devices cost, and effectively improve the process stability in the production process of the semiconductor device, and improve the heat dissipation capability of the semiconductor device.
  • a wide-bandgap semiconductor wafer such as gallium nitride
  • some embodiments of the present disclosure provide a semiconductor device.
  • the semiconductor device includes: a first substrate, at least one transistor, an auxiliary carrier, and a plurality of metal patterns.
  • the auxiliary carrier and the at least one transistor are disposed on the first substrate.
  • the orthographic projection of the auxiliary bearing portion on the first substrate is located outside the orthographic projection of the at least one transistor on the first substrate, and the boundary of the orthographic projection of the auxiliary bearing portion on the first substrate and the at least one transistor are on the first substrate.
  • the orthographic boundaries on the substrates are partially coincident.
  • Each of the at least one transistor includes a semiconductor layer, and gate, drain and source electrodes on a side of the semiconductor layer facing away from the first substrate.
  • the plurality of metal patterns are formed on a side of the auxiliary bearing portion facing away from the first substrate. At least one metal pattern of the plurality of metal patterns is coupled to the gate electrode, at least one metal pattern is coupled to the drain electrode, and the metal pattern coupled to the gate electrode is insulated from the metal pattern coupled to the drain electrode.
  • the auxiliary carrier and the at least one transistor are disposed on the first substrate, which means that the auxiliary carrier and the at least one transistor can be simultaneously transferred on the first substrate. That is to say, transistors or transistor components (such as semiconductor layers, etc.) can be prepared on a semiconductor wafer in advance, and then transferred to the first substrate synchronously with the auxiliary carrier, that is, the first substrate is not It is the substrate for the preparation of transistors.
  • the auxiliary bearing portion on the first substrate Since the orthographic projection of the auxiliary bearing portion on the first substrate is located outside the orthographic projection of the at least one transistor on the first substrate, and the boundary of the orthographic projection of the auxiliary bearing portion on the first substrate and the at least one transistor are on the first substrate.
  • the orthographic boundary portions on a substrate overlap, therefore, the auxiliary carrier can be formed on the side of the at least one transistor during the transistor transfer process, and transferred to the first substrate synchronously with the at least one transistor.
  • the auxiliary bearing portion is used to support and protect the at least one transistor, which can effectively improve the process stability in the production process of the semiconductor device.
  • the first substrate is not the fabrication substrate of the transistor.
  • the auxiliary carrier portion may be formed during the transfer process of the at least one transistor, and the metal pattern may be formed after the auxiliary carrier portion and the transistor are transferred to the first substrate. Therefore, the fabrication of transistors on a semiconductor wafer can be unaffected by the arrangement positions of other constituent elements such as metal patterns in the semiconductor device. In this way, in the process of mass-producing transistors on the semiconductor wafer, the semiconductor layer on the semiconductor wafer does not need to reserve a part of the passive region or only needs to reserve a very small part of the passive region. Therefore, the semiconductor layer on the semiconductor wafer can be effectively utilized and the active area of the transistor can be prepared, so as to ensure that the semiconductor wafer has higher area utilization and higher die-per-wafer.
  • the semiconductor device can also reduce the production of semiconductor devices by adopting the above structure cost.
  • the heat dissipation capability of the semiconductor device can also be effectively improved by using the first substrate, so that a larger power density can be achieved on the same active area area , or correspondingly reduce the area of the active region on the premise of achieving the same power, so as to further reduce the production cost of the semiconductor device.
  • the transistor generally further includes a first passivation layer on the surface of the semiconductor layer facing away from the first substrate.
  • the first passivation layer includes a plurality of openings.
  • the gate, source and drain of the transistor are respectively formed in the corresponding openings.
  • the surface of the auxiliary carrier portion facing away from the first substrate is flush or approximately flush with the surface of the gate electrode or the drain electrode facing away from the first substrate. In this way, a metal pattern with better flatness can be formed on the auxiliary bearing portion, so as to ensure the film-forming quality of the metal pattern.
  • the surface of the auxiliary carrier portion facing away from the first substrate is flush or approximately flush with the surface of the first passivation layer facing away from the first substrate.
  • the transistor further includes a second passivation layer.
  • the second passivation layer includes a plurality of openings.
  • the second passivation layer is formed on the surface of the first passivation layer away from the semiconductor layer, and is located on the side of the gate electrode, the source electrode and the drain electrode away from the semiconductor layer.
  • a surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with a surface of the second passivation layer facing away from the first substrate.
  • the metal pattern is coupled to the gate or drain through corresponding openings in the second passivation layer.
  • the transistor and the auxiliary carrier can be transferred to the first substrate synchronously, so that the gate of the transistor can be effectively protected by the second passivation layer electrode, source electrode and drain electrode, so as to avoid the gate, source and drain electrode of the transistor from being damaged by the transfer of the transistor.
  • the auxiliary bearing portion is located beside the transistor.
  • the auxiliary bearing portion is disposed on at least two sides of the at least one transistor, and the two sides include opposite sides or adjacent sides.
  • the auxiliary bearing portion is disposed around the periphery of the aforementioned at least one transistor. This embodiment of the present disclosure does not limit this.
  • the orthographic projection area of the aforementioned at least one transistor on the first substrate is the first area S1.
  • the orthographic projection area of the auxiliary bearing portion on the first substrate is the second area S2. In the embodiment of the present disclosure, it is limited:
  • the auxiliary bearing portion can be used to effectively support and protect the transistor, thereby improving the process stability in the production process of the semiconductor device.
  • the material of the auxiliary bearing portion includes silicon oxide, silicon nitride, silicon oxynitride, silicon, silicon carbide, aluminum nitride, aluminum oxide, epoxy resin, polyimide, or benzocyclobutene .
  • the auxiliary bearing portion is made of insulating material with certain mechanical strength, which can not only have good supporting strength, but also effectively insulate the semiconductor layer and the metal pattern.
  • the semiconductor device further includes a heat dissipation insulating layer.
  • the heat dissipation insulating layer is formed on the surfaces of the auxiliary carrier and the transistor facing away from the first substrate.
  • the metal pattern is formed on the surface of the heat dissipation insulating layer facing away from the auxiliary bearing portion.
  • the heat-dissipating insulating layer can be prepared and formed by using insulating materials with good heat-dissipating ability.
  • the heat-dissipating insulating layer is, for example, a diamond layer.
  • the metal pattern is formed on the surface of the heat-dissipating insulating layer away from the auxiliary bearing portion, and can effectively conduct the heat generated during the operation of the transistor through the heat-dissipating insulating layer, thereby effectively improving the heat dissipation capability of the semiconductor device.
  • the orthographic projection of the auxiliary bearing portion on the first substrate is located within the orthographic projection of the heat dissipation insulating layer on the first substrate. Part of the surface of the heat dissipation insulating layer is in direct contact with the first substrate. In this way, when the first substrate has high thermal conductivity, the heat dissipation insulating layer is in direct contact with the first substrate, and can also conduct heat to the first substrate, so as to further improve the heat dissipation capability of the semiconductor device.
  • the semiconductor device further includes: a metal layer formed on a surface of the first substrate facing away from the transistor.
  • a metal layer is formed on the surface of the first substrate facing away from the transistor, and the heat dissipation capability of the first substrate can also be improved by using the metal layer.
  • the metal layer can be formed by using a metal material with good heat dissipation capability, such as at least one of copper, aluminum, platinum, tungsten, nickel, iridium or cobalt.
  • the semiconductor device further includes at least one first via hole.
  • the first via hole penetrates at least the first substrate and the semiconductor layer.
  • the orthographic projection of the first via hole on the metal layer is located within the orthographic projection of the source electrode in the corresponding transistor on the metal layer.
  • the metal layer is coupled to the source through the first via hole.
  • the semiconductor device further includes at least one second via hole.
  • the second via hole penetrates at least the first substrate and the auxiliary bearing portion.
  • the orthographic projection of the second via hole on the metal layer is located within the orthographic projection of the corresponding metal pattern on the first substrate.
  • the metal layer is coupled with the metal pattern through the second via hole.
  • the metal layer is coupled to the corresponding source electrode or metal pattern, and the metal layer can also be used as a common electrode to provide a ground signal or a floating signal to transistors or other electronic components in the semiconductor device.
  • the layer structure through which the first via hole and the second via hole pass through is related to the layer structure in the semiconductor device, and can be set according to actual requirements.
  • the semiconductor device further includes a heat dissipation substrate.
  • the heat dissipation substrate is located on the side of the metal layer away from the first substrate.
  • the metal layer is welded on the heat dissipation substrate.
  • the heat-dissipating substrate is an aluminum substrate, a copper substrate, a diamond/metal composite substrate, a ceramic substrate, a rigid printed circuit board or a flexible printed circuit board and other substrates with high thermal conductivity.
  • a surface of the auxiliary carrier portion close to the first substrate is flush or substantially flush with a surface of the semiconductor layer close to the first substrate.
  • good bonding of both the auxiliary carrier part and the semiconductor layer and the first substrate is achieved, or a first substrate with good film formation quality is formed on the auxiliary carrier part and the semiconductor layer. Further, it is beneficial to improve the use reliability of the semiconductor device.
  • the semiconductor device further includes a non-conductive bonding layer.
  • the auxiliary carrier and the semiconductor layer of the transistor are bonded to the first substrate through a non-conductive bonding layer.
  • the use of the non-conductive bonding layer can not only enhance the bonding strength between the auxiliary bearing portion and the transistor and the first substrate, but also ensure that the transistor will not leak current due to its existence, which is beneficial to ensure the semiconductor device. electrical properties.
  • the transistor further includes: stacking a transition layer and a second substrate on a side of the semiconductor layer facing away from the gate.
  • the second substrate is a transistor fabrication substrate or a part of the fabrication substrate, for example, a base of a semiconductor wafer, on which the transition layer and the semiconductor layer can be epitaxially grown.
  • the second substrate is formed of a material having good lattice matching and thermal matching with the semiconductor layer.
  • the semiconductor layer includes a GaN layer
  • the second substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.
  • the surface of the auxiliary carrier part close to the first substrate is flush or substantially flush with the surface of the second substrate close to the first substrate.
  • good bonding of both the auxiliary carrier part and the second substrate with the first substrate is realized, or a first substrate with good film-forming quality is formed on the auxiliary carrier part and the second substrate. Further, it is beneficial to improve the use reliability of the semiconductor device.
  • the semiconductor device further includes a bonding layer.
  • the auxiliary carrier and the second substrate in the transistor may be bonded to the first substrate through a bonding layer, so as to enhance the bonding strength between each of the auxiliary carrier and the transistor and the first substrate using the bonding layer.
  • the bonding layer can be a non-conductive bonding layer, so that the non-conductive bonding layer is used to ensure that the transistor will not have leakage current due to its existence, which is beneficial to ensure the electrical performance of the semiconductor device.
  • the bonding layer may also be a conductive bonding layer. In this way, the use of the second substrate can eliminate the influence of the conductive bonding layer on the electrical performance of the semiconductor device.
  • the semiconductor device includes a first via hole
  • the first via hole includes a first sub via hole and a second sub via hole arranged in sections.
  • the first sub-conducting hole penetrates through the second substrate, the transition layer and the semiconductor layer, and two ends of the first sub-conducting hole are respectively coupled to the source electrode and the conductive bonding layer.
  • the second sub-via penetrates through the first substrate, and two ends of the second sub-via are respectively coupled to the conductive bonding layer and the metal layer.
  • the bonding layer is a conductive bonding layer
  • the first via hole is composed of the first sub via hole and the second sub via hole, which can reduce the difficulty of manufacturing the first via hole and ensure the first via hole.
  • the electrical connection performance of a via hole is especially for the case where the thickness of the first substrate and the transistor is relatively large.
  • the semiconductor device includes a second via hole
  • the second via hole includes a third sub via hole and a fourth sub via hole arranged in sections.
  • the third sub-via at least penetrates through the auxiliary bearing portion, and both ends of the third sub-via are respectively coupled with the metal pattern and the conductive bonding layer.
  • the fourth sub-via penetrates through the first substrate, and two ends of the fourth sub-via are respectively coupled to the conductive bonding layer and the metal layer.
  • the bonding layer is a conductive bonding layer
  • the second via hole is composed of the third sub via hole and the fourth sub via hole, which can reduce the difficulty of manufacturing the second via hole and ensure the first via hole.
  • the electrical connection performance of the two via holes is especially suitable for the case where the thickness of the first substrate and the auxiliary bearing portion is relatively large.
  • the first substrate includes: a single crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, a single crystal aluminum nitride substrate, a polycrystalline aluminum nitride substrate, a single crystal diamond substrate, a polycrystalline Diamond substrate, graphite substrate, multilayer graphene substrate or copper substrate.
  • the single crystal silicon carbide substrate includes: a high-purity semi-insulating single crystal silicon carbide substrate, or a vanadium-doped silicon carbide substrate.
  • the first substrate adopts a substrate whose cost is lower than that of a wide-bandgap semiconductor wafer, which is beneficial to reduce the production cost of semiconductor devices.
  • the first substrate is a substrate with high thermal conductivity. For example, under the condition of a temperature of 300K, the thermal conductivity of the first substrate is greater than 200W/mK, which can ensure that the semiconductor device has good heat dissipation capability.
  • the first substrate is a polycrystalline silicon carbide substrate, a polycrystalline aluminum nitride substrate or a polycrystalline diamond substrate.
  • the first substrate can be formed by a vapor deposition process.
  • the semiconductor device further includes a gas barrier layer.
  • the gas barrier layer is, for example, at least one of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer.
  • a gas barrier layer is formed on surfaces of the auxiliary carrier and the transistor close to the first substrate.
  • the first substrate is formed on a surface of the gas barrier layer facing away from the auxiliary carrier.
  • a gas barrier layer is arranged between the first substrate, the auxiliary bearing part, and the transistor, and the gas barrier layer can be used to effectively prevent the gas used in the deposition process of the first substrate from affecting the semiconductor device during the preparation process of the semiconductor device. layer causing damage or destruction.
  • the semiconductor device further includes: a plurality of bond pads.
  • the bond pads are formed on the corresponding metal patterns, and the orthographic projection of the bond pads on the first substrate is located in an area of the first substrate not covered by the transistors. In this way, it is convenient to bond the external metal wire on the surface of the bonding pad, so as to use the metal wire to couple with the external component, so as to realize the transmission of electrical signals between the semiconductor device and the external component.
  • the semiconductor layer includes a channel layer and a barrier layer that are stacked in a direction away from the first substrate.
  • the channel layer is a gallium nitride layer
  • the barrier layer is an aluminum gallium nitride layer or an aluminum nitride layer.
  • the channel layer is a gallium arsenide layer
  • the barrier layer is a gallium aluminum arsenide layer.
  • the channel layer is a gallium oxide layer
  • the barrier layer is an aluminum nitride layer or a gallium aluminum oxide layer.
  • the thickness of the transistor is less than 10 ⁇ m, which is beneficial to realize the thinning of the semiconductor device and reduce the thermal resistance of the semiconductor device.
  • the area ratio of the active region of the transistor in its semiconductor layer ranges from 80% to 100%, which can make the area utilization rate of the semiconductor wafer required for the preparation of the transistor reach 80% or more, so as to reduce the production of semiconductor devices. cost.
  • some embodiments of the present disclosure provide an electronic device.
  • the electronic device includes: at least one semiconductor device as described in any of the above embodiments.
  • the technical effects that can be achieved by the electronic device in the embodiments of the present disclosure are the same as the technical effects that can be achieved by the semiconductor devices in some of the foregoing embodiments, which will not be repeated here.
  • some embodiments of the present disclosure provide a method for fabricating a semiconductor device.
  • the manufacturing method of the semiconductor device includes the following steps.
  • a wafer is provided on which a plurality of transistors or partial layers of transistors are prepared, wherein the front side of the transistors or partial layers thereof is the outermost surface facing away from the wafer.
  • the wafer is cut along the thickness direction of the wafer to obtain a plurality of device particles.
  • a device particle includes at least one transistor or a partial layer of at least one transistor.
  • a support substrate is provided on which the front surface of the at least one device particle is bonded.
  • the front side of the device particle is the front side of the aforementioned transistor or a partial layer thereof.
  • an auxiliary support film is formed on the surface of the support substrate which is not covered with the device particles, and on the back surface of the device particles. Polishing the auxiliary carrier film and the device particles to obtain at least one transistor and an auxiliary carrier part located beside the at least one transistor. The polished surface of the auxiliary bearing portion and the polished surface of the transistor are located on the same plane.
  • a first substrate is provided, and the auxiliary bearing portion and the polished surface of the at least one transistor are synchronously bonded on the first substrate.
  • the first substrate is prepared on the polished surface of the auxiliary carrier and the transistor.
  • the support substrate is removed.
  • a plurality of metal patterns are formed on the side of the auxiliary bearing portion away from the first substrate, and the metal patterns are correspondingly coupled to the transistors.
  • a semiconductor device is obtained.
  • the fabrication method of the semiconductor device in the embodiment of the present disclosure has the same technical effect as the semiconductor device provided in the foregoing embodiments, and details are not described herein again.
  • the transistor and the auxiliary carrying portion can be transferred to the first substrate synchronously, which is easy to operate and is beneficial to improve production efficiency.
  • the transistor in the device particle includes at least a second substrate and a semiconductor layer epitaxially grown on the second substrate.
  • the second substrate is the portion of the wafer that is located in the device particles. Polishing the device particles further includes: exposing the surface of the semiconductor layer in the transistor close to the second substrate; or exposing the polished surface of the second substrate in the transistor.
  • the transistor in the device particle further includes: a first passivation layer, a gate electrode, a source electrode, a drain electrode, and a second passivation layer.
  • Preparing a plurality of transistors or partial layers of a plurality of transistors on a wafer includes: epitaxially growing a semiconductor layer on the wafer; forming a first passivation layer on a surface of the semiconductor layer facing away from the wafer; and forming a first passivation layer on the first passivation layer A plurality of openings are formed thereon, and a gate electrode, a source electrode and a drain electrode are respectively formed in the plurality of openings; a second passivation layer is formed on the surfaces of the first passivation layer, the gate electrode, the source electrode and the drain electrode which are away from the semiconductor layer chemical layer.
  • bonding the front surface of the device particles on the support substrate includes: bonding the surface of the second passivation layer away from the gate on the support substrate.
  • forming a plurality of metal patterns on the side of the auxiliary bearing portion that is away from the first substrate, so that the metal patterns are correspondingly coupled with the transistors further comprising: forming a plurality of openings in the second passivation layer; A plurality of metal patterns are formed on the side of the portion away from the first substrate, so that the plurality of metal patterns are correspondingly coupled to the gate and the drain through the openings in the second passivation layer.
  • the gate, source and drain of the transistor are isolated and protected by the second passivation layer, so that the gate, source and drain of the transistor can be avoided. and drain are damaged by transistor transfer.
  • forming a plurality of metal patterns on the side of the auxiliary carrier part away from the first substrate further comprising: forming a heat dissipation insulating layer on the surface of the auxiliary carrier part and the transistor away from the first substrate; The plurality of metal patterns are formed on a surface of the insulating layer facing away from the auxiliary bearing portion.
  • the function of the heat-dissipating insulating layer is as described above.
  • the front surface of the at least one device particle is bonded on the support substrate, further comprising: forming a temporary bonding layer on the support substrate; and bonding the front surface of the at least one device particle on the temporary bonding layer.
  • removing the support substrate further includes: removing the temporary bonding layer and the support substrate by using at least one process of laser treatment, heat treatment, chemical treatment, etching, grinding or polishing.
  • the temporary bonding layer is used to realize the bonding between the device particles and the supporting substrate, which is beneficial to reduce the difficulty of removing the supporting substrate and simplify the fabrication process of the semiconductor device.
  • forming the temporary bonding layer on the support substrate includes: using at least one material of glass, silicon dioxide or silicon nitride to form the temporary bonding layer on the support substrate by spin coating or vapor deposition process. In this way, it can be ensured that the temporary bonding layer will not be affected by the high temperature environment in the subsequent process, where the temperature of the high temperature environment is, for example, ⁇ 200°C.
  • the first substrate is prepared on the polished surfaces of the auxiliary carrier and the transistor using a vapor deposition process, for example, a chemical vapor deposition process or a physical vapor deposition process.
  • preparing a plurality of transistors or partial layers of a plurality of transistors on a wafer includes: epitaxially growing a semiconductor layer on the wafer; forming a first passivation layer on a surface of the semiconductor layer facing away from the wafer .
  • bonding the front surfaces of the device particles on the support substrate includes: bonding the surface of the first passivation layer away from the semiconductor layer on the support substrate.
  • forming a plurality of metal patterns on the side of the auxiliary bearing portion that is away from the first substrate, so that the metal patterns are correspondingly coupled to the transistors further comprising: forming a plurality of openings on the first passivation layer, and forming a plurality of openings on the first passivation layer A gate electrode, a source electrode and a drain electrode are respectively formed in the plurality of openings; a plurality of metal patterns are formed on the side of the auxiliary bearing portion that is away from the first substrate, and at least one metal pattern in the plurality of metal patterns is connected to the gate electrode Coupling, at least one metal pattern is coupled with the drain, and the metal pattern coupled with the gate is insulated from the metal pattern coupled with the drain.
  • preparing the first substrate on the polishing surface of the auxiliary carrier and the transistor further includes: forming a gas barrier layer on the polishing surface of the auxiliary carrier and the transistor, the gas barrier layer is, for example, a silicon layer, nitrogen at least one of a silicon nitride layer, an aluminum nitride layer or a silicon carbide layer; and a first substrate is formed on the surface of the gas barrier layer facing away from the auxiliary bearing portion.
  • a gas barrier layer is prepared in advance before depositing the first substrate, and the gas barrier layer can be used to prevent the gas used in the deposition process of the first substrate from causing damage or destruction to the semiconductor layer of the transistor.
  • the auxiliary carrier and the polished surface of the transistor are synchronously bonded to the first substrate.
  • bonding the auxiliary bearing portion and the polished surface of the transistor on the first substrate further comprising: forming a bonding layer on the first substrate, and bonding the auxiliary bearing portion and the polished surface of the transistor on the bonding layer. or, a bonding layer is formed on the polishing surface of the auxiliary bearing part and the transistor, and the first substrate is bonded on the bonding layer.
  • the structure and function of the bonding layer are as described above.
  • the fabrication methods of the semiconductor devices also have various implementations.
  • the method for fabricating a semiconductor device further includes: forming a metal layer on a surface of the first substrate facing away from the transistor.
  • the method for fabricating a semiconductor device further includes: forming a first via hole penetrating at least the first substrate and the semiconductor layer, and making the first via hole on the first substrate positive
  • the projection is located in the orthographic projection of the source electrode in the corresponding transistor on the first substrate; a metal layer is formed on the surface of the first substrate away from the transistor, so that the metal layer is coupled to the source electrode through the first via hole.
  • the first via hole also corresponds to penetrating the bonding layer or the gas barrier layer.
  • the semiconductor device further includes a conductive bonding layer between the first substrate and the second substrate.
  • the first via hole is composed of a first sub via hole and a second sub via hole which are arranged in sections.
  • forming a first via hole penetrating at least the first substrate and the semiconductor layer includes: forming a first sub-via hole penetrating the second substrate, the transition layer and the semiconductor layer, so that the One end is in direct contact with the corresponding source electrode; a conductive bonding layer is formed on the polishing surface of the auxiliary bearing part and the transistor, so that the conductive bonding layer is in direct contact with the other end of the first sub-conduction hole; the first substrate is bonded On the conductive bonding layer; form a second sub-via hole through the first substrate, so that one end of the second sub-via hole is in direct contact with the conductive bonding layer; form a metal layer on the first substrate, so that the metal layer The layer is in direct contact with the other end of the second sub-via.
  • the method for fabricating a semiconductor device further includes: forming a second via hole penetrating at least the first substrate and the auxiliary bearing portion, and making the second via hole on the first substrate
  • the orthographic projection is within the orthographic projection of the corresponding metal pattern on the first substrate; the metal layer is formed on the surface of the first substrate away from the semiconductor layer, so that the metal layer is coupled with the metal pattern through the second via hole.
  • the second via hole also corresponds to penetrating the bonding layer or the gas barrier layer.
  • the semiconductor device further includes a conductive bonding layer between the first substrate and the auxiliary carrier.
  • the second via hole is composed of a third sub via hole and a fourth sub via hole arranged in sections.
  • forming a second via hole penetrating at least the first substrate and the auxiliary carrying portion includes: forming a third sub-conducting hole penetrating the auxiliary carrying portion; forming a conductive bond on the polishing surface of the auxiliary carrying portion and the transistor layer, so that the conductive bonding layer is in direct contact with one end of the third sub-via; bonding the first substrate on the conductive bonding layer; forming a fourth sub-via penetrating the first substrate so that the fourth sub-via One end of the sub-conducting hole is in direct contact with the conductive bonding layer; a metal layer is formed on the first substrate, so that the metal layer is in direct contact with the other end of the fourth sub-conducting hole. In this way, after the metal pattern is subsequently formed, the metal pattern is in direct
  • the method for manufacturing a semiconductor device further includes: providing a heat dissipation substrate, and welding the metal layer on the heat dissipation substrate.
  • the function of the heat dissipation substrate is as described above.
  • the manufacturing method of the semiconductor device further includes: forming at least one bonding pad on the metal pattern, so that the orthographic projection of the bonding pad on the first substrate is located in an area of the first substrate not covered by the transistors.
  • the function of the keyboard is as described above.
  • the fabrication method of the semiconductor device in the embodiment of the present disclosure has the same technical effect as the semiconductor device provided in the foregoing embodiments, and details are not described herein again.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to some embodiments.
  • Fig. 2 is a schematic cross-sectional view of the semiconductor device shown in Fig. 1 along A-A' direction;
  • FIG. 3 is a schematic diagram of S100 of a method for fabricating a semiconductor device according to some embodiments
  • FIG. 4 is a schematic structural diagram of a transistor according to some embodiments.
  • FIG. 5 is a schematic diagram of S200 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 6 is a schematic diagram of S300 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 7 is a schematic diagram of a S400 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 8 is a schematic diagram of another S400 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 9 is a schematic diagram of S500 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 10 is a schematic diagram of the preparation of a non-conductive bonding layer according to some embodiments.
  • FIG. 11 is a schematic diagram of the preparation of another non-conductive bonding layer according to some embodiments.
  • FIG. 12 is a schematic diagram of S600 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 13 is a schematic diagram of S700 of a method for fabricating a semiconductor device according to some embodiments.
  • FIG. 14 is a supplementary schematic diagram of a method of fabricating a semiconductor device according to some embodiments.
  • FIG. 15 is a schematic diagram of S100 ′ according to another method of fabricating a semiconductor device in some embodiments.
  • FIG. 16 is a schematic diagram of S200 ′ according to another method of fabricating a semiconductor device in some embodiments.
  • 17 is a schematic diagram of S300 ′ to S500 ′ according to another method for fabricating a semiconductor device in some embodiments;
  • FIG. 18 is a schematic diagram of the preparation of a gas barrier layer according to some embodiments.
  • 19 is a schematic diagram of the fabrication of a first substrate according to some embodiments.
  • FIG. 20 is a schematic diagram of S600 ′ to S700 ′ according to another method for fabricating a semiconductor device in some embodiments;
  • Figure 21 is a schematic cross-sectional view along the A-A' direction of another semiconductor device shown in Figure 1;
  • Figure 22 is a schematic cross-sectional view along the A-A' direction of another semiconductor device shown in Figure 1;
  • Figure 23 is a schematic cross-sectional view along the A-A' direction of another semiconductor device shown in Figure 1;
  • 24 is a schematic structural diagram of another semiconductor device according to some embodiments.
  • Fig. 25 is a schematic cross-sectional view of the semiconductor device shown in Fig. 24 along the direction B-B';
  • Figure 26 is a schematic cross-sectional view along the A-A' direction of another semiconductor device shown in Figure 1;
  • FIG. 27 is a schematic diagram of the preparation of a transistor in the semiconductor device shown in FIG. 26;
  • FIG. 28 is a schematic diagram of bonding of a device particle during the preparation process of the semiconductor device shown in FIG. 26;
  • 29 is a schematic diagram of a positional relationship between an auxiliary carrier and a transistor according to some embodiments.
  • FIG. 30 is a schematic diagram of the positional relationship between another auxiliary bearing portion and a transistor according to some embodiments.
  • FIG. 31 is a schematic diagram of a positional relationship between yet another auxiliary bearing portion and a transistor according to some embodiments.
  • 32 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • FIG. 33 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • 34 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • 35 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • 36 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • FIG. 37 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • FIG. 38 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • 39 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • FIG. 40 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • 41 is a schematic structural diagram of yet another semiconductor device according to some embodiments.
  • Figure 42 is a schematic cross-sectional view of the semiconductor device shown in Figure 41 along the C-C' direction;
  • FIG. 43 is a schematic cross-sectional view of the semiconductor device shown in FIG. 41 along the E-F-G direction;
  • 44 is a schematic cross-sectional view of an electronic device according to some embodiments.
  • 45 is a schematic cross-sectional view of another electronic device according to some embodiments.
  • 201 and 201'-device particles 20-transistor; 21-second substrate;
  • H1-first via hole H11-first sub via hole; H12-second sub via hole;
  • L1-first inductor L2-second inductor; R1-resistance.
  • orientation terms such as “upper”, “lower”, “left” and “right” may include, but are not limited to, definitions relative to the orientations in which the components in the accompanying drawings are schematically placed. It should be understood that these directional terms may be Relative notions, they are used for relative description and clarification, which may vary accordingly depending on the orientation in which the components are placed in the drawings.
  • first”, “second” and other ordinal numbers are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as “first”, “second” etc. may expressly or implicitly include one or more of that feature.
  • “plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Semiconductor device refers to electronic devices that rely on the electrical properties of semiconductor materials to achieve specific functions.
  • Common semiconductor devices are, for example, transistor devices, ie electronic devices comprising at least one transistor.
  • transistor devices ie electronic devices comprising at least one transistor.
  • transistors There are various structures and types of transistors, and the embodiments of the present disclosure are only described by taking that the transistor is a field effect transistor or a transistor having a similar structure as an example.
  • the semiconductor device 100 includes a first substrate 11 and at least one transistor 20 and an auxiliary carrier 30 synchronously transferred onto the first substrate 11 .
  • the first substrate 11 is configured to carry the transistor 20 and the auxiliary carrying portion 30 .
  • the first substrate 11 can be a substrate with higher thermal conductivity and higher resistance value to ensure excellent heat dissipation capability and electrical performance of the semiconductor device 100 .
  • the first substrate 11 is a single crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, a polycrystalline aluminum nitride substrate, a polycrystalline diamond substrate, a graphite substrate, a multilayer graphene substrate, a copper substrate Substrates, or composite substrates laminated with multiple materials, etc.
  • the single crystal silicon carbide substrate includes: a high-purity semi-insulating single crystal silicon carbide substrate, or a vanadium-doped silicon carbide substrate.
  • the vanadium-doped silicon carbide substrate is doped with vanadium to increase the insulating properties of the silicon carbide, and its cost is lower than the high-purity semi-insulating single-crystal silicon carbide substrate.
  • the auxiliary bearing portion 30 and the aforementioned at least one transistor 20 are disposed on the first substrate 11 .
  • the orthographic projection of the auxiliary bearing portion 30 on the first substrate 11 is located outside the orthographic projection of the at least one transistor 20 on the first substrate 11 , and the boundary of the orthographic projection of the auxiliary bearing portion 30 on the first substrate 11 is the same as the orthographic projection of the at least one transistor 20 on the first substrate 11 .
  • the orthographic boundary portions of the at least one transistor 20 on the first substrate 11 overlap. That is, the auxiliary bearing portion 30 is formed on the side of the at least one transistor 20 .
  • the at least one transistor 20 is taken as a whole, and during the production process of transferring the at least one transistor 20 to the first substrate 11 , the auxiliary carrier 30 can support and protect the at least one transistor 20 .
  • the material and structure of the auxiliary bearing portion 30 can be selected and set according to actual needs, which is not limited in the embodiment of the present disclosure.
  • the transistor 20 is a high electron mobility transistor (High Electron Mobility Transistor, HEMT for short) as an example for description, but it is not limited thereto.
  • HEMT is a heterojunction field effect transistor, which can also be called a two-dimensional electron gas field effect transistor or a modulation-doped field effect transistor.
  • the transistor 20 includes a semiconductor layer 23 , and a gate electrode 25 , a source electrode 26 and a drain electrode 27 respectively formed on a side of the semiconductor layer 23 away from the first substrate 11 .
  • the semiconductor device 100 also includes a plurality of metal patterns 60 .
  • the plurality of metal patterns 60 are formed on a side of the auxiliary bearing portion 30 away from the first substrate 11 , at least one metal pattern of the plurality of metal patterns 60 is coupled to the gate 25 of the corresponding transistor 20 , and at least one metal pattern The pattern is coupled to the drain 27 in the corresponding transistor 20 , and the metal pattern coupled to the gate 25 is insulated from the metal pattern coupled to the drain 27 .
  • the source electrode 26 of the transistor 20 is coupled to at least one metal pattern among the above-mentioned plurality of metal patterns 60, or is coupled to other metal layers. Also, the metal pattern or metal layer coupled with the source electrode 26 , the metal pattern coupled with the gate electrode 25 , and the metal pattern coupled with the drain electrode 27 are insulated from each other.
  • the metal pattern 60 is used to transmit electrical signals to the electrodes (including the gate electrode 25 , the source electrode 26 or the drain electrode 27 ) coupled thereto in the transistor 20 .
  • the electrical coupling of external devices or the realization of specific functions of the semiconductor device 100 are limited.
  • the metal pattern 60 is a combination of one or more of metal electrodes, metal lines, bond pads, or pads.
  • the structures of the source electrode 26 and the drain electrode 27 in the transistor 20 are the same, and they are only used for coupling to different power sources or signal sources. Therefore, depending on the type of the transistor 20, the coupling between the source electrode 26 and the drain electrode 27 and the external elements can be interchanged according to the actual situation.
  • the structure of the semiconductor device 100 is as described above, and there may be various implementations for synchronously transferring the transistor 20 and the auxiliary carrier 30 to the first substrate 11 .
  • the transistor 20 and the auxiliary carrier 30 are synchronously bonded to the first substrate 11 .
  • the first substrate 11 is prepared on the surfaces of the transistor 20 and the auxiliary carrier 30 , so as to realize the synchronous transfer of the transistor 20 and the auxiliary carrier 30 .
  • the transistor 20 and the auxiliary carrier 30 are synchronously bonded to the first substrate 11 .
  • bonding means combining two dissimilar substances into one through interatomic forces.
  • the preparation method of the semiconductor device 100 includes: S100-S700.
  • a wafer 12 is provided, and a plurality of transistors 20 are prepared on the wafer 12 . Then, the wafer 12 is cut along the thickness direction of the wafer 12 to obtain a plurality of device particles 201 .
  • Each device particle 201 includes one or more transistors 20 .
  • the transistor 20 includes a second substrate 21 , a semiconductor layer 23 epitaxially grown on the second substrate 21 , and a gate electrode 25 , a drain electrode 27 and a source electrode 26 respectively formed on the semiconductor layer 23 .
  • the second substrate 21 in the transistor 20 is the portion of the wafer 12 that exists within the device particles 201 .
  • the semiconductor layer 23 is epitaxially grown on the wafer 12 , and a transition layer 22 , that is, a buffer layer, is usually grown between the wafer 12 and the semiconductor layer 23 .
  • the transition layer 22 can be used to improve the lattice quality of the surface portion of the wafer 12 to ensure the film formation quality of the semiconductor layer 23.
  • the semiconductor layer 23 of the transistor 20 includes a channel layer 231 and a barrier layer 232 stacked in a direction away from the second substrate 21 , and a heterojunction is formed between the barrier layer 232 and the channel layer 231 .
  • the wafer 12 can be provided in the form of a semiconductor wafer, that is, a transition layer and a semiconductor film have been grown on the surface of the wafer 12 .
  • the gallium nitride wafer 12 includes a substrate 121 and a gallium nitride layer 122 epitaxially grown on the substrate 121 .
  • the base 121 is, for example, a sapphire (Al2O3) substrate, a silicon (Si) substrate, or a silicon carbide (SiC) substrate.
  • the surface portion of the gallium nitride layer 122 can be used as the channel layer 231 in the transistor 20 .
  • the gallium nitride layer 122 is composed of the channel layer 231 and the transition layer 22 , that is, the part of the gallium nitride layer 122 other than the channel layer 231 , that is, it is located in the channel layer
  • the portion of 231 close to the side of the substrate 121 is the transition layer 22, that is, the buffer layer.
  • a barrier layer 232 can be formed.
  • the barrier layer 232 is, for example, an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer.
  • the transistor 20 further includes a first passivation layer 24 formed on the surface of the semiconductor layer 23 facing away from the second substrate 21 .
  • the first passivation layer 24 includes a plurality of openings, and the gate electrode 25 , the source electrode 26 and the drain electrode 27 are respectively formed in the corresponding openings and are in direct contact with the barrier layer 232 .
  • the gate 25 of the transistor 20 and the barrier layer 232 form a Schottky barrier.
  • the first passivation layer 24 and the gate insulating layer are made of insulating materials, such as silicon nitride, silicon oxide or silicon oxynitride and other inorganic insulating materials.
  • the barrier layer 232 forming the heterojunction and the channel layer 231 have different band gaps, and electrons will flow from the wide band gap semiconductor (ie, the barrier layer 232 ) to the narrow band gap semiconductor (ie channel layer 231), thereby forming a quantum well on the narrow band gap semiconductor side of the heterojunction interface.
  • the doping concentration of the wide-bandgap semiconductor is high and the conduction band difference between the heterojunctions is large, a high potential barrier will be formed between the gate 25 and the barrier layer 232, thereby limiting the freedom in the quantum well Electrons move in a direction perpendicular to the heterojunction interface.
  • the quantum well is a two-dimensional electron gas (2 Dimensional Electron Gas, 2DEG for short).
  • the 2DEG is located on the surface of the channel layer 231 in contact with the barrier layer 232 .
  • the concentration of 2DEG in the channel layer 231 can be controlled, thereby controlling the magnitude of the current in the channel layer 231 .
  • a support substrate 90 is provided, and the front surface S1 of at least one device particle 201 is bonded on the support substrate 90 .
  • two device particles 201 are bonded on the support substrate 90 as an example for illustration.
  • the support substrate 90 has a certain mechanical strength, and the support substrate 90 is, for example, a silicon substrate or a glass substrate.
  • the front side S1 of the device particle 201 refers to the surface of the transistor 20 facing away from the second substrate 21 , for example, the surface of the transistor 20 on the side where the gate 25 or the drain 27 is located.
  • the back surface S2 of the device particle 201 refers to the surface opposite to the front surface S1 of the device particle 201 , and is also the surface of the second substrate 21 in the transistor 20 facing away from the semiconductor layer 23 .
  • the surfaces of the gate electrode 25 , the source electrode 26 and the drain electrode 27 facing away from the semiconductor layer 23 are flush or substantially flush with the surface of the first passivation layer 24 facing away from the semiconductor layer 23 .
  • the device particles 201 and the support substrate 90 can have a larger contact area, so that the front surfaces of the device particles 201 can be easily bonded to the support substrate 90, and the two have a better bonding effect.
  • the bonding between the device particles 201 and the support substrate 90 can be realized by direct bonding or bonding by bonding layers.
  • bonding the front surface of the at least one device particle 201 on the support substrate 90 includes: forming a temporary bonding layer 91 on the support substrate 90 ; bonding the front surface of the at least one device particle 201 Bonded on the temporary bonding layer 91 .
  • the temporary bonding layer 91 refers to a bonding layer that can be debonded after bonding, that is, the temporary bonding layer 91 can be removed when it is not needed subsequently.
  • the temporary bonding layer 91 adopts at least one material of glass, silicon dioxide or silicon nitride, and is fabricated on the support substrate 90 by spin coating or vapor deposition process.
  • the temporary bonding layer 91 can be removed by using at least one of laser treatment, heat treatment, chemical treatment, etching, grinding or polishing without the need for its existence.
  • the temporary bonding layer 91 is formed by using the above materials, which can also ensure that the temporary bonding layer 91 will not be affected by the high temperature environment in the subsequent process.
  • the temperature of the high temperature environment is, for example, ⁇ 200°C.
  • the auxiliary carrier film 31 is formed on the surface of the support substrate 90 not covered by the device particles 201 and on the back surface S2 of the device particles 201 .
  • the auxiliary carrier film 31 is formed on the surface of the temporary bonding layer 91 which is not covered with the device particles 201 .
  • the auxiliary carrier film 31 is used to support and protect the transistor 20, and can be formed of an insulating material with a certain mechanical strength, such as silicon oxide, silicon nitride, silicon oxynitride, silicon, silicon carbide, aluminum nitride, aluminum oxide, epoxy resin, polyimide, or benzocyclobutene, etc.
  • the auxiliary carrier film 31 may be formed by a vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. The deposition thickness of the auxiliary carrier film 31 can be selected and set according to actual requirements.
  • the deposition thickness D2 of the auxiliary carrier film 31 is greater than the minimum thickness D1 of the transistor 20, and the minimum thickness D1 of the transistor 20 means that the transistor 20 does not include the second Thickness of substrate 21 and transition layer 22.
  • the auxiliary carrier film 31 and the device particles 201 are polished to obtain at least one transistor 20 and the auxiliary carrier portion 30 located beside the at least one transistor 20 .
  • the polished surface of the auxiliary bearing portion 30 is on the same plane as the polished surface of the transistor 20 .
  • polishing the auxiliary carrier film 31 refers to using a polishing process to thin the auxiliary carrier film 31 and perform surface flattening treatment. Since the auxiliary support film 31 is formed on the surface of the support substrate 90 not covered by the device particles 201 and the back surface S2 of the device particles 201 , in the process of polishing the auxiliary support film 31 , in order to make the transistors 20 in the device particles 201 When exposed, the portion of the auxiliary carrier film 31 located on the back surface S2 of the device particle 201 will be removed. In this way, in the process of polishing the auxiliary carrier film 31 and the device particles 201 , the auxiliary carrier film 31 can support and protect the device particles 201 , thereby reducing the difficulty of implementing the polishing process and improving production efficiency. In addition, the auxiliary bearing portion 30 obtained after polishing is located on the side of the transistor 20, and can also continuously perform auxiliary support and protection on the transistor 20 in the subsequent process.
  • the thinning of the auxiliary carrier film 31 can also be achieved by etching or grinding, so as to ensure that the formed auxiliary carrier portion 30 and the exposed surfaces of the transistor 20 have good surface flatness.
  • the transistor 20 may only include the semiconductor layer 23 and the first passivation layer 24 , the gate electrode 25 , the source electrode 26 and the drain electrode 27 on the semiconductor layer 23 . That is, the polished surface of the transistor 20 is the surface of the semiconductor layer 23 facing away from the gate 25, and the polished surface of the auxiliary bearing portion 30 is flush or substantially flush with the surface of the semiconductor layer 23 in the transistor 20 facing away from the gate 25, for example, as shown in FIG. shown in 7.
  • the transistor 20 further includes the second substrate 21 and the transition layer 22 . That is, the polished surface of the transistor 20 is the polished surface of the second substrate 21.
  • the polished surface of the auxiliary bearing portion 30 is flush or substantially flush with the polished surface of the second substrate 21 in the transistor 20 , as shown in FIG. 8 , for example.
  • the polished surface of the second substrate 21 is the surface after removing part of the base material. The thickness of the part removed by polishing of the second substrate 21 can be set according to actual requirements.
  • the gallium nitride layer 122 is epitaxially grown on the substrate 111 .
  • the surface portion of the gallium nitride layer 122 has good lattice quality and can be used to form the channel layer 231 in the transistor 20 .
  • a portion of the gallium nitride layer 122 close to the substrate 121 (ie, the transition layer 22 ) has poor lattice quality, which is likely to cause poor thermal conductivity of the transition layer 22 . Based on this, in the process of polishing the auxiliary carrier film 31 , the transition layer 22 and the second substrate 21 in the transistor 12 are removed by polishing, which can also effectively improve the heat dissipation capability of the semiconductor device 100 .
  • the first substrate 11 is provided, and the auxiliary carrier 30 and the polished surface of the transistor 20 are synchronously bonded on the first substrate 11 .
  • the transistor 20 only includes the semiconductor layer 23 and the first passivation layer 24 , the gate electrode 25 , the source electrode 26 and the drain electrode 27 on the semiconductor layer 23 for illustration.
  • the structure of the first substrate 11 can be referred to as described in some of the foregoing embodiments.
  • the auxiliary carrier 30 and the transistor 20 are transferred to the first substrate 11 after the preparation is completed. Based on this, in the case that the cost of the wafer 12 for preparing the transistor 20 is high, the first substrate 11 can be formed of a material or a wafer with a relatively low cost.
  • the polishing surface of the auxiliary bearing portion 30 is flush or approximately flush with the polishing surface of the transistor 20, which can ensure that the surfaces to be bonded of the auxiliary bearing portion 30 and the transistor 20 have high surface quality, thereby ensuring that the two are compatible with the first The substrates 11 can have a good bonding effect.
  • the bonding method between the auxiliary bearing portion 30 and the transistor 20 and the first substrate 11 can be realized by a direct bonding method or an indirect bonding method through a bonding layer.
  • the auxiliary bearing portion 30 and the transistor 20 are directly bonded on the first substrate 11 .
  • the surfaces to be bonded of the auxiliary carrier 30 and the transistor 20, and the surface to be bonded of the first substrate 11 can be surface-treated by plasma or ion beam or atomic beam, etc., so that the auxiliary carrier An amorphous interface layer formed by plasma or ion beam or atomic beam processing exists at the direct bonding interface of both the portion 30 and the transistor 20 with the first substrate 11 .
  • the first substrate 11 is a polycrystalline silicon carbide substrate, and the exposed surface of the transistor 20 is a gallium nitride surface, so that after the two are subjected to plasma treatment, the direct bond between the transistor 20 and the first substrate 11 There will be amorphous GaN and/or amorphous SiC interface layers at the interface.
  • the auxiliary bearing portion 30 and the transistor 20 are indirectly bonded on the first substrate 11 .
  • bonding the auxiliary carrier 30 and the transistor 20 on the first substrate 11 further comprising: forming a bonding layer 40 on the first substrate 11 , and bonding the auxiliary carrier 30 and the transistor 20 to the first substrate 11 .
  • the transistor 20 is bonded on the bonding layer 40 .
  • the semiconductor layer 23 of the transistor 20 is in direct contact with the bonding layer 40
  • the bonding layer 40 is a non-conductive bonding layer.
  • the non-conductive bonding layer 40 may cover the entire layer on the first substrate 11, or may only be formed in the to-be-bonded area of the first substrate 11, and the to-be-bonded area may be the first substrate 11 for connecting with the first substrate 11.
  • the region where the transistor 20 is bonded may also be the region where the first substrate 11 is used for bonding with the transistor 20 and the auxiliary bearing portion 30 .
  • bonding the auxiliary bearing portion 30 and the transistor 20 on the first substrate 11 further comprising: forming a bonding layer 40 on the auxiliary bearing portion 30 and the transistor 20 , and attaching the first substrate
  • the bottom 11 is bonded on the bonding layer 40 .
  • the semiconductor layer 23 of the transistor 20 is in direct contact with the bonding layer 40, and the bonding layer 40 is a non-conductive bonding layer.
  • the above-mentioned bonding layer 40 may also have other arrangements.
  • the bonding layer 40 includes a first non-conductive bonding layer and a second non-conductive bonding layer.
  • the first non-conductive bonding layer is formed on the auxiliary bearing portion 30 and the transistor 20
  • the second non-conductive bonding layer is formed on the first substrate 11, and then the first non-conductive bonding layer and the second non-conductive bonding layer are formed. Laminate bonding is also permitted.
  • a silicon nitride bonding layer can be formed on the polycrystalline diamond substrate, and a silicon nitride bonding layer (SiN) can be formed on the GaN substrate.
  • SiN is formed on the surface, thereby realizing the bonding of GaN/SiN-SiN/diamond.
  • the non-conductive bonding layer 40 can be made of non-conductive silicon (Si), silicon carbide (SiC), silicon nitride (SiN), silicon dioxide (SiO2), aluminum nitride (AlN) or aluminum oxide (Al2O3). etc. materials are prepared. In this way, the use of the non-conductive bonding layer 40 can not only enhance the bonding strength between the auxiliary bearing portion 30 and the transistor 20 and the first substrate 11, but also ensure that the transistor 20 does not leak current due to its existence, It is beneficial to ensure the electrical performance of the semiconductor device 100 .
  • the second substrate 21 of the transistor 20 is in direct contact with the bonding layer 40, and the bonding layer 40 may be a conductive bonding layer.
  • the conductive bonding layer 40 can be prepared by using metal materials, such as Ti, Cr, Ni, Cu, Au, and the like.
  • the second substrate 21 and the transition layer 22 are non-conductive materials, so the bonding layer 40 adopts a conductive bonding layer, and its existence will not affect the electrical performance of the semiconductor device 100 .
  • the above-mentioned removal of the supporting substrate 90 also includes removing the temporary bonding layer 91 .
  • the removal of the support substrate 90 and the temporary bonding layer 91 may be achieved by processes such as etching, grinding or polishing, but is not limited thereto.
  • the removal may also be performed by means of laser or chemical or thermal slip peeling.
  • the supporting substrate 90 can also be reused.
  • the auxiliary bearing portion 30 can support and protect the transistor 20 from the side thereof, thereby reducing the difficulty of removing the supporting substrate 90 and further improving the production efficiency.
  • a plurality of metal patterns 60 are formed on the side of the auxiliary bearing portion 30 away from the first substrate 11 , and at least one metal pattern of the plurality of metal patterns 60 is coupled to the gate 25 , at least one metal pattern is coupled to the drain electrode 27 , and the metal pattern coupled to the gate electrode 25 is insulated from the metal pattern coupled to the drain electrode 27 .
  • the above-mentioned plurality of metal patterns 60 further include at least one metal pattern coupled with the source electrode 26 , a metal pattern coupled with the source electrode 26 , a metal pattern coupled with the gate electrode 25 , and a metal pattern coupled with the drain electrode 27 .
  • the coupled metal patterns are all insulated.
  • the metal pattern coupled with the gate electrode 25 is the first metal pattern 61
  • the metal pattern coupled with the source electrode 26 is the second metal pattern 62
  • the metal pattern coupled with the drain electrode 27 is the third metal pattern
  • the metal pattern 63 will be described as an example.
  • the first metal pattern 61 , the second metal pattern 62 and the third metal pattern 63 are all patterns formed by using metal materials, and the patterns may be the same or different.
  • the first metal pattern 61, the second metal pattern 62 and the third metal pattern 63 can be prepared from metal materials with good electrical conductivity, such as at least one of copper, aluminum, gold, platinum, tungsten, nickel, iridium or cobalt. A sort of.
  • the patterns of the first metal pattern 61 , the second metal pattern 62 and the third metal pattern 63 can be designed according to actual requirements.
  • the first metal pattern 61, the second metal pattern 62 or the third metal pattern 63 is a single-layer pattern, and the single-layer pattern can be designed as one or more of metal electrodes, metal lines, bonding pads or pads The combination.
  • the first metal pattern 61, the second metal pattern 62 or the third metal pattern 63 is a multi-layer pattern provided on a multi-layer insulating film, and the multi-layer pattern can be designed as a capacitor, an inductor or a multi-layer metal wire A combination of at least two of them.
  • the metal pattern 60 is formed on the auxiliary bearing portion 30 .
  • the auxiliary bearing portion 30 is located beside the transistor 20 .
  • the auxiliary bearing portion 30 is formed of an insulating material, which can effectively insulate the metal pattern 60 and the semiconductor layer 23 in the transistor 20 , thereby ensuring the electrical performance of the transistor 20 .
  • one device particle 201 is used to prepare one semiconductor device 100, referring to the preparation methods in some of the foregoing embodiments, only one device particle 201 is transferred to the support substrate 90, and then a single semiconductor device can be prepared and obtained Device 100 .
  • a plurality of device particles 201 are transferred onto the support substrate 90 , and after the metal pattern 60 is prepared, as shown in FIG. 14 , a single semiconductor device 100 is obtained by cutting .
  • the transfer of the transistor 20 and the auxiliary carrier 30 is realized by preparing the first substrate 11 on the surface of the transistor 20 and the auxiliary carrier 30 .
  • the manufacturing method of the semiconductor device 100 includes S100' to S700'.
  • a wafer 12 is provided, and partial layers of a plurality of transistors 20 are prepared on the wafer 12 , for example, a semiconductor layer 23 and a first passivation layer 24 of the transistors 20 are prepared. Then, the wafer 12 is cut along the thickness direction of the wafer 12 to obtain a plurality of device particles 201'.
  • a device particle 201 ′ includes a second substrate 21 of at least one transistor 20 , a transition layer 22 , a semiconductor layer 23 and a first passivation layer 24 .
  • the structures of the second substrate 21 and the transition layer 22 are the same as described above.
  • the embodiment of the present disclosure only lacks the preparation of the gate 25 , the source electrode 26 and the drain electrode 27 in the transistor 20 , for the rest, please refer to the relevant information in some of the foregoing embodiments. The content is carried out and will not be described in detail.
  • the openings on the first passivation layer 24 for accommodating the gate electrode 25 , the source electrode 26 and the drain electrode 27 can be formed during the subsequent preparation of the gate electrode 25 , the source electrode 26 and the drain electrode 27 .
  • S100 ′ further includes: forming a plurality of openings in the first passivation layer 24 , and forming the source electrode 26 of the transistor 20 in the plurality of openings correspondingly and drain 27.
  • the gate 25 of the transistor 20 may be remanufactured in a subsequent process as appropriate. In this way, it is convenient to mass-produce more transistors 20 on the wafer 12 at a lower cost, and avoid damage to the prepared structures caused by subsequent high-temperature processes such as the formation process of the first substrate 11 .
  • a supporting substrate 90 is provided, and the front surface S1 of at least one device particle 201 ′ is bonded on the supporting substrate 90 .
  • the front side of the device particle 201 ′ appears as the surface of the first passivation layer 24 facing away from the semiconductor layer 23 .
  • the support substrate 90 is, for example, a glass substrate or a silicon substrate.
  • the device particles 201 ′ may be directly bonded on the support substrate 90 or indirectly bonded to the support substrate 90 through the temporary bonding layer 91 .
  • the bonding between the device particles 201 ′ and the support substrate 90 may be implemented with reference to the relevant content of S200 in the foregoing embodiment.
  • one device particle 201 ′ is bonded on the support substrate 90 as an example for illustration.
  • the auxiliary carrier film 31 is formed on the surface of the support substrate 90 not covered by the device particles 201 ′ and the back surface of the device particles 201 ′.
  • the auxiliary carrier film 31 is formed on the surface of the temporary bonding layer 91 not covered by the device particles 201 ′ and the back surface of the device particles 201 ′.
  • the transistor 20 obtained here refers to the structure of the transistor 20 that has been prepared in S100 ′, including some layers of the transistor 20 .
  • Polishing the device particles 201' further comprising: exposing the surface of the semiconductor layer 23 of the transistor 20 in the device particle 201' close to the second substrate 21, or making the polished surface of the second substrate 21 of the transistor 20 in the device particle 201' Bare (not shown in Figure 17).
  • the first substrate 11 is prepared on the auxiliary carrier 30 and the polished surface of the transistor 20 .
  • the first substrate 11 may be formed by a vapor deposition process, such as a chemical vapor deposition process or a physical vapor deposition process.
  • the preparation material of the first substrate 11 is, for example, polycrystalline silicon carbide, polycrystalline aluminum nitride or polycrystalline diamond.
  • the polished surface of the auxiliary carrier 30 and the polished surface of the semiconductor layer 23 or the second substrate 21 are located on the same plane.
  • a first substrate is prepared on the auxiliary bearing portion 30 and the polished surface of the transistor 20 . 11, further comprising: forming a gas barrier layer 111 on the polished surfaces of the auxiliary carrier part 30 and the transistor 20, and then forming the first substrate 11 on the surface of the gas barrier layer 111 away from the auxiliary carrier part 30.
  • the gas barrier layer 111 may be formed by using at least one of materials such as silicon (Si), silicon nitride (SiN), aluminum nitride (AlN), or silicon carbide (SiC).
  • the gas barrier layer 111 includes at least one of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer.
  • a gas barrier layer 111 is prepared in advance before depositing the first substrate 11 , and the gas barrier layer 111 can be used to prevent the semiconductor layer 23 from being caused by gases (eg, methane and hydrogen) used in the deposition process of the first substrate 11 . damage or destruction.
  • gases eg, methane and hydrogen
  • the first substrate 11 is a polycrystalline diamond substrate formed by a chemical vapor deposition process
  • a nanocrystalline diamond layer 112 with small diamond grains will be formed first, and then a microcrystalline diamond layer 113 will be formed as the diamond growth thickness increases.
  • the thickness of the nanocrystalline diamond layer 112 is very thin, which is much smaller than the thickness of the microcrystalline diamond layer 113 .
  • the polycrystalline diamond substrate prepared by the chemical vapor deposition process is a stack of the nanocrystalline diamond layer 112 and the microcrystalline diamond layer 113 .
  • the above-mentioned removal of the supporting substrate 90 also includes removing the temporary bonding layer 91.
  • the removal of the support substrate 90 and the temporary bonding layer 91 may be achieved by processes such as etching, grinding or polishing, but is not limited thereto.
  • the removal may also be performed by means of laser lift-off, thermal lift-off or chemical lift-off.
  • the supporting substrate 90 can also be reused.
  • the auxiliary bearing portion 30 can support and protect the transistor 20 from the side thereof, thereby reducing the difficulty of removing the supporting substrate 90 and further improving the production efficiency.
  • the transistor 20 or some layers of the transistor 20 can be prepared in advance on the wafer 12 , and then the supporting substrate 90 and the auxiliary carrier 30 can be prepared in advance. Simultaneously transferred to the first substrate 11 .
  • the auxiliary bearing portion 30 is formed on the side of the transistor 20 , and can perform auxiliary support and protection for the transistor 20 or part of the layer structure of the transistor 20 during the transfer process of the transistor 20 , thereby effectively improving the process stability during the production process of the semiconductor device 100 . sex.
  • the first substrate 11 is used to carry the transferred transistor 20 and the auxiliary carrying portion 30 , and the plane area of the first substrate 11 is generally larger than the orthographic projection area of the transistor 20 on the first substrate 11 . That is, there is an area on the first substrate 11 that is not covered by the transistor 20 ; this area can be used to accommodate the auxiliary carrier 30 and prepare other electronic components or to dissipate heat. That is to say, the fabrication of the transistor 20 on the wafer 12 may not be affected by the arrangement positions of other components such as the metal pattern 60 in the semiconductor device 100 .
  • the semiconductor film on the wafer 12 (eg, gallium nitride - the gallium nitride layer 122 on the wafer 12) does not need to reserve part of the passive area or only needs to reserve a part of the passive area. Just leave a small passive area part. Therefore, the semiconductor film on the wafer 12 can be effectively utilized and prepared as the channel layer 231 of the transistor 20 to ensure that the wafer 12 has a high area utilization rate, for example, the area utilization rate of the wafer 12 can reach 80% and above.
  • the area utilization ratio of the wafer 12 refers to the ratio of its usable area to its total planar area, and the usable area is the area that can be used to form the channel layer 231 in the transistor 20 .
  • the area ratio of the active region AR in the transistor 20 on the semiconductor layer 23 can be larger, and the area ratio refers to the area of the orthographic projection of the active region AR on the first substrate 11 and the semiconductor layer 23 The ratio of the orthographic projected area on the first substrate 11 .
  • the active region AR refers to: an effective region when the transistor 20 operates; that is, a region for forming a conductive channel in the semiconductor layer 23 of the transistor 20 .
  • the area ratio of the active region AR on the semiconductor layer 23 in the transistor 20 ranges from 80% to 100%; for example, 80%, 90% or 100%.
  • the first substrate 11 is formed of a material whose cost is lower than that of a wide bandgap semiconductor wafer such as gallium nitride, which is also beneficial to reduce the production cost of the semiconductor device 100 .
  • the first substrate 11 is formed of a material with high thermal conductivity. For example, under the condition of a temperature of 300K, the thermal conductivity of the first substrate 11 is greater than 200W/mK, which is also conducive to improving the heat dissipation capability of the semiconductor device 100 or reducing the thermal conductivity.
  • the active area of the semiconductor device 100 is small.
  • FIG. 2 , FIG. 21 , FIG. 22 , and FIG. 23 respectively show the cross-sectional structure of four different semiconductor devices 100 , and the four types of semiconductor devices 100 may be It is prepared by the corresponding steps in the aforementioned preparation method.
  • the transistor 20 in the semiconductor device 100 shown in FIG. 21 includes a transition layer 22 and a second substrate 21
  • the semiconductor device 100 shown in FIG. 22 further includes a bonding layer 40
  • the semiconductor device 100 shown in FIG. 23 further includes a gas barrier layer 111 .
  • the wafer used for preparing the transistor 20 is not limited to the gallium nitride wafer 12 , but can also be a gallium arsenide wafer, a gallium oxide wafer or a wafer with similar properties.
  • the wafer used to fabricate the transistor 20 is a gallium arsenide wafer.
  • the channel layer 231 of the semiconductor layer 23 is a gallium arsenide layer
  • the barrier layer 232 can be a gallium aluminum arsenide (AlGaAs) layer.
  • the fabrication of the transistor 20 on the gallium arsenide wafer is similar to the aforementioned fabrication of the transistor 20 on the gallium nitride wafer 12 , which is not described in detail here.
  • the wafer used to fabricate the transistor 20 is a gallium oxide wafer.
  • the channel layer 231 of the semiconductor layer 23 in the transistor 20 is a gallium oxide layer
  • the barrier layer 232 can be an aluminum nitride layer or a gallium aluminum oxide layer.
  • the fabrication of the transistor 20 on the gallium oxide wafer is similar to the aforementioned fabrication of the transistor 20 on the gallium nitride wafer 12 , which is not described in detail here.
  • the transistor 20 has high electron mobility, and the thickness of the transistor 20 can be set to be small, for example, less than 10 ⁇ m.
  • the transistor 20 only includes the semiconductor layer 23 , the first passivation layer 24 , and the gate electrode 25 , the source electrode 26 and the drain electrode 27 respectively disposed in the opening of the first passivation layer 24 .
  • the thickness D of 20 is less than 5 ⁇ m, for example 3 ⁇ m, 2 ⁇ m or 1 ⁇ m. Therefore, it is beneficial to realize the thinning of the semiconductor device 100 and reduce the thermal resistance of the semiconductor device 100 .
  • the number of transistors 20 may be one or more.
  • the number of transistors 20 is plural.
  • the plurality of transistors 20 may be distributed on the first substrate 11 in an array or arranged in a row.
  • the coupling between the metal pattern 60 and the transistor 20 can also be implemented in various ways. For example, as shown in FIG. 1 , the gate 25 of each transistor 20 is coupled with at least one first metal pattern 61; the source 26 of each transistor 20 is coupled with one second metal pattern 62; the The drain electrode 27 is coupled to a third metal pattern 63 . Or, for example, as shown in FIG.
  • each first metal pattern 61 is coupled to the gate electrode 25 of at least one transistor 20; each second metal pattern 62 is coupled to the source electrode 26 of at least one transistor 20; each The third metal patterns 63 are coupled to the drain 27 of the at least one transistor 20 .
  • This embodiment of the present disclosure does not limit this.
  • the semiconductor device 100 includes four transistors arranged side by side, and each transistor is denoted by code numbers M1 , M2 , M3 and M4 , respectively.
  • each transistor is denoted by code numbers M1 , M2 , M3 and M4 , respectively.
  • Part of the electrodes in the transistors M1, M2, M3 and M4 are shared, which can improve the distribution density of the transistors.
  • transistors M1 and M2 share a drain 27
  • transistors M3 and M2 share a source 26
  • transistors M4 and M3 share a drain 27 .
  • the gates 25 of the respective transistors M1 , M2 , M3 and M4 are interconnected and may be coupled to the same first metal pattern 61 .
  • the source electrodes 26 of the transistors M1 and M4 are located on the outer side and may be respectively coupled to a second metal pattern 62 .
  • the source 26 of the transistor M2 is located between the gates 25 of the transistors M2 and M3, and can be coupled to other conductive parts, for example, to the metal layer 80 on the backside of the first substrate 11 through the first via H1.
  • the drains 27 of the transistors M1 and M4 are interconnected and may be coupled to the same third metal pattern 63 .
  • the following embodiments are described by taking the semiconductor device 100 including only one transistor 20 as an example.
  • the structure of the semiconductor device 100 can be adapted according to the following related descriptions.
  • the source electrode 26 , the gate electrode 25 and the drain electrode 27 of the transistor 20 are elongated and distributed in parallel, and the gate electrode 25 is located between the source electrode 26 and the drain electrode 27 .
  • the plurality of metal patterns 60 in the semiconductor device 100 include two first metal patterns 61 , one second metal pattern 62 and one third metal pattern 63 .
  • the two first metal patterns 61 are located on two sides of the gate electrode 25 respectively, and are coupled to both ends of the gate electrode 25 along the length direction.
  • the second metal pattern 62 is located on the side of the source electrode 26 away from the gate electrode 25 and is coupled to the source electrode 26 .
  • the third metal pattern 63 is located on the side of the drain electrode 27 away from the gate electrode 25 and is coupled to the drain electrode 27 .
  • most of the first metal pattern 61 , the second metal pattern 62 and the third metal pattern 63 are formed on the surface of the auxiliary bearing portion 30 , that is, the first metal pattern 61 , the second metal pattern 63
  • the orthographic projection of most of the third metal pattern 62 and the third metal pattern 63 on the first substrate 11 is located in the region of the first substrate 11 not covered by the semiconductor layer 23 .
  • the metal pattern 60 is formed in the passive region of the semiconductor layer.
  • the semiconductor device 100 using the above structure may have lower production cost.
  • the surface of the auxiliary carrier 30 facing away from the first substrate 11 is flush with or substantially the same as the surface of the gate 25 or the drain 27 of the transistor 20 facing away from the first substrate 11 . flush.
  • the surfaces of the gate electrode 25 and the drain electrode 27 of the transistor 20 facing away from the first substrate 11 may be located on or substantially on the same plane. This facilitates the formation of the metal pattern 60 with better flatness on the auxiliary bearing portion 30 to ensure the film formation quality of the metal pattern 60 .
  • the surface of the auxiliary carrier 30 facing away from the first substrate 11 may be at a distance from the first substrate.
  • the farthest surface of the base 11 is flush or substantially flush.
  • the transistor 20 includes only the semiconductor layer 23 , the first passivation layer 24 , the gate electrode 25 , the source electrode 26 and the drain electrode 27 .
  • the surface of the auxiliary bearing portion 30 close to the first substrate 11 and the surface of the semiconductor layer 23 close to the first substrate 11 are formed in the same polishing process, and they are flush or substantially flush.
  • the transistor 20 further includes: a transition layer 22 and a second substrate 21 stacked on a side of the semiconductor layer 23 away from the gate electrode 25 .
  • the surface of the auxiliary carrier 30 close to the first substrate 11 and the surface of the second substrate 21 close to the first substrate 11 are formed in the same polishing process, and they are flush or substantially flush.
  • the first substrate 11 is formed by a vapor deposition process. As shown in FIG. 20 , the surface of the auxiliary carrier portion 30 facing away from the first substrate 11 is flush or substantially flush with the surface of the first passivation layer 24 facing away from the first substrate 11 .
  • the gate electrode 25 , the source electrode 26 and the drain electrode 27 are respectively formed in the corresponding openings of the first passivation layer 24 .
  • the gate electrode 25 , the source electrode 26 and the drain electrode 27 may protrude or not protrude from the surface of the first passivation layer 24 facing away from the semiconductor layer 24 .
  • the transistor 20 further includes a second passivation layer 28 .
  • the second passivation layer 28 is formed on the surface of the first passivation layer 24 away from the semiconductor layer 23 , and is located on the side of the gate electrode 25 , the source electrode 26 and the drain electrode 27 away from the semiconductor layer 23 .
  • the surface of the auxiliary carrier portion 30 facing away from the first substrate 11 is flush or substantially flush with the surface of the second passivation layer 28 facing away from the first substrate 11 .
  • the metal pattern 60 may be coupled with the gate electrode 25 , the source electrode 26 or the drain electrode 27 through corresponding openings in the second passivation layer 28 .
  • preparing a plurality of transistors 20 on the wafer 12 includes: epitaxially growing a semiconductor layer 23 on the wafer 12 ; forming a first passivation layer 24 on the surface of the semiconductor layer 23 away from the wafer 12 ; A plurality of openings are formed on the first passivation layer 24, and a gate electrode 25, a source electrode 26 and a drain electrode 27 are respectively formed in the plurality of openings; on the first passivation layer 24, the gate electrode 25, the source electrode 26 and the A second passivation layer 28 is formed on the surface of the drain electrode 27 facing away from the semiconductor layer 23 .
  • bonding the front surface of the device particle 201 ( 201 ′) on the support substrate 90 includes: bonding the surface of the second passivation layer 28 away from the gate electrode 25 on the support substrate 90 .
  • a plurality of metal patterns 60 are formed on the side of the auxiliary bearing portion 30 away from the first substrate 11 , so that the plurality of metal patterns 60 are coupled to the transistors 20 correspondingly, and further includes: in the second passivation layer 28 forming a plurality of openings; forming a plurality of metal patterns 60 on the side of the auxiliary bearing portion 30 away from the first substrate 11 , so that the plurality of metal patterns pass through the openings in the second passivation layer 28 and the gate electrode 25 and the source electrode 26.
  • the drain 27 is correspondingly coupled.
  • the transistor 20 and the auxiliary bearing portion 30 are synchronously transferred to the first substrate 11 ,
  • the gate 25 , the source 26 and the drain 27 of the transistor 20 can be effectively protected by the second passivation layer 28 , thereby preventing the gate 25 , the source 26 and the drain 27 of the transistor 20 from being damaged due to the transfer of the transistor 20 .
  • the auxiliary carrying portion 30 is used to assist in supporting the transistor 20 , and there may be various arrangements in which the auxiliary carrying portion 30 is located beside the transistor 20 .
  • the auxiliary bearing parts 30 are disposed on at least two sides of the transistor 20 .
  • the auxiliary bearing parts 30 are disposed on opposite sides of the transistor 20 , and the auxiliary bearing parts 30 include two sub-parts 31 and 32 which are independently arranged.
  • the auxiliary bearing parts 30 are disposed on adjacent two sides of the transistor 20 .
  • the auxiliary bearing portion 30 is disposed around the periphery of the transistor 20 .
  • the auxiliary carrying part 30 and the transistor 20 in the semiconductor device 100 are arranged on the first substrate 11.
  • the ratio of the orthographic projection area can be controlled within a reasonable range.
  • the orthographic projection area of the transistor 20 in the semiconductor device 100 on the first substrate 11 is the first area S1
  • the orthographic projection of the auxiliary bearing portion 30 on the first substrate 11 is the first area S1 .
  • the area is the second area S2, then: E.g, or 1.
  • the semiconductor device 100 further includes a heat dissipation insulating layer 50 formed on the surfaces of the auxiliary carrier 30 and the transistor 20 facing away from the first substrate 11 .
  • the metal pattern 60 is formed on the surface of the heat dissipation insulating layer 50 facing away from the auxiliary bearing portion 30 , and the metal pattern 60 can be correspondingly coupled to the electrodes in the transistor 20 through the opening in the heat dissipation insulating layer 50 .
  • the manufacturing method of the semiconductor device 100 further includes: forming a heat dissipation insulating layer 50 on the surfaces of the auxiliary bearing portion 30 and the transistor 20 away from the first substrate 11 , so that the foregoing plurality of metal patterns 60 are formed on the heat dissipation insulating layer 50 on the surface facing away from the auxiliary bearing portion 30 .
  • the heat-dissipating insulating layer 50 may be prepared and formed by using an insulating material with good heat-dissipating capability.
  • the heat dissipation insulating layer 50 is, for example, a diamond layer.
  • the metal pattern 60 is formed on the surface of the heat dissipation insulating layer 50 away from the auxiliary bearing portion 30 , and can effectively conduct the heat generated during the operation of the transistor 20 through the heat dissipation insulating layer 50 , thereby effectively improving the heat dissipation capability of the semiconductor device 100 .
  • the orthographic projection area of the auxiliary bearing portion 30 on the first substrate 11 is smaller than the plane area of the first substrate 11 .
  • Part of the surface of the heat dissipation insulating layer 50 may also be in direct contact with the first substrate 11 . That is, the heat-dissipating insulating layer 50 can simultaneously cover the auxiliary bearing portion 30 and the surface of the first substrate 11 that is not covered by the auxiliary bearing portion 30 , so that the orthographic projection of the auxiliary bearing portion 30 on the first substrate 11 is located in the heat-dissipating area.
  • the insulating layer 50 is in an orthographic projection on the first substrate 11 .
  • the heat dissipation insulating layer 50 is in direct contact with the first substrate 11 and can also conduct heat to the first substrate 11 to further improve the heat dissipation capability of the semiconductor device 100 .
  • the semiconductor device 100 further includes: a metal layer 80 formed on a surface of the first substrate 11 facing away from the transistor 11 .
  • the metal layer 80 is formed on the surface of the first substrate 11 away from the semiconductor layer 23 , and the heat dissipation capability of the first substrate 11 can be further improved by using the metal layer 80 .
  • the metal layer 80 may be formed by using a metal material with better heat dissipation capability, such as at least one of copper, aluminum, platinum, tungsten, nickel, iridium or cobalt.
  • the semiconductor device 100 further includes: a heat dissipation substrate 82 disposed on a side of the metal layer 80 away from the first substrate 11 .
  • the metal layer 80 can be soldered on the heat dissipation substrate 82, for example, using gold-tin soldering, copper-tin soldering, nano-silver sintering and other processes. That is, there is a welding layer 81 between the metal layer 80 and the heat dissipation substrate 82 , and the material of the welding layer 81 can be selected and set according to actual needs to ensure good welding quality between the metal layer 80 and the heat dissipation substrate 82 .
  • the metal layer 80 is welded on the heat dissipation substrate 82 , and the heat dissipation substrate 82 can be used to further improve the heat dissipation capability of the semiconductor device 100 .
  • the heat dissipation substrate 82 is a substrate with high thermal conductivity, such as an aluminum substrate, a copper substrate, a diamond/metal composite substrate, a ceramic substrate, a rigid printed circuit board or a flexible printed circuit board.
  • the preparation method further includes: forming a metal layer 80 on the surface of the first substrate 11 away from the transistor 20; 80 is welded on the heat dissipation substrate 82 .
  • the metal layer 80 can be used as a common electrode in addition to heat dissipation, so as to provide a ground signal or a floating signal to the transistor 20 or other electronic components in the semiconductor device 100 .
  • metal layer 80 may be coupled to source 26 or drain 27 in transistor 20 .
  • the semiconductor device 100 further includes at least one first via hole H1 .
  • the first via hole H1 penetrates at least the first substrate 11 and the semiconductor layer 23 , and the orthographic projection of the first via hole H1 on the metal layer 80 corresponds to the orthographic projection of the source electrode 26 in the transistor 20 on the metal layer 80 Inside.
  • the metal layer 80 may be coupled with the corresponding source electrode 26 through the first via hole H1.
  • the layer structure required to pass through the first via hole H1 is consistent with the layer structure between the metal layer 80 and the source electrode 26 .
  • the layer structure through which the first via hole H1 passes may be different, which will not be described in detail here.
  • the method for fabricating the semiconductor device 100 further includes: forming a first via hole H1 penetrating at least the first substrate 11 and the semiconductor layer 23 , and making the first via hole H1 in the first via hole H1 .
  • the orthographic projection on the substrate 11 lies within the orthographic projection of the source 26 in the corresponding transistor 20 on the first substrate 11 . In this way, after the metal layer 80 is formed on the surface of the first substrate 11 away from the transistor 20, the metal layer 80 can be coupled to the corresponding source electrode 26 through the first via hole H1.
  • the transistor 20 includes a transition layer 22 and a second substrate 21 .
  • the semiconductor device 100 also includes a bonding layer 40 between the first substrate 11 and the second substrate 21 .
  • the bonding layer 40 is a conductive bonding layer.
  • the first via hole H1 includes a first sub via hole H11 and a second sub via hole H12 which are arranged in sections.
  • the first sub-via hole H11 penetrates through the second substrate 21 , the transition layer 22 and the semiconductor layer 23 , and two ends of the first sub-via hole H1 are respectively coupled to the source electrode 26 and the conductive bonding layer 40 .
  • the second sub-via hole H12 penetrates through the first substrate 11 , and both ends of the second sub-via hole H12 are respectively coupled to the conductive bonding layer 40 and the metal layer 80 .
  • forming the first via hole H1 penetrating at least the first substrate 11 and the semiconductor layer 23 includes: forming the first via hole H1 penetrating the second substrate 21 , the transition layer 22 and the semiconductor layer 23 . the first sub-via hole H11, so that one end of the first sub-via hole H11 is in direct contact with the corresponding source electrode 26; a conductive bonding layer 40 is formed on the polished surface of the auxiliary bearing portion 20 and the transistor 20, so that the conductive bonding layer 40 is formed.
  • the layer 40 is in direct contact with the other end of the first sub-via hole H11; the first substrate 22 is bonded on the conductive bonding layer 40; the second sub-via hole H12 is formed through the first substrate 11, so that the One end of the two sub-via holes H12 is in direct contact with the conductive bonding layer 40 ; a metal layer 80 is formed on the first substrate 11 so that the metal layer 80 is in direct contact with the other end of the second sub-via hole H12 .
  • the preparation of the first via hole H1 is realized.
  • the first via hole H1 is composed of the first sub via hole H11 and the second sub via hole H12, which can reduce the difficulty of manufacturing the first via hole H1 and ensure the electrical connection of the first via hole H1. performance, especially when the thickness of the first substrate 11 and the transistor 20 is large.
  • the metal layer 80 may be coupled to a certain metal pattern 60 , for example, to the second metal pattern 62 .
  • the semiconductor device 100 further includes at least one second via hole H2.
  • the second via hole H2 penetrates at least the first substrate 11 and the auxiliary bearing portion 30 , and the orthographic projection of the second via hole H2 on the metal layer 80 is located at the orthographic projection of the corresponding metal pattern 60 on the first substrate 11 Inside.
  • the metal layer 80 may be coupled with the corresponding metal pattern 60 through the second via hole H2.
  • the layer structure that the second via hole H2 needs to penetrate is consistent with the layer structure between the metal layer 80 and the metal pattern 60 .
  • the layer structure through which the second via hole H2 passes may be different, which will not be described in detail here.
  • the preparation method of the semiconductor device 100 further includes: forming a second via hole H2 penetrating at least the first substrate 11 and the auxiliary bearing portion 30 , and making the second via hole H2 in the metal
  • the orthographic projection on the layer 80 lies within the orthographic projection of the corresponding metal pattern 60 on the first substrate 11 . In this way, after the metal layer 80 is formed on the surface of the first substrate 11 away from the transistor 20 , the metal layer 80 can be coupled to the corresponding metal pattern 60 through the second via hole H2 .
  • the transistor 20 includes a transition layer 22 and a second substrate 21 .
  • the semiconductor device 100 also includes a bonding layer 40 between the first substrate 11 and the second substrate 21 .
  • the bonding layer 40 is a conductive bonding layer.
  • the second via hole H2 includes a third sub via hole H21 and a fourth sub via hole H22 which are arranged in sections.
  • the third sub-via hole H21 penetrates through the auxiliary bearing portion 30 , and both ends of the third sub-via hole H21 are respectively coupled to the metal pattern 60 and the conductive bonding layer 40 .
  • the fourth sub-via hole H22 penetrates through the first substrate 11 , and two ends of the fourth sub-via hole H22 are respectively coupled to the conductive bonding layer 40 and the metal layer 80 .
  • forming the second via hole H2 penetrating at least the first substrate 11 and the auxiliary carrying portion 30 includes: forming a third sub-conducting hole H21 penetrating the auxiliary carrying portion 30 ;
  • a conductive bonding layer 40 is formed on the polished surfaces of the auxiliary bearing portion 30 and the transistor 20, so that the conductive bonding layer 40 is in direct contact with one end of the third sub-conduction hole H21; the first substrate 11 is bonded on the conductive bonding layer layer 40;
  • a fourth sub-conducting hole H22 is formed through the first substrate 11, so that one end of the fourth sub-conducting hole H22 is in direct contact with the conductive bonding layer 40;
  • a metal layer 80 is formed on the first substrate 11 , so that the metal layer 80 is in direct contact with the other end of the fourth sub-conduction hole H22.
  • the metal pattern 60 is in direct contact with the other end of the third sub-via hole H21, and the connection between the metal pattern 60 and the conductive bonding layer 40 can be realized through the third sub-via hole H21 the coupling.
  • the second via hole H2 is composed of the third sub via hole H21 and the fourth sub via hole H22, which can reduce the difficulty of manufacturing the second via hole H2 and ensure the electrical connection of the second via hole H2 performance, especially when the thickness of the first substrate 11 and the auxiliary bearing portion 30 is relatively large.
  • the through holes H22 include through holes and metal conductors filled in the through holes.
  • the metal conductor in the first via hole H1 or the second via hole H2 can be made of the same metal material as the metal layer 80 , to simplify the fabrication process of the semiconductor device 100 .
  • the metal patterns 60 are planar electrodes or metal lines.
  • the semiconductor device 100 further includes: a plurality of bonding pads 70 .
  • the bonding pads 70 are formed on the corresponding metal patterns 60 , and the orthographic projection of the bonding pads 70 on the first substrate 11 is located in the area of the first substrate 11 not covered by the transistors 20 .
  • the method for fabricating the semiconductor device 100 further includes: forming at least one bonding pad 70 on the metal pattern 60 , so that the orthographic projection of the bonding pad 70 on the first substrate 11 is located on the first substrate 11 . in the regions of the substrate 11 not covered by the transistors 20 .
  • the bonding pad 70 may be made of a metal material with good electrical conductivity and certain mechanical strength, such as at least one of gold, copper, aluminum, platinum, tungsten, nickel, iridium, or cobalt.
  • the material of the bonding pad 70 may be the same as or different from the material of the metal pattern 60 .
  • the material hardness of the bonding pad 70 is greater than that of the metal pattern 60 .
  • the bonding pad 70 is disposed on the surface corresponding to the metal pattern 60 in the shape of a boss, which is convenient for bonding external metal leads on the surface of the bonding pad 70, so as to use the metal leads to couple with the external components, so as to realize the semiconductor device 100 Transmission of electrical signals to and from external components.
  • the external component is, for example, a package casing or a transition substrate.
  • the semiconductor device 100 shown in FIG. 41 is used as an example for detailed description below.
  • a passive matching circuit can be fabricated in a region of the first substrate 11 not covered by the transistor 20 and the auxiliary bearing portion 30 by using the multi-layer pattern of the metal pattern 60 .
  • the passive matching circuit is fabricated on the surface of the auxiliary bearing portion 30 facing away from the first substrate 11 .
  • the passive matching circuit can generally be composed of at least one of capacitors, inductors, resistors, metal lines and metal vias.
  • the metal pattern 60 includes: a first metal pattern 61 coupled to the gate electrode 25, a second metal pattern 62 coupled to the source electrode 26, and a drain electrode 26. 27 is coupled to the third metal pattern 63.
  • the plurality of bond pads 70 include: at least one first bond pad 71 formed on the first metal pattern 61, at least one second bond pad 72 formed on the second metal pattern 62, and at least one second bond pad 72 formed on the second metal pattern 62. At least one third bond pad 73 on the third metal pattern 63 .
  • the first metal pattern 61 and the third metal pattern 63 each include two-layer patterns, and an insulating layer 32 is disposed between the first layer pattern and the second layer pattern.
  • the first layer pattern is formed on the first substrate 11
  • the second layer pattern is formed on the side of the first layer pattern that is away from the first substrate 11 , that is, the surface of the insulating layer 32 that is away from the first substrate 11 .
  • the insulating layer 32 may also be composed of the heat dissipation insulating layer 50 in some of the foregoing embodiments.
  • the second metal pattern 62 is a single-layer pattern, and the second metal pattern 62 is formed on the surface of the insulating layer 32 facing away from the first substrate 11 . In this way, the second metal pattern 62 can be formed synchronously with the second layer pattern in the first metal pattern 61 and the third metal pattern 63 .
  • At least a first capacitor C1 , a second capacitor C2 and a first inductor L1 can be formed using the first metal pattern 61 .
  • the first pole 611 of the first capacitor C1 and the first pole of the second capacitor C2 may be formed by the first layer pattern in the first metal pattern 61
  • the second pole 612 of the first capacitor C1 and the second capacitor C2 The second pole of the first metal pattern 61 may be formed by the second layer pattern.
  • the first inductor L1 adopts a trench inductor, which can be formed by using the second layer pattern in the first metal pattern 61 .
  • the interconnection between the first capacitor C1 , the second capacitor C2 , the first inductor L1 and the gate 25 of the transistor 20 may be implemented by metal wires or metal vias.
  • the first bonding pad 71 is formed on the second layer pattern of the first metal pattern 61 .
  • first resistor R1 and a second inductor L2 can be formed using the third metal pattern 63 .
  • the first resistor R1 may be formed of the first layer pattern in the third metal pattern 63 .
  • the second inductor L2 adopts a trench inductor, which can be formed by using the second layer pattern in the third metal pattern 63 .
  • the coupling between the first resistor R1 , the second inductor L2 and the drain electrode 27 of the transistor 20 can be realized by metal wires or metal vias.
  • the third bonding pad 73 is formed on the second layer pattern of the third metal pattern 63 .
  • the above-mentioned passive matching circuit can also be coupled to the metal layer 80 disposed on the first substrate 11 through a via hole penetrating the first substrate 11, so as to use the metal layer 80 to transmit ground signals or floating empty signal.
  • an electronic device 1000 includes: at least one semiconductor device 100 as described in any of the above embodiments.
  • the electronic device is, for example, a monolithic microwave integrated circuit (Monolithic Microwave Integrated Circuit, MMIC for short), an MMIC-based power amplifier, a mixer, a detector, a modulator, a phase shifter, or a power adapter and other electronic products.
  • MMIC Monolithic Microwave Integrated Circuit
  • the embodiments of the present disclosure do not specifically limit the specific form of the electronic device.
  • the electronic device 1000 is a power amplifier. 44 and 45 schematically illustrate two cross-sectional structures of the electronic device 1000, but are not limited thereto.
  • the semiconductor device 100 includes a heat dissipation substrate 82 .
  • the electronic device 1000 further includes a metal lead 1001 , an external lead 1002 and an insulating portion 1003 .
  • the insulating portion 1003 is formed on the exposed surface of the heat-dissipating substrate 82 using insulating material, such as ceramic material.
  • the external pins 1002 are provided on the surface of the insulating portion 1003 away from the heat-dissipating substrate 82 .
  • the metal patterns 60 or the bonding pads 70 in the semiconductor device 100 may be coupled to the external pins 1002 through metal leads 1001 correspondingly.
  • the structures of the metal leads 1001 , the external pins 1002 and the insulating portion 1003 can be selected and set according to actual needs. This embodiment of the present disclosure does not limit this.
  • the insulating portion 1003 adopts a ring-shaped structure, and there is a space between parts such as the first substrate 11 located on the heat dissipation substrate 82 in the semiconductor device 1000 and the inner sidewall of the insulating portion 1003 .
  • the external pins 1002 are formed of hollow metal sheets.
  • the metal lead 1001 is made of a metal material with good electrical conductivity and certain mechanical strength, such as at least one of gold, copper, aluminum, platinum, tungsten, nickel, iridium or cobalt.
  • the electronic device 1000 further includes a package cover 1004 .
  • the package cover 1004 can be fastened on the heat dissipation substrate 82 or the ceramic part 1003 . Parts of the external pins 1002 protrude from the package cover plate 1004 to facilitate the coupling of the electronic device 1000 with external components.
  • the advantages of the electronic device 1000 are the same as the advantages of the semiconductor device 100 in some of the foregoing embodiments, which will not be described in detail here.

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Abstract

本公开实施例提供一种半导体器件及其制备方法、电子设备，能够解决半导体器件制备过程中高成本晶圆有效利用率低的问题，并有效提升半导体器件生产过程中的工艺稳定性。该半导体器件包括：第一衬底、至少一个晶体管、辅助承载部以及多个金属图案。辅助承载部和该至少一个晶体管被设置于第一衬底上。辅助承载部在第一衬底上的正投影位于该至少一个晶体管在第一衬底上的正投影外，且辅助承载部在第一衬底上的正投影边界与该至少一个晶体管在第一衬底上的正投影边界部分重合。该多个金属图案形成于辅助承载部的背离第一衬底的一侧，且其中的至少一个金属图案与晶体管的栅极耦接，至少一个金属图案与晶体管的漏极耦接。

Description

半导体器件及其制备方法、电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种半导体器件及其制备方法、电子设备。
背景技术
基于III-V族元素的氮化物及其合金，例如氮化镓(GaN)，作为第三代半导体材料，其具有高击穿场强、高热稳定性、高电子饱和漂移速度等出色的性能。
目前，以氮化镓等宽禁带半导体作为半导体材料制备的半导体器件，例如异质结场效应晶体管(Heterojunction Field Effect Transistors，简称HFET)或高电子迁移率晶体管(High Electron Mobility Transistor，简称HEMT)器件，具有耐热、高频、大功率和抗辐射等特点，能够被广泛地应用于无线通信等领域。
示例的，氮化镓基高电子迁移率晶体管(GaN-HEMT)也可称为氮化镓基二维电子气场效应管或氮化镓基调制掺杂场效应管，其可以依赖于氮化镓晶圆制备获得。然而，氮化镓晶圆的成本高昂。在半导体器件由一个或多个GaN-HEMT构成，且利用氮化镓晶圆批量制备半导体器件的情况下，若氮化镓晶圆的面积利用率较低，则容易导致半导体器件的生产成本居高不下。
例如，在GaN-HEMT器件中，GaN半导体层包括有源区(active area)和无源区(passive area)，其中有源区是指GaN半导体层内用于形成导电沟道的区域，无源区为有源区之外的区域。GaN-HEMT器件中用于与外部电源或外部信号源互连的金属线或键合盘对应形成于无源区内。由此，GaN半导体层位于无源区内的部分实际上并未起到半导体的作用。也即，GaN半导体层位于有源区内的部分才为其可工作的有效部分。因此，有源区在整个GaN半导体层中的面积占比即为GaN半导体层的面积利用率。在一些情况下，有源区在整个GaN半导体层中的面积占比不足50％，即GaN半导体层的面积利用率不足50％，从而会造成严重的成本浪费。
发明内容
本公开实施例提供一种半导体器件及其制备方法、电子设备，用于解决半导体器件批量制备过程中氮化镓等宽禁带半导体晶圆的面积利用率低的问题，以降低半导体器件的生产成本，并有效提升半导体器件生产过程中的工艺稳定性，以及提升半导体器件的散热能力。
一方面，本公开一些实施例提供了一种半导体器件。该半导体器件包括：第一衬底、至少一个晶体管、辅助承载部、以及多个金属图案。辅助承载部和该至少一个晶体管被设置于第一衬底上。辅助承载部在第一衬底上的正投影位于该至少一个晶体管在第一衬底上的正投影外，且辅助承载部在第一衬底上的正投影边界与该至少一个晶体管在第一衬底上的正投影边界部分重合。该至少一个晶体管中的每个晶体管包括：半导体层，以及位于半导体层的背离第一衬底的一侧的栅极、漏极和源极。该多个金属图案形成于辅助承载部的背离第一衬底的一侧。该多个金属图案中的至少一个金属图案与栅极耦接，至少一个金属图案与漏极耦接，且与栅极耦接的金属图案和与漏极耦接的金属图案绝缘。
在本公开实施例中，辅助承载部和该至少一个晶体管被设置于第一衬底上，意味着辅助承载部和该至少一个晶体管可以被同步转移于第一衬底上。这也就是说，晶体管或晶体管的组成部分(例如半导体层等)可以预先在半导体晶圆上制备完成，然后再与辅助承载部同步转移至第一衬底上，也即：第一衬底并非是晶体管的制备衬底。由于辅助承载部在第一衬底上的正投影位于该至少一个晶体管在第一衬底上的正投影外，且辅助承载部在第一衬底上的正投影边界与该至少一个晶体管在第一衬底上的正投影边界部分重合，因此，辅助承载部可以在晶体管的转移过程中形成于该至少一个晶体管的旁侧，并与该至少一个晶体管同步转移至第一衬底上。这样利用辅助承载部对该至少一个晶体管进行支撑保护，可以有效提升半导体器件生产过程中的工艺稳定性。
此外，第一衬底并非是晶体管的制备衬底。并且，辅助承载部可以形成于该至少一个晶体管的转移过程中，金属图案又可以形成于辅助承载部和晶体管转移至第一衬底上之后。因此，晶体管在半导体晶圆上的制备可以不受半导体器件中金属图案等其他组成元件设置位置的影响。这样在半导体晶圆上批量制备晶体管的过程中，半导体晶圆上的半导体层无需预留无源区的部分或仅需预留很小的无源区部分即可。从而使得半导体晶圆上的半导体层能够被有效利用并制备出晶体管的有源区，以确保半导体晶圆具有较高的面积利用率和较高的芯片产出(die-per-wafer)。
基于此，在第一衬底的材料成本和转移工艺成本低于氮化镓等宽禁带半导体晶圆的材料成本和器件加工成本的情况下，半导体器件采用如上结构还可以降低半导体器件的生产成本。并且，在第一衬底采用具有较高热导率的材料的情况下，利用第一衬底还可以有效提升半导体器件的散热能力，从而可以在相同的有源区面积上实现更大的功率密度，或在实现相同功率的前提下对应缩小有源区面积，以进一步降低半导体器件的生产成本。
需要说明的是，晶体管通常还包括位于半导体层的背离第一衬底的表面上的第一钝化层。第一钝化层包括多个开口。晶体管中的栅极、源极和漏极分别形成于对应的开口内。
在一种可能的实施方式，辅助承载部的背离第一衬底的表面、与栅极或漏极的背离第一衬底的表面平齐或大致平齐。这样有利于在辅助承载部上形成具有较好平面度的金属图案，以确保金属图案的成膜质量。
在另一种可能的实施方式，辅助承载部的背离第一衬底的表面、与第一钝化层的背离第一衬底的表面平齐或大致平齐。这样可以在未制备晶体管的栅极、源极和漏极之前，便将晶体管和辅助承载部同步转移至第一衬底上，以利用第一钝化层有效保护半导体层，并避免晶体管的栅极、源极和漏极因晶体管的转移而受损。
在又一种可能的实施方式，晶体管还包括第二钝化层。第二钝化层包括多个开口。第二钝化层形成于第一钝化层的背离半导体层的表面上，且位于栅极、源极和漏极的背离半导体层的一侧。辅助承载部的背离所述第一衬底的表面、与第二钝化层的背离第一衬底的表面平齐或大致平齐。金属图案通过第二钝化层中对应的开口与栅极或漏极耦接。这样可以在制备晶体管的栅极、源极、漏极以及第二钝化层之后，再将晶体管和辅助承载部同步转移至第一衬底上，以利用第二钝化层有效保护晶体管的栅极、 源极和漏极，从而避免晶体管的栅极、源极和漏极因晶体管的转移而受损。
上述一些实施例中，辅助承载部位于晶体管旁侧的设置方式可以有多种。可选的，辅助承载部设置于前述至少一个晶体管的至少两侧，所述两侧包括相对的两侧或相邻的两侧。例如，辅助承载部环绕设置于前述至少一个晶体管的周侧。本公开实施例对此不作限定。
可选的，前述至少一个晶体管在第一衬底上的正投影面积为第一面积S1。辅助承载部在第一衬底上的正投影面积为第二面积S2。本公开实施例中，限定：
Figure PCTCN2020135857-appb-000001
能够利用辅助承载部对晶体管进行有效的支撑保护，从而提升半导体器件生产过程中的工艺稳定性。
在一些实施例中，辅助承载部的材料包括氧化硅、氮化硅、氮氧化硅、硅、碳化硅、氮化铝、氧化铝、环氧树脂、聚酰亚胺、或苯并环丁烯。辅助承载部采用具备一定机械强度的绝缘材料制备形成，不仅可以具有较好的支撑强度，还可以有效绝缘半导体层和金属图案。
在一些实施例中，半导体器件还包括散热绝缘层。散热绝缘层形成于辅助承载部和晶体管的背离第一衬底的表面上。金属图案形成于散热绝缘层的背离辅助承载部的表面上。散热绝缘层可以采用具有良好散热能力的绝缘材料制备形成。散热绝缘层例如为金刚石层。金属图案形成于散热绝缘层的背离辅助承载部的表面上，可以将晶体管工作过程中产生的热量利用散热绝缘层有效传导出去，从而有效提升半导体器件的散热能力。
可选的，辅助承载部在第一衬底上的正投影位于散热绝缘层在第一衬底上的正投影内。散热绝缘层的部分表面与第一衬底直接接触。如此，在第一衬底具有较高热导率的情况下，散热绝缘层与第一衬底直接接触，还可以传导热量至第一衬底，以进一步提升半导体器件的散热能力。
在一些实施例中，半导体器件还包括：形成于第一衬底的背离晶体管的表面上的金属层。本公开实施例在第一衬底的背离晶体管的表面上形成金属层，还可以利用金属层提升第一衬底的散热能力。金属层可以采用散热能力较好的金属材料制作形成，该金属材料例如为铜、铝、铂、钨、镍、铱或钴等中的至少一种。
可选的，半导体器件还包括至少一个第一导通孔。第一导通孔至少贯穿第一衬底和半导体层。第一导通孔在金属层上的正投影位于对应晶体管中的源极在金属层上的正投影内。金属层通过第一导通孔与源极耦接。
可选的，半导体器件还包括至少一个第二导通孔。第二导通孔至少贯穿第一衬底和辅助承载部。第二导通孔在金属层上的正投影位于对应的金属图案在第一衬底上的正投影内。金属层通过第二导通孔与金属图案耦接。
在上述一些实施例中，金属层与对应的源极或金属图案耦接，金属层还可以作为公共电极使用，以向半导体器件中的晶体管或其他电子元件提供接地信号或浮空信号。此外，第一导通孔和第二导通孔贯穿的层结构均与半导体器件中的层结构相关，根据实际需求设置即可。
在一些实施例中，半导体器件还包括散热基板。散热基板位于金属层的背离第一衬底的一侧。金属层焊接于散热基板上。如此，利用散热基板可以进一步提升半导体器件的散热能力。可选的，散热基板为铝基板、铜基板、金刚石/金属复合基板、陶瓷基板、硬式印刷电路板或软式印刷电路板等具有较高热导率的基板。
在一些实施例中，辅助承载部的靠近第一衬底的表面、与半导体层的靠近第一衬底的表面平齐或大致平齐。如此，方便于采用同一抛光工艺制备出辅助承载部和半导体层的平齐表面，以确保辅助承载部和半导体层均具有较好的表面质量。从而实现辅助承载部和半导体层二者与第一衬底的良好键合，或在辅助承载部和半导体层上形成具有良好成膜质量的第一衬底。进而，有利于提升半导体器件的使用可靠性。
可选的，半导体器件还包括非导电键合层。辅助承载部和晶体管的半导体层通过非导电键合层键合至第一衬底上。这样利用非导电键合层，不仅可以增强辅助承载部和晶体管各自与第一衬底之间的键合强度，还可以确保晶体管不会因其存在而出现漏电流等情况，有利于确保半导体器件的电学性能。
在另一些实施例中，晶体管还包括：层叠位于半导体层的背离栅极的一侧的过渡层和第二衬底。此处，第二衬底为晶体管的制备衬底或制备衬底的一部分，例如为半导体晶圆的基底，可以使得过渡层和半导体层外延生长于其上。第二衬底采用与半导体层具有较好晶格匹配和热匹配的材料构成。例如，半导体层包括GaN层，第二衬底为蓝宝石衬底、硅衬底或碳化硅衬底。
在此基础上，辅助承载部的靠近第一衬底的表面、与第二衬底的靠近第一衬底的表面平齐或大致平齐。如此，方便于采用同一抛光工艺制备出辅助承载部和第二衬底的平齐表面，以确保辅助承载部和第二衬底均具有较好的表面质量。从而实现辅助承载部和第二衬底二者与第一衬底的良好键合，或在辅助承载部和第二衬底上形成具有良好成膜质量的第一衬底。进而，有利于提升半导体器件的使用可靠性。
可选的，半导体器件还包括键合层。辅助承载部和晶体管中的第二衬底可以通过键合层键合至第一衬底上，以利用键合层增强辅助承载部和晶体管各自与第一衬底之间的键合强度。进一步地，该键合层可以为非导电键合层，以利用非导电键合层确保晶体管不会因其存在而出现漏电流等情况，有利于确保半导体器件的电学性能。或者，在第二衬底保留一定厚度且具备绝缘性能时，例如第二衬底为5μm-10um的半绝缘碳化硅衬底，该键合层也可以为导电键合层。这样利用第二衬底可以消除导电键合层对半导体器件电学性能的影响。
此外，在一种可能的实施方式中，半导体器件包括第一导通孔，第一导通孔包括分段设置的第一子导通孔和第二子导通孔。第一子导通孔贯穿第二衬底、过渡层和半导体层，第一子导通孔的两端分别与源极和导电键合层耦接。第二子导通孔贯穿第一衬底，第二子导通孔的两端分别与导电键合层和金属层耦接。如此，在键合层为导电键合层的情况下，第一导通孔由第一子导通孔和第二子导通孔构成，可以降低第一导通孔的制作难度，并确保第一导通孔的电连接性能，尤其是针对第一衬底和晶体管的厚度较大的情况。
在另一种可能的实施方式中，半导体器件包括第二导通孔，第二导通孔包括分段设置的第三子导通孔和第四子导通孔。第三子导通孔至少贯穿辅助承载部，第三子导 通孔的两端分别与金属图案和导电键合层耦接。第四子导通孔贯穿第一衬底，第四子导通孔的两端分别与导电键合层和金属层耦接。如此，在键合层为导电键合层的情况下，第二导通孔由第三子导通孔和第四子导通孔构成，可以降低第二导通孔的制作难度，并确保第二导通孔的电连接性能，尤其是针对第一衬底和辅助承载部的厚度较大的情况。
在一些实施例中，第一衬底包括：单晶碳化硅衬底、多晶碳化硅衬底、单晶氮化铝衬底、多晶氮化铝衬底、单晶金刚石衬底、多晶金刚石衬底、石墨衬底、多层石墨烯衬底或铜衬底。其中，单晶碳化硅衬底包括：高纯半绝缘单晶碳化硅衬底、或掺钒碳化硅衬底。第一衬底采用成本低于宽禁带半导体晶圆的衬底，有利于降低半导体器件的生产成本。第一衬底采用具有较高热导率的衬底，例如在温度为300K的条件下，第一衬底的热导率大于200W/mK，可以确保半导体器件具有良好的散热能力。
可选的，第一衬底为多晶碳化硅衬底、多晶氮化铝衬底或多晶金刚石衬底。如此，第一衬底可以采用气相沉积工艺制备形成。
在此基础上，半导体器件还包括气体阻挡层。气体阻挡层例如为硅层、氮化硅层、氮化铝层或碳化硅层中的至少一层。气体阻挡层形成于辅助承载部和晶体管的靠近第一衬底的表面上。第一衬底形成于气体阻挡层的背离辅助承载部的表面上。本公开实施例在第一衬底和辅助承载部、晶体管之间设置气体阻挡层，可以在半导体器件的制备过程中，利用气体阻挡层有效防止第一衬底沉积工艺中所使用的气体对半导体层造成损伤或破坏。
在一些实施例中，半导体器件还包括：多个键合盘。键合盘形成于对应的金属图案上，且键合盘在第一衬底上的正投影位于第一衬底的未被晶体管覆盖的区域内。这样方便于在键合盘的表面键合外接的金属线，从而利用该金属线与外接部件进行耦接，以实现半导体器件和外接部件之间电信号的传输。
需要补充的是，在上述一些实施例中，半导体层包括沿远离第一衬底的方向层叠设置的沟道层和势垒层。可选的，沟道层为氮化镓层，势垒层为氮化镓铝层或氮化铝层。或者，沟道层为砷化镓层，势垒层为砷化镓铝层。或者，沟道层为氧化镓层，势垒层为氮化铝层或氧化镓铝层。
此外，可选的，晶体管的厚度小于10μm，有利于实现半导体器件的轻薄化，以及降低半导体器件的热阻。晶体管的有源区在其半导体层中面积占比的取值范围为80％～100％，可以使得制备晶体管所需的半导体晶圆的面积利用率达到80％及以上，以降低半导体器件的生产成本。
另一方面，本公开一些实施例提供了一种电子设备。该电子设备包括：如上任一些实施例所述的至少一个半导体器件。本公开实施例中电子设备所能实现的技术效果同前述一些实施例中半导体器件所能实现的技术效果相同，此处不再赘述。
又一方面，本公开一些实施例提供了一种半导体器件的制备方法。该半导体器件的制备方法包括以下步骤。
首先，提供晶圆，在晶圆上制备多个晶体管或多个晶体管的部分层，其中，晶体管或其部分层的正面为背离晶圆的最外层表面。沿晶圆的厚度方向切割晶圆，获得多个器件颗粒。一个器件颗粒包括至少一个晶体管或至少一个晶体管的部分层。
其次，提供支撑基板，将至少一个器件颗粒的正面键合在支撑基板上。该器件颗粒的正面为前述晶体管或其部分层的正面。
然后，在支撑基板的未被器件颗粒覆盖的表面、以及器件颗粒的背面形成辅助承载膜。抛光辅助承载膜以及器件颗粒，获得至少一个晶体管、以及位于该至少一个晶体管旁侧的辅助承载部。辅助承载部的抛光表面与晶体管的抛光表面位于同一平面。
之后，提供第一衬底，将辅助承载部和该至少一个晶体管的抛光表面同步键合在第一衬底上。或者，在辅助承载部和晶体管的抛光表面上制备第一衬底。
之后，去除支撑基板。
最后，在辅助承载部的背离第一衬底的一侧形成多个金属图案，并使得金属图案与晶体管对应耦接。从而获得半导体器件。
本公开实施例中半导体器件的制备方法具有与前述实施例提供的半导体器件相同的技术效果，此处不再赘述。此外，本公开实施例中，借助支撑基板，可以将晶体管和辅助承载部同步转移至第一衬底上，其操作简单，有利于提高生产效率。
在一些实施例中，器件颗粒中的晶体管至少包括：第二衬底以及外延生长在第二衬底上的半导体层。该第二衬底为晶圆的位于器件颗粒中的部分。抛光器件颗粒，还包括：使得晶体管中的半导体层的靠近第二衬底的表面裸露；或，使得晶体管中的第二衬底的抛光表面裸露。
在一些实施例中，器件颗粒中的晶体管还包括：第一钝化层、栅极、源极、漏极和第二钝化层。
在晶圆上制备多个晶体管或多个晶体管的部分层，包括：在晶圆上外延生长半导体层；在半导体层的背离晶圆的表面上形成第一钝化层；在第一钝化层上形成多个开口，并在该多个开口内分别形成栅极、源极和漏极；在第一钝化层、栅极、源极和漏极的背离半导体层的表面上形成第二钝化层。
对应的，将器件颗粒的正面键合在支撑基板上，包括：将第二钝化层的背离栅极的表面键合在支撑基板上。
对应的，在辅助承载部的背离第一衬底的一侧形成多个金属图案，并使得金属图案与晶体管对应耦接，还包括：在第二钝化层中形成多个开口；在辅助承载部的背离第一衬底的一侧形成多个金属图案，使得该多个金属图案通过第二钝化层中的开口与栅极、漏极对应耦接。
由上，在将辅助承载部和晶体管同步转移至第一衬底上的过程中，利用第二钝化层隔离保护晶体管的栅极、源极和漏极，可以避免晶体管的栅极、源极和漏极因晶体管的转移而受损。
在一些实施例中，在辅助承载部的背离第一衬底的一侧形成多个金属图案，还包括：在辅助承载部和晶体管的背离第一衬底的表面上形成散热绝缘层；在散热绝缘层的背离辅助承载部的表面上形成该多个金属图案。散热绝缘层的功能如前所述。
在一些实施例中，将至少一个器件颗粒的正面键合在支撑基板上，还包括：在支撑基板上形成临时键合层；将至少一个器件颗粒的正面键合在临时键合层上。
对应的，去除支撑基板，还包括：采用激光处理、热处理、化学处理、刻蚀、研磨或抛光中的至少一种工艺，去除临时键合层和支撑基板。
本公开实施例中，利用临时键合层实现器件颗粒与支撑基板之间的键合，有利于降低支撑基板的去除难度，以简化半导体器件的制备工艺。
可选的，在支撑基板上形成临时键合层，包括：采用玻璃、二氧化硅或氮化硅中的至少一种材料，通过旋涂或气相沉积工艺在支撑基板上形成临时键合层。如此，可以确保临时键合层不会因后续工艺中的高温环境而受到影响，该高温环境的温度例如≥200℃。
在一些实施例中，第一衬底采用气相沉积工艺制备在辅助承载部和晶体管的抛光表面上，例如采用化学气相沉积工艺或物理气相沉积工艺形成。
基于此，可选的，在晶圆上制备多个晶体管或多个晶体管的部分层，包括：在晶圆上外延生长半导体层；在半导体层的背离晶圆的表面上形成第一钝化层。
对应的，将器件颗粒的正面键合在支撑基板上，包括：将第一钝化层的背离半导体层的表面键合在支撑基板上。
对应的，在辅助承载部的背离第一衬底的一侧形成多个金属图案，并使得金属图案与晶体管对应耦接，还包括：在第一钝化层上形成多个开口，并在该多个开口内分别形成栅极、源极和漏极；在辅助承载部的背离第一衬底的一侧形成多个金属图案，并使得该多个金属图案中的至少一个金属图案与栅极耦接，至少一个金属图案与漏极耦接，且与栅极耦接的金属图案和与漏极耦接的金属图案绝缘。
在一些实施例中，在辅助承载部和晶体管的抛光表面上制备第一衬底，还包括：在辅助承载部和晶体管的抛光表面上形成气体阻挡层，该气体阻挡层例如为硅层、氮化硅层、氮化铝层或碳化硅层中的至少一层；在气体阻挡层的背离辅助承载部的表面上形成第一衬底。本公开实施例在沉积第一衬底之前，预先制备气体阻挡层，可以利用气体阻挡层防止第一衬底沉积工艺中所使用的气体对晶体管的半导体层造成损伤或破坏。
在另一些实施例中，辅助承载部和晶体管的抛光表面被同步键合在第一衬底上。
可选的，将辅助承载部和晶体管的抛光表面键合在第一衬底上，还包括：在第一衬底上形成键合层，将辅助承载部和晶体管的抛光表面键合在键合层上；或，在辅助承载部和晶体管的抛光表面上形成键合层，将第一衬底键合在键合层上。键合层的结构和功能如前所述。
根据前述一些实施例中半导体器件的不同结构，半导体器件的制备方法也有多种实施方式。
在一种可能的实施方式中，半导体器件的制备方法还包括：在第一衬底的背离晶体管的表面上形成金属层。
在另一种可能的实施方式中，半导体器件的制备方法还包括：形成至少贯穿第一衬底和半导体层的第一导通孔，并使得第一导通孔在第一衬底上的正投影位于对应晶体管中源极在第一衬底上的正投影内；在第一衬底的背离晶体管的表面形成金属层，使得金属层通过第一导通孔与源极耦接。
在半导体器件还包括键合层或气体阻挡层的情况下，第一导通孔还对应贯穿键合层或气体阻挡层。
示例的，在晶体管包括过渡层和第二衬底的情况下，半导体器件还包括位于第一 衬底和第二衬底之间的导电键合层。第一导通孔由分段设置的第一子导通孔和第二子导通孔构成。对应的，形成至少贯穿第一衬底和半导体层的第一导通孔，包括：形成贯穿第二衬底、过渡层和半导体层的第一子导通孔，使得第一子导通孔的一端与对应的源极直接接触；在辅助承载部和晶体管的抛光表面上形成导电键合层，使得导电键合层与第一子导通孔的另一端直接接触；将第一衬底键合在导电键合层上；形成贯穿第一衬底的第二子导通孔，使得第二子导通孔的一端与导电键合层直接接触；在第一衬底上形成金属层，使得金属层与第二子导通孔的另一端直接接触。
在又一种可能的实施方式中，半导体器件的制备方法还包括：形成至少贯穿第一衬底和辅助承载部的第二导通孔，并使得第二导通孔在第一衬底上的正投影位于对应的金属图案在第一衬底上的正投影内；在第一衬底的背离半导体层的表面形成金属层，使得金属层通过第二导通孔与金属图案耦接。
在半导体器件还包括键合层或气体阻挡层的情况下，第二导通孔还对应贯穿键合层或气体阻挡层。
示例的，半导体器件还包括位于第一衬底和辅助承载部之间的导电键合层。第二导通孔由分段设置的第三子导通孔和第四子导通孔构成。对应的，形成至少贯穿第一衬底和辅助承载部的第二导通孔，包括：形成贯穿辅助承载部的第三子导通孔；在辅助承载部和晶体管的抛光表面上形成导电键合层，使得导电键合层与第三子导通孔的一端直接接触；将第一衬底键合在导电键合层上；形成贯穿第一衬底的第四子导通孔，使得第四子导通孔的一端与导电键合层直接接触；在第一衬底上形成金属层，使得金属层与第四子导通孔的另一端直接接触。如此，在后续形成金属图案之后，使得金属图案与第三子导通孔的另一端直接接触，便可以通过第三子导通孔实现金属图案与导电键合层之间的耦接。
在上述一些实施例的基础上，可选的，半导体器件的制备方法还包括：提供散热基板，将金属层焊接于散热基板上。散热基板的功能如前所述。
可选的，半导体器件的制备方法还包括：在金属图案上形成至少一个键合盘，使得键合盘在第一衬底上的正投影位于第一衬底的未被晶体管覆盖的区域内。键合盘的功能如前所述。
本公开实施例中半导体器件的制备方法具有与前述实施例提供的半导体器件相同的技术效果，此处不再赘述。
附图说明
为了更清楚地说明本公开一些实施例中的技术方案，下面将对一些实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据一些实施例中的一种半导体器件的结构示意图；
图2为图1所示的一种半导体器件的沿A-A’向的剖面示意图；
图3为根据一些实施例中一种半导体器件的制备方法的S100的示意图；
图4为根据一些实施例中一种晶体管的结构示意图；
图5为根据一些实施例中一种半导体器件的制备方法的S200的示意图；
图6为根据一些实施例中一种半导体器件的制备方法的S300的示意图；
图7为根据一些实施例中一种半导体器件的制备方法的一种S400的示意图；
图8为根据一些实施例中一种半导体器件的制备方法的另一种S400的示意图；
图9为根据一些实施例中一种半导体器件的制备方法的S500的示意图；
图10为根据一些实施例中一种非导电键合层的制备示意图；
图11为根据一些实施例中另一种非导电键合层的制备示意图；
图12为根据一些实施例中一种半导体器件的制备方法的S600的示意图；
图13为根据一些实施例中一种半导体器件的制备方法的S700的示意图；
图14为根据一些实施例中一种半导体器件的制备方法的补充示意图；
图15为根据一些实施例中另一种半导体器件的制备方法的S100'的示意图；
图16为根据一些实施例中另一种半导体器件的制备方法的S200'的示意图；
图17为根据一些实施例中另一种半导体器件的制备方法的S300'～S500'的示意图；
图18为根据一些实施例中一种气体阻挡层的制备示意图；
图19为根据一些实施例中一种第一衬底的制备示意图；
图20为根据一些实施例中另一种半导体器件的制备方法的S600'～S700'的示意图；
图21为图1所示的另一种半导体器件的沿A-A’向的剖面示意图；
图22为图1所示的又一种半导体器件的沿A-A’向的剖面示意图；
图23为图1所示的又一种半导体器件的沿A-A’向的剖面示意图；
图24为根据一些实施例中的另一种半导体器件的结构示意图；
图25为图24所示的一种半导体器件的沿B-B’向的剖面示意图；
图26为图1所示的又一种半导体器件的沿A-A’向的剖面示意图；
图27为图26所示的半导体器件中一种晶体管的制备示意图；
图28为图26所示的半导体器件的制备过程中一种器件颗粒的键合示意图；
图29为根据一些实施例中的一种辅助承载部和晶体管之间位置关系的示意图；
图30为根据一些实施例中的另一种辅助承载部和晶体管之间位置关系的示意图；
图31为根据一些实施例中的又一种辅助承载部和晶体管之间位置关系的示意图；
图32为根据一些实施例中的又一种半导体器件的结构示意图；
图33为根据一些实施例中的又一种半导体器件的结构示意图；
图34为根据一些实施例中的又一种半导体器件的结构示意图；
图35为根据一些实施例中的又一种半导体器件的结构示意图；
图36为根据一些实施例中的又一种半导体器件的结构示意图；
图37为根据一些实施例中的又一种半导体器件的结构示意图；
图38为根据一些实施例中的又一种半导体器件的结构示意图；
图39为根据一些实施例中的又一种半导体器件的结构示意图；
图40为根据一些实施例中的又一种半导体器件的结构示意图；
图41为根据一些实施例中的又一种半导体器件的结构示意图；
图42为图41所示的一种半导体器件的沿C-C’向的剖面示意图；
图43为图41所示的一种半导体器件的沿E-F-G向的剖面示意图；
图44为根据一些实施例中的一种电子设备的剖面示意图；
图45为根据一些实施例中的另一种电子设备的剖面示意图。
附图标记：
100-半导体器件；           11-第一衬底；           111-气体阻挡层；
12-晶圆；                  121-基底；              122-氮化镓层；
201和201'-器件颗粒；       20-晶体管；             21-第二衬底；
22-过渡层；                23-半导体层；           231-沟道层；
232-势垒层；               24-第一钝化层；         25-栅极；
26-源极；                  27-漏极；               28-第二钝化层；
30-辅助承载部；            31-辅助承载膜；         32-绝缘层；
40-键合层；                50-散热绝缘层；         60-金属图案；
61-第一金属图案；          62-第二金属图案；       63-第三金属图案；
70-键合盘；                71-第一键合盘；         72-第二键合盘；
73-第三键合盘；            80-金属层；             81-焊接层；
82-散热基板；              90-支撑基板；           91-临时键合层；
1000-电子设备；            1001-金属引线；         1002-外接引脚；
1003-绝缘部；              1004-封装盖板；
H1-第一导通孔；            H11-第一子导通孔；      H12-第二子导通孔；
H2-第二导通孔；            H21-第三子导通孔；      H22-第四子导通孔；
C1-第一电容；              C2-第二电容；
L1-第一电感；              L2-第二电感；           R1-电阻。
具体实施方式
下面将结合本公开一些实施例中的附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的一些实施例，本领域普通技术人员所能获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
术语“第一”、“第二”等序数仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等 的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
此外，为了清楚地表示附图中的多个层和区域，放大了图示中各层的厚度，以对各层之间的相对位置进行清楚示意。当表述为层、膜、区域、板等的部分位于其他部分“上方”或“上”时，该表述不仅包括“直接”在其他部分上方的情况，还包括其中间存在有其他层的情况。
半导体器件(Semiconductor Device)是指依赖于半导体材料的电学特性来实现特定功能的电子器件。常见的半导体器件例如为晶体管器件，也即包含至少一个晶体管在内的电子器件。晶体管的结构和种类繁多，本公开实施例仅以晶体管是场效应晶体管或具有类似结构的晶体管为例进行描述。
如图1和图2所示，本公开一些实施例提供了一种半导体器件100。该半导体器件100包括第一衬底11以及被同步转移至第一衬底11上的至少一个晶体管20和辅助承载部30。
第一衬底11被配置为承载晶体管20和辅助承载部30，第一衬底11可以采用具有较高热导率和较高电阻值的衬底，以确保半导体器件100的散热能力和电学性能优良。可选的，第一衬底11为单晶碳化硅衬底、多晶碳化硅衬底、多晶氮化铝衬底、多晶金刚石衬底、石墨衬底、多层石墨烯衬底、铜衬底、或多种材料层叠的复合衬底等。其中，单晶碳化硅衬底包括：高纯半绝缘单晶碳化硅衬底、或掺钒碳化硅衬底。与高纯半绝缘单晶碳化硅衬底相比，掺钒碳化硅衬底是通过掺杂钒元素来增加碳化硅的绝缘性的，其成本低于高纯半绝缘单晶碳化硅衬底。
辅助承载部30和前述至少一个晶体管20被设置于第一衬底11上。辅助承载部30在第一衬底11上的正投影位于该至少一个晶体管20在第一衬底11上的正投影外， 且辅助承载部30在第一衬底11上的正投影边界与该至少一个晶体管20在第一衬底11上的正投影边界部分重合。也即，辅助承载部30形成于该至少一个晶体管20的旁侧。这样将该至少一个晶体管20作为一个整体，在将该至少一个晶体管20转移至第一衬底11的生产过程中，利于辅助承载部30能够对该至少一个晶体管20进行支撑保护。辅助承载部30的材料和结构可以根据实际需求选择设置，本公开实施例对此不作限定。
在本公开实施例中，以晶体管20是高电子迁移率晶体管(High Electron Mobility Transistor，简称HEMT)为例进行说明，但并不限于此。HEMT为异质结场效应晶体管，也可称为是二维电子气场效应管或调制掺杂场效应管。
请继续参阅图1和图2，晶体管20包括：半导体层23，以及分别形成于半导体层23的背离第一衬底11的一侧的栅极25、源极26和漏极27。半导体器件100还包括多个金属图案60。该多个金属图案60形成于辅助承载部30的背离第一衬底11的一侧，该多个金属图案60中的至少一个金属图案与对应晶体管20中的栅极25耦接，至少一个金属图案与对应晶体管20中的漏极27耦接，且与栅极25耦接的金属图案、和与漏极27耦接的金属图案绝缘。
可选的，晶体管20中的源极26与上述多个金属图案60中的至少一个金属图案耦接，或者与其他的金属层耦接。并且，与源极26耦接的金属图案或金属层，和与栅极25耦接的金属图案、与漏极27耦接的金属图案均绝缘。
此处，金属图案60用于向晶体管20中与其耦接的电极(包括栅极25、源极26或漏极27)传输电信号，其图案可以根据实际需求设计，以利于实现半导体器件100与外部器件的电性耦接、或实现半导体器件100的特定功能为限。例如，金属图案60为金属电极、金属线、键合盘或焊盘中的一种或多种的组合。
此外，晶体管20中源极26和漏极27的结构相同，二者仅是用于耦接不同的电源或信号源。因此，按照晶体管20类型的不同，源极26和漏极27二者与外部元件之间的耦接可以根据实际情况互换设置。
在本公开实施例中，半导体器件100的结构如上所述，晶体管20和辅助承载部30同步转移至第一衬底11上的实现方式可以有多种。例如，将晶体管20和辅助承载部30同步键合至第一衬底11上。或者，还例如，在晶体管20和辅助承载部30的表面制备第一衬底11，从而实现晶体管20和辅助承载部30的同步转移。
在一些实施例中，晶体管20和辅助承载部30被同步键合至第一衬底11上。此处，“键合”是指通过原子间作用力将两种不同的物质结合为一体。相应的，该半导体器件100的制备方法包括：S100～S700。
S100，如图3所示，提供晶圆12，在晶圆12上制备多个晶体管20。然后，沿晶圆12的厚度方向切割晶圆12，获得多个器件颗粒201。每个器件颗粒201包括一个或多个晶体管20。晶体管20包括：第二衬底21、外延生长在第二衬底21上的半导体层23、以及分别形成于半导体层23上的栅极25、漏极27和源极26。
此处，晶体管20中的第二衬底21为晶圆12的存在于器件颗粒201内的部分。半导体层23外延生长在晶圆12上，晶圆12与半导体层23之间通常生长有过渡层22，也即缓冲层。过渡层22能够用于提升晶圆12表面部分的晶格质量，以确保半导体层 23的成膜质量。晶体管20的半导体层23包括沿远离第二衬底21的方向层叠设置的沟道层231和势垒层232，势垒层232与沟道层231之间形成异质结。
可以理解的是，在半导体器件100的实际生产过程中，晶圆12能够以半导体晶圆的方式提供，也即，晶圆12的表面已生长好过渡层和半导体膜。以氮化镓晶圆12为例，如图4所示，氮化镓晶圆12包括基底121和外延生长在基底121上的氮化镓层122。基底121例如为蓝宝石(Al2O3)衬底、硅(Si)衬底或碳化硅(SiC)衬底。氮化镓层122的表面部分可以作为晶体管20中的沟道层231使用。在本公开实施例中，氮化镓层122由沟道层231和过渡层22组成，也就是说，氮化镓层122中除了沟道层231之外的部分，也即其位于沟道层231的靠近基底121一侧的部分即为过渡层22，也即缓冲层。在氮化镓晶圆12的表面继续生长半导体膜，可以形成势垒层232，势垒层232例如为氮化镓铝(AlGaN)层或氮化铝(AlN)层。
如图3和图4中所示，晶体管20还包括形成于半导体层23的背离第二衬底21的表面上的第一钝化层24。第一钝化层24包括多个开口，栅极25、源极26和漏极27分别形成于对应的开口内，并与势垒层232直接接触。晶体管20的栅极25与势垒层232形成肖特基势垒。此外，栅极25与势垒层232之间设置有栅绝缘层，也是允许的。第一钝化层24和栅绝缘层为绝缘材料制成，例如可以采用氮化硅、氧化硅或氮氧化硅等无机绝缘材料制备获得。
根据半导体材料的物理特性，形成异质结的势垒层232与沟道层231的禁带宽度不同，电子会从宽禁带的半导体(即势垒层232)流向窄禁带的半导体(即沟道层231)，从而在异质结接触面的窄禁带半导体一侧形成量子阱。当宽禁带半导体的掺杂浓度较高，且异质结间的导带差较大时，栅极25与势垒层232之间会形成很高的势垒，从而限制量子阱中的自由电子在垂直于异质结接触面方向上移动。该量子阱即为二维电子气(2 Dimensional Electron Gas，简称2DEG)。2DEG位于沟道层231的与势垒层232接触的表面。通过调节栅极25与势垒层232之间肖特基势垒的大小，可以控制沟道层231中2DEG的浓度，从而控制沟道层231内电流的大小。
S200，如图5所示，提供支撑基板90，将至少一个器件颗粒201的正面S1键合在支撑基板90上。以下一些实施例中以支撑基板90上键合两个器件颗粒201为例进行示意。
此处，支撑基板90具备一定的机械强度，支撑基板90例如为硅基板或玻璃基板。器件颗粒201的正面S1是指晶体管20的背离第二衬底21的表面，例如晶体管20的位于栅极25或漏极27所在侧的表面。器件颗粒201的背面S2是指其正面S1相对的表面，也是晶体管20中第二衬底21的背离半导体层23的表面。
可选的，栅极25、源极26和漏极27的背离半导体层23的表面与第一钝化层24的背离半导体层23的表面平齐或大致平齐。如此可以使得器件颗粒201与支撑基板90之间具有较大的接触面积，从而方便于将器件颗粒201的正面键合在支撑基板90上，并使得二者之间具有较好的键合效果。
上述器件颗粒201与支撑基板90之间的键合可以采用直接键合的方式或通过键合层键合的方式实现。
在一些实施例中，如图5所示，将至少一个器件颗粒201的正面键合在支撑基板 90上，包括：在支撑基板90上形成临时键合层91；将至少一个器件颗粒201的正面键合在临时键合层91上。
此处，临时键合层91是指在键合之后还可以解除键合的键合层，也即，临时键合层91可以在后续不需要的情况下去除掉。
可选的，临时键合层91采用玻璃、二氧化硅或氮化硅中的至少一种材料，通过旋涂或气相沉积工艺制作在支撑基板90上。这样临时键合层91可以在不需要其存在的情况下，采用激光处理、热处理、化学处理、刻蚀、研磨或抛光等工艺中的至少一种去除掉。并且，临时键合层91采用如上材料形成，还可以确保临时键合层91不会因后续工艺中的高温环境而受到影响。高温环境的温度例如≥200℃。
S300，如图6所示，在支撑基板90的未被器件颗粒201覆盖的表面上、以及器件颗粒201的背面S2上形成辅助承载膜31。
在支撑基板90上形成有临时键合层91的情况下，辅助承载膜31形成于临时键合层91的未被器件颗粒201覆盖的表面上。
辅助承载膜31用于对晶体管20进行支撑保护，可以采用具有一定机械强度的绝缘材料形成，例如氧化硅、氮化硅、氮氧化硅、硅、碳化硅、氮化铝、氧化铝、环氧树脂、聚酰亚胺、或苯并环丁烯等。辅助承载膜31可以通过气相沉积工艺形成，例如物理气相沉积工艺或化学气相沉积工艺。辅助承载膜31的沉积厚度可以根据实际需求选择设置。
示例的，在采用化学气相沉积工艺形成辅助承载膜31的情况下，辅助承载膜31的沉积厚度D2大于晶体管20的最小厚度D1，该晶体管20的最小厚度D1是指晶体管20中不包含第二衬底21和过渡层22时的厚度。
S400，如图7所示，抛光辅助承载膜31以及器件颗粒201，获得至少一个晶体管20以及位于该至少一个晶体管20旁侧的辅助承载部30。辅助承载部30的抛光表面与晶体管20的抛光表面位于同一平面。
此处，抛光辅助承载膜31是指采用抛光工艺将辅助承载膜31减薄并做表面平整处理。由于辅助承载膜31形成于支撑基板90的未被器件颗粒201覆盖的表面、以及器件颗粒201的背面S2上，因此，在抛光辅助承载膜31的过程中，为了使得器件颗粒201中的晶体管20裸露，辅助承载膜31的位于器件颗粒201的背面S2上的部分会被去除掉。这样在抛光辅助承载膜31和器件颗粒201的过程中，辅助承载膜31能够对器件颗粒201进行支撑保护，从而降低了抛光工艺的实施难度，有利于提高生产效率。并且，抛光后获得的辅助承载部30位于晶体管20的旁侧，还可以在后续工艺中持续地对晶体管20进行辅助性的支撑保护。
此外，辅助承载膜31的减薄也可以通过刻蚀或研磨等方式实现，以确保形成的辅助承载部30和晶体管20的裸露表面具有较好的表面平整度为限。
可以理解的是，晶体管20可以仅包括半导体层23以及位于半导体层23上的第一钝化层24、栅极25、源极26和漏极27。也即，晶体管20的抛光表面为半导体层23的背离栅极25的表面，辅助承载部30的抛光表面与晶体管20中半导体层23的背离栅极25的表面平齐或大致平齐，例如图7中所示。
或者，晶体管20还包括第二衬底21和过渡层22在内。也即，晶体管20的抛光 表面为第二衬底21的抛光表面。辅助承载部30的抛光表面与晶体管20中第二衬底21的抛光表面平齐或大致平齐，例如图8中所示。此处，相比于器件颗粒201的背面S2，第二衬底21的抛光表面为其去除部分基底材料后的表面。第二衬底21因抛光去除部分的厚度，可以根据实际需求设置。
需要补充的是，请结合图4、图7和图8理解，以晶圆12为氮化镓晶圆为例，氮化镓层122外延生长在基底111上。氮化镓层122的表面部分的晶格质量较好，能够用于形成晶体管20中的沟道层231。氮化镓层122靠近基底121的部分(即过渡层22)的晶格质量较差，容易使得过渡层22的热导率较差。基于此，在抛光辅助承载膜31的过程中，晶体管12中的过渡层22和第二衬底21被抛光去除，还可以有效提升半导体器件100的散热能力。
S500，如图9所示，提供第一衬底11，将辅助承载部30和晶体管20的抛光表面同步键合在第一衬底11上。
以下一些实施例中以晶体管20仅包括半导体层23以及位于半导体层23上的第一钝化层24、栅极25、源极26和漏极27为例进行示意。
第一衬底11的结构可参见前述一些实施例中所述。此外，辅助承载部30和晶体管20是在制备完成之后再转移至第一衬底11上的。基于此，在用于制备晶体管20的晶圆12的成本高昂的情况下，第一衬底11可以采用成本相对较低的材料或晶圆构成。另外，辅助承载部30的抛光表面与晶体管20的抛光表面平齐或大致平齐，可以确保辅助承载部30和晶体管20的待键合表面具有较高的表面质量，从而保障二者与第一衬底11之间能够具有较好的键合效果。
辅助承载部30和晶体管20与第一衬底11之间的键合方式，可以采用直接键合的方式或通过键合层间接键合的方式实现。
示例的，辅助承载部30和晶体管20直接键合在第一衬底11上。这样在直接键合之前，辅助承载部30和晶体管20的待键合表面、以及第一衬底11的待键合表面可以采用等离子体或离子束或原子束等进行表面处理，以使得辅助承载部30和晶体管20二者与第一衬底11的直接键合界面存在因等离子体或离子束或原子束处理而形成的非晶界面层。例如，第一衬底11为多晶碳化硅衬底，晶体管20的裸露表面为氮化镓表面，这样在对二者进行等离子体处理之后，晶体管20与第一衬底11之间的直接键合界面便会存在非晶GaN和/或非晶SiC界面层。
示例的，辅助承载部30和晶体管20间接键合在第一衬底11上。
可选的，如图10所示，将辅助承载部30和晶体管20键合在第一衬底11上，还包括：在第一衬底11上形成键合层40，将辅助承载部30和晶体管20键合在键合层40上。此处，晶体管20的半导体层23与键合层40直接接触，键合层40采用非导电键合层。非导电键合层40可以整层覆盖在第一衬底11上，也可以仅形成于第一衬底11的待键合区域内，该待键合区域可以为第一衬底11用于与晶体管20键合的区域，也可以为第一衬底11用于与晶体管20以及辅助承载部30键合的区域。
可选的，如图11所示，将辅助承载部30和晶体管20键合在第一衬底11上，还包括：在辅助承载部30和晶体管20上形成键合层40，将第一衬底11键合在键合层40上。此处，晶体管20的半导体层23与键合层40直接接触，键合层40采用非导电 键合层。
上述键合层40还可以有其他的设置方式。例如，键合层40包括第一非导电键合层和第二非导电键合层。这样在辅助承载部30和晶体管20上形成第一非导电键合层，在第一衬底11上形成第二非导电键合层，然后将第一非导电键合层和第二非导电键合层键合，也是允许的。以第一衬底11为多晶金刚石衬底、晶体管20的裸露表面为氮化镓(GaN)表面为例，可以在多晶金刚石衬底上形成氮化硅键合层(SiN)，在GaN表面上形成SiN，从而实现GaN/SiN-SiN/金刚石的键合。
上述非导电键合层40可以采用非导电型的硅(Si)、碳化硅(SiC)、氮化硅(SiN)、二氧化硅(SiO2)、氮化铝(AlN)或氧化铝(Al2O3)等材料制备获得。如此，利用非导电键合层40不仅可以增强辅助承载部30和晶体管20各自与第一衬底11之间的键合强度，还可以确保晶体管20不会因其存在而出现漏电流等情况，有利于确保半导体器件100的电学性能。
此外，在晶体管20还包括第二衬底21和过渡层22的情况下，晶体管20的第二衬底21与键合层40直接接触，键合层40可以为导电键合层。导电键合层40可以采用金属材料制备获得，例如Ti、Cr、Ni、Cu、Au等。第二衬底21和过渡层22为非导电材料，因此键合层40采用导电键合层，并不会因其存在而影响半导体器件100的电学性能。
S600，如图12所示，去除支撑基板90。
在支撑基板90上形成有临时键合层91的情况下，上述去除支撑基板90也包括去除临时键合层91。此外，支撑基板90和临时键合层91的去除可以通过刻蚀、研磨或抛光等工艺实现，但并不限于此。例如，根据支撑基板90和临时键合层91的形成材料，其去除还可以采用激光或化学或热滑移剥离的方式去除。在可以完整获得支撑基板90的情况下，支撑基板90还可以重复性使用。
此外，在去除支撑基板90的过程中，辅助承载部30可以从晶体管20的旁侧对其进行支撑保护，从而降低支撑基板90的去除难度，以进一步提高生产效率。
S700，如图13所示，在辅助承载部30的背离第一衬底11的一侧形成多个金属图案60，并使得该多个金属图案60中的至少一个金属图案与栅极25耦接，至少一个金属图案与漏极27耦接，且与栅极25耦接的金属图案、和与漏极27耦接的金属图案绝缘。
可选的，上述多个金属图案60还包括与源极26耦接的至少一个金属图案，且与源极26耦接的金属图案，和与栅极25耦接的金属图案、与漏极27耦接的金属图案均绝缘。
为方便描述，以下以与栅极25耦接的金属图案为第一金属图案61、与源极26耦接的金属图案为第二金属图案62、与漏极27耦接的金属图案为第三金属图案63为例进行说明。
此处，第一金属图案61、第二金属图案62和第三金属图案63均为采用金属材料制备形成的图案，其图案相同或不同，均可。第一金属图案61、第二金属图案62和第三金属图案63的制备材料可以为导电性良好的金属材料，例如铜、铝、金、铂、钨、镍、铱或钴等金属中的至少一种。
第一金属图案61、第二金属图案62和第三金属图案63的图案可以根据实际需求设计。例如，第一金属图案61、第二金属图案62或第三金属图案63为单层图案，该单层图案可以设计为金属电极、金属线、键合盘或焊盘中的一种或多种的组合。或者，还例如，第一金属图案61、第二金属图案62或第三金属图案63为设置在多层绝缘膜上的多层图案，该多层图案可以设计为电容、电感或多层金属线中至少两种的组合。
此外，金属图案60形成于辅助承载部30上。辅助承载部30位于晶体管20的旁侧。辅助承载部30采用绝缘材料形成，可以有效绝缘金属图案60和晶体管20中的半导体层23，从而确保晶体管20的电学性能。
需要补充的是，在一个器件颗粒201用于制备一个半导体器件100的情况下，参照前述一些实施例中的制备方法，只转移一个器件颗粒201至支撑基板90上，便可制备获得单个的半导体器件100。或者，参照前述一些实施例中的制备方法，转移多个器件颗粒201至支撑基板90上，然后在制备完成金属图案60之后，如图14中所示，通过切割的方式获得单个的半导体器件100。
在另一些实施例中，晶体管20和辅助承载部30的转移，通过在晶体管20和辅助承载部30的表面制备第一衬底11实现。相应的，半导体器件100的制备方法包括S100'～S700'。
S100'，如图15所示，提供晶圆12，在晶圆12上制备多个晶体管20的部分层，例如制备晶体管20的半导体层23和第一钝化层24。然后，沿晶圆12的厚度方向切割晶圆12，获得多个器件颗粒201'。这样一个器件颗粒201'包括至少一个晶体管20的第二衬底21、过渡层22、半导体层23和第一钝化层24。此处，第二衬底21和过渡层22的结构同前所述。
与前述一些实施例中S100的制备过程相比，本公开实施例中仅是缺少了晶体管20中栅极25、源极26和漏极27的制备，其余均可参见前述一些实施例中的相关内容进行，不再详述。相应的，第一钝化层24上用于容置栅极25、源极26和漏极27的开口可以在后续制备栅极25、源极26和漏极27时形成。
需要说明的是，晶体管20中栅极25、源极26和漏极27的制备顺序，可根据具体的工艺温度进行调整，以后续工艺的温度不对前序工艺形成的结构产生损伤或破坏为限。例如，源极26和漏极27具有较好的耐高温特性，那么S100'还包括：在第一钝化层24中形成多个开口，在该多个开口内对应形成晶体管20的源极26和漏极27。晶体管20的栅极25视情况在后续工艺中再制备。如此，方便于在晶圆12上以更低的成本批量制备更多的晶体管20，并避免后续第一衬底11的形成工艺等高温工艺对已制备的结构产生破坏。
S200'，如图16所示，提供支撑基板90，将至少一个器件颗粒201'的正面S1键合在支撑基板90上。此处，器件颗粒201'的正面表现为第一钝化层24的背离半导体层23的表面。
支撑基板90例如为玻璃基板或硅基板。器件颗粒201'可以直接键合在支撑基板90上，或通过临时键合层91与支撑基板90间接键合。此外，器件颗粒201'与支撑基板90之间的键合实现，可以参照前述实施例中S200的相关内容执行。
以下一些实施例中以支撑基板90上键合一个器件颗粒201'为例进行示意。
S300'，如图17中的(a)所示，在支撑基板90的未被器件颗粒201'覆盖的表面、以及器件颗粒201'的背面形成辅助承载膜31。
在支撑基板90上形成有临时键合层91的情况下，辅助承载膜31形成于临时键合层91的未被器件颗粒201'覆盖的表面、以及器件颗粒201'的背面上。
辅助承载膜30的材料及制备工艺，可参见前述实施例中S300中的相关记载。
S400'，如图17中的(b)所示，抛光辅助承载膜31以及器件颗粒201'，获得至少一个晶体管20以及位于该至少一个晶体管20的旁侧的辅助承载部30。辅助承载部30的抛光表面与晶体管20的抛光表面(即裸露表面)位于同一平面。
此处获得的晶体管20是指S100'中已制备好的晶体管20的结构，包括晶体管20的部分层。抛光器件颗粒201'，还包括：使得器件颗粒201'中晶体管20的半导体层23的靠近第二衬底21的表面裸露，或者使得器件颗粒201'中晶体管20的第二衬底21的抛光表面裸露(图17中未示出)。
辅助承载膜31的抛光工艺和辅助承载部30的结构，可参见前述实施例中的相关记载。
S500'，如图17中的(c)所示，在辅助承载部30以及晶体管20的抛光表面上制备第一衬底11。
第一衬底11可以采用气相沉积工艺制备形成，例如化学气相沉积工艺或物理气相沉积工艺。第一衬底11的制备材料例如为多晶碳化硅、多晶氮化铝或多晶金刚石。
可以理解的是，在抛光辅助承载膜31和器件颗粒201'之后，辅助承载部30的抛光表面和半导体层23或第二衬底21的抛光表面位于同一平面。如此在具有较高平面度的表面沉积第一衬底11，可以确保第一衬底11的成膜质量。
需要补充的是，在一些示例中，特别是在晶体管20的抛光表面为半导体层23表面的示例中，如图18所示，在辅助承载部30以及晶体管20的抛光表面上制备第一衬底11，还包括：在辅助承载部30以及晶体管20的抛光表面上形成气体阻挡层111，然后在气体阻挡层111的背离辅助承载部30的表面上形成第一衬底11。气体阻挡层111可以采用硅(Si)、氮化硅(SiN)、氮化铝(AlN)或碳化硅(SiC)等材料中的至少一种制备形成。例如，气体阻挡层111包括硅层、氮化硅层、氮化铝层或碳化硅层中的至少一层。
本公开实施例在沉积第一衬底11之前，预先制备气体阻挡层111，可以利用气体阻挡层111防止第一衬底11沉积工艺中所使用的气体(例如甲烷和氢气)对半导体层23造成损伤或破坏。
此外，示例的，如图19所示，在辅助承载部30以及晶体管20的抛光表面上形成气体阻挡层111之后，若第一衬底11为采用化学气相沉积工艺形成的多晶金刚石衬底，那么在金刚石生长过程的初期会先形成金刚石晶粒很小的纳米晶金刚石层112，然后随着金刚石生长厚度的增加，形成微米晶金刚石层113。纳米晶金刚石层112的厚度很薄，其远小于微米晶金刚石层113的厚度。由此，采用化学气相沉积工艺制备的多晶金刚石衬底，为纳米晶金刚石层112和微米晶金刚石层113的叠层。
S600'，如图20中的(a)所示，去除支撑基板90。
在支撑基板90上形成有临时键合层91的情况下，上述去除支撑基板90也包括去 除临时键合层91。此外，支撑基板90和临时键合层91的去除可以通过刻蚀、研磨或抛光等工艺实现，但并不限于此。例如，根据支撑基板90和临时键合层91的形成材料，其去除还可以采用激光剥离、热剥离或化学剥离的方式去除。在可以完整获得支撑基板90的情况下，支撑基板90还可以重复性使用。
此外，在去除支撑基板90的过程中，辅助承载部30可以从晶体管20的旁侧对其进行支撑保护，从而降低支撑基板90的去除难度，以进一步提高生产效率。
S700'，如图20中的(b)所示，在第一钝化层24中形成贯穿其两侧表面的多个开口，并在该多个开口内对应形成晶体管20的栅极25、源极26和漏极27。然后，在辅助承载部30的背离第一衬底11的一侧形成多个金属图案60。从而获得半导体器件100。
此处，多个金属图案60的结构及其设置方式，可参见前述一些实施例中的相关记载。
综上，在本公开实施例的半导体器件100中，晶体管20或晶体管20的部分层(例如半导体层23等)可以预先在晶圆12制备完成，然后借助于支撑基板90，与辅助承载部30同步转移至第一衬底11上。辅助承载部30形成于晶体管20的旁侧，能够在晶体管20的转移过程中，对晶体管20或晶体管20的部分层结构进行辅助性的支撑保护，从而有效提升半导体器件100生产过程中的工艺稳定性。
第一衬底11用于承载转移后的晶体管20和辅助承载部30，第一衬底11的平面面积通常大于晶体管20在第一衬底11上的正投影面积。也即，第一衬底11上存在未被晶体管20覆盖的区域；该区域可以用于容置辅助承载部30以及制备其他的电子元件或用于散热。这也就是说，晶体管20在晶圆12上的制备，可以不受半导体器件100中金属图案60等其他组成元件设置位置的影响。这样在晶圆12上批量制备晶体管20的过程中，晶圆12上的半导体膜(例如氮化镓-晶圆12上的氮化镓层122)无需预留无源区的部分或仅需预留很小的无源区部分即可。从而使得晶圆12上的半导体膜能够被有效利用并制备为晶体管20的沟道层231，以确保晶圆12具有较高的面积利用率，例如使得晶圆12的面积利用率达到80％及以上。此处，晶圆12的面积利用率是指其可利用面积与其总平面面积的比值，该可利用面积为能够用于形成晶体管20中沟道层231的面积。
基于此，晶体管20中的有源区AR在半导体层23上的面积占比可以较大，该面积占比是指有源区AR在第一衬底11上的正投影面积与半导体层23在第一衬底11上的正投影面积的比值。有源区AR是指：晶体管20工作时的有效区域；也即，晶体管20的半导体层23内用于形成导电沟道的区域。可选的，晶体管20中有源区AR在半导体层23上的面积占比的取值范围为80％～100％；例如为80％、90％或100％。
此外，第一衬底11采用成本低于氮化镓等宽禁带半导体晶圆的材料形成，还有利于降低半导体器件100的生产成本。第一衬底11采用热导率较高的材料形成，例如在温度为300K的条件下，第一衬底11的热导率大于200W/mK，还有利于提升半导体器件100的散热能力或减小半导体器件100的有源区面积。
为了更清楚地说明本公开一些实施例中半导体器件100的结构，图2、图21、图22和图23分别示出了四种不同半导体器件100的剖面结构，且该四种半导体器件100 可以采用前述制备方法中的对应步骤制备获得。其中，与图2所示的半导体器件100相比，图21所示的半导体器件100中的晶体管20包括过渡层22和第二衬底21，图22所示的半导体器件100还包括键合层40，图23所示的半导体器件100还包括气体阻挡层111。
需要补充的是，用于制备晶体管20的晶圆并不限于氮化镓晶圆12，也可以为砷化镓晶圆、氧化镓晶圆或具有类似性能的晶圆。
示例的，用于制备晶体管20的晶圆为砷化镓晶圆。这样在制备获得的晶体管20中，半导体层23的沟道层231为砷化镓层，势垒层232可以为砷化镓铝(AlGaAs)层。此处，晶体管20在砷化镓晶圆上的制备与前述晶体管20在氮化镓晶圆12上的制备相似，此处不再详述。
示例的，用于制备晶体管20的晶圆为氧化镓晶圆。这样在制备获得的晶体管20中，晶体管20中半导体层23的沟道层231为氧化镓层，势垒层232可以为氮化铝层或氧化镓铝层。此处，晶体管20在氧化镓晶圆上的制备与前述晶体管20在氮化镓晶圆12上的制备相似，此处不再详述。
此外，在晶体管20为HEMT的一些实施例中，晶体管20具有较高的电子迁移率，晶体管20的厚度可以设置的较小，例如小于10μm。示例的，如图2所示，晶体管20仅包括半导体层23、第一钝化层24以及分别设置于第一钝化层24的开口内的栅极25、源极26和漏极27，晶体管20的厚度D小于5μm，例如为3μm、2μm或1μm。从而有利于实现半导体器件100的轻薄化，以及降低半导体器件100的热阻。
需要说明的是，半导体器件100中，晶体管20的数量可以为一个或多个。
在一些实施例中，晶体管20的数量为多个。多个晶体管20可以在第一衬底11上呈阵列状分布，或者排列成一排。此外，金属图案60与晶体管20之间的耦接也可以有多种实施。例如，如图1所示，每个晶体管20的栅极25与至少一个第一金属图案61耦接；每个晶体管20的源极26与一个第二金属图案62耦接；每个晶体管20的漏极27与一个第三金属图案63耦接。或者，还例如，如图24所示，每个第一金属图案61与至少一个晶体管20的栅极25耦接；每个第二金属图案62与至少一个晶体管20的源极26耦接；每个第三金属图案63与至少一个晶体管20的漏极27耦接。本公开实施例对此不作限定。
示例的，如图24和图25所示，半导体器件100包括四个并排设置的晶体管，各晶体管分别用代号M1、M2、M3和M4表示。晶体管M1、M2、M3和M4中的部分电极共用，可以提高晶体管的分布密度。例如，晶体管M1和M2共用一个漏极27，晶体管M3和M2共用一个源极26，晶体管M4和M3共用一个漏极27。此外，各晶体管M1、M2、M3和M4中的栅极25互连，可以与同一个第一金属图案61耦接。晶体管M1和M4的源极26位于外侧，可以分别与一个第二金属图案62耦接。晶体管M2的源极26位于晶体管M2和M3的栅极25之间，可以与其他的导电部耦接，例如通过第一导通孔H1与位于第一衬底11背面的金属层80耦接。晶体管M1和M4的漏极27互连，可以与同一个第三金属图案63耦接。
为了方便描述，以下一些实施例以半导体器件100中仅包括一个晶体管20为例进行说明。在半导体器件100中晶体管20的数量为多个的情况下，半导体器件100的结 构可以根据如下相关记载作适应性变化。
示例的，如图1和图2所示，晶体管20的源极26、栅极25和漏极27呈长条状，且三者平行分布，栅极25位于源极26和漏极27之间。半导体器件100中的多个金属图案60包括两个第一金属图案61、一个第二金属图案62和一个第三金属图案63。其中，两个第一金属图案61分别位于栅极25的两侧，并与栅极25沿长度方向的两端耦接。第二金属图案62位于源极26的远离栅极25的一侧，并与源极26耦接。第三金属图案63位于漏极27的远离栅极25的一侧，并与漏极27耦接。
请继续参阅图2，第一金属图案61、第二金属图案62和第三金属图案63中的大部分形成于辅助承载部30的表面上，也即，第一金属图案61、第二金属图案62和第三金属图案63中的大部分在第一衬底11上的正投影位于第一衬底11的未被半导体层23覆盖的区域内。这样在批量制备半导体器件100的过程中，在晶圆12为氮化镓晶圆或类似具有高昂成本的宽禁带半导体晶圆的情况下，与金属图案60形成在半导体层的无源区内相比，半导体器件100采用如上结构可以具有较低的生产成本。
在一些实施例中，如图2所示，辅助承载部30的背离第一衬底11的表面、与晶体管20中栅极25或漏极27的背离第一衬底11的表面平齐或大致平齐。可选的，晶体管20中栅极25和漏极27二者背离第一衬底11的表面可以位于或大致位于同一平面。这样有利于在辅助承载部30上形成具有较好平面度的金属图案60，以确保金属图案60的成膜质量。
在晶体管20中栅极25和漏极27二者背离第一衬底11的表面非同一平面的情况下，辅助承载部30的背离第一衬底11的表面可以与二者中距离第一衬底11最远的表面平齐或大致平齐。
此外，在一些示例中，如图2所示，晶体管20仅包括半导体层23、第一钝化层24、栅极25、源极26和漏极27。辅助承载部30的靠近第一衬底11的表面、与半导体层23的靠近第一衬底11的表面在同一抛光工艺中成型，二者平齐或大致平齐。
在另一些示例中，如图21所示，晶体管20还包括：层叠位于半导体层23的背离栅极25的一侧的过渡层22和第二衬底21。辅助承载部30的靠近第一衬底11的表面、与第二衬底21的靠近第一衬底11的表面在同一抛光工艺中成型，二者平齐或大致平齐。
在一些实施例中，第一衬底11采用气相沉积工艺制备形成。如图20中所示，辅助承载部30的背离第一衬底11的表面、与第一钝化层24的背离第一衬底11的表面平齐或大致平齐。在此基础上，栅极25、源极26和漏极27分别形成于第一钝化层24的对应开口内。栅极25、源极26和漏极27凸出或不凸出第一钝化层24的背离半导体层24的表面，均可。
此外，在另一些实施例中，如图26所示，晶体管20还包括第二钝化层28。第二钝化层28形成于第一钝化层24的背离半导体层23的表面上，且位于栅极25、源极26和漏极27的背离半导体层23的一侧。辅助承载部30的背离第一衬底11的表面、与第二钝化层28的背离第一衬底11的表面平齐或大致平齐。金属图案60可以通过第二钝化层28中对应的开口与栅极25、源极26或漏极27耦接。
对应的，请结合前述一些实施例中半导体器件100的制备方法理解。
如图27所示，在晶圆12上制备多个晶体管20，包括：在晶圆12上外延生长半导体层23；在半导体层23的背离晶圆12的表面上形成第一钝化层24；在第一钝化层24上形成多个开口，并在该多个开口内分别形成栅极25、源极26和漏极27；在第一钝化层24、栅极25、源极26和漏极27的背离半导体层23的表面上形成第二钝化层28。
如图28所示，将器件颗粒201(201')的正面键合在支撑基板90上，包括：将第二钝化层28的背离栅极25的表面键合在支撑基板90上。
最后，在辅助承载部30的背离第一衬底11的一侧形成多个金属图案60，并使得该多个金属图案60与晶体管20对应耦接，还包括：在第二钝化层28中形成多个开口；在辅助承载部30的背离第一衬底11的一侧形成多个金属图案60，使得该多个金属图案通过第二钝化层28中的开口与栅极25、源极26、漏极27对应耦接。
本公开实施例中，在制备晶体管20的栅极25、源极26、漏极27以及第二钝化层28之后，再将晶体管20和辅助承载部30同步转移至第一衬底11上，可以利用第二钝化层28有效保护晶体管20的栅极25、源极26和漏极27，从而避免晶体管20的栅极25、源极26和漏极27因晶体管20的转移而受损。
在上述一些实施例中，辅助承载部30用于辅助支撑晶体管20，辅助承载部30位于晶体管20旁侧的设置方式可以有多种。例如，辅助承载部30设置于晶体管20的至少两侧。
可选的，如图29所示，辅助承载部30设置于晶体管20的相对的两侧，辅助承载部30包括独立设置的两个子部31和32。
可选的，如图30所示，辅助承载部30设置于晶体管20的相邻的两侧。
可选的，如图31所示，辅助承载部30环绕设置于晶体管20的周侧。
此外，为了确保辅助承载部30能够对晶体管20进行有效的支撑保护，以提升半导体器件100生产过程中的工艺稳定性，辅助承载部30和半导体器件100中晶体管20在第一衬底11上的正投影面积的比值可以控制在合理的范围内。
可选的，请参阅图29～图31，以半导体器件100中晶体管20在第一衬底11上的正投影面积为第一面积S1，辅助承载部30在第一衬底11上的正投影面积为第二面积S2，那么：
Figure PCTCN2020135857-appb-000002
例如，
Figure PCTCN2020135857-appb-000003
或1。
在一些实施例中，如图32所示，半导体器件100还包括形成于辅助承载部30和晶体管20的背离第一衬底11的表面上的散热绝缘层50。金属图案60形成于散热绝缘层50的背离辅助承载部30的表面上，金属图案60可以通过散热绝缘层50中的开口与晶体管20中的电极对应耦接。
相应的，半导体器件100的制备方法还包括：在辅助承载部30和晶体管20的背离第一衬底11的表面上形成散热绝缘层50，以使得前述多个金属图案60形成于散热绝缘层50的背离辅助承载部30的表面上。
此处，散热绝缘层50可以采用具有良好散热能力的绝缘材料制备形成。散热绝缘层50例如为金刚石层。金属图案60形成于散热绝缘层50的背离辅助承载部30的表面上，可以将晶体管20工作过程中产生的热量利用散热绝缘层50有效传导出去，从 而有效提升半导体器件100的散热能力。
可选的，在一些实施例中，如图33所示，辅助承载部30在第一衬底11上的正投影面积小于第一衬底11的平面面积。散热绝缘层50的部分表面还可以与第一衬底11直接接触。也即，散热绝缘层50可以同时覆盖在辅助承载部30以及第一衬底11的未被辅助承载部30覆盖的表面上，使得辅助承载部30在第一衬底11上的正投影位于散热绝缘层50在第一衬底11上的正投影内。如此，在第一衬底11具有较高热导率的情况下，散热绝缘层50与第一衬底11直接接触，还可以传导热量至第一衬底11，以进一步提升半导体器件100的散热能力。
在一些实施例中，如图34所示，半导体器件100还包括：形成于第一衬底11的背离晶体管11的表面上的金属层80。本公开实施例在第一衬底11的背离半导体层23的表面上形成金属层80，可以利用金属层80进一步提升第一衬底11的散热能力。金属层80可以采用散热能力较好的金属材料制作形成，该金属材料例如为铜、铝、铂、钨、镍、铱或钴等中的至少一种。
进一步的，如图35所示，半导体器件100还包括：设置于金属层80的背离第一衬底11的一侧的散热基板82。金属层80可以焊接于散热基板82上，例如采用金-锡焊、铜-锡焊接、纳米银烧结等工艺。也即，金属层80与散热基板82之间存在焊接层81，焊接层81的材料可以根据实际需求选择设置，以确保金属层80和散热基板82之间具有较好的焊接质量为准。金属层80焊接于散热基板82上，可以利用散热基板82进一步提升半导体器件100的散热能力。
可选的，散热基板82为铝基板、铜基板、金刚石/金属复合基板、陶瓷基板、硬式印刷电路板或软式印刷电路板等具有较高热导率的基板。
相应的，半导体器件100的结构如上所示，在获得半导体器件100之前，其制备方法还包括：在第一衬底11的背离晶体管20的表面形成金属层80；提供散热基板82，将金属层80焊接于散热基板82上。
需要补充的是，在一些实施例中，金属层80除了散热使用外，还可以作为公共电极使用，以向半导体器件100中的晶体管20或其他电子元件提供接地信号或浮空信号。
在一些示例中，按照晶体管20类型的不同，金属层80可以与晶体管20中的源极26或漏极27耦接。
可选的，如图36所示，半导体器件100还包括至少一个第一导通孔H1。第一导通孔H1至少贯穿第一衬底11和半导体层23，且第一导通孔H1在金属层80上的正投影位于对应晶体管20中的源极26在金属层80上的正投影内。金属层80可以通过第一导通孔H1与对应的源极26耦接。
此处，第一导通孔H1所需贯穿的层结构、与位于金属层80和源极26之间的层结构相一致。按照半导体器件100结构的不同，第一导通孔H1贯穿的层结构可以不同，此处不再详述。
相应的，在形成金属层80之前，半导体器件100的制备方法还包括：形成至少贯穿第一衬底11和半导体层23的第一导通孔H1，并使得第一导通孔H1在第一衬底11上的正投影位于对应晶体管20中源极26在第一衬底11上的正投影内。如此，在第一 衬底11的背离晶体管20的表面形成金属层80后，可以使得金属层80通过第一导通孔H1与对应的源极26耦接。
可选的，如图37所示，晶体管20包括过渡层22和第二衬底21。半导体器件100还包括位于第一衬底11和第二衬底21之间的键合层40。键合层40为导电键合层。第一导通孔H1包括分段设置的第一子导通孔H11和第二子导通孔H12。其中，第一子导通孔H11贯穿第二衬底21、过渡层22和半导体层23，第一子导通孔H1的两端分别与源极26和导电键合层40耦接。第二子导通孔H12贯穿第一衬底11，第二子导通孔H12的两端分别与导电键合层40和金属层80耦接。
对应的，在半导体器件100的制备方法中，形成至少贯穿第一衬底11和半导体层23的第一导通孔H1，包括：形成贯穿第二衬底21、过渡层22和半导体层23的第一子导通孔H11，使得第一子导通孔H11的一端与对应的源极26直接接触；在辅助承载部20和晶体管20的抛光表面上形成导电键合层40，使得导电键合层40与第一子导通孔H11的另一端直接接触；将第一衬底22键合在导电键合层40上；形成贯穿第一衬底11的第二子导通孔H12，使得第二子导通孔H12的一端与导电键合层40直接接触；在第一衬底11上形成金属层80，使得金属层80与第二子导通孔H12的另一端直接接触。从而实现第一导通孔H1的制备。
由上，第一导通孔H1由第一子导通孔H11和第二子导通孔H12构成，可以降低第一导通孔H1的制作难度，并确保第一导通孔H1的电连接性能，尤其是针对第一衬底11和晶体管20的厚度较大的情况。
在另一些示例中，金属层80可以与某一金属图案60对应耦接，例如与第二金属图案62耦接。如此，如图38所示，半导体器件100还包括至少一个第二导通孔H2。第二导通孔H2至少贯穿第一衬底11和辅助承载部30，且第二导通孔H2在金属层80上的正投影位于对应的金属图案60在第一衬底11上的正投影内。金属层80可以通过第二导通孔H2与对应的金属图案60耦接。
此处，第二导通孔H2所需贯穿的层结构、与位于金属层80和金属图案60之间的层结构相一致。按照半导体器件100结构的不同，第二导通孔H2贯穿的层结构可以不同，此处不再详述。
相应的，在形成金属层80之前，半导体器件100的制备方法还包括：形成至少贯穿第一衬底11和辅助承载部30的第二导通孔H2，并使得第二导通孔H2在金属层80上的正投影位于对应的金属图案60在第一衬底11上的正投影内。如此，在第一衬底11的背离晶体管20的表面形成金属层80后，可以使得金属层80通过第二导通孔H2与对应的金属图案60耦接。
可选的，如图39所示，晶体管20包括过渡层22和第二衬底21。半导体器件100还包括位于第一衬底11和第二衬底21之间的键合层40。键合层40为导电键合层。第二导通孔H2包括分段设置的第三子导通孔H21和第四子导通孔H22。第三子导通孔H21贯穿辅助承载部30，第三子导通孔H21的两端分别与金属图案60和导电键合层40耦接。第四子导通孔H22贯穿第一衬底11，第四子导通孔H22的两端分别与导电键合层40和金属层80耦接。
对应的，在半导体器件100的制备方法中，形成至少贯穿第一衬底11和辅助承载 部30的第二导通孔H2，包括：形成贯穿辅助承载部30的第三子导通孔H21；在辅助承载部30和晶体管20的抛光表面上形成导电键合层40，使得导电键合层40与第三子导通孔H21的一端直接接触；将第一衬底11键合在导电键合层40上；形成贯穿第一衬底11的第四子导通孔H22，使得第四子导通孔H22的一端与导电键合层40直接接触；在第一衬底11上形成金属层80，使得金属层80与第四子导通孔H22的另一端直接接触。如此，在后续形成金属图案60之后，使得金属图案60与第三子导通孔H21的另一端直接接触，便可以通过第三子导通孔H21实现金属图案60与导电键合层40之间的耦接。
由上，第二导通孔H2由第三子导通孔H21和第四子导通孔H22构成，可以降低第二导通孔H2的制作难度，并确保第二导通孔H2的电连接性能，尤其是针对第一衬底11和辅助承载部30的厚度较大的情况。
需要补充的是，上述的第一导通孔H1、第二导通孔H2、第一子导通孔H11、第二子导通孔H21、第三子导通孔H21、以及第四子导通孔H22均包括通孔以及填充于通孔内的金属导体。在第一导通孔H1或第二导通孔H2不分段设置的情况下，第一导通孔H1或第二导通孔H2中的金属导体可以与金属层80采用相同的金属材料制备，以简化半导体器件100的制备工艺。
在一些实施例中，金属图案60为平面电极或金属线。在此基础上，如图40所示，半导体器件100还包括：多个键合盘70。键合盘70形成于对应的金属图案60上，键合盘70在第一衬底11上的正投影位于第一衬底11的未被晶体管20覆盖的区域内。
相应的，在获得半导体器件100之前，半导体器件100的制备方法还包括：在金属图案60上形成至少一个键合盘70，使得键合盘70在第一衬底11上的正投影位于第一衬底11的未被晶体管20覆盖的区域内。
此处，键合盘70可以采用导电性良好且具备一定机械强度的金属材料制备形成，该金属材料例如金、铜、铝、铂、钨、镍、铱或钴等中的至少一种。键合盘70的材料与金属图案60的材料相同或不同，均可。
示例的，键合盘70的材料硬度大于金属图案60的材料硬度。键合盘70呈凸台状设置于对应金属图案60的表面上，方便于在键合盘70的表面键合外接的金属引线，以利用该金属引线与外接部件耦接，从而实现半导体器件100和外接部件之间电信号的传输。外接部件例如为封装壳体或转接基板等。
为了更清楚地说明本公开一些实施例中半导体器件100的结构，例如在金属图案60为多层图案时半导体器件100的结构，以下以图41所示的半导体器件100为例进行详述。在半导体器件100中，利用金属图案60的多层图案可以在第一衬底11的未被晶体管20以及辅助承载部30覆盖的区域内制备出无源匹配电路。当然，无源匹配电路制作于辅助承载部30的背离第一衬底11的表面上，也是允许的。本公开实施例对此不作限定，根据实际需求选择设置即可。无源匹配电路通常可以由电容、电感、电阻、金属线以及金属导通孔中的至少一种构成。
按照金属图案60与晶体管20中各电极的耦接关系，金属图案60包括：与栅极25耦接的第一金属图案61，与源极26耦接的第二金属图案62，以及与漏极27耦接的第三金属图案63。相应的，多个键合盘70包括：形成于第一金属图案61上的至少 一个第一键合盘71，形成于第二金属图案62上的至少一个第二键合盘72，以及形成于第三金属图案63上的至少一个第三键合盘73。
示例的，请参阅图41、图42和图43，第一金属图案61和第三金属图案63均包括两层图案，其第一层图案和第二层图案之间设置有绝缘层32。其中，第一层图案形成于第一衬底11上，第二层图案形成于第一层图案的背离第一衬底11的一侧，即绝缘层32的背离第一衬底11的表面上。可选的，绝缘层32也可以由前述一些实施例中的散热绝缘层50构成。
此外，第二金属图案62为单层图案，第二金属图案62形成于绝缘层32的背离第一衬底11的表面上。这样第二金属图案62可以与第一金属图案61、第三金属图案63中的第二层图案同步形成。
如图41和图42中所示，利用第一金属图案61至少可以形成：第一电容C1、第二电容C2和第一电感L1。此处，第一电容C1的第一极611和第二电容C2的第一极可以由第一金属图案61中的第一层图案形成，第一电容C1的第二极612和第二电容C2的第二极可以由第一金属图案61中的第二层图案形成。第一电感L1采用沟槽式电感，可以利用第一金属图案61中的第二层图案形成。此外，第一电容C1、第二电容C2、第一电感L1与晶体管20中的栅极25彼此间的互连，可以通过金属线或金属导通孔实现。第一键合盘71形成于第一金属图案61的第二层图案上。
如图41和图43中所示，利用第三金属图案63至少可以形成：第一电阻R1和第二电感L2。此处，第一电阻R1可以由第三金属图案63中的第一层图案形成。第二电感L2采用沟槽式电感，可以利用第三金属图案63中的第二层图案形成。此外，第一电阻R1、第二电感L2和晶体管20中漏极27彼此间的耦接，可以通过金属线或金属导通孔实现。第三键合盘73形成于第三金属图案63的第二层图案上。
需要补充的是，上述无源匹配电路还可以通过贯穿第一衬底11的导通孔，与设置于第一衬底11上的金属层80耦接，以利用金属层80传输接地信号或浮空信号。
本公开实施例还提供了一种电子设备。如图44所示，电子设备1000包括：如上任一实施例所述的至少一个半导体器件100。该电子设备例如为单片微波集成电路(Monolithic Microwave Integrated Circuit，简称MMIC)、基于MMIC的功率放大器、混频器、检波器、调制器、移相器或者电源适配器等电子产品。本公开实施例对电子设备的具体形式不做特殊限制。
示例的，电子设备1000为功率放大器。图44和图45示意性的给出了电子设备1000的两种剖面结构，但不限于此。
如图44所示，半导体器件100包括散热基板82。电子设备1000还包括金属引线1001、外接引脚1002和绝缘部1003。绝缘部1003采用绝缘材料，例如陶瓷材料，形成于散热基板82的裸露表面上。外接引脚1002设置在绝缘部1003的背离散热基板82的表面上。半导体器件100中的金属图案60或键合盘70可以通过金属引线1001与外接引脚1002对应耦接。
金属引线1001、外接引脚1002以及绝缘部1003的结构，可以根据实际需求选择设置。本公开实施例对此不作限定。可选的，绝缘部1003采用环状结构，半导体器件1000中位于散热基板82上的第一衬底11等部分与绝缘部1003的内侧壁之间具有间 隔。外接引脚1002采用镂空的金属片构成。金属引线1001采用导电性良好且具备一定机械强度的金属材料制备形成，该金属材料例如为金、铜、铝、铂、钨、镍、铱或钴等中的至少一种。
在一些实施例中，如图45所示，电子设备1000还包括封装盖板1004。封装盖板1004可以扣合在散热基板82或陶瓷部1003上。外接引脚1002的部分伸出封装盖板1004设置，方便于实现电子设备1000与外界部件的耦接。
本公开实施例中，电子设备1000所具有的优势，与前述一些实施例中半导体器件100所具有的优势相同，此处不再详述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种半导体器件，包括：第一衬底、至少一个晶体管、辅助承载部、以及多个金属图案；其中，
    所述辅助承载部和所述至少一个晶体管被设置于所述第一衬底上；所述辅助承载部在所述第一衬底上的正投影位于所述至少一个晶体管在所述第一衬底上的正投影外，且所述辅助承载部在所述第一衬底上的正投影边界与所述至少一个晶体管在所述第一衬底上的正投影边界部分重合；
    所述至少一个晶体管中的每个晶体管包括：半导体层，以及位于所述半导体层的背离所述第一衬底的一侧的栅极、源极和漏极；
    所述多个金属图案形成于所述辅助承载部的背离所述第一衬底的一侧；所述多个金属图案中的至少一个金属图案与所述栅极耦接，至少一个金属图案与所述漏极耦接，且与所述栅极耦接的金属图案和与所述漏极耦接的金属图案绝缘。
  2. 根据权利要求1所述的半导体器件，其中，所述辅助承载部的背离所述第一衬底的表面、与所述栅极或所述漏极的背离所述第一衬底的表面平齐或大致平齐。
  3. 根据权利要求1所述的半导体器件，其中，所述晶体管还包括：位于所述半导体层的背离所述第一衬底的表面上的第一钝化层；所述第一钝化层包括多个开口，所述栅极、所述源极和所述漏极分别形成于对应的开口内；
    所述辅助承载部的背离所述第一衬底的表面、与所述第一钝化层的背离所述第一衬底的表面平齐或大致平齐。
  4. 根据权利要求1所述的半导体器件，其中，所述晶体管还包括：第一钝化层和第二钝化层；所述第一钝化层和所述第二钝化层均包括多个开口；
    所述第一钝化层形成于所述半导体层的背离所述第一衬底的表面上；所述栅极、所述源极和所述漏极分别形成于所述第一钝化层中对应的开口内；
    所述第二钝化层形成于所述第一钝化层的背离所述半导体层的表面上，且位于所述栅极、所述源极和所述漏极的背离所述半导体层的一侧；
    所述辅助承载部的背离所述第一衬底的表面、与所述第二钝化层的背离所述第一衬底的表面平齐或大致平齐；所述金属图案通过所述第二钝化层中对应的开口与所述栅极或所述漏极耦接。
  5. 根据权利要求1所述的半导体器件，还包括：散热绝缘层；
    所述散热绝缘层形成于所述辅助承载部和所述晶体管的背离所述第一衬底的表面上；所述金属图案形成于所述散热绝缘层的背离所述辅助承载部的表面上。
  6. 根据权利要求5所述的半导体器件，其中，所述辅助承载部在所述第一衬底上的正投影位于所述散热绝缘层在所述第一衬底上的正投影内；所述散热绝缘层的部分表面与所述第一衬底直接接触。
  7. 根据权利要求1所述的半导体器件，还包括：金属层和至少一个第一导通孔；其中，
    所述金属层形成于所述第一衬底的背离所述晶体管的表面上；
    所述第一导通孔至少贯穿所述第一衬底和所述半导体层；所述第一导通孔在所述金属层上的正投影位于对应晶体管中的所述源极在所述金属层上的正投影内；
    所述金属层通过所述第一导通孔与所述源极耦接。
  8. 根据权利要求1所述的半导体器件，还包括：金属层和至少一个第二导通孔；其中，
    所述金属层形成于所述第一衬底的背离所述晶体管的表面上；
    所述第二导通孔至少贯穿所述第一衬底和所述辅助承载部；所述第二导通孔在所述金属层上的正投影位于对应的金属图案在所述第一衬底上的正投影内；
    所述金属层通过所述第二导通孔与所述金属图案耦接。
  9. 根据权利要求7或8所述的半导体器件，还包括：散热基板；
    所述散热基板位于所述金属层的背离所述第一衬底的一侧；所述金属层焊接于所述散热基板上。
  10. 根据权利要求1～9中任一项所述的半导体器件，其中，
    所述辅助承载部的靠近所述第一衬底的表面、与所述半导体层的靠近所述第一衬底的表面平齐或大致平齐；
    所述半导体器件还包括：非导电键合层；
    所述辅助承载部和所述至少一个晶体管的半导体层通过所述非导电键合层，键合至所述第一衬底上。
  11. 根据权利要求1～9中任一项所述的半导体器件，其中，
    所述晶体管还包括：层叠位于所述半导体层的背离所述栅极的一侧的过渡层和第二衬底；所述辅助承载部的靠近所述第一衬底的表面、与所述第二衬底的靠近所述第一衬底的表面平齐或大致平齐；
    所述半导体器件还包括：导电键合层；
    所述辅助承载部和所述至少一个晶体管的第二衬底通过所述导电键合层，键合至所述第一衬底上。
  12. 根据权利要求1～9中任一项所述的半导体器件，还包括：气体阻挡层；
    所述气体阻挡层形成于所述辅助承载部和所述至少一个晶体管的靠近所述第一衬底的表面上；所述第一衬底形成于所述气体阻挡层的背离所述辅助承载部的表面上。
  13. 根据权利要求1～12中任一项所述的半导体器件，其中，所述半导体层包括沿远离所述第一衬底的方向层叠设置的沟道层和势垒层。
  14. 一种电子设备，包括：如权利要求1～13中任一项所述的至少一个半导体器件。
  15. 一种半导体器件的制备方法，包括：
    提供晶圆，在所述晶圆上制备多个晶体管或多个晶体管的部分层；所述晶体管或其部分层的正面为背离所述晶圆的最外层表面；
    沿所述晶圆的厚度方向切割所述晶圆，获得多个器件颗粒；一个器件颗粒包括至少一个晶体管或至少一个晶体管的部分层；
    提供支撑基板，将至少一个所述器件颗粒的正面键合在所述支撑基板上；所述器件颗粒的正面为所述晶体管或其部分层的正面；
    在所述支撑基板的未被所述器件颗粒覆盖的表面、以及所述器件颗粒的背面形成辅助承载膜；
    抛光所述辅助承载膜以及所述器件颗粒，获得所述至少一个晶体管、以及位于所述至少一个晶体管旁侧的辅助承载部，所述辅助承载部的抛光表面与所述至少一个晶体管的抛光表面位于同一平面；
    提供第一衬底，将所述辅助承载部和所述至少一个晶体管的抛光表面同步键合在所述第一衬底上；或，在所述辅助承载部和所述至少一个晶体管的抛光表面上制备第一衬底；
    去除所述支撑基板；
    在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，并使得所述多个金属图案与所述至少一个晶体管对应耦接；
    获得半导体器件。
  16. 根据权利要求15所述的半导体器件的制备方法，其中，所述器件颗粒中的所述晶体管至少包括：第二衬底以及外延生长在所述第二衬底上的半导体层；所述第二衬底为所述晶圆的位于所述器件颗粒中的部分；
    抛光所述器件颗粒，还包括：使得所述至少一个晶体管中的所述半导体层的靠近所述第二衬底的表面裸露；或，使得所述至少一个晶体管中的所述第二衬底的抛光表面裸露。
  17. 根据权利要求16所述的半导体器件的制备方法，其中，所述器件颗粒中的所述晶体管还包括：第一钝化层、栅极、源极、漏极和第二钝化层；
    在所述晶圆上制备多个晶体管或多个晶体管的部分层，包括：在所述晶圆上外延生长所述半导体层；在所述半导体层的背离所述晶圆的表面上形成第一钝化层；在所述第一钝化层上形成多个开口，并在所述多个开口内分别形成所述栅极、所述源极和所述漏极；在所述第一钝化层、所述栅极、所述源极和所述漏极的背离所述半导体层的表面上形成第二钝化层；
    将所述器件颗粒的正面键合在所述支撑基板上，包括：将所述第二钝化层的背离所述栅极的表面键合在所述支撑基板上；
    在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，并使得所述多个金属图案与所述至少一个晶体管对应耦接，还包括：在所述第二钝化层中形成多个开口；在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，使得所述多个金属图案通过所述第二钝化层中的开口与所述栅极、所述漏极对应耦接。
  18. 根据权利要求16所述的半导体器件的制备方法，其中，所述器件颗粒中的所述晶体管还包括：形成于所述半导体层的背离所述晶圆的表面上的第一钝化层；
    在所述晶圆上制备多个晶体管或多个晶体管的部分层，包括：在所述晶圆上外延生长所述半导体层；在所述半导体层的背离所述晶圆的表面上形成第一钝化层；
    将所述器件颗粒的正面键合在所述支撑基板上，包括：将所述第一钝化层的背离所述半导体层的表面键合在所述支撑基板上；
    在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，并使得所述多个金属图案与所述至少一个晶体管对应耦接，还包括：在所述第一钝化层上形成多个开口，并在所述多个开口内分别形成栅极、源极和漏极；在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，并使得所述多个金属图案中的至少一个金属图 案与所述栅极耦接，至少一个金属图案与所述漏极耦接，且与所述栅极耦接的金属图案和与所述漏极耦接的金属图案绝缘。
  19. 根据权利要求18所述的半导体器件的制备方法，其中，在所述辅助承载部和所述至少一个晶体管的抛光表面上制备第一衬底，还包括：
    在所述辅助承载部和所述至少一个晶体管的抛光表面上形成气体阻挡层，所述气体阻挡层包括硅层、氮化硅层、氮化铝层或碳化硅层中的至少一层；
    采用化学气相沉积工艺或物理气相沉积工艺，在所述气体阻挡层的背离所述辅助承载部的表面上形成所述第一衬底。
  20. 根据权利要求15所述的半导体器件的制备方法，其中，在所述辅助承载部的背离所述第一衬底的一侧形成多个金属图案，还包括：
    在所述辅助承载部和所述至少一个晶体管的背离所述第一衬底的表面上形成散热绝缘层；
    在所述散热绝缘层的背离所述辅助承载部的表面上形成所述多个金属图案。
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