WO2022113949A1 - 画像表示装置の製造方法および画像表示装置 - Google Patents

画像表示装置の製造方法および画像表示装置 Download PDF

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Publication number
WO2022113949A1
WO2022113949A1 PCT/JP2021/042841 JP2021042841W WO2022113949A1 WO 2022113949 A1 WO2022113949 A1 WO 2022113949A1 JP 2021042841 W JP2021042841 W JP 2021042841W WO 2022113949 A1 WO2022113949 A1 WO 2022113949A1
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Prior art keywords
light emitting
layer
image display
insulating film
display device
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Ceased
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PCT/JP2021/042841
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English (en)
French (fr)
Japanese (ja)
Inventor
肇 秋元
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Nichia Corp
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Nichia Corp
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Filing date
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Application filed by Nichia Corp filed Critical Nichia Corp
Priority to JP2022565334A priority Critical patent/JP7728516B2/ja
Priority to CN202180065689.4A priority patent/CN116235305B/zh
Publication of WO2022113949A1 publication Critical patent/WO2022113949A1/ja
Priority to US18/138,104 priority patent/US11880615B2/en
Priority to US18/318,104 priority patent/US12477886B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • the embodiment of the present invention relates to a method for manufacturing an image display device and an image display device.
  • a display device using a micro LED which is a fine light emitting element
  • a method of manufacturing a display device using micro LEDs a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced.
  • the number of micro LED elements increases as the image quality becomes higher, such as full HD, 4K, 8K, etc.
  • a large number of micro LEDs may be individually formed and transferred sequentially to a substrate on which a drive circuit or the like is formed.
  • the transfer process requires a huge amount of time. Further, a poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.
  • a technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the electrodes are attached to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1).
  • One embodiment of the present invention provides a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved.
  • the image display device is provided on a substrate having a first surface, a conductive layer provided on the first surface and containing a first portion of a single crystal metal, and the first portion.
  • a light emitting element having a bottom surface electrically connected to the first portion and including a light emitting surface which is a surface opposite to the bottom surface, a side surface of the light emitting element, the first surface, and the conductive layer.
  • a method for manufacturing an image display device that shortens the transfer process of the light emitting element and improves the yield is realized.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the image display device according to the sixth embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of 6th Embodiment.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the sixth embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of the modification of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of the modification of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of the modification of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of the modification of 6th Embodiment. It is a schematic cross-sectional view which illustrates the manufacturing method of the image display apparatus of the modification of 6th Embodiment.
  • FIG. 1 represents a cross section seen from an arrow on the AA'line of FIG. 4, which will be described later, and is a cross-sectional view in which cross sections in a plurality of planes perpendicular to the XY plane are connected on one plane. Also in other figures, as in FIG.
  • the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z axis is the XY plane.
  • the positive direction of the Z axis may be referred to as "up” or “upward”
  • the negative direction of the Z axis may be referred to as "down” or “downward”. This is not always the case.
  • the length in the direction along the Z axis may be referred to as height.
  • the subpixel 20 has a light emitting surface 151S substantially parallel to the XY plane.
  • the light emitting surface 151S is a surface that mainly emits light in the positive direction of the Z axis orthogonal to the XY plane.
  • the subpixel 20 further includes a color filter 180.
  • the color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via the transparent thin film adhesive layer 188.
  • the surface resin layer 170 is provided on the second interlayer insulating film 108 and the wiring layer 110.
  • the conductive layer 130 is provided on the first surface 102a.
  • the conductive layer 130 includes a connection plate (first portion) 130a.
  • the light emitting element 150 is provided on the connection plate 130a.
  • the connection plate 130a is a member having a film-like, layer-like, or plate-like conductivity having a shape such as a square or an arbitrary polygon, an ellipse, or a circle in an XY plan view.
  • the connection plate 130a is electrically connected to the light emitting element 150 at the bottom surface 153B of the light emitting element 150.
  • connection plate 130a is provided for each subpixel 20.
  • the different connection plates 130a may or may not be connected to each other in the conductive layer 130.
  • the different connection plates 130a are connected to, for example, the power line 3 of FIG. 3, which will be described later, via vias 161a and wiring (first wiring) 110a provided for each connection plate 130a.
  • Part or all of the conductive layer 130 is made of single crystal metal. It is preferable that the entire conductive layer 130 is formed of a single crystal metal layer. Part or all of the connecting plate 130a is made of single crystal metal. The portion of the connection plate 130a where the light emitting element 150 is provided is made of a single crystal metal, for example, forming a single crystal metal layer.
  • the single crystal metal layer may be a part in the thickness direction including the surface to which the bottom surface 153B of the light emitting element 150 is connected.
  • the outer circumference of the single crystal metal layer includes the outer circumference of the bottom surface 153B when projected onto the single crystal metal layer in XY plan view. That is, the outer circumference of the bottom surface 153B is arranged within the outer circumference of the single crystal metal.
  • the area of the single crystal metal layer is larger than the area of the bottom surface 153B.
  • the metal material forming the conductive layer 130 and the connection plate 130a is, for example, Cu, Hf, or the like.
  • the metal material used for the conductive layer 130 and the connection plate 130a is not limited to Cu and Hf as long as it is a metal material that can be single-crystallized by an annealing treatment consistent with the LTPS process. Since the connection plate 130a is made of a metal material or the like, it has high conductivity and can be electrically connected to the light emitting element 150 with low resistance.
  • the light emitting element 150 includes a bottom surface 153B and a light emitting surface 151S.
  • the light emitting element 150 is a prismatic or columnar element having a bottom surface 153B on the connection plate 130a.
  • the bottom surface 153B is provided on the connection plate 130a and is electrically connected to the connection plate 130a.
  • the light emitting surface 151S is a surface opposite to the bottom surface 153B of the light emitting element 150.
  • the outer circumference of the connection plate 130a is set to include the outer circumference of the light emitting element 150 when the light emitting element 150 is projected in XY plan view. That is, in XY plan view, the outer circumference of the light emitting element 150 is arranged within the outer circumference of the connection plate 130a.
  • the conductive layer 130 and the connecting plate 130a are made of a metal material or the like as described above, and have light reflectivity. Therefore, the connection plate 130a reflects the scattered light downward of the light emitting element 150 toward the light emitting surface 151S side, and substantially improves the luminous efficiency of the light emitting element 150.
  • the outer circumference of the connection plate 130a is set so as not to include the outer circumference of the transistor 103 when the transistor 103 is projected onto the plane including the connection plate 130a in XY plan view. That is, in the XY plan view, the outer circumference of the connection plate 130a is arranged outside the outer circumference of the transistor 103. By doing so, the transistor 103 is less likely to receive the reflected light from the connection plate 130a, and the probability of causing a malfunction can be sufficiently reduced.
  • the outer circumference of the transistor 103 in the XY plane view is the outer circumference of the TFT channel 104 in the XY plane view, and the same applies to the embodiments and modifications described later.
  • the light emitting element 150 includes a p-type semiconductor layer (first semiconductor layer) 153, a light emitting layer 152, and an n-type semiconductor layer (second semiconductor layer) 151.
  • the p-type semiconductor layer 153, the light emitting layer 152, and the n-type semiconductor layer 151 are laminated in this order from the bottom surface 153B toward the light emitting surface 151S. Therefore, the p-type semiconductor layer 153 is electrically connected to the connection plate 130a.
  • the shape of the light emitting element 150 in XY plane view is, for example, substantially a square or a rectangle.
  • the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corners may be rounded.
  • the shape of the light emitting element 150 in the XY plane view is a columnar shape, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse.
  • a gallium nitride based compound semiconductor including a light emitting layer such as In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) is preferably used.
  • the above-mentioned gallium nitride based compound semiconductor may be simply referred to as gallium nitride (GaN).
  • the light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode.
  • the wavelength of the light emitted by the light emitting element 150 is, for example, about 467 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 150 may be bluish purple emission of about 410 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be appropriate.
  • the area of the light emitting layer 152 in the XY plane view is set according to the light emitting colors of the red, green, and blue subpixels.
  • the area in the XY plane view may be simply referred to as an area.
  • the area of the light emitting layer 152 is appropriately set by the visual sensitivity, the conversion efficiency of the color conversion unit 182 of the color filter 180, and the like. That is, the area of the light emitting layer 152 of the subpixel 20 of each light emitting color may be the same, or may be different for each light emitting color.
  • the area of the light emitting layer 152 is the area of the area surrounded by the outer circumference of the light emitting layer 152 projected on the XY plane.
  • the first interlayer insulating film (first insulating film) 156 covers the first surface 102a and the conductive layer 130.
  • the first interlayer insulating film 156 covers the side surface of the light emitting element 150.
  • the first interlayer insulating film 156 does not cover the light emitting surface 151S.
  • the first interlayer insulating film 156 insulates the light emitting elements 150 from each other.
  • the first interlayer insulating film 156 insulates the light emitting element 150 from a circuit element such as a transistor 103.
  • the first interlayer insulating film 156 provides a flat surface for forming a circuit 101 including a circuit element such as a transistor 103.
  • the first interlayer insulating film 156 protects the light emitting element 150 from thermal stress and the like when forming the transistor 103 and the like by covering the light emitting element 150.
  • the first interlayer insulating film 156 is formed of an organic or inorganic insulating material.
  • the insulating material used for the first interlayer insulating film 156 is preferably a white resin. Since the white resin reflects the lateral emission light of the light emitting element 150 and the return light caused by the interface of the color filter 180, it is necessary to use the white resin for the first interlayer insulating film 156 to improve the luminous efficiency of the light emitting element 150. Contributes to substantial improvement.
  • the white resin is formed by dispersing scatterable fine particles having a Mie scattering effect in a silicon-based resin such as SOG (Spin On Glass) or a transparent resin such as a novolak-type phenol-based resin.
  • the scattering fine particles are colorless or white, and have a diameter of about 1/10 to several times the wavelength of the light emitted by the light emitting element 150.
  • the scatterable fine particles preferably used have a diameter of about 1 ⁇ 2 of the wavelength of light.
  • examples of such scattering fine particles include TiO 2 , Al 2 O 3 , ZnO, and the like.
  • the white resin can also be formed by utilizing a large number of fine pores dispersed in the transparent resin.
  • a SiO 2 film formed by ALD (Atomic-Layer-Deposition) or CVD (Chemical Vapor Deposition) may be used on top of SOG or the like. ..
  • the first interlayer insulating film 156 may be a black resin.
  • the black resin as the first interlayer insulating film 156, the scattering of light in the subpixel 20 is suppressed, and the stray light is suppressed more effectively.
  • An image display device in which stray light is suppressed can display a sharper image.
  • the transistor 103 is formed on the TFT lower layer film 106.
  • circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and the circuit 101 is formed by wiring or the like.
  • the transistor 103 corresponds to the drive transistor 26 in FIG. 3, which will be described later.
  • the selection transistor 24, the capacitor 28, and the like are circuit elements.
  • the circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a wiring layer 110.
  • the transistor 103 is an n-channel thin film transistor (TFT).
  • the transistor 103 includes a TFT channel 104 and a gate 107.
  • the TFT channel 104 is preferably formed by a Low Temperature Poly Silicon (LTPS) process.
  • LTPS Low Temperature Poly Silicon
  • the TFT channel 104 is formed by polycrystallizing and activating a region of amorphous Si formed on the TFT underlayer film 106. For example, laser annealing is used for polycrystallization and activation of the amorphous Si region.
  • the TFT formed by the LTPS process has sufficiently high mobility.
  • the TFT channel 104 includes regions 104s, 104i, 104d.
  • the regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106.
  • the area 104i is provided between the area 104s and the area 104d.
  • the regions 104s and 104d are doped with impurities such as phosphorus (P) by ion implantation or the like to form regions of an n-type semiconductor, and are ohmic-connected to the vias 111s and 111d.
  • the gate 107 is provided on the TFT channel 104 via the insulating layer 105.
  • the insulating layer 105 is provided to insulate the TFT channel 104 and the gate 107 and to insulate them from other adjacent circuit elements.
  • a potential higher than the region 104s is applied to the gate 107, a channel is formed in the region 104i, so that the current flowing between the regions 104s and 104d can be controlled.
  • the insulating layer 105 is, for example, SiO 2 .
  • the insulating layer 105 may be a multi-layered insulating layer containing SiO 2 or Si 3 N 4 depending on the covering region.
  • the gate 107 may be formed of, for example, polycrystalline Si or a refractory metal such as W or Mo.
  • the polycrystalline Si film of the gate 107 is formed by, for example, CVD.
  • the code of the wiring layer shall be displayed at the position next to one wiring included in the wiring layer to be labeled.
  • the translucent electrode 159d is provided over the wiring 110d.
  • the translucent electrode 159d is provided over the light emitting surface 151S.
  • the translucent electrode 159d is also provided between the wiring 110d and the light emitting surface 151S, and electrically connects the wiring 110d and the light emitting surface 151S.
  • the light emitting surface 151S is preferably roughened as in this example.
  • the light emitting element 150 can improve the light extraction efficiency.
  • the via 111s is provided between the wiring 110s and the area 104s, and electrically connects the wiring 110s and the area 104s.
  • the via 111d is provided between the wiring 110d and the area 104d, and electrically connects the wiring 110d and the area 104d.
  • the wiring 110s and the translucent electrode 159s are connected to the region 104s via the via 111s.
  • the region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the ground wire 4 via the via 111s, the wiring 110s, and the translucent electrode 159s.
  • the wiring 110d and the translucent electrode 159d are connected to the region 104d via the via 111d.
  • the region 104d is a drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the n-type semiconductor layer 151 via the via 111d, the wiring (second wiring) 110d, and the translucent electrode 159d.
  • the via 161a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 161a is provided between the wiring 110a and the connection plate 130a, and electrically connects the wiring 110a and the connection plate 130a. Therefore, the p-type semiconductor layer 153 is electrically connected to, for example, the power line 3 of the circuit of FIG. 3 via the connection plate 130a, the via 161a, the wiring 110a, and the translucent electrode 159a.
  • the wiring layer 110 and the vias 111s, 111d, 161a are formed of, for example, Al, Cu, or an alloy thereof. It may be formed by a laminated film of Al and Ti or the like. For example, in a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.
  • the surface resin layer 170 covers the second interlayer insulating film 108, the wiring layer 110, and the translucent electrodes 159s, 159d, 159a.
  • the surface resin layer 170 is also filled in the opening 158.
  • the surface resin layer 170 is provided on the light emitting surface 151S via the translucent electrode 159d.
  • the surface resin layer 170 filled in the opening 158 is a translucent electrode provided so as to cover the side surfaces of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. It is provided on 159d.
  • the surface resin layer 170 is a transparent resin, which protects the second interlayer insulating film 108, the wiring layer 110, and the translucent electrodes 159a, 159d, 159s, and provides a flattening surface for adhering the color filter 180. ..
  • the color filter 180 includes a light-shielding unit 181 and a color conversion unit 182.
  • the color conversion unit 182 is provided directly above the light emitting surface 151S of the light emitting element 150 according to the shape of the light emitting surface 151S.
  • the portion other than the color conversion unit 182 is a light-shielding unit 181.
  • the light-shielding unit 181 is a so-called black matrix, which reduces bleeding due to color mixing of light emitted from an adjacent color conversion unit 182 and makes it possible to display a sharp image.
  • the color conversion unit 182 has one layer or two or more layers.
  • FIG. 1 shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one layer or two layers is determined by the color of the light emitted by the subpixel 20, that is, the wavelength.
  • the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing red light.
  • the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing green light.
  • the emission color of the subpixel 20 is blue, it is preferably one layer.
  • the first layer is the color conversion layer 183 and the second layer is the filter layer 184.
  • the first color conversion layer 183 is provided at a position closer to the light emitting element 150.
  • the filter layer 184 is laminated on the color conversion layer 183.
  • the color conversion layer 183 converts the wavelength of the light emitted by the light emitting element 150 into a desired wavelength.
  • the light having a wavelength of 467 nm ⁇ 30 nm, which is the wavelength of the light emitting element 150 is converted into light having a wavelength of, for example, about 630 nm ⁇ 20 nm.
  • light having a wavelength of 467 nm ⁇ 30 nm, which is the wavelength of the light emitting element 150 is converted into light having a wavelength of, for example, about 532 nm ⁇ 20 nm.
  • the filter layer 184 blocks the wavelength component of blue light emission remaining without color conversion in the color conversion layer 183.
  • the light emitting element 150 may output the light through the color conversion layer 183 or output the light as it is without passing through the color conversion layer 183. You may do so.
  • the wavelength of the light emitted by the light emitting element 150 is about 467 nm ⁇ 30 nm, the light may be output without passing through the color conversion layer 183.
  • the wavelength of the light emitted by the light emitting element 150 is 410 nm ⁇ 30 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ⁇ 30 nm.
  • the sub-pixel 20 may have a filter layer 184.
  • the blue subpixel 20 may have a filter layer 184 through which blue light is transmitted, minute external light reflection other than blue light generated on the surface of the light emitting element 150 is suppressed.
  • FIG. 2 is a cross-sectional view schematically showing a part of an image display device according to a modified example of the present embodiment.
  • the subpixel 20a is different from the case of the first embodiment described above in the connection method between the light emitting element 150a and the wiring 110d1.
  • This modification is also different from the case of the first embodiment in that the translucent electrodes are not provided on the wirings 110s, 110d1, 110a.
  • this modification is the same as in the first embodiment, and the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • FIG. 2 also shows the structure above the surface resin layer 170. These superstructures are also the same as in the case of the first embodiment.
  • the subpixel 20a includes a light emitting element 150a and a wiring 110d1.
  • a part of the wiring 110d1 is provided above the area 104d.
  • the other part of the wiring 110d1 is provided so as to extend to the light emitting surface 151S, and the tip thereof is connected to the surface including the light emitting surface 151S.
  • the surface including the light emitting surface 151S is a surface in the same plane as the light emitting surface 151S.
  • the tip of the wiring 110d1 is connected to a surface other than the light emitting surface 151S on this surface.
  • the light emitting surface 151S is not roughened, but may be roughened. When the surface is not roughened, the step for roughening can be omitted.
  • FIG. 3 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 1 of the present embodiment includes a display area 2.
  • Subpixels 20 are arranged in the display area 2.
  • the sub-pixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.
  • Pixel 10 includes a plurality of sub-pixels 20 that emit light of different colors.
  • the subpixel 20R emits red light.
  • the subpixel 20G emits green light.
  • the subpixel 20B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 20R, 20G, and 20B emitting light at a desired brightness.
  • the image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7.
  • the row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2.
  • the row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2.
  • the row selection circuit 5 is electrically connected to the subpixels 20 in each column via the scanning line 6 to supply a selection signal to each subpixel 20.
  • the signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2.
  • the signal voltage output circuit 7 is electrically connected to the subpixel 20 of each line via the signal line 8 to supply a signal voltage to each subpixel 20.
  • the subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28.
  • the selection transistor 24 may be displayed as T1
  • the drive transistor 26 may be displayed as T2
  • the capacitor 28 may be displayed as Cm.
  • the light emitting element 22 is connected in series with the drive transistor 26.
  • the drive transistor 26 is an n-channel TFT, and the cathode electrode of the light emitting element 22 is connected to the drain electrode of the drive transistor 26.
  • the main electrodes of the drive transistor 26 and the selection transistor 24 are a drain electrode and a source electrode.
  • the anode electrode of the light emitting element 22 is connected to the p-type semiconductor layer.
  • the cathode electrode of the light emitting device is connected to the n-type semiconductor layer.
  • the series circuit of the light emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4.
  • the drive transistor 26 corresponds to the transistor 103 in FIG.
  • the light emitting element 22 corresponds to the light emitting element 150 in FIG.
  • the current flowing through the light emitting element 22 is determined by the voltage applied between the gate and the source of the drive transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.
  • the selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode.
  • the gate electrode of the selection transistor 24 is connected to the scanning line 6.
  • a capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.
  • the row selection circuit 5 selects one row from the array of subpixels 20 in the m row and supplies the selection signal to the scanning line 6.
  • the signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value for each subpixel 20 in the selected row.
  • a signal voltage is applied between the gate and the source of the drive transistor 26 of the subpixel 20 in the selected row.
  • the signal voltage is held by the capacitor 28.
  • the drive transistor 26 causes a current corresponding to the signal voltage to flow through the light emitting element 22.
  • the light emitting element 22 emits light with a brightness corresponding to the flowing current.
  • the anode electrode of the light emitting element 150 is arranged on the connection plate 130a and is electrically connected to the connection plate 130a.
  • the connection plate 130a is provided below the transistor 103 and the wiring layer 110 shown in FIG.
  • the connection plate 130a is electrically connected to the wiring 110a via the via 161a. More specifically, one end of the via 161a is connected to the connection plate 130a, and the other end of the via 161a is connected to the wiring 110a via the contact hole 161a1.
  • the cathode electrode of the light emitting element 150 is provided by the n-type semiconductor layer 151 shown in FIG.
  • the wiring 110d is covered with the translucent electrode 159d shown in FIG.
  • the translucent electrode 159d covers the light emitting surface 151S. Since the translucent electrode 159d is also provided between the wiring 110d and the light emitting surface 151S, the cathode electrode of the light emitting element 150 is electrically connected to the wiring 110d.
  • a part of the wiring 110d is connected to the drain electrode of the transistor 103 via the via 111d.
  • the drain electrode of the transistor 103 is the region 104d shown in FIG.
  • the source electrode of the transistor 103 is connected to the wiring 110s via the via 111s.
  • the source electrode of the transistor 103 is the region 104s shown in FIG.
  • the wiring layer 110 includes a ground wire 4, and the wiring 110s is connected to the ground wire 4.
  • the power line 3 is provided in a layer higher than the wiring layer 110.
  • an interlayer insulating film is further provided on the wiring layer 110.
  • the power line 3 is provided on the interlayer insulating film of the uppermost layer, and is insulated from the ground line 4.
  • the light emitting element 150 can be electrically connected to the wiring 110a provided on the upper layer of the light emitting element 150 by using the via 161a. Further, the light emitting element 150 exposes the light emitting surface 151S through the opening 158, and by providing the translucent electrode 159d over the opening 158, the transistor 103 provided above the light emitting element 150 via the wiring 110d. Can be electrically connected to.
  • FIG. 5A to 7B are schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.
  • a substrate (first substrate) 102 is prepared.
  • the substrate 102 is a translucent substrate, for example, a substantially rectangular glass substrate having a size of about 1500 mm ⁇ 1800 mm.
  • the conductive layer 1130 is formed on the first surface 102a.
  • the conductive layer (metal layer) 1130 is patterned so as to leave a portion where a light emitting layer is formed after forming a layer of a metal material on the entire surface of the first surface 102a by sputtering or the like.
  • the conductive layer 1130 may be provided with a mask having a pattern that opens a portion where the light emitting layer is formed on the first surface 102a, and then the patterned conductive layer 1130 may be formed.
  • the conductive layer 1130 is formed by using a metal material such as Cu or Hf.
  • a metal material such as Cu or Hf.
  • sputtering or the like is preferably used in order to form a film at a low temperature.
  • the patterned conductive layer 1130 is single crystallized by an annealing treatment.
  • the annealing treatment is applied so as to be single crystallized over the entire patterned conductive layer 1130.
  • an annealing treatment by laser irradiation is preferably used.
  • the conductive layer 1130 can be single-crystallized in a state where the influence of the temperature on the layer below the conductive layer 1130 is suppressed to a low temperature of about 400 ° C. to about 500 ° C., so that the substrate 102 is made of glass or an organic resin described later.
  • a flexible substrate or the like can be used.
  • the semiconductor layer 1150 is formed over the single crystallized conductive layer 1130a.
  • the semiconductor layer 1150 is formed in the order of the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 from the conductive layer 1130a in the positive direction of the Z axis.
  • a physical vapor deposition method such as thin film deposition, ion beam deposition, molecular beam epitaxy (MBE) or sputtering is used, and a low temperature sputtering method is preferably used.
  • MBE molecular beam epitaxy
  • a low temperature sputtering method it is preferable to assist with light or plasma at the time of film formation because the temperature can be lowered.
  • Epitaxy growth by MOCVD may exceed 1000 ° C.
  • a GaN crystal containing a light emitting layer can be epitaxially grown on a single crystal metal layer at a low temperature of about 400 ° C to 700 ° C (Non-Patent Document 1). See 2nd class).
  • Such a low temperature sputtering method is consistent with forming the semiconductor layer 1150 on a circuit board having a TFT or the like formed by the LTPS process.
  • Layer 1150 is formed.
  • amorphous deposits containing Ga or the like which is a material for growing species, may be deposited in a place where the conductive layer 1130a does not exist.
  • the conductive layer 1130a of a single crystal metal is used as a seed to promote the crystal formation of GaN.
  • a conductive buffer layer is provided on the conductive layer 1130a, and the semiconductor layer is formed on the buffer layer by the above-mentioned low-temperature sputtering method or the like. You may try to grow it.
  • the buffer layer may be of any type as long as it is a material that promotes GaN crystal formation. Graphene sheets in the case of other embodiments described later may be used.
  • the semiconductor layer 1150 shown in FIG. 5B is formed into a desired shape by etching or the like, and a light emitting element 150 is formed.
  • a dry etching process is used for forming the light emitting element 150, and anisotropic plasma etching (Reactive Ion Etching, RIE) is preferably used.
  • RIE reactive Ion Etching
  • the conductive layer 130 is formed by etching the conductive layer 1130a shown in FIG. 5B.
  • the connection plate (first portion) 130a is formed.
  • the conductive layer 1130a may be etched together with the semiconductor layer 1150 to form the connection plate 130a, and then the light emitting device 150 may be formed.
  • the connection plate 130a is formed on the first surface 102a, and the light emitting element 150 is formed on the connection plate 130a.
  • the outer circumference of the connection plate 130a is set to include the outer circumference of the light emitting element 150 when the light emitting element 150 is projected in XY plan view. That is, in XY plan view, the outer circumference of the light emitting element 150 is arranged within the outer circumference of the connection plate 130a.
  • the TFT channel (circuit element) 104 is formed on the TFT underlayer film 106.
  • the TFT channel 104 is formed as follows. First, amorphous Si is formed into the shape of the TFT channel 104. For example, CVD or the like is used for forming an amorphous Si film. The formed amorphous Si film is polycrystallized by laser annealing to form a TFT channel 104.
  • the via hole 162a is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the connection plate 130a.
  • the opening 158 reaches the light emitting surface 151S by removing a part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower layer film 106, and a part of the first interlayer insulating film 156. Is formed in.
  • the via hole 112d is formed so as to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104d.
  • the via hole 112s is formed so as to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104s.
  • RIE is used for forming the via holes 162a, 112d, 112s and the opening 158.
  • the via 161a is formed by filling the via hole 162a shown in FIG. 7A with a conductive material.
  • the vias 111d and 111s are also formed by filling the via holes 112d and 112s shown in FIG. 7A with a conductive material, respectively.
  • the wiring layer 110 including the wirings 110a, 110d, 110s is formed on the second interlayer insulating film 108.
  • the wirings 110a, 110d, 110s are connected to the vias 161a, 111d, 111s, respectively.
  • the wiring layer 110 may be formed at the same time as the vias 161a, 111d, 111s are formed.
  • the translucent conductive film is formed on the wiring layer 110 and the second interlayer insulating film 108, and the translucent electrodes 159a, 159d, 159s are formed.
  • the sub-pixel 20 of the image display device 1 of the present embodiment is formed by providing a color filter (wavelength conversion member) 180 or the like.
  • FIGS. 8A and 8B are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the present embodiment.
  • 8A and 8B show a process for forming the subpixel 20a shown in FIG.
  • the steps up to the step shown in FIG. 6B for forming the TFT channel 104, the insulating layer 105, and the gate 107 and forming the second interlayer insulating film 108 covering them are the same as those described above. There is.
  • the steps of FIGS. 8A and 8B will be described as being applied to the steps after the steps shown in FIG. 6B.
  • via holes 162a, 112d, 112s are formed.
  • the opening 158 is formed so as to reach the n-type semiconductor layer 151a.
  • the etching step for roughening can be omitted.
  • the vias 161a, 111d, 111s are formed by filling the via holes 162a, 112d, 112s shown in FIG. 8A with a conductive material.
  • the wiring layer 110 is formed, and the wirings 110a, 110d1, 110s are formed.
  • one end of the wiring 110d1 is connected to the via 111d.
  • the wiring 110d1 is provided so as to extend from the position connected to the via 111d to the light emitting surface 151S.
  • the other end of the wiring 110d1 is connected to a surface including the light emitting surface 151S. That is, the surface including the light emitting surface 151S is the n-type semiconductor layer 151a, and the wiring 110d1 is directly connected to the n-type semiconductor layer 151a.
  • the sub-pixel 20a of this modification is formed by providing the color filter 180 or the like.
  • the signal voltage output circuit 7 be incorporated in a semiconductor device manufactured by a manufacturing process capable of high integration by microfabrication.
  • the signal voltage output circuit 7 is mounted on another board together with the CPU and other circuit elements, and is provided, for example, before the incorporation of the color filter described later, or after the incorporation of the color filter, for example, at the peripheral edge of the display area. It is interconnected with the sub-pixels 20 and 20a via a connector or the like.
  • FIG. 9 is a schematic cross-sectional view illustrating the method for manufacturing the image display device of the present embodiment.
  • the figure above the arrow shows the configuration including the color filter 180
  • the figure below the arrow shows the structure including the light emitting element 150 and the like formed in the above-mentioned steps.
  • FIG. 9 shows a step of adhering a color filter to a structure including a light emitting element 150 and the like by an arrow.
  • the display of components other than the components on the illustrated substrate 102 is omitted.
  • the omitted components are the circuit 101 including the TFT channel 104, the wiring layer 110, and the like shown in FIG. 1, and the via 161a.
  • FIGS. 9 is a schematic cross-sectional view illustrating the method for manufacturing the image display device of the present embodiment.
  • the figure above the arrow shows the configuration including the color filter 180
  • the figure below the arrow shows the structure including the light emitting element 150 and the like formed in the above-mentioned steps.
  • the structure including the light emitting element 150, the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, the second interlayer insulating film 108, and the surface resin layer 170 is included. It is called a light emitting circuit unit 172.
  • a structure including a substrate 102, a conductive layer 130, a light emitting circuit unit 172, and components whose display is omitted is referred to as a structure 1192.
  • the TFT channel 104, the gate 107, the vias 111s, 111d, and the wiring layer 110 are not shown.
  • the color filter (wavelength conversion member) 180 is adhered to the structure 1192 on one side.
  • the other surface of the color filter 180 is adhered to the glass substrate 186.
  • a transparent thin film adhesive layer 188 is provided on one surface of the color filter 180, and is adhered to the exposed surface of the surface resin layer 170 of the structure 1192 via the transparent thin film adhesive layer 188.
  • the color filter 180 has color conversion units arranged in the positive direction of the X-axis in the order of red, green, and blue.
  • a red color conversion layer 183R is provided on the first layer
  • a green color conversion layer 183G is provided on the first layer
  • a filter layer 184 is provided on the second layer in each case.
  • Each is provided.
  • a single-layer color conversion layer 183B may be provided, or a filter layer 184 may be provided.
  • a light-shielding unit 181 is provided between the color conversion units, and the frequency characteristics of the filter layer 184 can be changed for each color of the color conversion unit.
  • the color conversion layer 183 be as thick as possible in order to improve the color conversion efficiency.
  • the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambersian, whereas the emission angle of the non-color-converted blue light is limited by the light-shielding portion 181. .. Therefore, there arises a problem that the display color of the display image is dependent on the viewing angle.
  • the thickness of the color conversion layer 183 should be about half the opening size of the light-shielding portion 181. Is desirable.
  • FIG. 11 is a schematic perspective view illustrating the image display device according to the present embodiment.
  • a light emitting circuit unit 172 having a large number of subpixels 20 is provided on the substrate 102.
  • the conductive layer 130 shown in FIG. 9 includes a connection plate 130a.
  • the connection plate 130a is provided on the substrate 102 according to each of the subpixels 20.
  • a color filter 180 is provided on the light emitting circuit unit 172.
  • Other embodiments and modifications described later have the same configurations as those shown in FIG. 11.
  • the light emitting element 150 is formed by etching the semiconductor layer 1150 in which crystals are grown on the substrate 102. After that, the light emitting element 150 is covered with the first interlayer insulating film 156, and a circuit 101 including a circuit element such as a transistor 103 for driving the light emitting element 150 is built on the first interlayer insulating film 156. Therefore, the manufacturing process is remarkably shortened as compared with transferring the individualized light emitting elements to the substrate 102 individually.
  • the number of sub-pixels exceeds 24 million, and in the case of an 8K image quality image display device, the number of sub-pixels exceeds 99 million. It would take an enormous amount of time to individually form such a large number of light emitting elements and mount them on a circuit board. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Further, if a large number of light emitting elements are individually mounted, the yield is reduced due to poor connection at the time of mounting, and further cost increase is unavoidable.
  • the glass substrate formed as described above is covered with an interlayer insulating film, and a drive circuit including a TFT or the like, a scanning circuit, or the like is formed on the flattened surface by using an LTPS process or the like. Can be done. Therefore, there is an advantage that the existing flat panel display manufacturing process and plant can be used.
  • the conductive layer 130 is formed on the first surface 102a of the substrate 102.
  • the conductive layer 130 includes a connection plate 130a.
  • the light emitting element 150 is formed on the connection plate 130a and is electrically connected to the connection plate 130a at the bottom surface 153B.
  • the connection plate 130a is made of a highly conductive material such as a metal material. Therefore, the p-type semiconductor layer 153 of the light emitting element 150 can be electrically connected to another circuit with low resistance.
  • connection plate 130a can be formed of a metal material having light reflectivity such as Cu or Hf.
  • the outer periphery of the connection plate 130a is formed so as to include the outer periphery of the light emitting element 150 when the light emitting element 150 is projected in XY plan view. That is, in XY plan view, the outer circumference of the light emitting element 150 is arranged within the outer circumference of the connection plate 130a. Therefore, the connection plate 130a also functions as a light reflecting plate, and can substantially improve the luminous efficiency of the light emitting element 150 by reflecting the scattered light or the like downward of the light emitting element 150 on the light emitting surface 151S.
  • FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • the p-type semiconductor layer 253 provides the light emitting surface 253S and the configuration of the transistor 203 is different from that of the other embodiments described above.
  • the same components as in the case of other embodiments are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 220 of the image display device of the present embodiment includes a substrate 102, a conductive layer 130, a light emitting element 250, a first interlayer insulating film 156, a transistor 203, and a second interlayer insulation.
  • the film 108 and the wiring layer 110 are included.
  • the light emitting element 250 is provided on the connection plate 130a.
  • the outer circumference of the connection plate 130a is set to include the outer circumference of the light emitting element 250 when the light emitting element 250 is projected in XY plan view. That is, in XY plan view, the outer circumference of the light emitting element 250 is arranged within the outer circumference of the connection plate 130a. Therefore, the light scattered downward of the light emitting element 250 can be reflected to the light emitting surface 253S side, and the luminous efficiency of the light emitting element 250 is substantially improved as in the case of the other embodiments described above. Is.
  • the light emitting element 250 includes an n-type semiconductor layer 251, a light emitting layer 252, and a p-type semiconductor layer 253.
  • the n-type semiconductor layer 251 and the light emitting layer 252 and the p-type semiconductor layer 253 are laminated in this order from the bottom surface 251B toward the light emitting surface 253S.
  • the light emitting surface 253S is provided by the p-type semiconductor layer 253.
  • the light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiment described above. That is, the wavelength of the light emitted by the light emitting element 250 is, for example, blue light emission of about 467 nm ⁇ 30 nm or blue-purple light emission of about 410 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 250 is not limited to the above-mentioned value, and may be appropriate.
  • the via 161k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 161k is provided between the wiring 210k and the connection plate 130a, and electrically connects the wiring 210k and the connection plate 130a.
  • the wiring 110s is electrically connected to, for example, the power line 3 shown in FIG. 13, which will be described later.
  • the wiring 110d is electrically connected to the p-type semiconductor layer 253 via the translucent electrode 159d.
  • the translucent electrode 159d is provided over the light emitting surface 253S of the roughened p-type semiconductor layer 253.
  • the translucent electrode 159d is provided over the wiring 110d.
  • the translucent electrode 159d is also provided between the light emitting surface 253S and the wiring 110d, and electrically connects the p-type semiconductor layer 253 and the wiring 110d.
  • the wiring 110d1 may be extended and directly connected to the p-type semiconductor layer 253 as in the example shown in FIG.
  • FIG. 13 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 201 of the present embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207.
  • the sub-pixels 220 are arranged in a grid pattern on the XY plane, as in the case of the other embodiments described above.
  • Pixel 10 includes a plurality of sub-pixels 220 that emit light of different colors, as in the case of the other embodiments described above.
  • the subpixel 220R emits red light.
  • the subpixel 220G emits green light.
  • the sub-pixel 220B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 220R, 220G, and 220B emitting light at a desired brightness.
  • One pixel 10 includes three sub-pixels 220R, 220G, 220B, and the sub-pixels 220R, 220G, 220B are linearly arranged on the X-axis, for example, as in this example.
  • sub-pixels of the same color may be arranged in the same column, or sub-pixels of different colors may be arranged in each column as in this example.
  • the subpixel 220 includes a light emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228.
  • the selection transistor 224 may be displayed as T1
  • the drive transistor 226 may be displayed as T2
  • the capacitor 228 may be displayed as Cm.
  • a selection transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208.
  • the capacitor 228 is connected between the gate electrode of the drive transistor 226 and the power line 3.
  • the row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage having a polarity different from that of the other embodiment described above to the signal line 208 in order to drive the drive transistor 226 which is a transistor of the p channel.
  • the row selection circuit 205 supplies a selection signal to the scanning line 206 so as to sequentially select one row from the array of subpixels 220 in the m row.
  • the signal voltage output circuit 207 supplies a signal voltage having the required analog voltage value for each subpixel 220 in the selected row.
  • the drive transistor 226 of the subpixel 220 in the selected row causes a current corresponding to the signal voltage to flow through the light emitting element 222.
  • the light emitting element 222 emits light with a brightness corresponding to the current flowing through the light emitting element 222.
  • FIG. 14A to 16B are schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.
  • the substrate 102 in which the conductive layer 1130 described in relation to FIG. 5A of the other embodiment described above is formed on the first surface 102a can be used.
  • the steps after FIG. 14A will be described as being applied after the step of FIG. 5A.
  • the conductive layer 1130 shown in FIG. 5A is subjected to a single crystallization treatment and is single crystallized on the first surface 102a.
  • Layer 1130a is formed.
  • the semiconductor layer 1150 is formed on the conductive layer 1130a.
  • the semiconductor layer 1150 is formed in the order of the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 from the conductive layer 1130a in the positive direction of the Z axis.
  • the semiconductor layer 1150 is formed by using the same film forming technique as in the case of the other embodiments described above. That is, the low temperature sputtering method is preferably used for forming the semiconductor layer 1150, and other physical vapor deposition methods such as thin film deposition, ion beam deposition, and MBE are used.
  • the semiconductor layer 1150 shown in FIG. 14A is formed into a desired shape, and a light emitting element 250 is formed.
  • a dry etching process is used, and RIE is preferably used.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 102a, the conductive layer 130, and the light emitting element 250.
  • the TFT lower layer film 106 is formed over the exposed surface of the first interlayer insulating film 156.
  • CVD or the like is used to form the TFT underlayer film 106.
  • the TFT channel 204 is formed at a predetermined position on the TFT underlayer film 106 and is activated or the like.
  • the insulating layer 105 is formed over the TFT underlayer film 106 and the TFT channel 204.
  • the gate 107 is formed on the TFT channel 204 via the insulating layer 105.
  • the LTPS process is preferably used as the above forming process.
  • the second interlayer insulating film 108 is formed over the insulating layer 105 and the gate 107.
  • the via hole 162k is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the connection plate 130a.
  • the opening 158 reaches the light emitting surface 253S by removing a part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower layer film 106, and a part of the first interlayer insulating film 156. Is formed in.
  • the central portion of the surface of the p-type semiconductor layer 253 exposed by removing the first interlayer insulating film 156 and the like is etched in the thickness direction of the p-type semiconductor layer 253, and the light emitting surface 253S is used.
  • the light emitting surface 253S is preferably roughened as in the case of the other embodiments described above.
  • the vias 161k, 111d, 111s are formed by filling the via holes 162k, 112d, 112s shown in FIG. 16A with a conductive material.
  • the wiring layer 110 including the wirings 210k, 110d, 110s is subsequently formed, and the wirings 210k, 110d, 110s are connected to the vias 161k, 111d, 111s, respectively.
  • the sub-pixel 220 of the image display device 201 of the present embodiment is formed by providing the color filter 180 or the like.
  • FIG. 17 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • This embodiment differs from the other embodiments described above in that the graphene layer 140 is provided on the conductive layer 130 and the graphene sheet 140a is provided between the connection plate 130a and the light emitting element 150. ..
  • the same components as in the case of the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the graphene sheet 140a has an outer circumference that substantially coincides with the outer circumference of the light emitting element 150 in XY plan view.
  • the light emitting element 150 is configured in the same manner as in the case of the first embodiment. That is, the p-type semiconductor layer 153, the light emitting layer 152, and the n-type semiconductor layer 151 are laminated in this order from the bottom surface 153B toward the light emitting surface 151S.
  • the bottom surface 153B is a p-type semiconductor layer 153, and the p-type semiconductor layer 153 is electrically connected to the connection plate 130a via the graphene sheet 140a.
  • the light emitting surface 151S is roughened, but the roughening can be omitted.
  • the effect of the image display device of this embodiment will be described.
  • the light emitting element 150 is formed via the graphene sheet 140a formed on the connection plate 130a of the single crystal metal. Therefore, the image display device of the present embodiment can obtain a light emitting element 150 having a higher quality crystal structure. Therefore, the yield of the image display device can be improved.
  • FIG. 21 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • the via 461a is different from the case of the first embodiment in that the via 461a is provided between the connection plate 130a and the wiring 410d.
  • the light emitting element 150 is also different from the case of the first embodiment in that it is driven by the p-type transistor 203.
  • the same components as in the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • connection plate 130a is provided as in the case of the first embodiment. That is, the connection plate 130a is provided directly below the light emitting element 150, and the outer periphery of the connection plate 130a includes the outer periphery of the light emitting element 150 when the light emitting element 150 is projected onto the connection plate 130a in XY plan view. Is set to. That is, in XY plan view, the outer circumference of the light emitting element 150 is arranged within the outer circumference of the connection plate 130a. Therefore, the connection plate 130a also functions as a light reflection plate, and substantially improves the luminous efficiency of the light emitting element 150.
  • the translucent electrode 159k is provided over the wiring 410k.
  • the translucent electrode 159k is provided over the light emitting surface 151S.
  • the translucent electrode 159k is provided between the wiring 410k and the light emitting surface 151S. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit shown in FIG. 13 via the translucent electrode 159k and the wiring (fourth wiring) 410k.
  • the vias 461a, 111d, 111s and wirings 410k, 410d, 110s are formed of the same materials and manufacturing methods as in the case of the above-mentioned other embodiments and modifications thereof.
  • the via hole 462a is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the connection plate 130a.
  • the openings 158 and the via holes 112d, 112s are formed in the same manner as in the other embodiments described above.
  • the via holes 462a, 112d, 112s shown in FIG. 22A are filled with a conductive material, and vias 461a, 111d, 111s are formed.
  • the wiring layer 110 is formed on the second interlayer insulating film 108.
  • a translucent conductive film is formed on the wiring layer 110, and translucent electrodes 159k, 159d, and 159s are formed.
  • the effect of the image display device of this embodiment will be described.
  • the image display device of the present embodiment has the following effects in addition to the effects of the first embodiment described above. That is, in the present embodiment, it is possible to have a circuit configuration in which the light emitting element 150 is driven by the transistor 203 of the p channel while the light emitting surface 151S is the n-type semiconductor layer 151. Therefore, flexible circuit design is possible by expanding variations such as circuit layout.
  • the image display device of the present embodiment includes subpixels 520.
  • Subpixel 520 includes a substrate 502.
  • the substrate 502 includes a first surface 502a.
  • a layer 507 containing a silicon compound is formed on the first surface 502a.
  • the layer 507 containing the silicon compound is formed of SiO 2 , SiN x , or the like. Since the conductive layer 130 is made of a metal material, the layer 507 containing the silicon compound is provided in order to improve the adhesion between the substrate 502 and the conductive layer 130.
  • the conductive layer 130 and the connection plate 130a are provided on the first surface 502a via a layer 507 containing a silicon compound.
  • a layer 507 containing a silicon compound the structure and components above the conductive layer 130 and the connection plate 130a are the same as in the first embodiment described above, and detailed description thereof will be omitted.
  • the substrate 502 has flexibility.
  • the substrate 502 is made of, for example, a polyimide resin or the like.
  • the first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, and the like are preferably formed of a material having a certain degree of flexibility depending on the flexibility of the substrate 502.
  • the wiring layer 110 having the longest wiring length has the highest risk of being destroyed during bending.
  • the inner surface that bends when the image display device is bent is reduced by receiving compressive stress, and the outer surface is stretched by receiving elongation stress.
  • a neutral surface in which both stresses cancel each other exists inside the image display device, and the neutral surface does not expand or contract due to stress due to bending.
  • a plurality of protective films may be provided on the front surface or the back surface of the image display device to reduce the stress due to bending. Further, it is desirable to adjust the film thickness, film quality, material, etc. of these protective films so that the neutral surface overlaps with the position of the wiring layer 110.
  • the structure and components above the layer 507 containing the silicon compound are the same as in the first embodiment, but may be other embodiments or modifications described above. Further, in the case of the sixth embodiment described later, it is also possible to apply the flexible substrate 502 in the case of the present embodiment.
  • FIG. 24A and 24B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • the substrate 1002 includes two layers of substrates 102 and 502.
  • the substrate (first substrate) 102 is, for example, a glass substrate.
  • the substrate (second substrate) 502 is provided on the first surface 102a of the substrate 102.
  • the substrate 502 is formed by applying polyimide on the first surface 102a and firing it.
  • an inorganic film such as SiN x may be formed on the first surface 102a.
  • the substrate 502 is formed by applying a polyimide material on an inorganic film and firing it.
  • a layer 507 containing a silicon compound is formed over the first surface 502a of the substrate 502.
  • the first surface 502a of the substrate 502 is a surface opposite to the surface on which the substrate 102 is provided.
  • the conductive layer 1130 is formed and patterned on the exposed surface of the layer 507 containing the silicon compound formed on the substrate 1002. Then, for example, by applying the steps described above in FIGS. 5B-7B, 9 and 10A-10D, the superstructure of the subpixel 520 is formed.
  • the removal of the substrate 102 is not limited to the above-mentioned time point, but can be performed at an appropriate time point.
  • the substrate 102 is preferably removed after the step of forming the wiring layer 110 is completed. By removing the substrate 102 at an appropriate time, it may be possible to reduce defects such as cracks and chips in the manufacturing process.
  • the effect of the image display device of this embodiment will be described.
  • the image display device of this embodiment has the following effects in addition to the effects of the other embodiments described above. That is, since the substrate 502 has flexibility, it can be bent as an image display device, and can be attached to a curved surface, used for a wearable terminal, or the like without any discomfort.
  • FIG. 25 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • a plurality of light emitting surfaces 653S1 and 653S2 on a single semiconductor layer 650 including a light emitting layer, an image display device having higher luminous efficiency is realized.
  • the same components as in the case of the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the conductive layer 130 and the connection plate 630a are connected to, for example, the ground wire 4 of the circuit of FIG.
  • the transistors 203-1 and 203-2 of the p-channel electrons are injected from one of the semiconductor layers 650 via the conductive layer 130 and the connection plate 130a.
  • the transistors 203-1 and 203-2 of the p-channel holes are injected from the other side of the semiconductor layer 650 via the wiring layer 110. Holes and electrons are injected into the semiconductor layer 650, and the light emitting layer 652 is made to emit light by the combination of holes and electrons.
  • the conductive layer 130 is provided on the first surface 102a.
  • the conductive layer 130 includes a connection plate 630a.
  • the semiconductor layer 650 is provided on the first surface 102a via the connection plate 630a.
  • the semiconductor layer 650 has a bottom surface 651B, and the connection plate 630a is connected to the bottom surface 651B.
  • the outer circumference of the connection plate 630a is set to include the outer circumference of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a in XY plan view. That is, in the XY plan view, the outer circumference of the semiconductor layer 650 is arranged within the outer circumference of the connection plate 630a.
  • connection plate 630a Since the conductive layer 130 and the connection plate 630a are made of a metal material such as Cu or Hf, they have light reflectivity. Therefore, the connection plate 630a reflects the downward scattered light of the semiconductor layer 650 toward the upper light emitting surfaces 653S1 and 653S2. Therefore, the substantial luminous efficiency of the semiconductor layer 650 is improved.
  • the semiconductor layer 650 includes a plurality of light emitting surfaces 653S1 and 653S2.
  • the semiconductor layer 650 is a prismatic or columnar laminate having a bottom surface 651B connected to the connection plate 630a.
  • the light emitting surfaces 653S1 and 653S2 are surfaces on the opposite side of the bottom surface 651B.
  • the light emitting surfaces 653S1 and 653S2 are preferably planes in a plane substantially parallel to the bottom surface 651B.
  • the plane including the light emitting surface 653S1 and the plane including the light emitting surface 653S2 may be the same plane or different planes.
  • the light emitting surfaces 653S1 and 653S2 are provided apart from each other in the X-axis direction.
  • the semiconductor layer 650 includes an n-type semiconductor layer 651, a light emitting layer 652, and a p-type semiconductor layer 653.
  • the n-type semiconductor layer 651, the light emitting layer 652, and the p-type semiconductor layer 653 are laminated in this order from the bottom surface 651B toward the light emitting surfaces 653S1 and 653S2.
  • the bottom surface 651B is an n-type semiconductor, and the n-type semiconductor layer 651 is electrically connected to an external circuit connected via the bottom surface 651B and the connection plate 630a.
  • the external circuit is, for example, the ground wire 4 of the circuit of FIG.
  • the p-type semiconductor layer 653 has two light emitting surfaces 653S1 and 653S2 on the upper surface. That is, one subpixel group 620 contains substantially two subpixels. In this embodiment, as in the case of the other embodiments described above, the display area is formed by arranging the subpixel group 620 including substantially two subpixels in a grid pattern.
  • the first interlayer insulating film (first insulating film) 156 covers the first surface 102a, the conductive layer 130, the side surface of the n-type semiconductor layer 651, the side surface of the light emitting layer 652, and the side surface of the p-type semiconductor layer 653.
  • the first interlayer insulating film 156 covers a part of the upper surface of the p-type semiconductor layer 653. Of the p-type semiconductor layer 653, the light emitting surfaces 653S1 and 653S2 are not covered with the first interlayer insulating film 156.
  • the first interlayer insulating film 156 is preferably a white resin, as in the case of the other embodiments described above.
  • the TFT lower layer film 106 is formed over the first interlayer insulating film 156.
  • the TFT underlayer film 106 is not provided on the light emitting surfaces 653S1 and 653S2.
  • the TFT underlayer film 106 is flattened, and TFT channels 204-1, 204-2 and the like are formed on the TFT underlayer film 106.
  • the insulating layer 105 covers the TFT underlayer film 106 and the TFT channels 204-1 and 204-2.
  • the gate 107-1 is provided on the TFT channel 204-1 via the insulating layer 105.
  • the gate 107-2 is provided on the TFT channel 204-2 via the insulating layer 105.
  • Transistor 203-1 includes a TFT channel 204-1 and a gate 107-1.
  • Transistor 203-2 includes TFT channel 204-2 and gate 107-2.
  • the TFT channels 204-1 and 204-2 include a p-shaped doped region, and the transistors 203-1 and 203-2 are p-channel TFTs.
  • the transistor 203-1 is provided at a position closer to the light emitting surface 653S1 than the light emitting surface 653S2.
  • the transistor 203-2 is provided at a position closer to the light emitting surface 653S2 than the light emitting surface 653S1.
  • the light emitting surfaces 653S1 and 653S2 pass through openings 658-1 and 658-2 formed by removing a part of each of the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106 and the first interlayer insulating film 156. Is exposed.
  • the openings 658-1 and 658-2 are filled with the surface resin layer 170.
  • the light emitting surfaces 653S1 and 653S2 are squares, rectangles, other polygons, circles, etc. in XY plan view.
  • the shape of the uppermost portion of the openings 658-1 and 658-2 can also be a square, a rectangle, another polygon, a circle, or the like.
  • the openings 658-1 and 658-2 have an area that increases upward, for example, for the purpose of reducing light reflection on the wall surface of the openings 658-1 and 658-2 and causing loss. As described above, it is preferable that the shape is tapered.
  • the shapes of the light emitting surfaces 653S1 and 653S2 and the shapes of the uppermost portions of the openings 658-1 and 658-2 may or may not be similar.
  • the wiring layer 110 is provided on the second interlayer insulating film 108.
  • the wiring layer 110 includes wirings 610s1,610d1,610d2,610s2.
  • the wirings 610s1 and 610s2 are connected to, for example, the power line 3 of the circuit shown in FIG.
  • the translucent electrode 659d1 is provided over the wiring 610d1 together with the light emitting surface 653S1.
  • the translucent electrode 659d1 is also provided between the light emitting surface 653S1 and the wiring 610d1, and electrically connects the light emitting surface 653S1 and the wiring 610d1.
  • the translucent electrode 659s1 is provided over the wiring 610s1. Therefore, the p-type semiconductor layer 653 is electrically connected to the region corresponding to the drain electrode of the TFT channel 204-1 via the light emitting surface 653S1, the translucent electrode 659d1, the wiring 610d1, and the via 111d1.
  • the region corresponding to the source electrode of the TFT channel 204-1 is electrically connected to the power line 3 via the via 111s1, the wiring 610s1, and the translucent electrode 659s1.
  • the translucent electrode 659d2 is provided on the light emitting surface 653S2 and over the wiring 610d2.
  • the translucent electrode 659d2 is also provided between the light emitting surface 653S2 and the wiring 610d2, and electrically connects the light emitting surface 653S2 and the wiring 610d2.
  • the translucent electrode 659s2 is provided over the wiring 610s2. Therefore, the p-type semiconductor layer 653 is electrically connected to the region corresponding to the drain electrode of the TFT channel 204-2 via the light emitting surface 653S2, the translucent electrode 659d2, the wiring 610d2 and the via 111d2.
  • the region corresponding to the source electrode of the TFT channel 204-2 is electrically connected to the power line 3 via the via 111s2, the wiring 610s2 and the translucent electrode 659s2.
  • the drift current flowing in the direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 651 and the p-type semiconductor layer 653. Therefore, the holes injected from the light emitting surfaces 653S1 and 653S2 and the electrons injected from the connection plate 630a both proceed along the stacking direction of the semiconductor layer 650. Since the light emitting surfaces 653S1 and 653S2 rarely serve as a light emitting source on the outside, the transistors 203-1 and 203-2 selectively select a plurality of light emitting surfaces 653S1 and 653S2 provided on one semiconductor layer 650. Can be made to emit light.
  • the light emitting source in the semiconductor layer 650 is almost determined by the arrangement of the light emitting surfaces 653S1 and 653S2.
  • 26A to 28B are schematic cross-sectional views illustrating the method for manufacturing the image display device of the present embodiment.
  • a patterned conductive layer is formed on the first surface 102a, and the formed conductive layer is single-crystallized to form the conductive layer 1130a. It can be the same as the embodiment. It is assumed that the process of FIG. 26A is applied after the conductive layer 1130a is formed on the first surface 102a in the process of FIG. 5A.
  • the semiconductor layer 1150 shown in FIG. 26A is formed into a semiconductor layer 650 having a desired shape by using a dry etching technique such as RIE.
  • the desired shape is, for example, a square or a rectangle, or another polygon, a circle, or the like in an XY plan view.
  • the conductive layer 1130a is formed by etching or the like to form the conductive layer 130 including the connection plate 630a.
  • the outer circumference of the connection plate 630a is set to include the outer circumference of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a in XY plan view. That is, in the XY plan view, the outer circumference of the semiconductor layer 650 is arranged within the outer circumference of the connection plate 630a.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 102a, the conductive layer 130, and the semiconductor layer 650.
  • via holes 112d1, 112s1 that penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the TFT channel 204-1 are formed.
  • Via holes 112d2 and 112s2 that penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the TFT channel 204-2 are formed.
  • a part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower layer film 106, and a part of the first interlayer insulating film 156 are removed to form an opening 658-1 reaching the light emitting surface 653S1.
  • the light emitting surfaces 653S1 and 653S2 are each roughened. After that, a translucent conductive film is provided so as to cover the wiring layer 110, and translucent electrodes 659d1, 659s1, 659d2, 659s2 are formed.
  • the translucent electrode 659d1 is formed so as to cover the light emitting surface 653S1 and electrically connects the light emitting surface 653S1 and the wiring 610d1.
  • the translucent electrode 659d2 is formed so as to cover the light emitting surface 653S2, and electrically connects the light emitting surface 653S2 and the wiring 610d2.
  • a subpixel group 620 having a semiconductor layer 650 having two light emitting surfaces 653S1 and 653S2 is formed.
  • two light emitting surfaces 653S1 and 653S2 are provided on one semiconductor layer 650, but the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are one semiconductor. It can also be provided on the layer 650. As an example, one row or two rows of subpixels may be realized by a single semiconductor layer 650. As a result, as will be described later, it is possible to reduce the recombination current that does not contribute to light emission per light emitting surface and to increase the effect of realizing a finer light emitting element.
  • FIG. 29 is a schematic cross-sectional view illustrating a part of the image display device according to the modified example of the present embodiment.
  • This modification is different from the case of the sixth embodiment described above in that two p-type semiconductor layers 6653a1 and 6653a2 are provided on the light emitting layer 652.
  • the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • the image display device of this modification includes a sub-pixel group 620a.
  • the subpixel group 620a includes a semiconductor layer 650a.
  • the semiconductor layer 650a includes an n-type semiconductor layer 651, a light emitting layer 652, and p-type semiconductor layers 6653a1,6653a2.
  • the light emitting layer 652 is laminated on the n-type semiconductor layer 651.
  • the p-type semiconductor layers 6653a1 and 6653a2 are both laminated on the light emitting layer 652.
  • the p-type semiconductor layers 6653a1 and 6653a2 are formed in an island shape on the light emitting layer 652, and in this example, they are arranged apart from each other along the X-axis direction.
  • a first interlayer insulating film 156 is provided between the p-type semiconductor layers 6653a1 and 6653a2, and the p-type semiconductor layers 6653a1 and 6653a2 are separated by a first interlayer insulating film 156.
  • the p-type semiconductor layers 6653a1 and 6653a2 have substantially the same shape in XY plan view, and the shape is substantially square or rectangular, and is another polygonal shape, a circle, or the like. May be good.
  • the light emitting surface 6653S2 is exposed through an opening 658-2 formed by removing a part of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. There is.
  • the exposed light emitting surface 6653S2 is a surface of the p-type semiconductor layer 6653a2.
  • the shape of the light emitting surface 6653S1 and 6653S2 in the XY plan view has substantially the same shape as the shape of the light emitting surface in the case of the sixth embodiment, and has a shape such as a square.
  • the shapes of the light emitting surfaces 6653S1 and 6653S2 are not limited to the square shape as in the present embodiment, but may be a polygon such as a circle, an ellipse, or a hexagon.
  • the shapes of the light emitting surfaces 6653S1 and 6653S2 may be similar to or different from the shapes of the openings 658-1 and 658-2.
  • the translucent electrode 659d1 is provided over the light emitting surface 6653S1 and is provided over the wiring 610d1.
  • the translucent electrode 659d1 is provided between the light emitting surface 6653S1 and the wiring 610d1, and electrically connects the light emitting surface 6653S1 and the wiring 610d1.
  • the translucent electrode 659d2 is provided over the light emitting surface 6653S2 and is provided over the wiring 610d2.
  • the translucent electrode 659d2 is provided between the light emitting surface 6653S2 and the wiring 610d2, and electrically connects the light emitting surface 6653S2 and the wiring 610d2.
  • FIG. 30A to 31B are schematic cross-sectional views illustrating a method for manufacturing an image display device of this modification.
  • the steps up to the step shown in FIG. 26A are the same as those in the sixth embodiment, and the steps after FIG. 30A are applied after the steps shown in FIG. 26A.
  • the semiconductor layer 1150 shown in FIG. 26A is etched to form the light emitting layer 652 and the n-type semiconductor layer 651. Further etching is performed to form two p-type semiconductor layers 6653a1 and 6653a2.
  • the etching for forming the p-type semiconductor layers 6653a1 and 6653a2 may be performed beyond the depth reaching the light emitting layer 652 and the n-type semiconductor layer 651.
  • the p-type semiconductor layer is formed by deep etching as described above, it is desirable to etch the outside of the light emitting surfaces 6653S1 and 6653S2 shown in FIG. 25 by 1 ⁇ m or more.
  • the conductive layer 1130a shown in FIG. 26A is etched to form the conductive layer 130 including the connection plate 630a.
  • the conductive layer 1130a may be etched together with the semiconductor layer 1150 to form the connection plate 630a, and then the semiconductor layer 650 may be formed, as in the case of the other embodiments described above.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 102a, the conductive layer 130, and the semiconductor layer 650a.
  • the wiring layer 110 including the wiring 610d1,610s1,610d2,610s2 is formed as in the case of the sixth embodiment. After that, a translucent conductive film covering the wiring layer 110 is formed. The translucent conductive film is formed on the translucent electrodes 659d1, 659s1, 659d2, 659s2.
  • the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are provided on one semiconductor layer 650a. May be good.
  • FIG. 32 is a graph illustrating the characteristics of the pixel LED element.
  • the vertical axis of FIG. 32 represents the luminous efficiency [%] of the pixel LED element.
  • the horizontal axis represents the current density of the current flowing through the pixel LED element as a relative value.
  • the luminous efficiency of the pixel LED element increases substantially constant or monotonously.
  • the luminous efficiency decreases monotonically. That is, the pixel LED element has an appropriate current density that maximizes the luminous efficiency.
  • the light emitting device is formed by individually separating all the layers of the semiconductor layer 1150 including the light emitting layer by etching or the like. At this time, the joint surface between the light emitting layer and the p-shaped semiconductor layer is exposed at the end of the light emitting element. Similarly, the joint surface between the light emitting layer and the n-type semiconductor layer is exposed at the end.
  • the semiconductor layers 650 and 650a have four side surfaces, two light emitting surfaces and four ends.
  • the region between the openings 658-1 and 658-2 has few electrons and holes injected and hardly contributes to light emission, it can be considered that the number of ends contributing to light emission is six.
  • the number of end portions of the semiconductor layer is substantially reduced, so that recombination that does not contribute to light emission is reduced. By reducing the recombination that does not contribute to light emission, the drive current for each light emitting surface is reduced.
  • the sub-pixel group 620 of the sixth embodiment has a light emitting surface 653S1.
  • the distance between the light emitting surface and the light emitting surface 653S2 is substantially shortened.
  • the p-type semiconductor layer is shared as in the case of the sixth embodiment, a part of the holes injected into the driven light emitting surface is split and not driven.
  • the light emitting surface may emit a small amount of light.
  • the p-type semiconductor layer is separated into two, and each p-type semiconductor layer has a light emitting surface, so that a slight light emission is generated on the light emitting surface on the undriven side. It can be reduced.
  • the semiconductor layer including the light emitting layer is formed by crystal growth from the n-type semiconductor layer on the connection plate 630a, which is preferable from the viewpoint of reducing the manufacturing cost.
  • the stacking order of the n-type semiconductor layer and the p-type semiconductor layer is changed, and the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer are laminated in this order from the side of the connection plate 630a. It may be done as described above.
  • connection plate 630a for wiring, the semiconductor layer below the semiconductor layers 650 and 650a is electrically connected to the external circuit regardless of the via for each light emitting surface. Can be done. Therefore, it is not necessary to secure a region for via connection on the connection plate 630a, which enables high-density arrangement of circuit elements. In addition, since the wiring lead-out structure for connecting to the external wiring is simplified, the yield is expected to be improved.
  • the image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.
  • FIG. 33 is a block diagram illustrating an image display device according to the present embodiment.
  • FIG. 33 shows the main parts of the configuration of a computer display.
  • the image display device 701 includes an image display module 702.
  • the image display module 702 is, for example, an image display device having the configuration of the first embodiment described above.
  • the image display module 702 includes a display area 2, a row selection circuit 5, and a signal voltage output circuit 7 in which a plurality of subpixels including the subpixel 20 are arranged.
  • the image display device 701 further includes a controller 770.
  • the controller 770 inputs a control signal separated and generated by an interface circuit (not shown) to control the drive and drive order of each subpixel to the row selection circuit 5 and the signal voltage output circuit 7.
  • FIG. 34 is a block diagram illustrating an image display device according to a modified example of the present embodiment.
  • FIG. 34 shows the configuration of a high-definition flat-screen television.
  • the image display device 801 includes an image display module 802.
  • the image display module 802 is, for example, an image display device 1 having the configuration of the first embodiment described above.
  • the image display device 801 includes a controller 870 and a frame memory 880.
  • the controller 870 controls the drive order of each subpixel in the display area 2 based on the control signal supplied by the bus 840.
  • the frame memory 880 stores display data for one frame and is used for processing such as smooth moving image reproduction.
  • the image display device 801 has a receiving unit 820 and a signal processing unit 830.
  • An antenna 822 is connected to the receiving unit 820, and a necessary signal is separated and generated from the radio wave received by the antenna 822.
  • the signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 820 is converted into image data, audio data, etc. by the signal processing unit 830. Separated and generated.
  • an image display device provided with an image display module having an appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.
  • the image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, but may be a modification thereof or the case of another embodiment. Further, it goes without saying that the image display module in the case of the present embodiment and the modified example has a configuration including a large number of sub-pixels as shown in FIG.
  • 1,201,701,801 image display device 2 display area, 3 power supply line, 4 ground line, 5,205 line selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8,208 signal line, 10 pixels, 20, 20a, 220, 320, 420,520 subpixels, 22,222 light emitting elements, 24,224 selection transistors, 26,226 drive transistors, 28,228 capacitors, 101 circuits, 102,502 boards, 102ath 1st surface, 103,203,203-1,203-2 transistor, 104,204,204-1,204-2 TFT channel, 105 insulation layer, 107,107-1,107-2 gate, 108 second interlayer insulation Film, 110 wiring layer, 110a, 110d, 410d, 410k wiring, 130 conductive layer, 130a, 630a connection plate, 140 graphene layer, 140a graphene sheet, 150,250 light emitting element, 151S, 253S, 653S1,653S2,6653S1,6653S2 Light emitting surface, 153B, 251B, 6

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