WO2022100408A1 - 一种多层外延减压生长方法 - Google Patents

一种多层外延减压生长方法 Download PDF

Info

Publication number
WO2022100408A1
WO2022100408A1 PCT/CN2021/125608 CN2021125608W WO2022100408A1 WO 2022100408 A1 WO2022100408 A1 WO 2022100408A1 CN 2021125608 W CN2021125608 W CN 2021125608W WO 2022100408 A1 WO2022100408 A1 WO 2022100408A1
Authority
WO
WIPO (PCT)
Prior art keywords
reaction chamber
power device
epitaxy
manufacturing
wafer
Prior art date
Application number
PCT/CN2021/125608
Other languages
English (en)
French (fr)
Inventor
侯龙
Original Assignee
重庆万国半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆万国半导体科技有限公司 filed Critical 重庆万国半导体科技有限公司
Publication of WO2022100408A1 publication Critical patent/WO2022100408A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like

Definitions

  • the invention relates to the technical field of epitaxial growth of super junction power devices, in particular to a multi-layer epitaxial decompression growth method.
  • the epitaxial growth of super junction power devices is different from the epitaxial growth of ordinary power devices, and multi-layer epitaxy needs to be grown (generally more than eight layers are required).
  • Multi-layer epitaxy has higher requirements for pattern distortion, pattern drift, slip line and wafer curvature radius, especially for 12-inch silicon wafers due to their larger size
  • the sheet is more easily deformed, which puts forward higher and more stringent requirements for equipment and processes.
  • the purpose of the present invention is to provide a multi-layer epitaxial decompression growth method.
  • a multi-layer epitaxy decompression growth method comprising the steps:
  • the step A specifically includes the following steps:
  • Step S1 heating the reaction chamber of the decompression epitaxy growth equipment to 1150-1190° C., and pouring high-purity HCL gas into the reaction chamber to clean the chamber and the residual deposition layer on the carrier base to remove impurities inside the reaction chamber , the base speed is 25 rpm;
  • step S2 high-purity H 2 is introduced into the reaction chamber while the temperature in the reaction chamber is lowered to 700-900° C., and the rotation speed of the base is reduced to 0.
  • the flow rate of the high-purity H 2 is 50-90 L/min.
  • the step B specifically includes the following steps:
  • Step S3 loading the single crystal silicon wafer on the wafer carrier base, and increasing the base rotation speed to 35 rpm;
  • the size of the single crystal silicon wafer is 12 inches;
  • Step S4 reducing the pressure in the reaction chamber from atmospheric pressure to 30-130 Torr, while heating the reaction chamber to 1000-1150 °C, and the flow rate of the carrier gas high-purity H 2 is 40-80 L/min;
  • Step S5 pre-flow DCS gas, and then pass the DCS gas into the reaction chamber to grow epitaxy to obtain a wafer;
  • the DCS gas pre-flow time is greater than or equal to at least 20s, and the growth rate of epitaxy is 0.5-2.0um/min;
  • step S6 the vacuuming of the reaction chamber is stopped, the pressure in the reaction chamber is returned to atmospheric pressure, and the temperature of the reaction chamber is lowered to below 900°C, and the epitaxial wafer is taken out.
  • the heating rate of the reaction chamber in step S4 is 2-8°C/sec.
  • the pressure in the reaction chamber is reduced from atmospheric pressure to 50-100 Torr, and at the same time, the temperature of the reaction chamber is raised to 1050-1130°C.
  • the pressure in the reaction chamber is reduced from atmospheric pressure to 75 Torr, while the temperature of the reaction chamber is raised to 1110°C.
  • the step C specifically includes the following steps:
  • Step S7 after each step A and B, it is necessary to implant the N-type and P-type that need to be doped into the epitaxial pattern sheet in the design area; and remove and clean the photoresist, oxide layer and other impurities introduced by photolithography and ion implantation ;
  • Step S8 repeating steps A and B for 3 to 5 times, patterning the epitaxial wafer by photolithography and etching; and removing and cleaning the photoresist, oxide layer introduced by photolithography, etching or ion implantation and other impurities.
  • the depth of the pattern is 0.8-1.5um.
  • the present invention has the following beneficial effects:
  • the decompression epitaxy process takes less time than the existing ordinary epitaxy process, and the equipment capacity is increased by about 31.1%;
  • FIG. 1 is a schematic structural diagram of the integration of a trench power device and a source capacitor according to Embodiment 1 of the present invention
  • FIG. 2 is a comparison diagram of the curvature radius of a trench power device and a source capacitor integrated in Embodiment 1 of the present invention and a trench power device and a source capacitor integrated by a common process.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • step S1 the temperature of the reaction chamber of the decompression epitaxy growth equipment is increased to 1150°C, and high-purity HCL gas is introduced into the reaction chamber to clean the chamber and the residual deposition layer on the carrier base, and remove impurities inside the reaction chamber.
  • the base speed is 25 rpm.
  • step S2 high-purity H 2 is introduced into the reaction chamber to purge the residual HCl gas and reaction products in the reaction chamber, and at the same time, the temperature in the reaction chamber is lowered to 700° C., and the rotation speed of the base is reduced to 0 ;
  • the flow rate is 50L/min.
  • Step S3 load the 12-inch single-crystal silicon wafer on the wafer carrier base, and increase the rotation speed of the base to 35 rpm.
  • Step S4 reducing the pressure in the reaction chamber from atmospheric pressure to 30 Torr, while heating the reaction chamber to 1150° C., the heating rate is 8° C./sec, and the flow rate of the carrier gas high-purity H 2 is 40 L/min.
  • Step S5 pre-flow DCS gas for at least 20 seconds, and then pass the DCS gas into the reaction chamber to grow the first layer of intrinsic epitaxy, and the growth rate is 0.5-2.0 um/min.
  • Step S6 after the growth of the epitaxial layer is completed, the vacuuming of the reaction chamber is stopped, the pressure in the reaction chamber is returned to atmospheric pressure, and the temperature of the reaction chamber is lowered to below 900°C, and the epitaxial wafer is taken out.
  • Step S7 after repeating steps S1 to S6 3 times, after each step A and B, the N-type and P-type that need to be doped are implanted in the epitaxial pattern sheet in the design area; and the light introduced by photolithography and ion implantation is removed and cleaned. Resist, oxide layers and other impurities.
  • step S8 the epitaxial wafer is subjected to photolithography and pattern etching, and the pattern depth is 0.8um; the photoresist, oxide layer and other impurities introduced by photolithography, etching or ion implantation are removed and cleaned.
  • Steps S1 to S6 are repeated to perform the second layer epitaxy.
  • the decompression epitaxy process reduces the time by 10.6% compared with the normal pressure epitaxy process, and the equipment capacity is increased by about 30.2%. As shown in Figure 1, the decompression epitaxy process is better in maintaining the shape of the pattern, which can reduce the number of super junction power devices. For the lithography process, as shown in Figure 2, the low-temperature decompression epitaxy process improves the warpage of the wafer, which is more conducive to the subsequent process.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • step S1 the temperature of the reaction chamber of the decompression epitaxy growth equipment is raised to 1175 °C, and high-purity HCL gas is introduced into the reaction chamber to clean the chamber and the residual deposition layer on the carrier base, and remove impurities inside the reaction chamber.
  • the base speed is 25 rpm.
  • step S2 high-purity H 2 is introduced into the reaction chamber to purge the residual HCl gas and reaction products in the reaction chamber, and at the same time, the temperature in the reaction chamber is lowered to 800° C., and the rotation speed of the base is reduced to 0 ;
  • the flow rate is 75L/min.
  • Step S3 load the 12-inch single-crystal silicon wafer on the wafer carrier base, and increase the rotation speed of the base to 35 rpm.
  • Step S4 reducing the pressure in the reaction chamber from atmospheric pressure to 80 Torr, while heating the reaction chamber to 1100° C., the heating rate is 5° C./sec, and the flow rate of the carrier gas high-purity H 2 is 60 L/min.
  • Step S5 pre-flow DCS gas for at least 20 seconds, and then pass the DCS gas into the reaction chamber to grow the first layer of intrinsic epitaxy, and the growth rate is 0.5-2.0 um/min.
  • Step S6 after the growth of the epitaxial layer is completed, the vacuuming of the reaction chamber is stopped, the pressure in the reaction chamber is returned to atmospheric pressure, and the temperature of the reaction chamber is lowered to below 900°C, and the epitaxial wafer is taken out.
  • Step S7 after repeating steps S1 to S6 4 times, after each step A and B, the N-type and P-type that need to be doped are implanted in the epitaxial pattern sheet in the design area; and the light introduced by photolithography and ion implantation is removed and cleaned. Resist, oxide layers and other impurities.
  • step S8 the epitaxial wafer is subjected to photolithography and pattern etching, and the pattern depth is 1.1um; the photoresist, oxide layer and other impurities introduced by photolithography, etching or ion implantation are removed and cleaned.
  • Steps S1 to S6 are repeated to perform the second layer epitaxy.
  • the decompression epitaxy process reduces the time by 12.8% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 31.1%.
  • the decompression epitaxy process is better in maintaining the shape of the pattern, which can reduce the two lithography processes of super junction power devices.
  • the epitaxial low temperature process improves the warpage of the wafer, which is more conducive to the subsequent process.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • step S1 the temperature of the reaction chamber of the decompression epitaxy growth equipment is increased to 1190°C, and high-purity HCL gas is introduced into the reaction chamber to clean the chamber and the residual deposition layer on the carrier base, and remove impurities inside the reaction chamber.
  • the base speed is 25 rpm.
  • step S2 high-purity H 2 is introduced into the reaction chamber to purge the residual HCl gas and reaction products in the reaction chamber, and at the same time, the temperature in the reaction chamber is lowered to 900° C., and the rotation speed of the base is reduced to 0 ;
  • the flow rate is 90L/min.
  • Step S3 load the 12-inch single-crystal silicon wafer on the wafer carrier base, and increase the rotation speed of the base to 35 rpm.
  • Step S4 reducing the pressure in the reaction chamber from atmospheric pressure to 130 Torr, and simultaneously heating the reaction chamber to 1000° C., the heating rate is 2° C./sec, and the flow rate of the carrier gas high-purity H 2 is 80 L/min.
  • Step S5 pre-flow DCS gas for at least 20 seconds, and then pass the DCS gas into the reaction chamber to grow the first layer of intrinsic epitaxy, and the growth rate is 0.5-2.0 um/min.
  • Step S6 after the growth of the epitaxial layer is completed, the vacuuming of the reaction chamber is stopped, the pressure in the reaction chamber is returned to atmospheric pressure, and the temperature of the reaction chamber is lowered to below 900°C, and the epitaxial wafer is taken out.
  • Step S7 after repeating steps S1 to S6 5 times, after each step A and B, the N-type and P-type that need to be doped are implanted in the epitaxial pattern sheet in the design area; and the light introduced by photolithography and ion implantation is removed and cleaned. Resist, oxide layers and other impurities.
  • step S8 the epitaxial wafer is subjected to photolithography and pattern etching, and the pattern depth is 1.5um; the photoresist, oxide layer and other impurities introduced by photolithography, etching or ion implantation are removed and cleaned.
  • Steps S1 to S6 are repeated to perform the second layer epitaxy.
  • the decompression epitaxy process reduces the time by 11.0% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 30.5%.
  • the epitaxial low temperature process improves the warpage of the wafer, which is more conducive to the subsequent process.
  • a trench power device integrated with a source capacitor and a manufacturing method thereof are different from Embodiment 2 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 50 Torr in step S4, and the temperature of the reaction chamber is raised to 1130°C.
  • the final decompression epitaxy process reduces the time by 11.5% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 30.1%.
  • the lithography process and the decompression epitaxy low temperature process improve the warpage of the wafer, which is more conducive to the subsequent process.
  • the warpage of the wafer is improved, which is more conducive to the subsequent process.
  • the final decompression epitaxy process is 12.1% shorter than the ordinary epitaxy process time, and the equipment capacity is increased by about 31.0%.
  • the lithography process and the decompression epitaxy low temperature process improve the warpage of the wafer, which is more conducive to the subsequent process.
  • the warpage of the wafer is improved, which is more conducive to the subsequent process.
  • a trench power device integrated with a source capacitor and a manufacturing method thereof differs from Embodiment 2 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 75 Torr in step S4, and the temperature of the reaction chamber is raised to 1110°C.
  • the final decompression epitaxy process is 13.7% shorter than the ordinary epitaxy process time, and the equipment capacity is increased by about 32.9%.
  • the lithography process and the decompression epitaxy low temperature process improve the warpage of the wafer, which is more conducive to the subsequent process.
  • An integration of a trench power device and a source capacitor and a manufacturing method thereof differs from Embodiment 1 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 25 Torr in step S4, and the temperature of the reaction chamber is raised to 1150°C.
  • the other operation steps are basically the same, and the technical effect is that the time of the decompression epitaxy process is reduced by 5.2% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 18.2%.
  • a trench power device integrated with a source capacitor and a manufacturing method thereof differs from Embodiment 1 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 30 Torr in step S4, and the temperature of the reaction chamber is raised to 1200°C.
  • the other operation steps are basically the same, and the technical effect: the reduced pressure epitaxy process time is reduced by 4.6% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 17.2%.
  • An integration of a trench power device and a source capacitor and a manufacturing method thereof differs from Embodiment 3 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 140 Torr in step S4, while the temperature of the reaction chamber is raised to 1000°C.
  • the other operation steps are basically the same, and the technical effect: the reduced pressure epitaxy process time is reduced by 4.7% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 21.9%
  • An integration of a trench power device and a source capacitor and a manufacturing method thereof differs from Embodiment 3 in that the pressure in the reaction chamber is reduced from atmospheric pressure to 130 Torr in step S4, while the temperature of the reaction chamber is raised to 950°C.
  • the other operation steps are basically the same, and the technical effect: the reduced pressure epitaxy process time is reduced by 6.1% compared with the ordinary epitaxy process, and the equipment capacity is increased by about 20.9%

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本发明公开了多层外延减压生长方法，涉及超级结型功率器件外延生长技术领域，包括如下步骤：A、减压外延生长设备的反应腔前处理；B、外延减压生长步骤；C、每重复步骤A、B 3～5次后进行一次图形刻蚀步骤；D、图形刻蚀的后处理。减压外延工艺比普通外延工艺时间减少10％以上，设备产能提升可达30％以上，本申请所指减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，本申请所指减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。

Description

一种多层外延减压生长方法 技术领域
本发明涉及超级结型功率器件外延生长技术领域，尤其涉及一种多层外延减压生长方法。
背景技术
超级结型功率器件外延生长与普通功率器件外延生长不同，需要生长多层外延(一般都要求在八层以上)。多层外延对外延的图形畸变、图形漂移、滑移线(Slip line)以及晶圆曲率半径都有更高的要求，尤其是12寸硅片由于其尺寸的变大，导致其比小尺寸硅片更易变形，这就对设备和工艺都提出了更高更严苛的要求。
产品开发初期因为常压工艺高成长速率的特性，一般采用的是常压外延，但由于现有常压(AP)外延设备在多层外延超级结产品应用中多层外延需要图形对准，容易产生图形畸变、图形漂移性能差；而如果为解决优化图形畸变和漂移的问题，根据常压外延工艺的特性，只能提高外延工艺的温度，又会导致整个12寸硅片的变形、滑移线的问题变得很突出，并且，为了改善硅片变形、滑移线的问题，需要更平缓的温度变化过程，这又会导致每片wafer的工艺时间变长；无论是单杂质注入还是双杂质注入的多次外延超结工艺，外延导致的图形畸变、图形漂移会对后续光刻对准工艺提出极大挑战，如果对准差别台大会导致掺杂不平衡而影响产品良率。
发明内容
为解决现有技术中的缺陷，本发明的目的在于提供一种多层外延减压生长方法。
本发明的目的是通过以下技术方案实现的：一种多层外延减压生长方法，包括如下步骤：
A、减压外延生长设备的反应腔前处理；
B、外延减压生长步骤；
C、每重复步骤A、B 3～5次后进行一次图形刻蚀步骤；
D、图形刻蚀的后处理。
优选地，所述步骤A具体包括如下步骤：
步骤S1、将减压外延生长设备的反应腔升温至1150～1190℃，向反应腔体内通入高纯HCL气体清洁腔体以及载片基座上残余的沉积层，去除反应腔体内部的杂质，基座转速为25转/分钟；
步骤S2、向反应腔体内通入高纯H 2同时将反应腔体内的温度降温至700～900℃，基座转速降为0。
优选地，所述高纯H 2的流量为50～90L/min。
优选地，所述步骤B具体包括如下步骤：
步骤S3、将单晶硅片装载到载片基座上，将基座转速升至35转/分钟；
所述单晶硅片的尺寸为12寸；
步骤S4、将反应腔体内的压力从大气压降低至30～130Torr，同时将反应腔升温至1000～1150℃，载气高纯H 2的流量为40～80L/min；
步骤S5、预流DCS气体，然后将DCS气体通入反应腔生长外延得到晶圆；
所述DCS气体预流时间大于或等于至少20s，外延的生长速率为0.5～2.0um/min；
步骤S6、停止对反应腔体抽真空，使反应腔体内的压强回到大气压，同时将反应腔降温至900℃以下，取出外延片。
优选地，步骤步骤S4反应腔升温的速度为2～8℃/秒。
优选地，所述步骤S4中反应腔体内的压力从大气压降低至50～100Torr，同时反应腔升温至1050～1130℃。
优选地，所述步骤S4中反应腔体内的压力从大气压降低至75Torr，同时反应腔升温至1110℃。
优选地，所述步骤C具体包括如下步骤：
步骤S7、每次步骤A、B后需要在外延图形片在设计区域注入需要掺杂的N型及P型；并去除并清洗光刻和离子注入所引入的光刻胶，氧化层及其他杂质；
步骤S8、重复步骤A、B 3～5次后将生长完外延的晶圆通过光刻和刻蚀做图形；并去除并清洗光刻、刻蚀或离子注入所引入的光刻胶，氧化层及其他杂质。
优选地，所述图形的深度为0.8～1.5um。
综上所述，与现有技术相比，本发明具有如下的有益效果：
(1)减压外延工艺比现有普通外延工艺时间减少，设备产能提升约31.1％；
(2)减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺；
(3)减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明实施例1一种沟槽功率器件与源极电容集成的结构示意图；
图2为本发明实施例1一种沟槽功率器件与源极电容集成与普通工艺得到的沟槽功率器件与源极电容集成的曲率半径对比图。
具体实施方式
以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进，这些都属于本发明的保护范围。在本文中所披露的范围的端点和任何值都不限于该精确的范围或值，这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说，各个范围的端点值之间、各个范围的端点值和单独的点值之间，以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围，这些数值范围应被视为在本文中具体公开，下面结合具体实施例对本发明进行详细说明：
实施例1
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、将减压外延生长设备的反应腔升温至1150℃，向反应腔体内通入高纯HCL气体清洁腔体以及载片基座上残余的沉积层，去除反应腔体内部的杂质，此时基座转速为25转/分钟。
步骤S2、向反应腔体内通入高纯H 2吹扫反应腔体内残留的HCl气体及反应产物，同时将反应腔体内的温度降温至700℃，基座转速降为0；高纯H 2的流量为50L/min。
步骤S3、将12寸单晶硅片装载到载片基座上，将基座转速升至35转/分钟。
步骤S4、将反应腔体内的压力从大气压降低至30Torr，同时将反应腔升温至1150℃，升温速度为8℃/秒，载气高纯H 2的流量为40L/min。
步骤S5、预流DCS气体至少20秒钟，然后将DCS气体通入反应腔生长第一层本征外延，生长速率为0.5～2.0um/min。
步骤S6、外延层生长完成后，停止对反应腔体抽真空，使反应腔体内的压强回到大气压，同时将反应腔降温至900℃以下，取出外延片。
步骤S7、重复步骤S1～S6 3次后，每次步骤A、B后在外延图形片在设计区域注入需要掺杂的N型及P型；并去除并清洗光刻和离子注入所引入的光刻胶，氧化层及其他杂质。
步骤S8、将生长完外延的晶圆通过光刻和刻蚀图形，图形深度为0.8um；去除并清洗光刻，刻蚀或离子注入所引入的光刻胶，氧化层及其他杂质。
重复步骤S1～S6做第二层外延即可。
技术效果：减压外延工艺比常压外延工艺时间减少10.6％，设备产能提升约30.2％，如图1所示，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，如图2所示，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
实施例2
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、将减压外延生长设备的反应腔升温至1175℃，向反应腔体内通入高纯HCL气体清洁腔体以及载片基座上残余的沉积层，去除反应腔体内部的杂质，此时基座转速为25转/分钟。
步骤S2、向反应腔体内通入高纯H 2吹扫反应腔体内残留的HCl气体及反应产物，同时将反应腔体内的温度降温至800℃，基座转速降为0；高纯H 2的流量为75L/min。
步骤S3、将12寸单晶硅片装载到载片基座上，将基座转速升至35转/分钟。
步骤S4、将反应腔体内的压力从大气压降低至80Torr，同时将反应腔升温至1100℃，升温速度为5℃/秒，载气高纯H 2的流量为60L/min。
步骤S5、预流DCS气体至少20秒钟，然后将DCS气体通入反应腔生长第一层本征外延，生长速率为0.5～2.0um/min。
步骤S6、外延层生长完成后，停止对反应腔体抽真空，使反应腔体内的压强回到大气压，同时将反应腔降温至900℃以下，取出外延片。
步骤S7、重复步骤S1～S6 4次后，每次步骤A、B后在外延图形片在设计区域注入需要掺杂的N型及P型；并去除并清洗光刻和离子注入所引入的光刻胶，氧化层及其他杂质。
步骤S8、将生长完外延的晶圆通过光刻和刻蚀图形，图形深度为1.1um；去除并清洗光刻，刻蚀或离子注入所引入的光刻胶，氧化层及其他杂质。
重复步骤S1～S6做第二层外延。
技术效果：减压外延工艺比普通外延工艺时间减少12.8％，设备产能提升约31.1％，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
实施例3
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、将减压外延生长设备的反应腔升温至1190℃，向反应腔体内通入高纯HCL气体清洁腔体以及载片基座上残余的沉积层，去除反应腔体内部的杂质，此时基座转速为25转/分钟。
步骤S2、向反应腔体内通入高纯H 2吹扫反应腔体内残留的HCl气体及反应产物，同时将反应腔体内的温度降温至900℃，基座转速降为0；高纯H 2的流量为90L/min。
步骤S3、将12寸单晶硅片装载到载片基座上，将基座转速升至35转/分钟。
步骤S4、将反应腔体内的压力从大气压降低至130Torr，同时将反应腔升温至1000℃，升温速度为2℃/秒，载气高纯H 2的流量为80L/min。
步骤S5、预流DCS气体至少20秒钟，然后将DCS气体通入反应腔生长第一层本征外延，生长速率为0.5～2.0um/min。
步骤S6、外延层生长完成后，停止对反应腔体抽真空，使反应腔体内的压强回到大气压，同时将反应腔降温至900℃以下，取出外延片。
步骤S7、重复步骤S1～S6 5次后，每次步骤A、B后在外延图形片在设计区域注入需要掺杂的N型及P型；并去除并清洗光刻和离子注入所引入的光刻胶，氧化层及其他杂质。
步骤S8、将生长完外延的晶圆通过光刻和刻蚀图形，图形深度为1.5um；去除并清洗光刻，刻蚀或离子注入所引入的光刻胶，氧化层及其他杂质。
重复步骤S1～S6做第二层外延。
技术效果：减压外延工艺比普通外延工艺时间减少11.0％，设备产能提升约30.5％，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
实施例4
一种沟槽功率器件与源极电容集成及其制造方法，与实施例2的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至50Torr，同时反应腔升温至1130℃。
其他操作步骤基本相同，技术效果：最终减压外延工艺比普通外延工艺时间减少11.5％，设备产能提升约30.1％，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
使wafer的翘曲改善，更利于后续工艺。
实施例5
一种沟槽功率器件与源极电容集成及其制造方法，与实施例2的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至100Torr，同时反应腔升温至1050℃。
其他操作步骤基本相同，技术效果：最终减压外延工艺比普通外延工艺时间减少12.1％，设备产能提升约31.0％，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
使wafer的翘曲改善，更利于后续工艺。
实施例6
一种沟槽功率器件与源极电容集成及其制造方法，与实施例2的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至75Torr，同时反应腔升温至1110℃。
其他操作步骤基本相同，技术效果：最终减压外延工艺比普通外延工艺时间减少13.7％，设备产能提升约32.9％，减压外延工艺对图形的保形更好，可以减少超级结型功率器件两道光刻工艺，减压外延低温工艺使wafer的翘曲改善，更利于后续工艺。
对比例1
一种沟槽功率器件与源极电容集成及其制造方法，与实施例1的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至25Torr，同时反应腔升温至1150℃。
其他操作步骤基本相同，技术效果：减压外延工艺比普通外延工艺时间减少5.2％，设备产能提升约18.2％。
对比例2
一种沟槽功率器件与源极电容集成及其制造方法，与实施例1的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至30Torr，同时反应腔升温至1200℃。
其他操作步骤基本相同，技术效果：减压外延工艺比普通外延工艺时间减少4.6％，设备产能提升约17.2％。
对比例3
一种沟槽功率器件与源极电容集成及其制造方法，与实施例3的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至140Torr，同时反应腔升温至1000℃。
其他操作步骤基本相同，技术效果：减压外延工艺比普通外延工艺时间减少4.7％，设备产能提升约21.9％
对比例4
一种沟槽功率器件与源极电容集成及其制造方法，与实施例3的区别之处在于，所述步骤S4中反应腔体内的压力从大气压降低至130Torr，同时反应腔升温至950℃。
其他操作步骤基本相同，技术效果：减压外延工艺比普通外延工艺时间减少6.1％，设备产能提升约20.9％
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变化或修改，这并不影响本发明的实质内容。在不冲突的情况下，本申请的实施例和实施例中的特征可以任意相互组合。

Claims (9)

  1. 一种多层外延减压生长方法，其特征在于，包括如下步骤：
    A、减压外延生长设备的反应腔前处理；
    B、外延减压生长步骤；
    C、每重复步骤A、B 3～5次后进行一次图形刻蚀步骤；
    D、图形刻蚀的后处理。
  2. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤A具体包括如下步骤：
    步骤S1、将减压外延生长设备的反应腔升温至1150～1190℃，向反应腔体内通入高纯HCL气体，基座转速为25转/分钟；
    步骤S2、向反应腔体内通入高纯H 2同时将反应腔体内的温度降温至700～900℃，基座转速降为0。
  3. 根据权利要求2所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述高纯H 2的流量为50～90L/min。
  4. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤B具体包括如下步骤：
    步骤S3、将单晶硅片装载到载片基座上，将基座转速升至35转/分钟；
    所述单晶硅片的尺寸为12寸；
    步骤S4、将反应腔体内的压力从大气压降低至30～130Torr，同时将反应腔升温至1000～1150℃，载气高纯H 2的流量为40～80L/min；
    步骤S5、预流硅源气体，然后将硅源气体通入反应腔生长外延得到晶圆；
    所述硅源气体为DCS气体，所述硅源气体的预流时间大于或等于至少20s，外延的生长速率为0.5～2.0um/min；
    步骤S6、停止对反应腔体抽真空，使反应腔体内的压强回到大气压，同时将反应腔降温至900℃以下，取出外延片。
  5. 根据权利要求4所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S4中反应腔升温的速度为2～8℃/秒。
  6. 根据权利要求4所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S4中反应腔体内的压力从大气压降低至50～100Torr，同时反应腔升温至1050～1130℃。
  7. 根据权利要求6所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S4中反应腔体内的压力从大气压降低至75Torr，同时反应腔升温至1110℃。
  8. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤C具体包括如下步骤：
    步骤S7、每次步骤A、B后需要在外延图形片在设计区域注入需要掺杂的N型及P型；并去除并清洗光刻和离子注入所引入的光刻胶，氧化层及其他杂质；
    步骤S8、重复步骤A、B 3～5次后将生长完外延的晶圆通过光刻和刻蚀做图形；并去除并清洗光刻、刻蚀或离子注入所引入的光刻胶，氧化层及其他杂质。
  9. 根据权利要求8所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述图形的深度为0.8～1.5um。
PCT/CN2021/125608 2020-11-12 2021-10-22 一种多层外延减压生长方法 WO2022100408A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011264301.7 2020-11-12
CN202011264301.7A CN112382560A (zh) 2020-11-12 2020-11-12 一种多层外延减压生长方法

Publications (1)

Publication Number Publication Date
WO2022100408A1 true WO2022100408A1 (zh) 2022-05-19

Family

ID=74583581

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/125608 WO2022100408A1 (zh) 2020-11-12 2021-10-22 一种多层外延减压生长方法

Country Status (2)

Country Link
CN (1) CN112382560A (zh)
WO (1) WO2022100408A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112382560A (zh) * 2020-11-12 2021-02-19 重庆万国半导体科技有限公司 一种多层外延减压生长方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030068502A1 (en) * 1999-08-30 2003-04-10 Komatsu Denshi Kinzoku Kabushiki Kaisha Method of manufacturing epitaxial silicon wafer
CN102479805A (zh) * 2010-11-30 2012-05-30 比亚迪股份有限公司 一种超级结半导体元件及其制造方法
CN103811328A (zh) * 2014-03-05 2014-05-21 上海先进半导体制造股份有限公司 防止多层外延生长时背面形成多晶颗粒的方法及背封结构
CN103820849A (zh) * 2012-11-16 2014-05-28 有研半导体材料股份有限公司 一种减压生产12寸单晶硅外延片的工艺
CN108447772A (zh) * 2018-03-23 2018-08-24 南京国盛电子有限公司 一种coolmos用硅外延片的制造方法
CN110379704A (zh) * 2019-07-19 2019-10-25 中国电子科技集团公司第四十六研究所 一种高压功率器件用硅外延片的制备方法
CN112382560A (zh) * 2020-11-12 2021-02-19 重庆万国半导体科技有限公司 一种多层外延减压生长方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5533067B2 (ja) * 2010-03-15 2014-06-25 富士電機株式会社 超接合半導体装置の製造方法
CN109065612A (zh) * 2018-09-12 2018-12-21 深圳尚阳通科技有限公司 一种超级结mosfet结构及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030068502A1 (en) * 1999-08-30 2003-04-10 Komatsu Denshi Kinzoku Kabushiki Kaisha Method of manufacturing epitaxial silicon wafer
CN102479805A (zh) * 2010-11-30 2012-05-30 比亚迪股份有限公司 一种超级结半导体元件及其制造方法
CN103820849A (zh) * 2012-11-16 2014-05-28 有研半导体材料股份有限公司 一种减压生产12寸单晶硅外延片的工艺
CN103811328A (zh) * 2014-03-05 2014-05-21 上海先进半导体制造股份有限公司 防止多层外延生长时背面形成多晶颗粒的方法及背封结构
CN108447772A (zh) * 2018-03-23 2018-08-24 南京国盛电子有限公司 一种coolmos用硅外延片的制造方法
CN110379704A (zh) * 2019-07-19 2019-10-25 中国电子科技集团公司第四十六研究所 一种高压功率器件用硅外延片的制备方法
CN112382560A (zh) * 2020-11-12 2021-02-19 重庆万国半导体科技有限公司 一种多层外延减压生长方法

Also Published As

Publication number Publication date
CN112382560A (zh) 2021-02-19

Similar Documents

Publication Publication Date Title
WO2018120731A1 (zh) 硅外延片的制造方法
WO2022100408A1 (zh) 一种多层外延减压生长方法
KR101559977B1 (ko) 실리콘 에피텍셜 웨이퍼 및 그 제조방법
CN110767742A (zh) 晶圆背封结构、晶圆背封结构的制造方法
JP5664534B2 (ja) エピタキシャル炭化珪素ウエハの製造方法
JPWO2010035409A1 (ja) シリコンエピタキシャルウェーハの製造方法
JP2911694B2 (ja) 半導体基板及びその製造方法
JP7231120B2 (ja) エピタキシャルウェーハの製造方法
CN116646237A (zh) 一种背封硅片结构及其制备方法
CN113035688B (zh) 一种半导体结构及其制作方法
CN112038213B (zh) 一种SiC衬底双面生长SiC外延层的方法及应用
JP2019067887A (ja) 窒化珪素パッシベーション膜の成膜方法及び半導体装置の製造方法
US6344380B1 (en) Manufacturing of gate electrodes having silicon of different grain sizes and different surface roughness
CN115287752B (zh) 一种改善超重掺b硅外延片翘曲度的外延方法
CN113517173B (zh) 一种同质外延β-Ga2O3薄膜及其制备方法
KR20020028488A (ko) 에피층 성장 방법 및 이를 이용한 트랜지스터 제조 방법
JP2013191889A (ja) シリコンエピタキシャルウェーハ
KR100830997B1 (ko) 평탄도가 개선된 실리콘 에피택셜 웨이퍼 제조 방법
US20240158953A1 (en) Alpha gallium oxide thin-film structure having high conductivity obtained using selective area growth in hvpe growth manner and method for manufacturing the same
TW200910425A (en) Method for growing germanium film by pattern definition and high temperature cycle annealing process
JP2018006384A (ja) ＳｉＣエピタキシャルウェハの製造方法
JP2006080486A (ja) エピタキシャル膜の形成方法と、これを用いた薄膜形成方法、及び半導体装置の製造方法
JP2978318B2 (ja) エピタキシャル層の形成方法
KR20240110355A (ko) Soi기판층을 이용한 잔류응력이 감소된 단결정 다이아몬드 기판 및 이의 제조방법
WO2013023528A1 (zh) 一种电容及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21890935

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21890935

Country of ref document: EP

Kind code of ref document: A1