200910425 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種圖形定義與循環式高溫退火 r 處理成長鍺薄膜之方法，尤指一種利用超高真空化學 氣相磊晶法（UH V/C VD )，並結合圖形定義及循環式 高溫退火處理（Cycle Annealing )，可提供石夕基板上高 品質鍺蟲晶層（Ge Epitaxial Layers )沉積之方法。 【先前技術】 按，中華民國專利公告第200504883號及美國專 利公告第6723622B2號，其皆係採用漸進緩衝矽鍺層 (Graded Buffer Layers )之方法，其在成長鍺蠢晶層 之前，係必須成長多層漸進緩衝碎鍺層在一咬基板 上。然而，該法由於在製程中所需之步驟過多，將造 成生產量（Throughput )受限，因此並無法提高業界 對量產之需求。 另外，亦有文獻記載採用選擇性成長方法 (Selectively Epitaxial Growth )及多步驟生長方法 (Multi-step Growth )，其中，該選擇性成長方法係在 一含有圖形化非結晶形性氧化層之矽基板上，成長一 鍺磊晶層。然而，此法只能製造出部分品質較高之鍺 磊晶層，其餘大部分之鍺磊晶層則會在該非結晶形性 氧化層上方形成複晶形態，並且產生晶粒間隙，造成 鍺磊晶層品質劣化。 200910425 而該多步驟生長方法則係在成長錯蟲晶層之前， 必須多次成長漸進緩衝層於一石夕基板上。然而， /於製程所需時間過長’且含有不易控制製程條：等 問題’因此不僅產量受限，且亦不適用於產業作量產 用。 里座 T上所述纟於傳統之方法含有製程時間過長、 步驟過多、不諸料件及品f不佳等 此係無法提高產品之品質及生產量，故， = 係無法符合使用者於實際使用時之所需。 【發明内容】 树明之主要目的係在於’藉由圖形定義將差排 (Dlslocatlon)缺陷揭限化’並在 =理後，更可降低該_之差排缺陷二I: 進而提升該鍺遙晶層之品質，具有可降低 成本及簡化製程之優點。 本發明之次要目的係在於，可適用在石夕基板上鍺 ::及尚速鍺元件’或光電元件上之任何晶格不匹配 (Latt丨ce-mismatched)之磊晶系統上製作。 式古、之目的’本發明係—種圖形定義與循環 皿退火處理成長鍺薄膜之方法，係先利用一超高 二相蟲晶法在一石夕基板上沉積一石夕緩衝層及 夕t曰曰層’而後進行微影姓刻以在該石夕錯蟲晶層 疋義出所需之圖形，接著再於該石夕鍺蟲晶層上沉積 6 200910425 一鍺磊晶層，並進行一循環式高溫退火處理，以獲得 一將差排缺陷侷限於該矽鍺磊晶層側壁之結構。 【實施方式】 r 請參閱『第1圖〜第7圖』所示，係分別為本發 明之製作流程示意圖、本發明之超高真空化學氣相磊 晶結構示意圖、本發明之微影圖形結構示意圖、本發 明之蝕刻定義圖形結構示意圖、本發明之鍺磊晶層沉 積示意圖、本發明之循環式高溫退火處理示意圖及本 發明之差排缺陷侷限化結構示意圖。如圖所示：本發 明係一種圖形定義與循環式高溫退火處理成長鍺薄膜 之方法’其至少包括下列步驟： (A )超高真空化學氣相磊晶法（uhv/CVD ) 1 1 :如第2圖所示，選擇一矽基板2 1，且該矽基板 2 1係先經過溼式清潔，再以氟化氫（Hydr〇gen Fluoride，HF )溶液浸泡並高溫烘烤以去除表面自然形 成之氧化層，之後利用一超高真空化學氣相磊晶法， 於一特定操作條件下，在此清潔過後之矽基板2 1上 /儿積—石夕緩衝層（Buffer Layer) 2 2及一 0.08微米厚 度之石夕鍺磊晶層（Si〇.8Ge〇.2) 2 3 ; (B )微影（Lithography)製程12 :如第3圖 所示’在進行一〗_線（微影製程前，先於該矽 錯蟲晶層2 3表面塗佈一層光阻2 4，再以一光罩於 邊光阻2 4上投影出所需之圖形； 200910425 ,(C)蝕刻製程2 3:如第4圖所示，進行—蝕 」襄私，以乾式電漿儀刻（Dry p〗asma 將裸 露之矽鍺磊晶層2 3移除掉後，再去除該光阻，進而 '於該矽鍺磊晶層2 3上定義出所需之圖形； (D )鍺磊晶層（Ge Epitaxial Layers )沉積丄 4 : 如第5圖所示，在經過該微影蝕刻後，利用一四氫化 錯（Germanium tetrahydride，GeH4)之反應氣體以 ίο毫-升/分鐘（sccm)之質量流量，於42〇〇c下反應 個小時，進而在該矽鍺磊晶層2 3上沉積一 〇 % 微米厚度之鍺磊晶層2 5 ; (E )循環式高溫退火處理（cycie Annealing) 15 .如第6圖所示，使用一高溫爐退火裝置3進行 一循環式高溫退火處理，在780。^下持溫丨〇分鐘後， 升溫至900°C再持溫1〇分鐘，並以此模式循環 (Period) 5個階段，·以及 (F )差排（Dislocation)缺陷侷限化1 6 :如 第7圖所不，在經過該循環式高溫退火處理後，即可 將差排缺陷4侷限於該矽鍺磊晶層2 3之側壁2 3 1 ’藉此以完成一可提供該矽基板2 1上高品質鍺磊 晶層2 5沉積，之方法。 如是’使本發明能藉由圖形定義將差排缺陷侷限 化’並利用圖形化後之矽鍺磊晶層其表面能以阻擋該 鍺蟲晶層之差排缺陷’而在結合該循環式高溫退火處 理後’更可降低該錯遙晶層之差排缺陷密度及表面粗 200910425 Μ度’進而提升該鍺遙晶層之品質，因此本發明能降 低成本及簡化製程，可適用在石夕基板上錯元件及 鍺元件，或光電元件上之任何晶格不匹配 (LauiCe-mismatched)之磊晶系統上製作具 整合於標準之石夕晶圓半導體製程。 ,、 ，上所述，本發明係—種圖形定義與循環式高溫 退火處理成長鍺薄膜之方法’可有效改善習用之種種 缺點-，藉由圖形定義將差排缺_限切職晶 側壁’並在結合循環式高溫退火處理後，可降低^ 晶層之差排缺陷密度及表面祕度，以提升鍺蟲晶= 之品質’並降低成本及簡化製程，可適用在任何晶格 不匹配（Latt1Ce-mismatched)之磊晶系統上製作且 有容易整合於標準之石夕晶圓半導體製程，進而使本發 明之産生能更進步、更實用、更符合使用者之所須： 確已符合發明專利申請之要m法提出專利申靖。 惟以上所述者，僅為本發明之較佳實施例而已， 當不能以此限定本發明實施之範圍；&，凡依本 申請專利範圍及發明說明書内容所作之簡單的等^變 化與修姊’皆應仍屬本發明專利涵蓋之範圍内。 200910425 【圖式簡單說明】 第1圖，係本發明之製作流程示意圊。 第2圖’係本發明之超高真空化學氣相磊晶結構示意 r 圖。 第3圖，係本發明之微影圖形結構示意圖。 第4圖’係本發明之蝕刻定義圖形結構示意圖。 第5圖，係本發明之鍺磊晶層沉積示意圖。 第6圖，係本發明之循環式高溫退火處理示意圖。 第7圖，係本發明之差排缺陷侷限化結構示青圖。 【主要元件符號說明】 步驟（A )超高真空化學氣相磊晶法1 1 步驟（B)微影製程12 步驟（C )蝕刻製程1 3 步驟（D )鍺磊晶層沉積1 4 步驟（E )循環式高溫退火處理1 5 步驟（F )差排缺陷侷限化1 6 矽基板2 1 石夕緩衝層2 2 矽鍺磊晶層2 3 側壁2 3 1 光阻2 4 10 200910425 錯遙晶層2 5 高溫爐退火裝置3 差排缺陷4200910425 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for patterning and circulating high temperature annealing to process a grown tantalum film, and more particularly to an ultrahigh vacuum chemical vapor phase epitaxy method (UH V) /C VD ), combined with graphic definition and cyclic annealing (Cycle Annealing), provides a method for depositing high-quality Ge Epitaxial Layers on the Shixi substrate. [Prior Art] According to the Republic of China Patent Publication No. 200504883 and the U.S. Patent No. 6,723,262 B2, which are methods of progressively buffering layered layers, which must be grown before growing into a stupid layer. The multilayer progressive buffering crumb layer is on a bite substrate. However, this method does not increase the throughput of the industry due to the excessive number of steps required in the process, which limits the throughput. In addition, there are also literatures describing the use of Selectively Epitaxial Growth and Multi-step Growth, wherein the selective growth method is based on a germanium substrate containing a patterned amorphous oxide layer. On, grow a layer of epitaxial layer. However, this method can only produce some high-quality germanium epitaxial layers, and most of the other epitaxial layers will form a polycrystalline form above the amorphous oxide layer, and a grain gap will be generated, resulting in The quality of the crystal layer is deteriorated. 200910425 The multi-step growth method is to grow the progressive buffer layer on a stone substrate several times before growing the crystal layer. However, the time required for the process is too long and contains problems such as difficulty in controlling the process bar: etc. Therefore, not only is production limited, but it is also not suitable for industrial production. The traditional method described in the seat T contains the process time is too long, too many steps, no material parts and poor product f, etc. This system can not improve the quality and production capacity of the product, so = can not meet the user's Required for actual use. [Summary of the Invention] The main purpose of Shuming is to 'define the Dlslocatlon defect by the definition of the figure' and to reduce the difference of the defect after the correction. I: The quality of the layer has the advantage of reducing costs and simplifying the process. A secondary object of the present invention is that it can be applied to an epitaxial system of any lattice mismatch (Latt丨-mismatched) on a 夕 基板 substrate. The purpose of the present invention is to define a pattern definition and a method for annealing and growing a thin film by circulating a dish. First, an ultra-high two-phase crystal method is used to deposit a stone buffer layer and a 曰曰t曰曰 layer on a substrate. 'The lithography is then engraved to delineate the desired pattern in the diarrhea layer, and then a layer of epitaxial layer is deposited on the diarrhea layer, and a cycle of high temperature is deposited. An annealing treatment is performed to obtain a structure in which the difference in the defect is limited to the sidewall of the epitaxial layer. [Embodiment] r Please refer to FIG. 1 to FIG. 7 for a schematic diagram of the manufacturing process of the present invention, a schematic diagram of the ultra-high vacuum chemical vapor phase epitaxy structure of the present invention, and a lithographic pattern structure of the present invention. The schematic diagram, the schematic diagram of the etching definition pattern of the present invention, the schematic diagram of the epitaxial layer deposition of the present invention, the schematic diagram of the cyclic high-temperature annealing treatment of the present invention, and the schematic diagram of the localized structure of the differential defect of the present invention. As shown in the figure: the present invention is a method for pattern definition and cyclic high temperature annealing to grow a tantalum film, which comprises at least the following steps: (A) Ultra-high vacuum chemical vapor epitaxy (uhv/CVD) 1 1 : As shown in Fig. 2, a substrate 2 1 is selected, and the germanium substrate 2 1 is first wet-cleaned, then immersed in a hydrogen fluoride (HF) solution and baked at a high temperature to remove the naturally formed oxidation of the surface. The layer is then subjected to an ultra-high vacuum chemical vapor epitaxy method under a specific operating condition, after cleaning the substrate 2 1 on the substrate, the buffer layer (Buffer Layer) 2 2 and a 0.08 μm layer. The thickness of the stone layer (Si〇.8Ge〇.2) 2 3 ; (B) Lithography process 12: as shown in Figure 3 'under the 〗 _ line (before the lithography process, Applying a layer of photoresist 2 4 to the surface of the ruthenium layer 2 3, and projecting a desired pattern on the edge photoresist 24 by a mask; 200910425, (C) etching process 2 3: In the figure 4, the eclipse is carried out, and the dry plasma is engraved (Dry p) asma removes the exposed epitaxial layer 2 3 . Removing the photoresist, and then defining a desired pattern on the germanium epitaxial layer 2; (D) depositing epitaxial layer (Ge Epitaxial Layers): as shown in FIG. 5, after passing through the After the lithography, a reaction gas of a Germanium tetrahydride (GeH4) is used for a reaction time at 42 〇〇c at a mass flow rate of ίο-liter/min (sccm), and then the epitaxial crystal is epitaxially formed. Depositing a 〇% micron thick tantalum epitaxial layer 25 on layer 2; (E) Cyclic high temperature annealing (cycie Annealing) 15. As shown in Fig. 6, using a high temperature furnace annealing device 3 for a cycle After high temperature annealing, after holding temperature for 780 ° C, the temperature is raised to 900 ° C and then held for 1 〇 minutes, and this mode is cycled (Period) 5 stages, · and (F) Dislocation Limitation of defects 1 6 : As shown in Fig. 7, after the cyclic high-temperature annealing treatment, the poor row defect 4 can be limited to the sidewall 2 3 1 ' of the germanium epitaxial layer 2 3 to complete A method of depositing a high quality germanium epitaxial layer 25 on the germanium substrate 2 1 can be provided as follows. Defining the limitation of the difference in the defect and using the surface of the epitaxial layer after patterning to block the difference in the defect of the aphid layer, and after combining the cyclic high-temperature annealing treatment, the error can be further reduced. The difference between the retardation density of the crystal layer and the surface roughness 200910425 Μ degree' further enhances the quality of the free-standing crystal layer, so the invention can reduce the cost and simplify the process, and can be applied to the wrong component and the germanium component on the stone substrate, or photoelectric Any of the crystallographically mismatched (LauiCe-mismatched) epitaxial systems on the component are fabricated on a standard semiconductor wafer semiconductor process. As described above, the present invention is a method for defining a pattern and a cyclic high-temperature annealing process for growing a thin film, which can effectively improve various disadvantages of the conventional use--by pattern definition, the defect is limited to the cut sidewall. And combined with cyclic high temperature annealing treatment, it can reduce the difference of defect density and surface fineness of the crystal layer to improve the quality of mites crystal = reduce cost and simplify the process, and can be applied to any lattice mismatch ( The Latt1Ce-mismatched) epitaxial system is fabricated and easily integrated into the standard Shixi wafer semiconductor process, which makes the invention more progressive, practical, and user-friendly: Apply for the m method to apply for a patent application. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto; & simple changes and modifications made in accordance with the scope of the patent application and the contents of the invention姊' should still be within the scope of the invention patent. 200910425 [Simplified description of the drawings] Fig. 1 is a schematic diagram of the production process of the present invention. Figure 2 is a schematic view of the ultra-high vacuum chemical vapor epitaxy structure of the present invention. Fig. 3 is a schematic view showing the structure of a lithography pattern of the present invention. Fig. 4 is a schematic view showing the structure of an etching definition of the present invention. Fig. 5 is a schematic view showing the deposition of a germanium epitaxial layer of the present invention. Figure 6 is a schematic view of the cyclic high temperature annealing treatment of the present invention. Fig. 7 is a plan view showing the localization of the defective defect of the present invention. [Main component symbol description] Step (A) Ultra-high vacuum chemical vapor epitaxy 1 1 Step (B) lithography process 12 Step (C) Etching process 1 3 Step (D) 锗 epitaxial layer deposition 1 4 steps ( E) Cyclic high temperature annealing treatment 1 5 Step (F) Difference of defect defects 1 6 矽 Substrate 2 1 夕 缓冲 buffer layer 2 2 矽锗 Epitaxial layer 2 3 Side wall 2 3 1 Photoresist 2 4 10 200910425 Layer 2 5 high temperature furnace annealing device 3 differential discharge defect 4