WO2022100104A1 - 具有埋入式位线的半导体装置及其制备方法 - Google Patents

具有埋入式位线的半导体装置及其制备方法 Download PDF

Info

Publication number
WO2022100104A1
WO2022100104A1 PCT/CN2021/103087 CN2021103087W WO2022100104A1 WO 2022100104 A1 WO2022100104 A1 WO 2022100104A1 CN 2021103087 W CN2021103087 W CN 2021103087W WO 2022100104 A1 WO2022100104 A1 WO 2022100104A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
trench
active region
substrate
primary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/103087
Other languages
English (en)
French (fr)
Inventor
李冉
金星
程明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US17/599,393 priority Critical patent/US12120868B2/en
Publication of WO2022100104A1 publication Critical patent/WO2022100104A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present application relates to, but is not limited to, a semiconductor device having a buried bit line and a method for fabricating the same.
  • DRAM Dynamic Random Access Memory
  • the present application provides a semiconductor device with buried bit lines and a method for fabricating the same.
  • the semiconductor device with buried bit lines can significantly reduce the width of the bit line, and can significantly avoid the collapse of the bit line and the defects and defects caused by twisting. rate loss.
  • the present application provides a method for fabricating a semiconductor device with buried bit lines, which includes the steps of: providing a substrate, and forming a plurality of active regions defined by isolation structures in the substrate, the The source region extends along the first direction; a bit line trench is formed, the bit line trench extends along the second direction, and the bit line trench sequentially passes through the active region and the isolation structure in an S-type trend , the second direction and the first direction form an acute included angle; a bit line structure is formed in the bit line trench, and the bit line structure includes a bit line and a cover formed at the bottom of the bit line trench an isolation layer for the bit line; a word line structure is formed in the substrate, the word line structure extends along a third direction, and sequentially passes through the active region and the isolation structure, the third direction Perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structure, and in the active region, the bit line is spaced from the word line structure.
  • the present application also provides a semiconductor device with a buried bit line, which includes: a substrate in which a plurality of active regions defined by isolation structures are disposed, the active regions are along a first direction extending; bit line trenches extend along a second direction, and the bit line trenches sequentially pass through the active region and the isolation structure in an S-shaped direction, the second direction and the first direction are Acute angle; bit line structure, including bit line and isolation layer, the bit line is formed in the bit line trench, the isolation layer covers the bit line and fills the bit line trench; word line structure , extending along a third direction, and passing through the active region and the isolation structure in turn, the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located in the word Below the line structure, in the active region, the bit line and the word line structure are spaced apart.
  • One advantage of the present application is that an "S"-shaped buried bit line can be formed in the substrate. Compared with the traditional non-buried bit line, the buried bit line of the present application does not need to be deposited on the two sides of the bit line. The insulating layer is deposited on the side, so the line width of the bit line can be significantly reduced, and the collapse of the non-buried bit line, the defects caused by twisting and the loss of yield can be significantly avoided.
  • Another advantage of the present application is that since the bit line is buried in the substrate, the height of the capacitor contact hole is greatly reduced, and the capacitor contact hole is directly formed on the insulating layer, which greatly simplifies the manufacturing process of the capacitor contact hole and reduces the capacitance The process difficulty and defects of the contact holes can effectively improve the yield.
  • the preparation method of the present application directly omits the manufacturing process of the bit line contact pad (BLC), which greatly reduces the manufacturing cost and process procedure.
  • Another advantage of the present application is that the preparation method of the present application ingeniously constructs an "S"-type buried bit line structure, so that the bit line is located under the word line structure, and the bit line and the word line are made by the etching selection ratio.
  • the overlapping positions form a height difference to avoid short circuits.
  • FIG. 1 is a process flow diagram of a method for fabricating a semiconductor device with buried bit lines according to an embodiment of the present application
  • FIGS. 2A to 2M are schematic views of structures formed in a method for fabricating a semiconductor device with buried bit lines according to an embodiment of the present application.
  • FIG. 1 is a process flow diagram of a method for fabricating a semiconductor device with buried bit lines according to an embodiment of the present application. Please refer to FIG. 1 .
  • the fabrication method of the present application includes the following steps: step S10 , providing a substrate, and in the step S10 , a substrate is provided.
  • step S11 forming bit line trenches, the bit line trenches extending along the second direction, and the Bit line trenches pass through the active region and the isolation structure in an S-shaped direction, and the second direction and the first direction form an acute included angle;
  • step S12 forming in the bit line trench A bit line structure, the bit line structure includes a bit line formed at the bottom of the bit line trench and an isolation layer covering the bit line;
  • step S13 a word line structure is formed in the substrate, the word line The structure extends in a third direction, and passes through the active region and the isolation structure in sequence, the third direction is perpendicular to the second direction, and in the isolation structure, the bit line is located in the word Below the line structure, in the active region, the bit line and the word line structure are spaced apart.
  • FIGS. 2A to 2M are schematic views of structures formed in a method for fabricating a semiconductor device with buried bit lines according to an embodiment of the present application.
  • step S10 a substrate 200 is provided, and a plurality of active regions 220 defined by the isolation structures 210 are formed in the substrate 200 , and the active regions 220 extend along the first direction, as shown in FIGS. 2A to 2E .
  • the substrate 200 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, or the like.
  • a suitable semiconductor material can be selected as the substrate 200 according to the actual requirements of the device, which is not limited herein.
  • the substrate 200 is a single crystal silicon substrate.
  • the active region 220 is formed by doping the substrate 200 through a process such as plasma implantation.
  • the active region 220 extends along a first direction (the B direction in FIG. 2A ).
  • This embodiment exemplifies a method for forming a plurality of active regions 220 defined by isolation structures 210 in the substrate 200 .
  • an isolation structure 210 is formed in the substrate 200 , and the substrate 200 is divided into a plurality of primary regions 201 by the isolation structure 210 .
  • the isolation structure 210 is Shallow Trench Isolation (STI for short), and in other embodiments of the present application, the isolation structure 210 may be a structure capable of isolation.
  • FIGS. 2B and 2C wherein FIG. 2B is a top view, and FIG. 2C is a cross-sectional view along the line A-A in FIG. 2B , a bit line primary trench 202 is formed in the substrate 200 , and the bit line primary trench is formed in the substrate 200 .
  • the trench 202 extends along the second direction, and the bit line primary trench 202 passes through the primary region 201 and the isolation structure 210 in sequence, and the direction of the bit line primary trench 202 is the same as that of the bit line trench formed subsequently.
  • 230 (shown in Figure 2F) goes in the same direction.
  • the substrate 200 is processed by photolithography and etching processes to form the bitline primary trenches 202 in the substrate 200 .
  • the bit line primary trench 202 extends along the second direction and passes through the primary region 201 and the isolation structure 210 in an S-shaped trend.
  • the fact that the primary bit line trenches 202 extend along the second direction means that the overall extending direction of the primary bit line trenches 202 is the second direction.
  • the second direction and the first direction form an acute angle. As shown in FIG. 2B , the second direction is the C direction, the first direction is the B direction, and the C direction and the B direction form an acute included angle.
  • the depth of the bit line primary trench 202 into the substrate 200 is smaller than the depth of the isolation structure 210 into the substrate 200, that is, in the substrate 200, the bit line primary trench 202
  • the bottom surface of the isolation structure 210 is located above the bottom surface of the isolation structure 210 to ensure that the isolation structure 210 can effectively isolate and avoid leakage of adjacent devices.
  • FIGS. 2D and 2E wherein FIG. 2D is a top view, and FIG. 2E is a cross-sectional view along line A-A in FIG. 2D , the primary region 201 is doped to form the active region 220 .
  • the bit line primary trench 202 is formed in the substrate 200 , when the primary region 201 is doped, the dopant will be along the upper surface of the primary region 201 and the bit line primary trench. If the bottom surface and side surface of 202 are doped, the active region 220 forms a first doped region 220A in the area below the bit line primary trench 202, and in the side area of the bit line primary trench 202, the The active region 220 forms a second doped region 220B. The heights of the first doped region 220A and the second doped region 220B are different.
  • the height H1 of the first doped region 220A refers to the distance between the upper surface of the first doped region 220A and the bottom surface of the semiconductor device
  • the height H2 of the second doped region 220B refers to the second doped region 220B.
  • the height H1 of the first doped region 220A is smaller than the height H2 of the second doped region 220B, that is, the active region 220 includes a first doped region 220A and a second doped region 220B with different surface heights.
  • the primary region 201 may be doped by a plasma implantation process to form the active region 220 .
  • the conductivity type of the active region 220 depends on the type of dopant. For example, if phosphorus (P), arsenic (As) or other suitable n-type dopants are doped into the primary region 201, the conductivity type of the active layer 220 is N-type. Boron (B), gallium (Ga) or other suitable p-type dopants, the conductivity type of the active layer 220 is P-type.
  • the primary region 201 is doped with an N-type dopant, and the conductivity type of the active region 220 is N-type.
  • bit line primary trenches 202 are first formed in the substrate 200, and then the substrate 200 is doped to form the active region 220.
  • the active region 220 includes surfaces with different heights The first doped region 220A and the second doped region 220B.
  • the bit line primary trench 202 may not be formed, but after the primary region 201 is formed, the substrate 200 is directly doped to form an active region 220 with a uniform height.
  • Step S11 forming a bit line trench 230 , the bit line trench 230 extending along the second direction, and the bit line trench 230 passing through the active region 220 and the isolation structure 210 in an S-shaped direction in sequence 2F and 2G, wherein, FIG. 2F is a top view, and FIG. 2G is a cross-sectional view along line A-A in FIG. 2F.
  • the bit line trenches 230 may be formed through photolithography and etching processes.
  • the bit line trench 230 is formed at the bottom of the bit line primary trench 202, and the width of the bit line trench 230 is smaller than that of the bit line The width of the primary trench 202 .
  • the width of the bit line trench 230 refers to the dimension of the bit line trench 230 parallel to the substrate 200
  • the width of the bit line primary trench 202 refers to the bit line primary trench 202 A dimension parallel to the direction of the substrate 200 .
  • the bit line trenches 230 extend from the bottom of the bit line primary trenches 202 to the interior of the substrate 200 .
  • the bit line trench 230 is formed in the first doped region 220A of the active region 220 , and the bit line trench 230 is deep into the substrate 200 to a depth
  • the depth of the isolation structure 210 is smaller than the depth of the isolation structure 210 into the substrate 200 , that is, in the substrate 200 , the bottom surface of the bit line trench 230 is located above the bottom surface of the isolation structure 210 to ensure the isolation.
  • the structure 210 can effectively isolate and avoid leakage of adjacent devices.
  • the depth of the bit line trench 230 is smaller than the depth of the first doped region 220A to improve the performance of the subsequently formed bit line structure 240 (shown in FIG. 2I ).
  • Step S12 forming a bit line structure 240 in the bit line trench 230, the bit line structure 240 including a bit line 241 formed at the bottom of the bit line trench 230 and an isolation layer 242 covering the bit line 241 2H and FIG. 2I, wherein, FIG. 2H is a top view, and FIG. 2I is a cross-sectional view along the line A-A in FIG. 2H.
  • a bit line 241 is deposited at the bottom of the bit line trench 230, the bit line 241 may be a conductive material such as tungsten, and an isolation layer 242 is covered on the bit line 241, and the isolation layer 242 may be oxidized A material such as silicon dioxide, the isolation layer 242 protects the bit line 241 .
  • the isolation layer 242 also fills the bit line primary trench 202 , and the upper surface of the isolation layer 242 is flush with the upper surface of the substrate 200 to provide a basis for subsequent process steps.
  • a buried bit line structure is formed.
  • Step S13 forming a word line structure 250 in the substrate 200, the word line structure 250 extending along a third direction and passing through the active region 220 and the isolation structure 210 in sequence, the third direction Perpendicular to the second direction, in the isolation structure 210, the bit line 241 is located below the word line structure 250, in the active region 220, the bit line 241 and the word line
  • the structures 250 are arranged at intervals, as shown in FIG. 2J and FIG. 2K , wherein FIG. 2J is a top view, and FIG. 2K is a cross-sectional view along the line A-A in FIG. 2J .
  • the word line structure may be formed.
  • the self-aligned double pattern process the reverse self-aligned double pattern process, and the like.
  • the word line structure 250 is composed of a multi-layer structure, such as an insulating layer, a barrier layer, a metal layer, a passivation layer, and the like.
  • the word line structure 250 extends along a third direction (the D direction as shown in FIG. 2J ), the third direction (the D direction) is perpendicular to the second direction (the C direction), and There is an included angle with the first direction (B direction).
  • the bit line 241 is located below the word line structure 250 refers to the upper and lower relationship between the two in the thickness direction of the substrate 200 , and is not limited to being directly below.
  • the word line structure 250 and the bit line 241 in the isolation structure 210 have an overlapping region, that is, the bit line 241 is located in the in the area below the word line structure 250 .
  • the bit line 241 and the word line structure 250 are spaced apart, and there is no overlapping area between the word line structure 250 and the bit line 241 .
  • the word line structure 250 of the present application can be arranged to pass through the word line structure 250 of the isolation structure 210 .
  • the depth is less than the depth of the word line structures 250 passing through the active region 220 to avoid shorting the word line structures 250 and the bit lines 241 within the isolation structure 210 .
  • the word line structure 250 includes a first word line structure 250A passing through the isolation structure 210 and a second word line structure 250B passing through the active region 220 .
  • the depth of the first word line structure 250A within the isolation structure 210 is smaller than the depth of the second word line structure 250B passing through the active region 220 .
  • the method for realizing that the depth of the first word line structure 250A is smaller than the depth of the second word line structure 250B may be: when forming the trench of the word line structure, the active region 220 and the isolation structure 210 are etched with an etchant.
  • the word line structure trenches of different depths are formed in the active region 220 and the isolation structure 210 due to the different etching rates, so that the word line structures 250 formed in the word line structure trenches have different depths.
  • a step of thinning the active region 220 on the upper surface of the active region 220 is also included.
  • the active region 220 may be polished by a chemical mechanical polishing (CMP) process, so as to reduce the difficulty of the subsequent formation of the word line structure 250 .
  • CMP chemical mechanical polishing
  • the step of forming the word line structure 250 in the substrate 200 further includes the following step: as shown in FIG. 2L , forming an insulating layer 260 on the surface of the substrate 200 .
  • the insulating layer 260 protects the surface of the substrate 200 and serves as insulation.
  • the insulating layer 260 may be an insulating layer such as a silicon nitride layer.
  • the step further includes the following step: forming a capacitor contact hole, the capacitor contact hole penetrates the insulating layer 260 to the active region 220, and the capacitor contact hole is in the capacitor contact hole.
  • Conductive plugs 270 are formed, and the conductive plugs 270 are in contact with the active regions 220, as shown in FIG. 2M.
  • the conductive plug 270 is used to electrically connect the capacitor formed above the substrate 200 with the active region 220 .
  • the capacitor contact hole can be directly formed by photolithography process exposure and one-time etching, and the preparation process is simple.
  • the method for fabricating a semiconductor device with a buried bit line can form an "S" type buried bit line in a substrate.
  • the buried The bit line does not need to deposit insulating layers on both sides of the bit line, so the line width can be significantly reduced, and the collapse of the non-buried bit line, defects and yield loss caused by twisting can be significantly avoided.
  • the bit line is buried in the substrate, the height of the capacitor contact hole is greatly reduced, and the capacitor contact hole is directly formed on the insulating layer, which greatly simplifies the manufacturing process of the capacitor contact hole and reduces the process difficulty of the capacitor contact hole. and defects, effectively improving the yield.
  • the preparation method of the present application directly omits the manufacturing process of the bit line contact pad (BLC), which greatly reduces the manufacturing cost and process procedure.
  • the preparation method of the present application ingeniously constructs an "S" type buried bit line structure, so that the bit line is located under the word line structure, and the position where the bit line and the word line overlap are formed by the etching selection ratio. height difference to avoid short circuits.
  • the present application also provides a semiconductor device having a buried bit line.
  • the semiconductor device of the present application includes a substrate 200 , a bit line trench 230 (shown in FIG. 2F ), a bit line structure 240 and a word line structure 250 (shown in FIG. 2J ).
  • a plurality of active regions 220 defined by the isolation structures 210 are disposed in the substrate 200 , and the active regions 220 extend along a first direction (direction B in FIG. 2A ).
  • the isolation structure 210 is Shallow Trench Isolation (STI for short), and in other embodiments of the present application, the isolation structure 210 may be a structure capable of isolation.
  • the substrate 200 further includes a bit line primary trench 202, the bit line primary trench 202 extends along the second direction (direction C as shown in FIG. 2B ), and the bit line primary trench 202 The trenches 202 pass through the active region 220 and the isolation structure 210 in sequence.
  • the active region 220 includes a first doped region 220A located below the bitline primary trench 202 and a second doped region 220B located beside the bitline primary trench 202, as shown in FIG. 2E.
  • the heights of the first doped region 220A and the second doped region 220B are different.
  • the height H1 of the first doped region 220A refers to the distance between the upper surface of the first doped region 220A and the bottom surface of the semiconductor device, and the height H2 of the second doped region 220B refers to the second doped region 220B. The distance between the top surface of the doped region 220B and the bottom surface of the semiconductor device.
  • the height H1 of the first doped region 220A is smaller than the height H2 of the second doped region 220B, that is, the surface height of the active region 220 is different.
  • the bit line primary trench 202 runs through the active region 220 and the isolation structure 210 in a second direction in an "S" shape.
  • the primary bit line trench 202 may not be provided, and the surface height of the active region 220 is the same, and the doping depth is also the same.
  • the bit line trenches 230 extend along the second direction (the C direction shown in FIG. 2F ), and the bit line trenches 230 pass through the active region 220 and the isolation structure in an “S” shape in sequence. 210.
  • the second direction (direction C shown in FIG. 2F ) and the first direction (direction B shown in FIG. 2F ) form an acute included angle.
  • the bit line trench 230 is provided at the bottom of the bit line primary trench 202, that is, the bit line trench 230 is formed from the The bottom of the bit line primary trench 202 extends toward the inside of the substrate 200 .
  • the bit line trench 230 is located in the active region 220 , the bit line trench 230 is located within the range of the first doped region 220A of the active region 220 .
  • the depth of the bit line trench 230 into the substrate 200 is smaller than the depth of the isolation structure 210 into the substrate 200, that is, in the In the substrate 200 , the bottom surface of the bit line trench 230 is disposed on the bottom surface of the isolation structure 210 . Since the bit line trench 230 is disposed at the bottom of the bit line primary trench 202, the direction of the bit line trench 230 is the same as the direction of the bit line primary trench 202, both of which are "S" "type trend. The width of the bit line trench 230 is smaller than the width of the bit line primary trench 202 .
  • the bit line structure 240 includes a bit line 241 and an isolation layer 242 .
  • the bit line 241 is formed in the bit line trench 230 , and the isolation layer 242 covers the bit line 241 and fills the bit line trench 230 .
  • the isolation layer 242 also fills the bit line primary trench 202 .
  • the upper surface of the isolation layer 242 is flush with the upper surface of the substrate 200 .
  • the word line structure 250 extends along a third direction (direction D as shown in FIG. 2J ), and passes through the active region 220 and the isolation structure 210 in sequence.
  • the third direction (direction D as shown in FIG. 2J ) is perpendicular to the second direction (direction C as shown in FIG. 2J ), and has a angle.
  • the bit line 241 is located below the word line structure 250 , and in the active region 220 , the bit line 241 and the word line structure 250 are spaced apart.
  • the word line structure 250 is composed of a multi-layer structure, such as an insulating layer, a barrier layer, a metal layer, a passivation layer, and the like.
  • the word line structure 250 includes a first word line structure 250A passing through the isolation structure 210 and a second word line structure 250B passing through the active region 220 .
  • the depth of the first word line structure 250A passing through the isolation structure 210 is smaller than the depth of the second word line structure 250B passing through the active region 220 to avoid that the word line structure 250 and the The bit line 241 is shorted.
  • the semiconductor device further includes an insulating layer 260 and a conductive plug 270 .
  • the insulating layer 260 is disposed on the surface of the substrate 200 and covers the word line structure 250 , the isolation layer 242 and the exposed active region 220 .
  • the insulating layer 260 has a capacitor contact hole, and the capacitor contact hole penetrates the insulating layer 260 to the active region 220 .
  • Conductive plugs 270 are formed in the capacitor contact holes and are in contact with the active regions 220 .
  • the conductive plug 270 is used to electrically connect the capacitor formed above the substrate 200 with the active region 220 .
  • the semiconductor device of the present application adopts an "S" type buried bit line structure. Compared with the traditional non-buried bit line, there is no need to deposit insulating layers on both sides of the bit line, so the line width can be significantly reduced, and Defects and yield loss caused by the collapse of non-buried bit lines and distortion can be significantly avoided.
  • the bit line is buried in the substrate, the height of the capacitor contact hole is greatly reduced, and the capacitor contact hole is directly formed on the insulating layer, which greatly simplifies the manufacturing process of the capacitor contact hole and reduces the process difficulty of the capacitor contact hole. and defects, effectively improving the yield.
  • the semiconductor device of the present application does not need to provide a bit line contact pad (BLC) structure, which greatly reduces manufacturing costs and process procedures.
  • BLC bit line contact pad
  • the bit line of the semiconductor device of the present application is located below the word line structure, and the overlapping position of the bit line and the word line forms a height difference, thereby avoiding short circuit between the bit line and the word line structure, and greatly improving the performance of the semiconductor device.
  • the "S" type buried bit line structure is adopted in the semiconductor device, the line width can be significantly reduced, and the non-buried bit lines can be significantly avoided Collapse, distortion caused by defects and yield loss.
  • the bit line is buried in the substrate, the height of the capacitor contact hole is greatly reduced, and the capacitor contact hole is directly formed on the insulating layer, which greatly simplifies the manufacturing process of the capacitor contact hole and reduces the process difficulty of the capacitor contact hole. and defects, effectively improving the yield.
  • the preparation method of the semiconductor device not only reduces the manufacturing cost and process procedure, but also ingeniously constructs an "S"-shaped buried bit line structure to avoid short circuits.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

本申请提供一种具有埋入式位线的半导体装置及其制备方法。具有埋入式位线的半导体装置的制备方法包括如下步骤：提供一衬底；形成位线沟槽；于所述位线沟槽内形成位线结构；于所述衬底中形成字线结构。具有埋入式位线的半导体装置包括衬底、位线沟槽、位线结构和字线结构。

Description

具有埋入式位线的半导体装置及其制备方法
本申请要求在2020年11月12日提交中国专利局、申请号为202011261602.4、发明名称为“具有埋入式位线的半导体装置及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种具有埋入式位线的半导体装置及其制备方法。
背景技术
随着集成电路技术的不断发展，半导体集成电路器件特征尺寸不断缩小。例如，动态随机存储器(英文：Dynamic Random Access Memory，简称：DRAM)作为一种广泛应用多计算机系统的半导体集成电路器件，其关键尺寸也越来越小，制造难度越来越大，制程工艺越来越复杂，成本也越来越高。
如何优化工艺流程可以有效的提高公司的生产效率和降低生产运营成本越来越受到重视。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供一种具有埋入式位线的半导体装置及其制备方法，具有埋入式位线的半导体装置能够显著降低位线线宽，且能显著避免位线倒塌，扭曲造成的缺陷及良率损失。
本申请提供了一种具有埋入式位线的半导体装置的制备方法，其包括如下步骤：提供一衬底，于所述衬底中形成由隔离结构界定的多个有源区，所述有源区沿第一方向延伸；形成位线沟槽，所述位线沟槽沿第二方向延伸，且所述位线沟槽以S型走向依次穿过所述有源区及所述隔离结构，所述第二方向与所述第一方向呈锐角夹角；于所述位线沟槽内形成位线结构，所述位线结构包括形成于所述位线沟槽底部的位线及覆盖所述位线的隔离层；于所述衬底中形成 字线结构，所述字线结构沿第三方向延伸，且依次穿过所述有源区及所述隔离结构，所述第三方向与所述第二方向垂直，在所述隔离结构中，所述位线位于所述字线结构的下方，在所述有源区中，所述位线与所述字线结构间隔设置。
本申请还提供了一种具有埋入式位线的半导体装置，其包括：衬底，所述衬底中设置有由隔离结构界定的多个有源区，所述有源区沿第一方向延伸；位线沟槽，沿第二方向延伸，且所述位线沟槽以S型走向依次穿过所述有源区及所述隔离结构，所述第二方向与所述第一方向呈锐角夹角；位线结构，包括位线及隔离层，所述位线形成于所述位线沟槽内，所述隔离层覆盖所述位线且填充所述位线沟槽；字线结构，沿第三方向延伸，且依次穿过所述有源区及所述隔离结构，所述第三方向与所述第二方向垂直，在所述隔离结构中，所述位线位于所述字线结构的下方，在所述有源区中，所述位线与所述字线结构间隔设置。
本申请的一优点在于，能够在衬底内形成“S”型埋入式位线，相较于传统的非埋入式的位线，本申请埋入式位线不需要沉积在位线两侧沉积绝缘层，因此位线的线宽可以显著降低，而且能显著避免非埋入式位线倒塌，扭曲造成的缺陷及良率损失。
本申请另一优点在于，由于位线埋入衬底内，使得电容接触孔的高度大大降低，电容接触孔直接在绝缘层上形成，极大的简化了电容接触孔的制造工艺，减少了电容接触孔的工艺难度和缺陷，有效的提高良率。同时，本申请制备方法直接省去了位线接触垫(BLC)的制造过程，极大的减少了制造成本和工艺程序。
本申请再一优点在于，本申请制备方法巧妙的构建了一种“S”型埋入式的位线结构，使位线位于字线结构下方，并通过刻蚀选择比使位线和字线重叠的位置形成高低差从而避免短路。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本申请实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本申请的一些实施例，而不是全 部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是本申请实施例的具有埋入式位线的半导体装置的制备方法的工艺流程图；
图2A～图2M是本申请实施例的具有埋入式位线的半导体装置的制备方法中所形成的结构的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
下面结合附图和具体实施例方式对本申请提供的具有埋入式位线的半导体装置及其制备方法做详细说明。
图1是本申请一实施例的具有埋入式位线的半导体装置的制备方法的工艺流程图，请参阅图1，本申请制备方法包括如下步骤：步骤S10，提供一衬底，于所述衬底中形成由隔离结构界定的多个有源区，所述有源区沿第一方向延伸；步骤S11，形成位线沟槽，所述位线沟槽沿第二方向延伸，且所述位线沟槽以S型走向依次穿过所述有源区及所述隔离结构，所述第二方向与所述第一方向呈锐角夹角；步骤S12，于所述位线沟槽内形成位线结构，所述位线结构包括形成于所述位线沟槽底部的位线及覆盖所述位线的隔离层；步骤S13，于所述衬底中形成字线结构，所述字线结构沿第三方向延伸，且依次穿过所述有源区及所述隔离结构，所述第三方向与所述第二方向垂直，在所述隔离结构中，所述位线位于所述字线结构的下方，在所述有源区中，所述位线与所述字线结构间隔设置。
图2A～图2M是本申请一实施例的具有埋入式位线的半导体装置的制备方法中所形成的结构的示意图。
步骤S10，提供一衬底200，于所述衬底200中形成由隔离结构210界定的多个有源区220，所述有源区220沿第一方向延伸，如图2A～2E所示。
所述衬底200可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等。其中可根据器件的实际需求，选择合适的半导体材料作为所述衬底200，在此不作限定。在该实施例中，所述衬底200为单晶硅衬底。
所述有源区220为对所述衬底200采用等离子体注入等工艺进行掺杂而成。所述有源区220沿第一方向(如图2A中的B方向)延伸。
本实施例列举一种于所述衬底200中形成由隔离结构210界定的多个有源区220的方法。
如图2A所示，其为俯视图，于所述衬底200中形成隔离结构210，所述衬底200被所述隔离结构210分为多个初级区域201。在本实施例中，所述隔离结构210是浅沟槽隔离(Shallow Trench Isolation，简称STI)，在本申请其它实施例中，所述隔离结构210可为能够起到隔离作用的结构。
如图2B及图2C所示，其中，图2B为俯视图，图2C为沿图2B中A-A线的截面图，于所述衬底200中形成位线初级沟槽202，所述位线初级沟槽202沿第二方向延伸，且所述位线初级沟槽202依次穿过所述初级区域201及所述隔离结构210，所述位线初级沟槽202的走向与后续形成的位线沟槽230(绘示于图2F)的走向相同。
光刻及刻蚀工艺对所述衬底200进行处理，以在所述衬底200中形成所述位线初级沟槽202。所述位线初级沟槽202沿第二方向延伸，并以S型走向依次穿过所述初级区域201及所述隔离结构210。所述位线初级沟槽202沿第二方向延伸是指所述位线初级沟槽202整体延伸方向为第二方向。所述第二方向与所述第一方向呈一锐角。如图2B所示，所述第二方向为C方向，所述第一方向为B方向，所述C方向与所述B方向呈锐角夹角。所述位线初级沟槽202深入所述衬底200中的深度小于所述隔离结构210深入所述衬底200中的深度，即在所述衬底200内，所述位线初级沟槽202的底面位于所述隔离结构210的底面之上，以保证所述隔离结构210能够有效地起到隔离作用，避免相邻器件漏电。
如图2D及图2E所示，其中，图2D为俯视图，图2E为沿图2D中A-A线的截面图，对所述初级区域201进行掺杂，形成所述有源区220。
由于所述衬底200中形成有位线初级沟槽202，则在对所述初级区域201进行掺杂时，掺杂物质会沿所述初级区域201的上表面及所述位线初级沟槽202的底面与侧面掺杂，则在所述位线初级沟槽202下方区域，所述有源区220形成第一掺杂区域220A，在所述位线初级沟槽202侧方区域，所述有源区220形成第二掺杂区域220B。所述第一掺杂区域220A与所述第二掺杂区域220B的高度不同。其中，所述第一掺杂区域220A的高度H1是指所述第一掺杂区域220A的上表面与半导体装置底面的距离，所述第二掺杂区域220B的高度H2是指所述第二掺杂区域220B的上表面与半导体装置底面的距离。所述第一掺杂区域220A的高度H1小于所述第二掺杂区域220B的高度H2，即所述有源区220包括表面高低不同的第一掺杂区域220A和第二掺杂区域220B。
其中，可采用等离子注入工艺对所述初级区域201进行掺杂，形成有源区220。所述有源区220的导电类型取决于掺杂物质的种类。例如，若向初级区域201中掺杂磷(P)、砷(As)或其他合适的n型掺杂剂，则所述有源层220的导电类型为N型，若向初级区域201中掺杂硼(B)、镓(Ga)或其他合适的p型掺杂剂，则所述有源层220的导电类型为P型。在本实施例中，向所述初级区域201掺杂N型掺杂剂，所述有源区220的导电类型为N型。
在本实施例中，先在所述衬底200中形成位线初级沟槽202，再对所述衬底200进行掺杂形成所述有源区220，所述有源区220包括表面高低不同的第一掺杂区域220A和第二掺杂区域220B。而在其他实施例中，也可不形成所述位线初级沟槽202，而是在形成所述初级区域201后，直接对所述衬底200进行掺杂，形成高度一致的有源区220。
步骤S11，形成位线沟槽230，所述位线沟槽230沿第二方向延伸，且所述位线沟槽230以S型走向依次穿过所述有源区220及所述隔离结构210，所述第二方向与所述第一方向呈锐角夹角，请参阅图2F及图2G，其中，图2F为俯视图，图2G为沿图2F中A-A线的截面图。
步骤S11中，可通过光刻及刻蚀工艺形成所述位线沟槽230。在本实施例中，由于存在位线初级沟槽202，则所述位线沟槽230形成在所述位线初级沟槽202的底部，所述位线沟槽230的宽度小于所述位线初级沟槽202的宽度。其中，所述位线沟槽230的宽度是指所述位线沟槽230平行所述衬底200方向的尺寸，所述位线初级沟槽202的宽度是指所述位线初级沟槽202平行于所述衬底200 方向的尺寸。不论是在于隔离结构210中，还是在有源区220中，所述位线沟槽230均自所述位线初级沟槽202的底部向所述衬底200的内部延伸。
在所述有源区220中，所述位线沟槽230形成在所述有源区220的第一掺杂区域220A中，且所述位线沟槽230深入所述衬底200中的深度小于所述隔离结构210深入所述衬底200中的深度，即在所述衬底200内，所述位线沟槽230的底面位于所述隔离结构210的底面之上，以保证所述隔离结构210能够有效地起到隔离作用，避免相邻器件漏电。在一些实施例中，所述位线沟槽230的深度小于所述第一掺杂区域220A的深度，以提高后续形成的位线结构240(绘示于图2I中)的性能。
步骤S12，于所述位线沟槽230内形成位线结构240，所述位线结构240包括形成于所述位线沟槽230底部的位线241及覆盖所述位线241的隔离层242，如图2H及图2I所示，其中，图2H为俯视图，图2I为沿图2H中A-A线的截面图。
步骤S12中，在所述位线沟槽230底部沉积位线241，所述位线241可为钨等导电材料，在所述位线241上覆盖隔离层242，所述隔离层242可为氧化物等材料，例如二氧化硅，所述隔离层242保护所述位线241。在本实施例中，所述隔离层242还填充所述位线初级沟槽202，所述隔离层242的上表面与所述衬底200上表面平齐，为后续的工艺步骤提供基础。步骤S12中，形成埋入式位线结构。
步骤S13，于所述衬底200中形成字线结构250，所述字线结构250沿第三方向延伸，且依次穿过所述有源区220及所述隔离结构210，所述第三方向与所述第二方向垂直，在所述隔离结构210中，所述位线241位于所述字线结构250的下方，在所述有源区220中，所述位线241与所述字线结构250间隔设置，如图2J及图2K所示，其中，图2J为俯视图，图2K为沿图2J中A-A线的截面图。
步骤S13中，可形成所述字线结构。例如，自对准双图形工艺、反向自对准双图形工艺等。所述字线结构250由多层结构构成，例如绝缘层、阻挡层、金属层及钝化层等。
在本实施例中，所述字线结构250沿第三方向(如图2J所示的D方向)延 伸，所述第三方向(D方向)与所述第二方向(C方向)垂直，并与所述第一方向(B方向)具有一夹角。
在所述隔离结构210中，所述位线241位于所述字线结构250的下方是指在所述衬底200的厚度方向两者的上下关系，而并非限定是在正下方。例如，在本实施例中，在所述衬底200厚度方向上，在所述隔离结构210内所述字线结构250与所述位线241存在重叠区域，即所述位线241位于所述字线结构250下方的区域内。在所述有源区220内，所述位线241与所述字线结构250间隔设置，所述字线结构250与所述位线241并不存在重叠区域。由于在所述隔离结构210内所述字线结构250与所述位线241存在重叠区域，则本申请所述字线结构250可设置为，穿过所述隔离结构210的字线结构250的深度小于穿过所述有源区220的字线结构250的深度，以避免在隔离结构210内，所述字线结构250与所述位线241短路。字线结构250包括穿过所述隔离结构210的第一字线结构250A和穿过所述有源区220的第二字线结构250B。具体地说，请参阅图2K，位于所述隔离结构210内的第一字线结构250A的深度小于穿过所述有源区220的第二字线结构250B的深度。其中，第一字线结构250A的深度小于第二字线结构250B的深度的实现方法可以为，在形成所述字线结构的沟槽时，利用刻蚀物对有源区220及隔离结构210的刻蚀速率不同而在有源区220及隔离结构210中形成不同深度的字线结构沟槽，进而使得形成在所述字线结构沟槽内的字线结构250具有不同的深度。
在于所述衬底200中形成字线结构250的步骤之前(即步骤S13之前)，还包括于所述有源区220上表面减薄所述有源区220的步骤。具体地说，可通过化学机械研磨(CMP)工艺研磨所述有源区220，以降低后续形成字线结构250的工艺难度。
在本实施例中，于所述衬底200中形成字线结构250的步骤之后还包括如下步骤：如图2L所示，于所述衬底200表面形成绝缘层260。所述绝缘层260保护所述衬底200表面，并作绝缘之用。所述绝缘层260可为氮化硅层等绝缘层。
于所述衬底200表面形成绝缘层260的步骤之后还包括如下步骤：形成电容接触孔，所述电容接触孔贯穿所述绝缘层260至所述有源区220，在所述电容接触孔中形成导电插塞270，所述导电插塞270与所述有源区220接触，如图 2M所示。所述导电插塞270用于将形成在所述衬底200上方的电容与有源区220电连接。其中，电容接触孔可直接由光刻工艺曝光及一次蚀刻而形成，制备工艺简单。
本申请提供的具有埋入式位线的半导体装置的制备方法能够在衬底内形成“S”型埋入式位线，相较于传统的非埋入式的位线，本申请埋入式位线不需要沉积在位线两侧沉积绝缘层，因此线宽可以显著降低，而且能显著避免非埋入式位线倒塌，扭曲造成的缺陷及良率损失。另外，由于位线埋入衬底内，使得电容接触孔的高度大大降低，电容接触孔直接在绝缘层上形成，极大的简化了电容接触孔的制造工艺，减少了电容接触孔的工艺难度和缺陷，有效的提高良率。同时，本申请的制备方法直接省去了位线接触垫(BLC)的制造过程，极大的减少了制造成本和工艺程序。另外，本申请的制备方法巧妙的构建了一种“S”型埋入式的位线结构，使位线位于字线结构下方，并通过刻蚀选择比使位线和字线重叠的位置形成高低差从而避免短路。
本申请还提供一种具有埋入式位线的半导体装置。请参阅图2M，在一实施例中，本申请半导体装置包括衬底200、位线沟槽230(绘示于图2F)、位线结构240及字线结构250(绘示于图2J)。
所述衬底200内设置有由隔离结构210界定的多个有源区220，所述有源区220沿第一方向(如图2A中的B方向)延伸。在本实施例中，所述隔离结构210是浅沟槽隔离(Shallow Trench Isolation，简称STI)，在本申请其它实施例中，所述隔离结构210可为能够起到隔离作用的结构。
在本实施例中，所述衬底200还包括位线初级沟槽202，所述位线初级沟槽202沿第二方向(如图2B所示C方向)延伸，且所述位线初级沟槽202依次穿过所述有源区220及所述隔离结构210。
所述有源区220包括位于所述位线初级沟槽202下方的第一掺杂区域220A及位于所述位线初级沟槽202侧方的第二掺杂区域220B，如图2E所示。所述第一掺杂区域220A与所述第二掺杂区域220B的高度不同。其中，所述第一掺杂区域220A的高度H1是指所述第一掺杂区域220A的上表面与半导体装置底面的距离，所述第二掺杂区域220B的高度H2是指所述第二掺杂区域220B的上表面与半导体装置底面的距离。所述第一掺杂区域220A的高度H1小于所述第二掺杂区域220B的高度H2，即所述有源区220的表面高低不同。在所述衬 底200中，所述位线初级沟槽202以“S”型走向沿第二方向依次穿过所述有源区220及隔离结构210。
在本申请其他实施例中，也可不设置所述初级位线沟槽202，则所述有源区220的表面高度一致，掺杂深度也相同。
所述位线沟槽230沿第二方向(如图2F所示C方向)延伸，且所述位线沟槽230以“S”型走向依次穿过所述有源区220及所述隔离结构210。所述第二方向(如图2F所示C方向)与所述第一方向(如图2F所示B方向)呈锐角夹角。
在本实施例中，由于设置有所述位线初级沟槽202，则所述位线沟槽230设置在所述位线初级沟槽202的底部，即所述位线沟槽230自所述位线初级沟槽202的底部向所述衬底200内部延伸。当所述位线沟槽230位于所述有源区220时，所述位线沟槽230位于所述有源区220的所述第一掺杂区域220A范围内。当所述位线沟槽230位于所述隔离结构210时，所述位线沟槽230深入所述衬底200中的深度小于所述隔离结构210深入所述衬底200中的深度，即在所述衬底200内，所述位线沟槽230的底面设置于所述隔离结构210的底面之上。由于所述位线沟槽230设置在所述位线初级沟槽202的底部，则所述位线沟槽230的走向与所述位线初级沟槽202的走向相同，两者均呈“S”型走向。所述位线沟槽230的宽度小于所述位线初级沟槽202的宽度。
所述位线结构240包括位线241及隔离层242。所述位线241形成于所述位线沟槽230内，所述隔离层242覆盖所述位线241且填充所述位线沟槽230。在本实施例中，所述隔离层242还填充所述位线初级沟槽202。所述隔离层242的上表面与所述衬底200上表面平齐。
如图2J所示，所述字线结构250沿第三方向(如图2J所示D方向)延伸，且依次穿过所述有源区220及所述隔离结构210。所述第三方向(如图2J所述D方向)与所述第二方向(如图2J所述C方向)垂直，，并与所述第一方向(如图2J所述B方向)具有一夹角。在所述隔离结构210中，所述位线241位于所述字线结构250的下方，在所述有源区220中，所述位线241与所述字线结构250间隔设置。
所述字线结构250由多层结构构成，例如绝缘层、阻挡层、金属层及钝化层等。
在所述衬底200厚度方向上，在所述隔离结构210内所述字线结构250与所述位线241存在重叠区域，在所述有源区220内，所述字线结构250与所述位线241并不存在重叠区域。字线结构250包括穿过所述隔离结构210的第一字线结构250A和穿过所述有源区220的第二字线结构250B。穿过所述隔离结构210的第一字线结构250A的深度小于穿过所述有源区220的第二字线结构250B的深度，以避免在隔离结构210内，所述字线结构250与所述位线241短路。
如图2M所示，所述半导体装置还包括绝缘层260及导电插塞270。
所述绝缘层260设置在所述衬底200表面，并覆盖所述字线结构250、隔离层242及暴露的有源区220。
所述绝缘层260具有电容接触孔，所述电容接触孔贯穿所述绝缘层260至所述有源区220。导电插塞270形成于所述电容接触孔中，并与所述有源区220接触。所述导电插塞270用于将形成在所述衬底200上方的电容与有源区220电连接。
本申请的半导体装置采用“S”型埋入式位线结构，相较于传统的非埋入式的位线，不需要沉积在位线两侧沉积绝缘层，因此线宽可以显著降低，而且能显著避免非埋入式位线倒塌，扭曲造成的缺陷及良率损失。另外，由于位线埋入衬底内，使得电容接触孔的高度大大降低，电容接触孔直接在绝缘层上形成，极大的简化了电容接触孔的制造工艺，减少了电容接触孔的工艺难度和缺陷，有效的提高良率。同时，本申请的半导体装置并不需要设置位线接触垫(BLC)结构，极大的减少了制造成本和工艺程序。另外，本申请的半导体装置的位线位于字线结构下方，并且位线和字线重叠的位置形成高低差从而避免位线与字线结构短路，大大提高了半导体装置的性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。
工业实用性
本申请所提供的具有埋入式位线的半导体装置及其制备方法，半导体装置 中采用“S”型埋入式位线结构，线宽可以显著降低，而且能显著避免非埋入式位线倒塌，扭曲造成的缺陷及良率损失。另外，由于位线埋入衬底内，使得电容接触孔的高度大大降低，电容接触孔直接在绝缘层上形成，极大的简化了电容接触孔的制造工艺，减少了电容接触孔的工艺难度和缺陷，有效的提高良率。同时，半导体装置的制备方法不仅减少了制造成本和工艺程序，而且巧妙的构建了一种“S”型埋入式的位线结构避免短路。

Claims (15)

  1. 一种具有埋入式位线的半导体装置的制备方法，其特征在于，包括如下步骤：
    提供一衬底(200)，于所述衬底(200)中形成由隔离结构(210)界定的多个有源区(220)，所述有源区(220)沿第一方向延伸；
    形成位线沟槽(230)，所述位线沟槽(230)沿第二方向延伸，且所述位线沟槽(230)以S型走向依次穿过所述有源区(220)及所述隔离结构(210)，所述第二方向与所述第一方向呈锐角夹角；
    于所述位线沟槽(230)内形成位线结构(240)，所述位线结构(240)包括形成于所述位线沟槽(230)底部的位线(241)及覆盖所述位线(241)的隔离层(242)；
    于所述衬底(200)中形成字线结构(250)，所述字线结构(250)沿第三方向延伸，且依次穿过所述有源区(220)及所述隔离结构(210)，所述第三方向与所述第二方向垂直，在所述隔离结构(210)中，所述位线(241)位于所述字线结构(250)的下方，在所述有源区(220)中，所述位线(241)与所述字线结构(250)间隔设置。
  2. 根据权利要求1所述的具有埋入式位线的半导体装置的制备方法，其特征在于，于所述衬底(200)中形成由隔离结构(210)界定的多个有源区(220)的方法包括如下步骤：
    在所述衬底(200)中形成隔离结构(210)，所述衬底(200)被所述隔离结构(210)分为多个初级区域(201)；
    对所述初级区域(201)进行掺杂，形成所述有源区(220)。
  3. 根据权利要求2所述的具有埋入式位线的半导体装置的制备方法，其特征在于，对所述初级区域(201)进行掺杂，形成所述有源区(220)的步骤之前还包括如下步骤：
    于所述衬底(200)中形成位线初级沟槽(202)，所述位线初级沟槽(202)沿第二方向延伸，且所述位线初级沟槽(202)依次穿过所述有源区(220)及所述隔离结构(210)，所述位线初级沟槽(202)的走向与所述位线沟槽(230) 的走向相同；
    在对所述初级区域(201)进行掺杂，形成所述有源区(220)的步骤中，所述有源区(220)包括高度不同的第一掺杂区域(220A)及第二掺杂区域(220B)，其中，所述第一掺杂区域(220A)为所述位线初级沟槽(202)下方的区域，所述第二掺杂区域(220B)为所述位线初级沟槽(202)侧方的区域。
  4. 根据权利要求3所述的具有埋入式位线的半导体装置的制备方法，其特征在于，在形成所述位线沟槽(230)的步骤中，在所述位线初级沟槽(202)底部形成所述位线沟槽(230)，且所述位线沟槽(230)的宽度小于所述位线初级沟槽(202)的宽度。
  5. 根据权利要求4所述的具有埋入式位线的半导体装置的制备方法，其特征在于，于所述位线沟槽(230)底部形成位线(241)，并形成覆盖所述位线(241)的隔离层(242)的步骤中，所述隔离层(242)还填充所述位线初级沟槽(202)。
  6. 根据权利要求1所述的具有埋入式位线的半导体装置的制备方法，其特征在于，于所述衬底(200)中形成字线结构(250)的步骤之前还包括自所述有源区(220)上表面减薄所述有源区(220)的步骤。
  7. 根据权利要求1所述的具有埋入式位线的半导体装置的制备方法，其特征在于，穿过所述隔离结构(210)的字线结构(250)的深度小于穿过所述有源区(220)的字线结构(250)的深度。
  8. 根据权利要求1所述的具有埋入式位线的半导体装置的制备方法，其特征在于，于所述衬底(200)中形成字线结构(250)的步骤之后还包括于所述衬底(200)表面形成绝缘层(260)的步骤。
  9. 根据权利要求8所述的具有埋入式位线的半导体装置的制备方法，其特征在于，于所述衬底(200)表面形成绝缘层(260)的步骤之后还包括如下步骤：
    形成电容接触孔，所述电容接触孔贯穿所述绝缘层(260)至所述有源区(220)；
    在所述电容接触孔中形成导电插塞，所述导电插塞与所述有源区(220)接触。
  10. 根据权利要求3所述的具有埋入式位线的半导体装置的制备方法，其特征在于，所述第一掺杂区域(220A)的高度小于所述第二掺杂区域(220B)的高度。
  11. 一种具有埋入式位线的半导体装置，其特征在于，包括：
    衬底(200)，所述衬底(200)中设置有由隔离结构(210)界定的多个有源区(220)，所述有源区(220)沿第一方向延伸；
    位线沟槽(230)，沿第二方向延伸，且所述位线沟槽(230)以S型走向依次穿过所述有源区(220)及所述隔离结构(210)，所述第二方向与所述第一方向呈锐角夹角；
    位线结构(240)，包括位线(241)及隔离层(242)，所述位线(241)形成于所述位线沟槽(230)内，所述隔离层(242)覆盖所述位线(241)且填充所述位线沟槽(230)；
    字线结构(250)，沿第三方向延伸，且依次穿过所述有源区(220)及所述隔离结构(210)，所述第三方向与所述第二方向垂直，在所述隔离结构(210)中，所述位线(241)位于所述字线结构(250)的下方，在所述有源区(220)中，所述位线(241)与所述字线结构(250)间隔设置。
  12. 根据权利要求11所述的具有埋入式位线的半导体装置，其特征在于，所述衬底(200)还包括位线初级沟槽(202)，所述位线初级沟槽(202)沿第二方向延伸，且所述位线初级沟槽(202)依次穿过所述有源区(220)及所述隔离结构(210)，所述位线初级沟槽(202)的走向与所述位线沟槽(230)的走向相同，所述有源区(220)包括位于所述位线初级沟槽(202)下方的第一掺杂区域(220A)及位于所述位线初级沟槽(202)侧方的第二掺杂区域(220B)，所述位线沟槽(230)位于所述第一掺杂区域(220A)，且所述隔离层(242)还填充所述位线初级沟槽(202)。
  13. 根据权利要求12所述的具有埋入式位线的半导体装置，其特征在于，所述位线沟槽(230)的宽度小于所述位线初级沟槽(202)的宽度。
  14. 根据权利要求12所述的具有埋入式位线的半导体装置，其特征在于，穿过所述隔离结构(210)的字线结构(250)的深度小于穿过所述有源区(220)的字线结构(250)的深度。
  15. 根据权利要求11所述的具有埋入式位线的半导体装置，其特征在于，还包括：
    绝缘层(260)，设置在所述衬底(200)表面，所述绝缘层(260)具有电容接触孔，所述电容接触孔贯穿所述绝缘层(260)至所述有源区(220)；
    导电插塞，形成于所述电容接触孔中，并与所述有源区(220)接触。
PCT/CN2021/103087 2020-11-12 2021-06-29 具有埋入式位线的半导体装置及其制备方法 Ceased WO2022100104A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/599,393 US12120868B2 (en) 2020-11-12 2021-06-29 Semiconductor device with buried bit line and preparation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011261602.4A CN114496929B (zh) 2020-11-12 2020-11-12 具有埋入式位线的半导体装置及其制备方法
CN202011261602.4 2020-11-12

Publications (1)

Publication Number Publication Date
WO2022100104A1 true WO2022100104A1 (zh) 2022-05-19

Family

ID=81490539

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/103087 Ceased WO2022100104A1 (zh) 2020-11-12 2021-06-29 具有埋入式位线的半导体装置及其制备方法

Country Status (3)

Country Link
US (1) US12120868B2 (zh)
CN (1) CN114496929B (zh)
WO (1) WO2022100104A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117545274B (zh) * 2024-01-08 2024-05-03 长鑫新桥存储技术有限公司 一种半导体结构及其制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096669A1 (en) * 2008-10-16 2010-04-22 Qimonda Ag Memory cell array comprising wiggled bit lines
CN102034824A (zh) * 2009-09-24 2011-04-27 三星电子株式会社 包括掩埋字线的半导体器件
CN102339831A (zh) * 2010-07-20 2012-02-01 力晶科技股份有限公司 垂直沟道晶体管阵列及其制造方法
CN102610612A (zh) * 2011-01-18 2012-07-25 力晶科技股份有限公司 垂直沟道晶体管阵列及其制造方法
CN106992156A (zh) * 2016-01-21 2017-07-28 美光科技公司 存储器阵列及其制造方法
US20190273082A1 (en) * 2014-09-18 2019-09-05 Micron Technology, Inc. Semiconductor Device Having a Memory Cell and Method of Forming the Same
CN111900164A (zh) * 2020-06-22 2020-11-06 中国科学院微电子研究所 半导体结构及制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091094A (en) * 1998-06-11 2000-07-18 Siemens Aktiengesellschaft Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips
JP2012248686A (ja) * 2011-05-27 2012-12-13 Elpida Memory Inc 半導体装置及びその製造方法
CN108878424B (zh) * 2018-06-25 2024-03-29 长鑫存储技术有限公司 一种采用埋入式位线的晶体管结构及其制造方法
KR102611116B1 (ko) * 2018-08-16 2023-12-08 에스케이하이닉스 주식회사 반도체 메모리 장치
CN111223860B (zh) * 2018-11-27 2024-05-21 长鑫存储技术有限公司 半导体器件及其制备方法
TWI685841B (zh) * 2019-03-08 2020-02-21 華邦電子股份有限公司 動態隨機存取記憶體及其製造方法
CN116825838B (zh) * 2022-03-17 2026-01-23 长鑫存储技术有限公司 半导体结构及其制造方法、存储器及其制造方法
CN114639721B (zh) * 2022-04-29 2022-08-05 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法
CN115642129B (zh) * 2022-08-05 2025-09-19 长鑫存储技术有限公司 半导体结构及其制作方法、存储器
US20240057312A1 (en) * 2022-08-09 2024-02-15 Changxin Memory Technologies, Inc. Array structure, semiconductor structure, and method for manufacturing semiconductor structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096669A1 (en) * 2008-10-16 2010-04-22 Qimonda Ag Memory cell array comprising wiggled bit lines
CN102034824A (zh) * 2009-09-24 2011-04-27 三星电子株式会社 包括掩埋字线的半导体器件
CN102339831A (zh) * 2010-07-20 2012-02-01 力晶科技股份有限公司 垂直沟道晶体管阵列及其制造方法
CN102610612A (zh) * 2011-01-18 2012-07-25 力晶科技股份有限公司 垂直沟道晶体管阵列及其制造方法
US20190273082A1 (en) * 2014-09-18 2019-09-05 Micron Technology, Inc. Semiconductor Device Having a Memory Cell and Method of Forming the Same
CN106992156A (zh) * 2016-01-21 2017-07-28 美光科技公司 存储器阵列及其制造方法
CN111900164A (zh) * 2020-06-22 2020-11-06 中国科学院微电子研究所 半导体结构及制备方法

Also Published As

Publication number Publication date
US12120868B2 (en) 2024-10-15
US20230103902A1 (en) 2023-04-06
CN114496929B (zh) 2023-10-31
CN114496929A (zh) 2022-05-13

Similar Documents

Publication Publication Date Title
TWI615921B (zh) 記憶體陣列中具有共平面數位線接觸結構及儲存節點接觸結構的半導體記憶體元件及其製作方法
TWI841912B (zh) 半導體記憶體裝置
US20190035806A1 (en) Semiconductor devices
CN113035872A (zh) 半导体结构及其制作方法
JP2002026293A (ja) 自己整合コンタクトを有する半導体メモリ素子およびその製造方法
US7271056B2 (en) Method of fabricating a trench capacitor DRAM device
CN115312466A (zh) 半导体结构及其形成方法
CN116133414A (zh) 半导体存储器件及其制造方法
CN115132664B (zh) 半导体结构及其形成方法
TWI675453B (zh) 記憶體元件及其製造方法
US12120868B2 (en) Semiconductor device with buried bit line and preparation method thereof
TW202320065A (zh) 半導體記憶體裝置
CN116546814B (zh) 半导体结构及其形成方法、存储器
EP4195898A1 (en) Semiconductor memory devices and methods of fabricating the same
TW202404043A (zh) 半導體元件
CN115472610A (zh) 半导体存储装置及其制作方法
KR20090012834A (ko) 반도체 소자 및 그 제조 방법
US20250071980A1 (en) Semiconductor device
TWI892745B (zh) 半導體裝置及其形成方法
US20240023319A1 (en) Semiconductor device
CN113764416B (zh) 半导体结构及其形成方法、动态随机存储器、电子设备
EP4340563A1 (en) Preparation method for semiconductor structure, and semiconductor structure
WO2023245722A1 (zh) 半导体结构及其形成方法、存储器
TW202420567A (zh) 半導體裝置
KR20260029779A (ko) 반도체 장치 및 그 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21890635

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21890635

Country of ref document: EP

Kind code of ref document: A1