WO2022083597A1 - 3d nand存储器及其形成方法 - Google Patents

3d nand存储器及其形成方法 Download PDF

Info

Publication number
WO2022083597A1
WO2022083597A1 PCT/CN2021/124789 CN2021124789W WO2022083597A1 WO 2022083597 A1 WO2022083597 A1 WO 2022083597A1 CN 2021124789 W CN2021124789 W CN 2021124789W WO 2022083597 A1 WO2022083597 A1 WO 2022083597A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
hole
forming
metal
metal silicide
Prior art date
Application number
PCT/CN2021/124789
Other languages
English (en)
French (fr)
Inventor
宋豪杰
高倩
鲍琨
何欢
黄亚俊
马艳三
Original Assignee
长江存储科技有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN202180010962.3A priority Critical patent/CN115004368A/zh
Publication of WO2022083597A1 publication Critical patent/WO2022083597A1/zh
Priority to US18/090,440 priority patent/US20230142924A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • the present disclosure relates to a 3D NAND memory and a method of forming the same.
  • NAND flash memory is a better storage device than hard disk drives, and has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and good performance.
  • the NAND flash memory with a planar structure is approaching the limit of practical expansion.
  • a NAND memory with a 3D structure is proposed.
  • the present disclosure provides a method for forming a 3D NAND memory, including:
  • a semiconductor substrate is provided, the semiconductor substrate has a well region, a stack structure in which sacrificial layers and isolation layers are alternately stacked is formed on the well region of the semiconductor substrate, and an end of the stack structure has a step structure;
  • the polysilicon layer having a surface lower than the top surface of the dielectric layer
  • a first contact plug connected to the second metal silicide layer is formed in the first through hole, and a second contact plug connected to the surface of the corresponding step structure is formed in the second through hole.
  • the formation process of the first metal silicide layer and the through hole contact metal layer is: forming a first metal layer in the channel through hole on the surface of the dielectric layer and the polysilicon layer; annealing is performed to make the first metal layer react with a part of the polysilicon layer on the storage structure, and a first metal silicide layer is formed on the surface of the polysilicon layer, and the surface of the first metal silicide layer is lower than the surface of the polysilicon layer.
  • the top surface of the dielectric layer; the unreacted first metal layer is removed, and a through hole is formed on the surface of the first metal silicide layer to contact the metal layer, and the through hole contacts the surface of the metal layer and the top surface of the dielectric layer. flush.
  • the material of the first metal silicide layer is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide, or a combination thereof.
  • the formation process of the control gate structure is as follows: forming a hard mask layer on the stack structure; forming gate isolation grooves in the hard mask layer and the stack structure; forming a gate isolation groove along the gate isolation groove removing the sacrificial layer; forming a control gate structure at the position where the sacrificial layer is removed; forming an array common source in the gate spacer.
  • the method further includes: forming in the hard mask layer a bit line connected to the through hole contact metal layer, the size of the bit line being smaller than that of the through hole contact metal layer.
  • the formation process of the second metal silicide layer, the first contact plug, the second contact plug, and the bit line includes: etching the hard mask layer and the dielectric layer, and in the hard mask forming a first through hole exposing the surface of a portion of the well region on one side of the stack structure and a plurality of second through holes exposing the surface of the corresponding step structure in the layer and the dielectric layer, and forming an exposing through hole in the hard mask layer a third through hole on the surface of a part of the metal layer, the size of the third through hole is smaller than the size of the through hole contacting the metal layer; a second metal is formed in the first through hole and on the surface of the hard mask layer annealing to make the second metal layer react with silicon in the well region to form a second metal silicide layer on the surface of the well region; removing the unreacted second metal layer; in the first through hole A metal layer is filled in the second through hole and the third through hole, a first contact plug connected to the second metal silicide layer
  • the second metal silicide layer material is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide or a combination thereof
  • the storage structure includes a charge storage layer on the sidewall surface of the channel through hole and a channel layer on the sidewall surface of the charge storage layer.
  • the charge storage layer includes a blocking layer on the sidewall surface of the channel through hole, a charge trapping layer on the sidewall surface of the blocking layer, and a tunneling layer on the sidewall surface of the charge trapping layer.
  • control gate structure includes a gate dielectric layer and a gate electrode on the gate dielectric layer.
  • the forming process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line includes: etching the hard mask layer and the dielectric layer, and the hard mask layer and the dielectric layer are etched. forming a first through hole in the dielectric layer exposing the surface of a portion of the well region on one side of the stack structure and a plurality of second through holes exposing the surface of the corresponding step structure, and forming in the hard mask layer exposing the through hole contact a third through hole on a part of the surface of the metal layer, the size of the third through hole is smaller than the size of the through hole contacting the metal layer; a second metal layer is formed in the first through hole and on the surface of the hard mask layer; Perform annealing to make the second metal layer react with the silicon in the well region to form a second metal silicide layer on the surface of the well region; remove the unreacted second metal layer; The second through hole and the third through hole are filled with a metal layer, a first contact plug connected to the second
  • 1A-1D are schematic cross-sectional structural diagrams of a formation process of a 3D NAND memory
  • 2-10 are schematic cross-sectional structural diagrams of the formation process of the 3D NAND memory provided by some embodiments of the present disclosure.
  • the thickness of the first metal silicide layer formed in the related art is difficult to meet the performance requirements.
  • FIG. 1A-1D are schematic cross-sectional structural diagrams of a formation process of a 3D NAND memory.
  • a semiconductor structure includes: a semiconductor substrate 10 having a well region 20 in the semiconductor substrate; One end has a stepped structure 21; the first dielectric layer 15 covering the stacked structure 12 and the semiconductor substrate 10 on one side of the stacked structure 12; a channel through hole penetrating the first dielectric layer 15 and the stacked structure 12, located in the channel through hole The channel structure 18 and the polysilicon layer 19 in the remaining channel vias on the channel structure 18 .
  • the channel structure 18 includes a charge storage layer 17 on the surface of the sidewall of the channel through hole and a channel layer 16 on the surface of the charge storage layer 17 .
  • a mask layer 22 is formed on the stacked structure 12 ; a gate spacer (Gate Line Slite, GLS) 23 is formed in the mask layer 22 and the stacked structure 12 ; a dielectric material is formed in the gate spacer 23 layer (eg, oxide sidewalls); removing the sacrificial layer along the gate spacer 23; forming a control gate structure 131 where the sacrificial layer is removed.
  • An array common source (Array Common Source, ACS) 24 is formed in the gate spacer 23 (eg, in the gate spacer 23 formed in the oxide sidewall).
  • the material of the mask layer 22 may be the same as the material of the dielectric material layer formed in the gate spacer 23 .
  • a first through hole exposing part of the surface of the well region 20 on one side of the stack structure 12 and exposing the surface of the corresponding step structure 21 are formed in the mask layer 22 and the first dielectric layer 15 by a first photolithography process
  • a plurality of second through holes are formed in the mask layer 22
  • bit line contact through holes exposing the polysilicon layer 19 are formed in the mask layer 22 .
  • a first metal silicide layer 26 and a second metal silicide layer 25 are formed in the bit line contact through hole and the first through hole, respectively.
  • the first contact plug 27 needs to have a lower contact resistance when connecting with the well region, so When forming the second metal silicide layer 25, more metal needs to be deposited to form a thicker second metal silicide layer 25, and the hole depth on the channel structure is shallower, if the same amount of metal is deposited in the same process step. metal, the thickness of the first metal silicide layer 26 formed by annealing in the bit line contact via will be thicker.
  • the inventors of the present disclosure have noticed during research that when the first metal silicide layer is formed on the channel hole in the related art, a void is easily formed at the conductive plug of the channel hole. ), resulting in increased contact resistance, resulting in a small overall channel current and degradation of the low-temperature characteristics of the device.
  • the metal layer material is filled in the first through holes, the second through holes, the bit line contact through holes and the remaining gate spacers on the array common source 24 to form the first contact plugs 27, the second contact plugs 30, Bit line contact plugs (Bit Line Via) 28 and fourth contact plugs 29 . Since the bitline contact via is formed in the same step as the first via, the diameter of the bitline contact via may be different from the diameter of the polysilicon layer 19 , eg, the diameters of the bitline contact via and the bitline contact plug 28 smaller than the diameter of the polysilicon layer 19 .
  • a second dielectric layer 31 is formed on the mask layer 22, and a fourth through hole exposing the bit line contact plug 28 is formed in the second dielectric layer 31 by a second photolithography process.
  • the diameter of the bit line contact structure in the quad via is reduced, for example, it is smaller than the diameter of the channel via or the first metal silicide layer, so the diameter of the formed fourth via is smaller than that of the bit line contact.
  • the diameter of the hole, the fourth through hole is filled with conductive material to form the bit line connection structure 32, and the diameter of the finally formed bit line connection structure 32 is smaller than the diameter of the channel through hole or the first metal silicide layer.
  • the bit line connection structure 32 is in conductive contact with the first metal silicide layer 26 through the bit line contact plug 28 .
  • the inventor of the present disclosure found through research that the thickness of the first metal silicide layer formed in the related art would be too thick, which does not meet the performance requirements. Further research found that the existing first metal silicide layer and the second metal silicide layer formed in the same process step. However, since a lower contact resistance is required when the first contact plug is connected to the well region, more metal needs to be deposited to form a thicker second metal silicide layer when forming the second metal silicide layer. Due to the hole depth of the first via hole, the hole depth of the bit line contact via hole on the channel structure is shallower. If the same amount of metal is deposited in the same process step, the bit line contact via hole with the shallower hole depth will be formed by annealing.
  • the thickness of the first metal silicide layer will be thicker, that is, the thickness of the first metal silicide layer formed in the bit line contact via hole with a shallower hole depth is greater than the thickness of the second metal layer formed in the first via hole with a deeper hole depth The thickness of the silicide layer.
  • the photolithography process for forming the bit line connection structure is not compatible with the photolithography process for forming the first metal silicide layer and the second metal silicide layer.
  • the present disclosure provides a method of forming a 3D NAND memory by forming a memory structure in a channel via hole and a polysilicon layer on the memory structure, the polysilicon layer having a surface lower than a top surface of the dielectric layer after that, forming a first metal silicide layer and a through-hole contact metal layer on the surface of the polysilicon layer; replacing the sacrificial layer with a control gate structure; forming an exposed layer in the dielectric layer forming a first through hole on the surface of a portion of the well region on one side of the stack structure and a plurality of second through holes exposing the surface of the corresponding step structure; forming a second metal silicide layer on the surface of the well region at the bottom of the first through hole; A first contact plug connected to the second metal silicide layer is formed in the first through hole, and a second contact plug connected to the surface of the corresponding step structure is formed in the second through hole.
  • the step of forming the first metal silicide layer and the subsequent step of forming the second metal silicide are not performed in the same step, so when forming the first metal silicide, the thickness of the first metal silicide layer to be formed can be adjusted independently, so that the first metal silicide layer is formed.
  • the thickness of a metal silicide layer is not limited by the process of forming the second metal silicide layer, so that the thickness of the formed first metal silicide layer meets the performance requirements, so as to reduce the probability of the occurrence of holes in the first metal silicide layer And the probability of increased contact resistance and decreased yield.
  • 2-10 are schematic cross-sectional structural diagrams of the formation process of the 3D NAND memory provided by some embodiments of the present disclosure.
  • the formation method of the 3D NAND memory described in the present disclosure is not limited to being used to form a 3D NAND memory, but can also be used to form a three-dimensional non-volatile memory such as a 3D Re-RAM memory and a 3D PCM memory.
  • the semiconductor layer may be the semiconductor substrate 100 , and for the convenience of description, the semiconductor layer will be described as the semiconductor substrate 100 hereinafter, but the embodiments of the present disclosure are not limited thereto.
  • the semiconductor substrate 100 has a well region 110 , a stack structure 111 in which sacrificial layers 103 and isolation layers 104 are alternately stacked is formed on the well region 110 of the semiconductor substrate, and an end of the stack structure 111 has steps structure 11; forming a dielectric layer 105 covering the semiconductor substrate 100 and the stacked structure 111; forming a number of channel vias in the dielectric layer 105 and the stacked structure 111 through the thickness of the stacked structure; A storage structure 108 and a polysilicon layer 111 located on the storage structure 108 are formed in the storage structure 108 .
  • each channel through hole is provided with a channel structure, and the channel through hole and the channel structure constitute a channel hole.
  • the storage structure 108 is the channel
  • the material of the semiconductor layer may include (eg, may be) any one of single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), polycrystalline silicon or any combination; it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide and other III-V compounds.
  • the material of the semiconductor substrate 100 is single crystal silicon (Si).
  • the semiconductor substrate 100 has a well region 110 therein.
  • the well region 110 may be a P-type well region.
  • the well region 110 may be an N-type well region.
  • the stacked structure 111 includes several alternately stacked sacrificial layers 103 and isolation layers 104 (eg, electrical isolation layers, insulating layers), the sacrificial layers 103 are subsequently removed to form a cavity, and then a control is formed where the sacrificial layer 103 is removed.
  • Gate structure (Word line).
  • the isolation layer 104 serves as electrical isolation between the control gates of different layers, and between the control gates and other devices (conductive contacts, channel holes, etc.).
  • the sacrificial layer may include a dielectric material, a semiconductor material, or a conductive material.
  • the isolation layer may include electrical isolation material, insulating material, or dielectric material.
  • the alternate stacking of the sacrificial layers 103 and the isolation layers 104 includes the alternate arrangement of the sacrificial layers 103 and the isolation layers 104 .
  • the alternate stacking of the sacrificial layer 103 and the isolation layer 104 may be that after a layer of the sacrificial layer 103 is formed, a layer of the isolation layer 104 is formed on the surface of the sacrificial layer 103, and then the sacrificial layer 103 and Step of isolation layer 104 on sacrificial layer 103 .
  • the bottommost layer of the stacked structure 111 is a sacrificial layer 103
  • the topmost layer is a layer of isolation layer 104
  • a buffer oxide layer 101 is also formed between the bottommost layer of the stacked structure 111 and the semiconductor substrate 100 .
  • a buffer oxide layer 101 is further formed between the stacked structure 111 and the semiconductor substrate 100 .
  • the number of layers of the stack structure 111 (the number of layers of the double-layer stack structure of the sacrificial layer 103 and the isolation layer 104 in the stack structure 111 ) is determined according to the number of memory cells to be formed in the vertical direction.
  • the number of layers of the stack structure 111 may be 8 layers, 32 layers, 64 layers, etc.
  • the materials of the sacrificial layer 103 and the isolation layer 104 are different.
  • the sacrificial layer 103 has a high etching selectivity ratio relative to the isolation layer 104. Therefore, when the sacrificial layer 103 is removed, the isolation layer 104 The amount of etching is small or negligible to ensure the flatness of the isolation layer 104 .
  • the material of the isolation layer 104 can be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride carbide, and the material of the sacrificial layer 103 can be silicon oxide, silicon nitride, silicon oxynitride, and carbon nitride.
  • the material of the isolation layer 104 is silicon oxide
  • the material of the sacrificial layer 103 is silicon nitride
  • the isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.
  • the bottommost sacrificial layer 103 in the stacked structure 111 can be used as a bottom select gate sacrificial layer, and a bottom select gate (BSG) can be correspondingly formed at the position where the bottom select gate sacrificial layer is removed subsequently.
  • the topmost sacrificial layer 103 in the first stack structure 111 is used as the top selective gate sacrificial layer, and a top selective gate (TSG) is formed correspondingly at the position where the top selective gate sacrificial layer is removed.
  • one end of the stacked structure 111 has a stepped structure 11 , and the stepped structure 11 includes several steps that are gradually raised in a stepped shape.
  • the top surface of the dielectric layer 105 is higher than the top surface of the stacked structure 111 , and the material of the dielectric layer 105 is silicon oxide.
  • the forming process for forming the dielectric layer 105 may be plasma enhanced chemical vapor deposition deposition process, atmospheric pressure chemical vapor deposition process, low pressure chemical vapor deposition process, high density plasma chemical vapor deposition process or atomic layer chemical vapor deposition process.
  • the semiconductor substrate 100 exposed at the bottom of the through-channel holes is continuously etched to form recesses in the semiconductor substrate 100 .
  • the material is silicon, germanium or silicon germanium;
  • a storage structure 108 is formed on the semiconductor epitaxial layer, and the surface of the storage structure 108 is lower than the surface of the dielectric layer 105; the remaining channel via holes are formed on the storage structure 108
  • the polysilicon layer 109 for example, the surface of the polysilicon 109 is flush with the surface of the dielectric layer 105 .
  • Each channel through hole is provided with a channel structure, and the channel through hole and the channel structure constitute a channel hole.
  • the storage structure 108 includes a charge storage layer 107 located on the sidewall surface of the channel through hole and a channel layer 106 located on the surface of the charge storage layer 107 .
  • the charge storage layer 107 may be a charge storage functional layer including a stacked charge blocking layer, a charge trapping layer, and a tunneling layer.
  • the method for forming the charge storage functional layer includes: forming a charge blocking layer on the surface of the sidewall of the channel through hole; forming a charge trapping layer on the surface of the charge blocking layer; and forming a tunnel layer on the surface of the charge trapping layer.
  • the material of the charge blocking layer and the tunnel layer may be the same, for example, the material of the charge blocking layer and the tunnel layer is a silicon oxide layer, and the material of the charge trapping layer is a silicon nitride layer.
  • the charge storage layer 107 includes a blocking layer on the sidewall surface of the channel via, a charge trapping layer on the sidewall surface of the blocking layer, and a tunneling layer on the sidewall surface of the charge trapping layer.
  • the material of the blocking layer and the tunneling layer is silicon oxide
  • the material of the charge trapping layer is silicon nitride
  • the material of the channel layer 106 is polysilicon.
  • the polysilicon layer 109 is etched back so that the surface of the remaining polysilicon layer 109 is lower than the surface of the dielectric layer 105 .
  • the polysilicon layer can be etched back by using a wet etching process or an isotropic plasma etching process.
  • the polysilicon layer may be etched back through an etching process, so that the surface of the remaining polysilicon layer 109 is lower than the surface of the dielectric layer 105, thereby forming a recess at the polysilicon layer of the channel via.
  • the etching rate of the selected etching material for the polysilicon layer is greater than that for the dielectric layer 105.
  • the dielectric layer 105 and the charge storage functional layer (tunnel layer) of the channel structure Through layer) can be used as an etch stop layer for etching the polysilicon layer, so that the polysilicon layer can be etched without an additional mask layer, thereby reducing the number of masks required for the process.
  • the first metal silicide layer and the through hole contact metal layer can be formed in the recess.
  • the via contact metal layer may be a bit line contact plug.
  • the polysilicon layer 109 is etched back to the position where the first metal silicide layer and the through hole contact metal layer on the first metal silicide layer can be subsequently formed.
  • the first metal silicide layer and the via contact metal layer are formed within the channel via.
  • the diameter of the via contact metal layer is equal to the diameter of the polysilicon layer 109.
  • the diameter of the via contact metal layer is equal to the diameter of the first metal silicide layer.
  • a first metal silicide layer 112 (refer to FIG. 4 ) and a via contact metal layer 113 (refer to FIG. 5 ) on the first metal silicide layer 112 are formed on the surface of the polysilicon layer 109 .
  • the formation process of the first metal silicide layer 112 and the through hole contact metal layer 113 is as follows: forming a first metal layer on the surface of the dielectric layer 105 and the channel through holes on the polysilicon layer 109 (not shown in the figure); annealing the first metal layer to make the first metal layer react with part of the polysilicon layer 109 on the storage structure to form a first metal silicide on the surface of the polysilicon layer 109 layer 112, the surface of the first metal silicide layer 112 is lower than the top surface of the dielectric layer 105; the unreacted first metal layer is removed, and a via hole is formed on the surface of the first metal silicide layer 112 to contact the metal Layer 113 , the surface of the via contact metal layer 113 is flush with the top surface of the dielectric layer 105 .
  • the material of the via-contact metal layer is different from the material of the first metal layer.
  • the material of the first metal layer is one or more of nickel, cobalt, tantalum and titanium.
  • the first metal layer is formed by sputtering, and the thickness of the first metal layer is smaller than the radius of the channel through hole.
  • the annealing includes a first annealing and a second annealing performed at one time, and the temperature of the second annealing is higher than that of the first annealing.
  • the first annealing is immersion annealing
  • the annealing temperature is 220-320 degrees Celsius
  • the annealing time is 30-90 seconds
  • the second annealing is millisecond annealing
  • the annealing temperature is 700-950 degrees Celsius
  • the annealing temperature is 700-950 degrees Celsius.
  • the duration is 0.25-20 milliseconds.
  • a wet etching process may be used to remove the unreacted first metal layer.
  • the material of the first metal silicide layer 112 to be formed is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide, or a combination thereof.
  • the step of forming the first metal silicide layer 112 and the subsequent step of forming the second metal silicide are not performed in the same step, so by adjusting the thickness of the first metal layer separately, the formation of The thickness of the first metal silicide layer 112 is determined so that the thickness of the first metal silicide layer is not limited by the process of forming the second metal silicide layer, so that the thickness of the first metal silicide layer 112 meets the performance requirements.
  • the thickness of the first metal layer is 7 nm-50 nm
  • the thickness of the first metal silicide layer 112 is 7 nm-50 nm.
  • the formation process of the through-hole contact metal layer 113 is as follows: forming a metal layer on the dielectric layer 105 and the first metal silicide 112; planarizing and removing the metal layer higher than the surface of the dielectric layer 105; A through-hole contact metal layer 113 is formed on a metal silicide layer 112 .
  • the through-hole contact metal layer 113 is subsequently used for connection with the bit line, and when the second metal silicide layer is subsequently formed, the second metal layer can be isolated from the first metal silicide layer 112 to prevent the formation of the first metal silicide layer.
  • the thickness of the silicide layer 112 is changed, and the through hole contact metal layer 113 can also serve as an etch stop layer when the third through hole is subsequently formed in the hard mask layer.
  • the via contact metal layer 113 is a bit line contact plug (Bit Line Via).
  • the subsequently formed bit line connection structure is in conductive contact with the first metal silicide layer through the bit line contact plug.
  • the bit line contact plugs are formed in the channel vias without passing through an additional mask layer to form the bit line contact plugs.
  • the material of the through hole contact metal layer 113 may be tungsten.
  • the sacrificial layer is replaced with a control gate structure 123 .
  • the formation process of the control gate structure 123 is as follows: forming a hard mask layer 114 on the stacked structure 111 ; forming gate isolation trenches 115 in the hard mask layer 114 and the stacked structure 111 ; Remove the sacrificial layer along the gate spacer 115 ; form a control gate structure 113 at the position where the sacrificial layer is removed.
  • the method further includes removing the hard mask layer 114 and forming a second dielectric layer on the dielectric layer 105 .
  • the location of the second dielectric layer is the same as that of the hard mask layer 114 in FIGS. 6-10 .
  • the location of the second dielectric layer is the same as that of the hard mask layer 114 in FIGS. 6-10 (ie, the hard mask layer 114 in FIGS. 6-10 is replaced by the second dielectric layer)
  • the second dielectric layer includes (eg, is) silicon oxide.
  • the hard mask layer 114 may be a single layer or a multi-layer stack structure.
  • the material of the hard mask layer 114 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
  • a bottom select gate (BSG) 122 may be formed at a corresponding position after removing the bottommost sacrificial layer (bottom select gate sacrificial layer) in the stack structure.
  • a top select gate (TSG) 124 may be formed at a corresponding position after the topmost sacrificial layer (top select gate sacrificial layer) is removed. The bottom select gate sacrificial layer and the top select gate sacrificial layer are removed simultaneously with other sacrificial layers, and the bottom select gate 122 and the top select gate 124 are formed simultaneously with the control gate structure 133 .
  • the control gate structure 103 includes a gate dielectric layer and a gate electrode on the gate dielectric layer.
  • the control gate structure 103 may be a high-K dielectric layer and a metal gate located on the surface of the high-K dielectric layer, and the material of the metal gate may be W, Al, Cu, Ti, Ag, Au , Pt, Ni one or more.
  • the material of the high-K dielectric layer is HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 or BaSrTiO.
  • the control gate structure 103 may include a silicon oxide dielectric layer and a polysilicon gate on the dielectric layer.
  • an array common source (Array Common Source, ACS) 116 is formed in the gate spacer (Gate Line Slite, GLS) 115 (refer to FIG. 6 ).
  • isolation spacers are formed on the sidewalls of the gate spacers 115 .
  • the isolation spacers include electrical isolation layers (eg, dielectric layers) deposited on the sidewalls of the gate spacers 115 .
  • the Array Common Source (ACS) 116 includes a conductive layer of a conductive material such as titanium nitride, W, Co, Cu, Al, doped silicon, or silicide, and the electrical isolation layer may be a silicon oxide layer and other insulating material layers.
  • the surface on which the array common source electrode 116 is formed is lower than the surface of the hard mask layer 114 , and the material of the array common source electrode 116 is a polysilicon layer.
  • a patterned photoresist layer 130 is formed on the hard mask layer 114; using the patterned photoresist layer 130 as a mask, the hard mask layer 114 and the dielectric layer are etched 105 , in the hard mask layer 114 and the dielectric layer 105 , a first through hole 117 exposing a part of the surface of the well region 110 on one side of the stack structure 111 and a plurality of second through holes exposing the surface of the corresponding step structure 11 are formed 118 , and form a third through hole 119 in the hard mask layer 114 that exposes part of the surface of the through hole contact metal layer 113 , and the size of the third through hole 119 is smaller than the size of the through hole contact metal layer 113 .
  • a first contact plug connected to the well region 110 is subsequently formed in the first through hole 117
  • a second contact plug connected to the stepped structure 11 is subsequently formed in the second through hole 118
  • the third through hole In step 119, a bit line connection structure (Bit Line contact) connected to the via contact metal layer 113 is subsequently formed.
  • the thickness of the via contact metal layer (bit line contact plug) is smaller than that of the bit line connection structure.
  • the size of the third through hole 119 is smaller than the size of the through hole contact metal layer 113 (or the channel through hole), and the corresponding diameter of the subsequently formed bit line connection structure is smaller than that of the through hole contact metal layer 113 (or the channel through hole).
  • the diameter of the via hole so that the diameter of the formed bit line connection structure can be smaller.
  • the diameter of the third through hole 119 may be 1/4-2/3 of the diameter of the through hole contacting the metal layer 113 (or the channel through hole).
  • the hard mask layer 114 and the dielectric layer 105 may be etched by an anisotropic dry etching process, such as an anisotropic plasma etching process.
  • an anisotropic dry etching process such as an anisotropic plasma etching process.
  • the materials of the hard mask layer and the dielectric layer are the same.
  • the first metal silicide layer 112 is formed first, and then the second metal silicide layer is formed, not only the thickness of the first metal silicide layer 112 can be individually controlled, but the performance requirements are met.
  • the first metal silicide layer 112 it is not necessary to form a mask layer (the position of the first metal silicide layer 112 is directly defined by the channel via), and the second metal silicide layer and the first contact plug,
  • the second contact plug and the bit line connection structure only need to be formed by one photolithography process, and a bit line connection structure with a smaller diameter can be formed by one photolithography process, which saves the cost.
  • the thickness of the first metal silicide layer 112 can be individually controlled.
  • the thickness of the first metal silicide layer and the thickness of the second metal silicide layer can also be made the same.
  • the first metal silicide layer 112 is formed first, and then the second metal silicide layer is formed, not only the thickness of the first metal silicide layer 112 can be individually controlled to meet performance requirements, but also When the first through hole 117 and the third through hole 119 are formed through the hard mask layer 114, since the first metal silicide layer 112 has already been formed, the size of the third through hole 119 will not affect the size of the first metal silicide layer.
  • the size of the third via hole 119 can be set to be smaller than the size of the via contact metal layer 113 (or the channel via hole) at this time, so that the hard mask layer 114 of the second metal silicide layer can be formed by forming the second metal silicide layer.
  • a bit line connection structure with a size smaller than that of the via-contact metal layer 113 (or the channel via hole) can be formed, so the formation of the second metal silicide layer and the first contact plug, the second contact plug and the bit line connection structure only A photolithography process needs to be formed once, and a bit line with a smaller size can be formed through a single photolithography process, which saves costs.
  • a photolithography process is used when the first metal silicide layer and the second metal silicide layer are formed.
  • the photolithography process only bit line contact plugs can be formed, and a photolithography process is required to form a bit line connection structure with a size smaller than that of the bit line contact plugs.
  • the first metal silicide layer and the bit line contact plugs in contact with the first metal silicide layer have been formed before the photolithography process of the layer, so in the photolithography process for forming the second metal silicide layer, a size smaller than The first metal silicide layer or the bit line contacts the third through hole 119 of the plug, and a bit line connection structure is formed through the third through hole 119 .
  • the first metal silicide layer and the via contact metal layer ie, the bit line contact plug
  • the bit line connection structure can be formed in one photolithography process.
  • a second metal silicide layer 120 is formed on the surface of the well region at the bottom of the first through hole 117 .
  • the formation process of the second metal silicide layer 120 includes: forming a second metal layer in the first through hole 117 and on the surface of the hard mask layer 105; The two metal layers react with the silicon in the well region to form a second metal silicide layer 120 on the surface of the well region; the unreacted second metal layer is removed. It should be noted that, when the second metal layer is deposited in the first through hole 117 , the second metal layer usually exists on the surface of the hard mask layer 105 .
  • the material of the second metal layer is one or more of nickel, cobalt, tantalum and titanium.
  • the formation process of the second metal layer is sputtering.
  • the annealing includes a first annealing and a second annealing performed at one time, and the temperature of the second annealing is higher than that of the first annealing.
  • the first annealing is immersion annealing
  • the annealing temperature is 220-320 degrees Celsius
  • the annealing time is 30-90 seconds
  • the second annealing is millisecond annealing
  • the annealing temperature is 700-950 degrees Celsius
  • the annealing temperature is 700-950 degrees Celsius.
  • the duration is 0.25-20 milliseconds.
  • a wet etching process may be used to remove the unreacted second metal layer.
  • the material of the second metal silicide layer 112 to be formed is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide, or a combination thereof.
  • a first contact plug 125 connected to the second metal silicide layer 120 is formed in the first through hole, and a second contact plug 125 connected to the surface of the corresponding step structure 11 is formed in the second through hole
  • a bit line contact structure (Bit Line contact) 127 connected to the through hole contact metal layer 113 is formed in the third through hole.
  • the first contact plug 125 , the second contact plug 126 and the bit line connection structure 127 are formed in the same step, and before the first contact plug 125 , the second contact plug 126 and the bit line connection structure 127 are formed,
  • the patterned photoresist layer 130 is removed to expose the remaining gate spacers on the array common source electrode 116 , while the first contact plug 125 , the second contact plug 126 and the bit line connection structure 127 are formed , and a fourth contact plug 128 is formed in the remaining gate spacers on the array common source 116 .
  • the fourth contact plug may be used to electrically lead out the common source of the array, so the fourth contact plug may be referred to as a source contact plug.
  • the forming process of the first contact plug 125 , the second contact plug 126 , the bit line connection structure 127 and the fourth contact plug 128 is: forming the first through hole, the second through hole and the second through hole. holes, third through holes and the remaining gate spacers on the array common source 116 and a metal layer covering the surface of the hard mask layer 114, the metal layer material may be tungsten; a planarization process (such as chemical mechanical polishing) process) removing the metal layer higher than the surface of the hard mask layer 114, forming a first contact plug 125 in the first through hole, forming a second contact plug 126 in the second through hole, A bit line connection structure 127 is formed in the third through hole, and a fourth contact plug 128 is formed in the remaining gate spacer on the array common source 116 .
  • the first through hole 117 and the third through hole 117 are formed in the method.
  • the first metal silicide layer 112 has been formed before the through hole 119, so the diameter of the third through hole (bit line connection structure) can be controlled by the photolithography process for forming the first through hole.
  • the diameter of the bit line connection structure can be controlled by the method provided by the embodiment of the present disclosure.
  • the method provided by the embodiment of the present disclosure can The diameter of the bit line connection structure is freely controlled so that the diameter of the bit line connection structure can be adapted to smaller and smaller memory cells.
  • the longitudinal height of the finally formed 3D NAND memory (refer to FIG. 1D ) in the related art is larger than the longitudinal height of the finally formed 3D NAND memory (refer to FIG. 10 ) of the present disclosure.
  • the vertical size of the device can be reduced.
  • An embodiment of the present disclosure further provides a memory, including: a semiconductor layer, a stack structure on the semiconductor layer, and a dielectric layer covering the semiconductor layer and the stack structure; a channel formed through the stack structure a hole, the channel hole includes a channel structure, a polysilicon layer, a first metal silicide layer and a through-hole contact metal layer on the first metal silicide layer; a second metal silicide formed in the dielectric layer layer and a first contact plug, the second metal silicide layer is located on the semiconductor layer, the first contact plug is located on the second metal silicide layer; wherein the through hole contacts the metal layer Contact plugs for bit lines.
  • the diameter of the via contact metal layer is equal to the diameter of the polysilicon layer.
  • the method further includes: a second dielectric layer on the dielectric layer; a bit line connection structure located in the second dielectric layer, the bit line connection structure located on the via contact metal layer ; The diameter of the bit line connection structure is smaller than the diameter of the channel hole.
  • the thickness of the via contact metal layer is less than the thickness of the bit line connection structure.
  • the diameter of the bit line connection structure is smaller than the diameter of the first contact plug.
  • an end of the stacked structure has a stepped structure; further comprising: a second contact plug located in the dielectric layer, the second contact plug is connected to a corresponding surface of the stepped structure; a second The diameter of the contact plug is larger than the diameter of the bit line connection structure.
  • the method further includes: an array common source electrode and a fourth contact plug located in the stacked structure, the array common source electrode is located on the semiconductor layer, and the fourth contact plug is located on the array common source electrode. on the source.
  • An embodiment of the present disclosure further provides a storage system, including: the memory as described above; and a storage controller coupled to the memory.
  • the memory may specifically be a 3D NAND memory.
  • the storage system may be an electronic computer, a smart phone, a smart TV, a smart set-top box, a smart router, an electronic digital camera, an SSD, or other devices with memory.
  • the storage system of the present disclosure generally further includes a controller, an input-output device, a display device, and the like.
  • the memory is used to store files or data and be called by the controller.
  • the storage controller can write data to the memory, that is, the memory provided by the present disclosure, and can also read data from the memory, that is, the memory provided by the present disclosure.
  • the input and output device is used to input commands or output signals, and the display device visualizes the signals to realize various functions of the storage system.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种3D NAND存储器的形成方法，在沟道通孔中形成存储结构和位于所述存储结构上的多晶硅层，所述多晶硅层的表面低于所述介质层的顶部表面后，在所述多晶硅层表面形成第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；将所述牺牲层替换为控制栅结构；在所述介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔；在所述第一通孔底部的阱区表面形成第二金属硅化物层；在所述第一通孔中形成第一接触插塞，在所述第二通孔中形成第二接触插塞。

Description

3D NAND存储器及其形成方法
相关申请的交叉引用
本公开基于申请号为202011117206.4、申请日为2020年10月19日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及一种3D NAND存储器及其形成方法。
背景技术
NAND闪存是一种比硬盘驱动器更好的存储设备，随着人们追求功耗低、质量轻和性能佳的非易失存储产品，在电子产品中得到了广泛的应用。目前，平面结构的NAND闪存已近实际扩展的极限，为了进一步的提高存储容量，降低每比特的存储成本，提出了3D结构的NAND存储器。
相关技术中在沟道孔(channel hole)上形成第一金属硅化物层时，容易在沟道孔的导电插塞(plug)处形成空洞(void)，从而造成接触电阻变大。
发明内容
本公开提供了一种3D NAND存储器的形成方法，包括：
提供半导体衬底，所述半导体衬底中具有阱区，所述半导体衬底的阱区上形成有牺牲层和隔离层交替层叠的堆叠结构，所述堆叠结构的端部具有台阶结构；
形成覆盖所述半导体衬底和堆叠结构的介质层；
在所述介质层和堆叠结构中形成若干贯穿堆叠结构厚度的沟道通孔；
在所述沟道通孔中形成存储结构和位于所述存储结构上的多晶硅层，所述多晶硅层的表面低于所述介质层的顶部表面；
在所述多晶硅层表面形成第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；
将所述牺牲层替换为控制栅结构；
在所述介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔；
在所述第一通孔底部的阱区表面形成第二金属硅化物层；
在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞，在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞。
可选的，所述第一金属硅化物层和通孔接触金属层的形成过程为：在所述介质层表面和多晶硅层上的沟道通孔中形成第一金属层；对第一金属层进行退火，使所述第一金属层与所述存储结构上的部分多晶硅层反应，在所述多晶硅层的表面形成第一金属硅化物层，所述第一金属硅化物层的表面低于所述介质层的顶部表面；去除未反应的第一金属层，在所述第一金属硅化物层表面形成通孔接触金属层，所述通孔接触金属层的表面与所述介质层的顶部表面齐平。
可选的，所述第一金属硅化物层的材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合。
可选的，所述控制栅结构的形成过程为：在所述堆叠结构上形成硬掩膜层；在所述硬掩膜层和堆叠结构中形成栅极隔槽；沿所述栅极隔槽去除所述牺牲层；在所述去除牺牲层的位置形成控制栅结构；在所述栅极隔槽中形成阵列共源极。
可选的，还包括：在所述硬掩膜层中形成与所述通孔接触金属层连接的位线，所述位线的尺寸小于通孔接触金属层的尺寸。
可选的，所述第二金属硅化物层、第一接触插塞、第二接触插塞和位线的形成过程包括：刻蚀所述硬掩膜层和介质层，在所述硬掩膜层和介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔，以及在所述硬掩膜层中形成暴露出通孔接触金属层部分表面的第三通孔，所述第三通孔的尺寸小于所述通孔接触金属层的尺寸；在所述第一通孔中以及硬掩膜层的表面形成第二金属层；进行退火，使所述第二金属层与所述阱区中的硅反应，在阱区表面形成第二金属硅化物层；去除未反应的第二金属层；在所述第一通孔、第二通孔和第三通孔中填充金属层，在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞，在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞，在所述第三通孔中形成与所述通孔接触金属层连接的位线。
可选的，所述第二金属硅化物层材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合
可选的，所述存储结构包括位于沟道通孔侧壁表面上的电荷存储层和位于电荷存储层侧壁表面的沟道层。
可选的，所述电荷存储层包括位于沟道通孔侧壁表面上的阻挡层、位于阻挡层侧壁表面上的电荷捕获层以及位于电荷捕获层侧壁表面上的隧穿层。
可选的，所述控制栅结构包括栅介质层和位于栅介质层上的栅电极。
进一步，所述第二金属硅化物层、第一接触插塞、第二接触插塞和位线的形成过程包括：刻蚀所述硬掩膜层和介质层，在所述硬掩膜层和介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构 表面的若干第二通孔，以及在所述硬掩膜层中形成暴露出通孔接触金属层部分表面的第三通孔，所述第三通孔的尺寸小于所述通孔接触金属层的尺寸；在所述第一通孔中以及硬掩膜层的表面形成第二金属层；进行退火，使所述第二金属层与所述阱区中的硅反应，在阱区表面形成第二金属硅化物层；去除未反应的第二金属层；在所述第一通孔、第二通孔和第三通孔中填充金属层，在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞，在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞，在所述第三通孔中形成与所述通孔接触金属层连接的位线。
附图说明
图1A-图1D为一种3D NAND存储器的形成过程的剖面结构示意图；
图2-图10为本公开的一些实施例提供的3D NAND存储器的形成过程的剖面结构示意图。
具体实施方式
如背景技术所言，相关技术中形成的第一金属硅化物层厚度难以满足性能要求。
图1A-1D为一种3D NAND存储器的形成过程的剖面结构示意图。参考图1A，提供半导体结构，半导体结构包括：半导体衬底10，半导体衬底中具有阱区20；半导体衬底10上具有牺牲层13和隔离层14交替层叠的堆叠结构12，堆叠结构12的一端具有台阶结构21；覆盖堆叠结构12和堆叠结构12一侧的半导体衬底10的第一介质层15；贯穿第一介质层15和堆叠结构12的沟道通孔，位于沟道通孔中的沟道结构18和位于沟道结构18上剩余的沟道通孔中的 多晶硅层19。沟道结构18包括位于沟道通孔侧壁表面上的电荷存储层17和位于电荷存储层17表面的沟道层16。
参考图1B，在堆叠结构12上形成掩膜层22；在掩膜层22和堆叠结构12中形成栅极隔槽(Gate Line Slite，GLS)23；在栅极隔槽23中形成介电材料层(例如，氧化物侧壁)；沿栅极隔槽23去除牺牲层；在去除牺牲层的位置形成控制栅结构131。在栅极隔槽23中(例如，形成了氧化物侧壁中的栅极隔槽23中)形成阵列共源极(Array Common Source，ACS)24。掩膜层22的材料可以与栅极隔槽23中形成介电材料层的材料相同。
参考图1C，通过第一光刻工艺在掩膜层22和第一介质层15中形成暴露出堆叠结构12一侧的阱区20部分表面的第一通孔以及暴露出相应的台阶结构21表面的若干第二通孔，以及在掩膜层22中形成暴露出多晶硅层19的位线接触通孔。在位线接触通孔和第一通孔内分别形成第一金属硅化物层26和第二金属硅化物层25，由于第一接触插塞27与阱区连接时需要较低的接触电阻，因而形成第二金属硅化物层25时需要沉积较多的金属，以形成较厚的第二金属硅化物层25，而沟道结构上的孔深较浅，如果在同一工艺步骤中沉积同样多的金属，则位线接触通孔内退火形成的第一金属硅化物层26的厚度会较厚。然而，本公开的发明人在研究中注意到相关技术中在沟道孔(channel hole)上形成第一金属硅化物层时，容易在沟道孔的导电插塞(plug)处形成空洞(void)，从而造成接触电阻变大，从而导致整体沟道电流偏小，器件的低温特性退化(degrade)。
在第一通孔、第二通孔、位线接触通孔和阵列共源极24上剩余的栅极隔槽内填充金属层材料以形成第一接触插塞27、第二接触插塞30、位线接触插塞(Bit Line Via)28和第四接触插塞29。由于位线接触通孔与第一通孔在同 一步骤中形成，因此位线接触通孔的直径可能与多晶硅层19的直径不同，例如，位线接触通孔和位线接触插塞28的直径小于多晶硅层19的直径。
参考图1D，在掩膜层22上形成第二介质层31，通过第二光刻工艺在第二介质层31内形成暴露出位线接触插塞28的第四通孔，为了使得形成在第四通孔中的位线连接结构(Bit Line contact)的直径降低，例如使其小于沟道通孔或第一金属硅化物层的直径，因此形成的第四通孔的直径小于位线接触通孔的直径，在第四通孔内填充导电材料以形成位线连接结构32，且最终形成的位线连接结构32的直径小于沟道通孔或第一金属硅化物层的直径。位线连接结构32通过位线接触插塞28与第一金属硅化物层26导电接触。
本公开的发明人通过研究发现，相关技术中形成第一金属硅化物层的厚度会过厚，不满足性能要求，进一步研究发现，现有的第一金属硅化物层和第二金属硅化物层在同一工艺步骤中形成。然而，由于第一接触插塞与阱区连接时需要较低的接触电阻，因而形成第二金属硅化物层时需要沉积较多的金属以形成较厚的第二金属硅化物层，而相较于第一通孔的孔深，沟道结构上位线接触通孔的孔深较浅，如果在同一工艺步骤中沉积同样多的金属，则孔深较浅的位线接触通孔内退火形成的第一金属硅化物层的厚度会较厚，即孔深较浅的位线接触通孔内形成的第一金属硅化物层的厚度大于孔深较深的第一通孔内形成的第二金属硅化物层的厚度。由此容易在沟道孔的导电插塞(plug)处形成空洞(void)，从而造成接触电阻变大，进而导致整体沟道电流偏小，器件的低温特性退化(degrade)的问题。
此外，为了使得位线连接结构的尺寸小于沟道通孔或第一金属硅化物层的尺寸，需要额外通过一次光刻工艺(形成第一通孔和第三通孔时需要一次光刻工艺，并在第一通孔和第三通孔内分别形成第一金属硅化物层和第二金属硅化 物层，形成位线接触通孔时需要再做一次光刻工艺)来形成尺寸小于沟道通孔或第一金属硅化物层的尺寸的位线连接结构，增加了成本。例如，形成位线连接结构的光刻工艺与形成第一金属硅化物层和第二金属硅化物层时的光刻工艺不能兼容。
例如，本公开提供了一种3D NAND存储器的形成方法，在沟道通孔中形成存储结构和位于所述存储结构上的多晶硅层，所述多晶硅层的表面低于所述介质层的顶部表面后，在所述多晶硅层表面形成第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；将所述牺牲层替换为控制栅结构；在所述介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔；在所述第一通孔底部的阱区表面形成第二金属硅化物层；在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞，在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞。形成第一金属硅化物层的步骤与后续形成第二金属硅化物的步骤不在同一步骤进行，因而在形成第一金属硅化物时，可以单独调节形成的第一金属硅化物层的厚度，使得第一金属硅化物层的厚度不会受到形成第二金属硅化物层工艺的限制，使得形成的第一金属硅化物层的厚度满足性能要求，以降低第一金属硅化物层中的孔洞出现的概率以及接触电阻增加和良率降低的概率。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图2-10为本公开一些实施例提供的3D NAND存储器的形成过程的剖面结 构示意图。
需要说明的是，本公开中所描述的3D NAND存储器的形成方法不限于用于形成3D NAND存储器，还可以用于形成3D Re-RAM存储器、3D PCM存储器等三维非易失性存储器。
参考图2，提供半导体层。例如，半导体层可以是半导体衬底100，为方便描述，后续将半导体层描述为半导体衬底100，但本公开的实施例不限于此。例如，所述半导体衬底100中具有阱区110，所述半导体衬底的阱区110上形成有牺牲层103和隔离层104交替层叠的堆叠结构111，所述堆叠结构111的端部具有台阶结构11；形成覆盖所述半导体衬底100和堆叠结构111的介质层105；在所述介质层105和堆叠结构111中形成若干贯穿堆叠结构厚度的沟道通孔；在所述沟道通孔中形成存储结构108和位于所述存储结构108上的多晶硅层111。在一些示例中，各沟道通孔内设置有沟道结构，沟道通孔和沟道结构构成沟道孔(channel hole)，这里，存储结构108即为沟道结构。
例如，半导体层(半导体衬底100)的材料可以包括(例如，可以为)单晶硅(Si)、单晶锗(Ge)、硅锗(GeSi)、碳化硅(SiC)、多晶硅的任一种或任意组合；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。例如，半导体衬底100的材料为单晶硅(Si)。
所述半导体衬底100中具有阱区110。所述阱区110可以为P型阱区。例如，阱区110可以为N型阱区。
所述堆叠结构111包括若干交替层叠的牺牲层103和隔离层104(例如：电隔离层，绝缘层)，所述牺牲层103后续去除以形成空腔，然后在去除牺牲层103的位置形成控制栅结构(Word line)。所述隔离层104作为不同层的控 制栅之间，以及控制栅与其他器件(导电接触部、沟道孔等)之间的电学隔离。在一些实施例中，牺牲层可以包括电介质材料、半导体材料或者导电材料。隔离层可以包括电隔离材料、绝缘材料或电介质材料。
所述牺牲层103和隔离层104交替层叠包括牺牲层103和隔离层104交替排布。在一具体实施方式中，牺牲层103和隔离层104交替层叠可以为在形成一层牺牲层103后，在该牺牲层103的表面形成一层隔离层104，然后依次循环进行形成牺牲层103和位于牺牲层103上的隔离层104的步骤。例如，所述堆叠结构111的最底层为一层牺牲层103，最顶层为一层隔离层104；所述堆叠结构111的最底层与半导体衬底100之间还形成有缓冲氧化层101。
在一实施例中，所述堆叠结构111与半导体衬底100之间还形成有缓冲氧化层101。
所述堆叠结构111的层数(堆叠结构111中的牺牲层103和隔离层104的双层堆叠结构的层数)，根据垂直方向所需形成的存储单元的个数来确定，所述堆叠结构111的层数可以为8层、32层、64层等，堆叠结构111的层数越多，越能提高集成度。本实施例中，仅以堆叠结构111的层数为6层作为示例进行说明。
所述牺牲层103与隔离层104的材料不相同，后续去除牺牲层103时，使牺牲层103相对于隔离层104具有高的刻蚀选择比，因而在去除牺牲层103时，对隔离层104的刻蚀量较小或者忽略不计，保证隔离层104的平坦度。
所述隔离层104的材料可以为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种，所述牺牲层103的材料可以为氧化硅、氮化硅、氮氧化硅、氮碳化硅、无定型硅、无定形碳、多晶硅中的一种。本实施例中，所述隔离层104的材料为氧化硅，牺牲层103的材料为氮化硅，所述隔离层104和牺牲层103采用化 学气相沉积工艺形成。
在一实施例中，所述堆叠结构111中最底层一层牺牲层103可以作为底部选择栅牺牲层，后续在去除底部选择栅牺牲层的位置可以对应形成底部选择栅(Bottom Selective Gate，BSG)，将所述第一堆叠结构111中最顶层的一层牺牲层103作为顶部选择栅牺牲层，后续在去除顶部选择栅牺牲层的位置对应形成顶部选择栅(Top Selective Gate，TSG)。
在一实施例中，所述堆叠结构111的一端具有台阶结构11，所述台阶结构11包括呈阶梯型逐渐抬高的若干台阶。
所述介质层105的顶部表面高于所述堆叠结构111的顶部表面，所述介质层105的材料为氧化硅，例如，形成所述介质层105的形成工艺可以为等离子体增强化学汽相淀积工艺、大气压化学汽相淀积工艺、低压化学汽相淀积工艺、高密度等离子体化学汽相淀积工艺或原子层化学汽相淀积工艺。
在一实施例中，在所述的介质层105和堆叠结构111中形成有若干沟道通孔后，继续刻蚀沟道通孔底部暴露的半导体衬底100，在半导体衬底100中形成凹槽；在凹槽中通过选择性外延工艺形成半导体外延层，例如，所述半导体外延层的表面低于最底层的隔离层104的表面并高于半导体衬底100的表面，所述半导体外延层的材料为硅、锗或硅锗；在半导体外延层上形成存储结构108，所述存储结构108的表面低于介质层105的表面；在所述存储结构108上形成填充剩余的沟道通孔的多晶硅层109，例如，所述多晶硅109的表面与介质层105的表面齐平。各沟道通孔内设置有沟道结构，沟道通孔和沟道结构构成沟道孔(channel hole)，这里，存储结构108即为沟道结构。
所述存储结构108包括位于沟道通孔侧壁表面上的电荷存储层107和位于电荷存储层107表面的沟道层106。在一些实施例中，电荷存储层107可以为 电荷存储功能层，电荷存储功能层包括层叠的电荷阻挡层、电荷捕获层和隧穿层。电荷存储功能层的形成方法包括：在沟道通孔侧壁表面形成电荷阻挡层；在电荷阻挡层表面形成电荷捕获层；在电荷捕获层表面形成隧道层。电荷阻挡层与隧道层的材料可以相同，例如，电荷阻挡层与隧道层的材料为氧化硅层，电荷捕获层的材料为氮化硅层。
在一实施例中，所述电荷存储层107包括位于沟道通孔侧壁表面上的阻挡层、位于阻挡层侧壁表面上的电荷捕获层以及位于电荷捕获层侧壁表面上的隧穿层。所述阻挡层和隧穿层的材料为氧化硅，所述电荷捕获层的材料为氮化硅，所述沟道层106的材料为多晶硅。
参考图3，回刻蚀所述多晶硅层109，使得剩余的多晶硅层109的表面低于所述介质层105的表面。
回刻蚀所述多晶硅层可以采用湿法刻蚀工艺或者各项同性的等离子体刻蚀工艺。在一些实施例中，可以通过刻蚀工艺回刻蚀多晶硅层，使得剩余的多晶硅层109的表面低于所述介质层105的表面，从而在沟道通孔的多晶硅层处形成凹陷。在回刻蚀多晶硅层过程中，选用的刻蚀材料对于多晶硅层的刻蚀速率大于对于介质层105的刻蚀速率，此种情况下，介质层105以及沟道结构的电荷存储功能层(隧穿层)可以作为刻蚀多晶硅层的刻蚀阻挡层，从而无需通过额外的掩膜层即可实现对多晶硅层的刻蚀，由此可以降低工艺所需的掩膜板的数目。而后续即可在凹陷内形成第一金属硅化物层和通孔接触金属层。这里，通孔接触金属层可以为位线接触插塞。
回刻蚀所述多晶硅层109的可以用于后续形成第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层的位置。在本公开实施例中，第一金属硅化物层和通孔接触金属层(位线接触插塞)形成于沟道通孔内。例如，通孔接 触金属层的直径等于多晶硅层109的直径。例如，通孔接触金属层的直径等于第一金属硅化物层的直径。
参考图4和图5，在所述多晶硅层109表面形成第一金属硅化物层112(参考图4)和位于第一金属硅化物层112上的通孔接触金属层113(参考图5)。
在一实施例中，所述第一金属硅化物层112和通孔接触金属层113的形成过程为：在所述介质层105表面和多晶硅层109上的沟道通孔中形成第一金属层(图中未示出)；对第一金属层进行退火，使所述第一金属层与所述存储结构上的部分多晶硅层109反应，在所述多晶硅层109的表面形成第一金属硅化物层112，所述第一金属硅化物层112的表面低于所述介质层105的顶部表面；去除未反应的第一金属层，在所述第一金属硅化物层112表面形成通孔接触金属层113，所述通孔接触金属层113的表面与所述介质层105的顶部表面齐平。在一些实施例中，通孔接触金属层的材料和第一金属层的材料不同。
所述第一金属层的材料为镍、钴、钽、钛中一种或几种。所述第一金属层的形成工艺为溅射，所述第一金属层的厚度小于沟道通孔的半径。
所述退火包括一次进行的第一退火和第二退火，第二退火的温度高于第一退火的温度。在一实施例中，所述第一退火是浸入式退火，退火温度为220-320摄氏度，退火时长为30-90秒，所述第二退火是毫秒退火，退火温度为700-950摄氏度，退火时长为0.25-20毫秒。
去除所述未反应的第一金属层可以采用湿法刻蚀工艺。
所述形成的第一金属硅化物层112的材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合。在本公开的一些实施例中，形成第一金属硅化物层112的步骤与后续形成第二金属硅化物的步骤不在同一步骤进行，因而通过单独调节第一金属层的厚度，从而可以单独调节形成的第一金属硅化物层112的 厚度，使得第一金属硅化物层的厚度不会受到形成第二金属硅化物层工艺的限制，使得形成的第一金属硅化物层112的厚度满足性能要求。在一实施例中，所述第一金属层的厚度为7nm-50nm，所述第一金属硅化物层112的厚度为7nm-50nm。
例如，所述通孔接触金属层113的形成过程为：在所述介质层105和第一金属硅化物112上形成金属层；平坦化去除高于所述介质层105表面的金属层，在第一金属硅化物层112上形成通孔接触金属层113。所述通孔接触金属层113后续用于与位线连接，并且在后续形成第二金属硅化物层时，能将第二金属层与第一金属硅化物层112隔离，防止形成的第一金属硅化物层112的厚度发生变化，所述通孔接触金属层113还可以作为后续在硬掩膜层中形成第三通孔时的刻蚀停止层。在一些实施例中，通孔接触金属层113即为位线接触插塞(Bit Line Via)。后续形成的位线连接结构通过位线接触插塞与第一金属硅化物层导电接触。本公开实施例中将位线接触插塞形成在沟道通孔内，而无需通过额外的掩膜层用以形成位线接触插塞。
例如，所述通孔接触金属层113的材料可以为钨。
参考图6，将所述牺牲层替换为控制栅结构123。
在一实施例中，所述控制栅结构123的形成过程为：在所述堆叠结构111上形成硬掩膜层114；在所述硬掩膜层114和堆叠结构111中形成栅极隔槽115；沿所述栅极隔槽115去除所述牺牲层；在所述去除牺牲层的位置形成控制栅结构113。
在一些示例中，在形成栅极隔槽115之后，该方法还包括去除硬掩膜层114，并在介质层105上形成第二介质层。例如，第二介质层的位置与图6-图10中的硬掩膜层114的位置相同。鉴于第二介质层的位置与图6-图10中的硬掩膜 层114的位置相同(也即，图6-图10中的硬掩膜层114被替换为第二介质层)，不再提供额外的附图示出第二介质层以及包括第二介质层的存储器的结构。例如，第二介质层包括(例如，为)氧化硅。
例如，所述硬掩膜层114可以为单层或多层堆叠结构。例如，所述硬掩膜层114的材料为氧化硅、氮化硅、氮氧化硅、碳化硅中的一种或几种。
去除所述牺牲层采用湿法刻蚀工艺。在一实施例中，所述堆叠结构中的最底层的一层牺牲层(底部选择栅牺牲层)去除后对应的位置可以对应形成底部选择栅(Bottom Selective Gate，BSG)122，所述堆叠结构中的最顶层的一层牺牲层(顶部选择栅牺牲层)去除后对应的位置可以对应形成顶部选择栅(Top Selective Gate，TSG)124。所述底部选择栅牺牲层和顶部选择栅牺牲层与其他牺牲层同时去除，所述底部选择栅122和顶部选择栅124与控制栅结构133同时形成。
所述控制栅结构103包括栅介质层和位于栅介质层上的栅电极。在一实施例中，所述控制栅结构103可以为高K介质层和位于高K介质层表面的金属栅极，所述金属栅极的材料可以为W、Al、Cu、Ti、Ag、Au、Pt、Ni其中一种或几种。所述高K介质层的材料HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2、Al 2O 3、SrTiO 3或BaSrTiO。在其他实施例中，所述控制栅结构103可以包括氧化硅介质层和位于介质层上的多晶硅栅极。
参考图7，在所述栅极隔槽(Gate Line Slite，GLS)115(参考图6)中形成阵列共源极(Array Common Source，ACS)116。
在形成阵列共源极116之前，在所述栅极隔槽115的侧壁形成隔离侧墙。所述隔离侧墙包括沉积在栅极隔槽115的侧壁上的电隔离层(例如，电介质层)。例如，阵列共源极(Array Common Source，ACS)116包括诸如氮化钛、W、 Co、Cu、Al、掺杂的硅或硅化物等导电材料的导电层，电隔离层可以为氧化硅层等绝缘材料层。
在本公开的一些实施例，所述形成阵列共源极116的表面低于硬掩膜层114的表面，所述阵列共源极116的材料为多晶硅层。
参考图8，在所述硬掩膜层114上形成图形化的光刻胶层130；以所述图形化的光刻胶层130为掩膜，刻蚀所述硬掩膜层114和介质层105，在所述硬掩膜层114和介质层105中形成暴露出堆叠结构111一侧的阱区110部分表面的第一通孔117以及暴露出相应的台阶结构11表面的若干第二通孔118，以及在所述硬掩膜层114中形成暴露出通孔接触金属层113部分表面的第三通孔119，所述第三通孔119的尺寸小于所述通孔接触金属层113的尺寸。
所述第一通孔117中后续形成与阱区110连接的第一接触插塞，所述第二通孔118中后续形成与台阶结构11连接的第二接触插塞，所述第三通孔119中后续形成与通孔接触金属层113连接的位线连接结构(Bit Line contact)。通孔接触金属层(位线接触插塞)的厚度小于位线连接结构的厚度。
所述第三通孔119的尺寸小于所述通孔接触金属层113(或沟道通孔)的尺寸，相应的后续形成的位线连接结构的直径小于通孔接触金属层113(或沟道通孔)的直径，使得形成的位线连接结构的直径可以较小。在一实施例中，所述第三通孔119的直径可以为所述通孔接触金属层113(或沟道通孔)的直径的1/4-2/3。
例如，刻蚀所述硬掩膜层114和介质层105可以采用各项异性的干法刻蚀工艺，比如各项异性的等离子体刻蚀工艺。这里，硬掩膜层和介质层的材料相同。
在本公开的一些实施例中由于先形成了第一金属硅化物层112，后形成第 二金属硅化物层，不仅使得第一金属硅化物层112的厚度可以单独被控制，满足性能要求。例如，形成第一金属硅化物层112时无需形成掩膜层(第一金属硅化物层112的位置直接通过沟道通孔限定)，而形成第二金属硅化物层以及第一接触插塞、第二接触插塞和位线连接结构只需要形成一次光刻工艺，并且通过一次光刻工艺可以形成直径较小的位线连接结构，节约了成本。
在本公开的一些实施例中由于先形成了第一金属硅化物层112，后形成第二金属硅化物层，使得第一金属硅化物层112的厚度可以单独被控制。例如，还可以使得第一金属硅化物层的厚度和第二金属硅化物层的厚度一致。
在本公开的一些实施例中由于先形成了第一金属硅化物层112，后形成第二金属硅化物层，不仅使得第一金属硅化物层112的厚度可以单独被控制，满足性能要求，而且在通过硬掩膜层114形成第一通孔117和第三通孔119时，由于第一金属硅化物层112已经形成，因此第三通孔119的尺寸不会影响第一金属硅化物层的尺寸，从而此时可以将第三通孔119的尺寸设置为小于所述通孔接触金属层113(或沟道通孔)的尺寸，从而通过形成第二金属硅化物层的硬掩膜层114即可形成尺寸小于通孔接触金属层113(或沟道通孔)的位线连接结构，因而形成第二金属硅化物层以及第一接触插塞、第二接触插塞和位线连接结构只需要形成一次光刻工艺，并且通过一次光刻工艺就可以形成尺寸较小的位线，节约了成本。
相关技术中第一金属硅化物层和第二金属硅化物层在同一工艺步骤中形成的方法中，在形成第一金属硅化物层和第二金属硅化物层时使用一次光刻工艺，在该光刻工艺中仅能形成位线接触插塞，还需进行一次光刻工艺才能形成尺寸小于位线接触插塞的位线连接结构，而本公开实施例中，由于在形成第二金属硅化物层的光刻工艺之前就已经形成了第一金属硅化物层以及与第一金 属硅化物层接触的位线接触插塞，因此在形成第二金属硅化物层的光刻工艺中可以形成尺寸小于第一金属硅化物层或位线接触插塞的第三通孔119，并通过该第三通孔119形成位线连接结构。换言之，相较于相关技术，本公开实施例中仅通过Recess工艺即可形成第一金属硅化物层和通孔接触金属层(即位线接触插塞)，而无需使用掩膜层，且仅通过一次光刻工艺即可形成位线连接结构。
参考图9，在所述第一通孔117底部的阱区表面形成第二金属硅化物层120。
在一实施例中，所述第二金属硅化物层120的形成过程包括：在所述第一通孔117中以及硬掩膜层105的表面形成第二金属层；进行退火，使所述第二金属层与所述阱区中的硅反应，在阱区表面形成第二金属硅化物层120；去除未反应的第二金属层。需要说明的是，在第一通孔117中沉积第二金属层时，通常会使得硬掩膜层105的表面上也存在第二金属层。
所述第二金属层的材料为镍、钴、钽、钛中一种或几种。所述第二金属层的形成工艺为溅射。
所述退火包括一次进行的第一退火和第二退火，第二退火的温度高于第一退火的温度。在一实施例中，所述第一退火是浸入式退火，退火温度为220-320摄氏度，退火时长为30-90秒，所述第二退火是毫秒退火，退火温度为700-950摄氏度，退火时长为0.25-20毫秒。
去除所述未反应的第二金属层可以采用湿法刻蚀工艺。
所述形成的第二金属硅化物层112的材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合。
参考图10，在所述第一通孔中形成与第二金属硅化物层120连接的第一接触插塞125，在所述第二通孔中形成与相应的台阶结构11表面连接的第二接触 插塞126，在所述第三通孔中形成与所述通孔接触金属层113连接的位线连接结构(Bit Line contact)127。
所述第一接触插塞125、第二接触插塞126和位线连接结构127在同一步骤中形成，在形成第一接触插塞125、第二接触插塞126和位线连接结构127之前，去除所述图形化的光刻胶层130，暴露出阵列共源极116上剩余的栅极隔槽，在形成第一接触插塞125、第二接触插塞126和位线连接结构127的同时，在所述阵列共源极116上剩余的栅极隔槽中形成第四接触插塞128。第四接触插塞可以用于将阵列共源极电引出，因此第四接触插塞可以称为源极接触插塞。
在一些实施例中，第一接触插塞125、第二接触插塞126、位线连接结构127和第四接触插塞128的形成过程为：形成填充满所述第一通孔、第二通孔、第三通孔和阵列共源极116上剩余的栅极隔槽以及覆盖所述硬掩膜层114表面的金属层，所述金属层材料可以为钨；平坦化工艺(比如化学机械研磨工艺)去除高于硬掩膜层114表面的金属层，在所述第一通孔中形成第一接触插塞125，在所述第二通孔中形成第二接触插塞126，在所述第三通孔中形成位线连接结构127，在所述阵列共源极116上剩余的栅极隔槽中形成第四接触插塞128。
例如，相较于相关技术中第一金属硅化物层和第二金属硅化物层在同一工艺步骤中形成的方法，本公开上述3D NAND存储器的形成方法中在形成第一通孔117和第三通孔119之前就已经先形成了第一金属硅化物层112，因此通过形成第一通孔的光刻工艺即可以控制第三通孔(位线连接结构)的直径。而随着存储器集成度越来越高，存储单元的尺寸会越来越小，而通过本公开实施例提供的方法可以控制位线连接结构的直径，换言之，通过本公开实施例提供的方法可以自由控制位线连接结构的直径，以使得位线连接结构的直径可以适 应于越来越小的存储单元。
进一步地，相较于相关技术中需两次光刻工艺即其需形成一层掩膜层加一层第二介质层才能形成位线接触插塞(位于掩膜层中)和位线连接结构(位于第二介质层中)，本公开中仅需一次光刻工艺即只需形成一层硬掩膜层即可形成位线接触插塞(位于沟道通孔内)和位线连接结构(位于硬掩膜层或第二介质层中)。从而导致相关技术中最终形成的3D NAND存储器(参考图1D)的纵向高度大于本公开最终形成的3D NAND存储器(参考图10)的纵向高度。换言之通过本公开提供的3D NAND存储器的形成方法，可以减小器件的纵向尺寸。
本公开实施例中还提供一种存储器，包括：半导体层、位于所述半导体层上的堆叠结构和覆盖所述半导体层和所述堆叠结构的介质层；形成贯穿所述堆叠结构的的沟道孔，所述沟道孔包括沟道结构、多晶硅层、第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；形成于所述介质层内的第二金属硅化物层和第一接触插塞，所述第二金属硅化物层位于所述半导体层上，所述第一接触插塞位于所述第二金属硅化物层上；其中，所述通孔接触金属层为位线接触插塞。
在一些实施例中，所述通孔接触金属层的直径与所述多晶硅层的直径相等。
在一些实施例中，还包括：位于所述介质层上的第二介质层；位于所述第二介质层内的位线连接结构，所述位线连接结构位于所述通孔接触金属层上；所述位线连接结构的直径小于所述沟道孔的直径。
在一些实施例中，所述通孔接触金属层的厚度小于所述位线连接结构的厚度。
在一些实施例中，所述位线连接结构的直径小于所述第一接触插塞的直径。
在一些实施例中，所述堆叠结构的端部具有台阶结构；还包括：位于所述介质层内的第二接触插塞，所述第二接触插塞与相应的台阶结构表面连接；第二接触插塞的直径大于所述位线连接结构的直径。
在一些实施例中，还包括：位于堆叠结构中的阵列共源极和第四接触插塞，所述阵列共源极位于所述半导体层上，所述第四接触插塞位于所述阵列共源极上。
本公开实施例中还提供一种存储系统，包括：如上所述的存储器；以及存储控制器，其与所述存储器耦接。
在一些实施例中，所述存储器具体可以为3D NAND存储器。
具体而言，存储系统可以为电子计算机、智能手机、智能电视、智能机顶盒、智能路由器、电子数码相机、SSD等具有存储器的设备。本公开的存储系统通常还包括控制器、输入输出装置、显示装置等。存储器用于存储文件或数据，并供控制器调用。具体而言，存储控制器可以向存储器，即本公开提供的存储器中写入数据，也可以从存储器，即本公开提供的存储器中读取数据。输入输出装置用于输入指令或输出信号，显示装置将信号可视化，实现存储系统的各种功能。
需要说明的是，以上存储器和存储系统的描述，与上述3D NAND存储器的形成方法实施例的描述是类似的，具有同3D NAND存储器的形成方法实施例相似的有益效果，因此不做赘述。对于本公开实施例存储器和存储系统中未披露的技术细节，请参照本公开实施例中3D NAND存储器的形成方法的描述而理解。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些 改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种3D NAND存储器的形成方法，其中，包括：
    提供半导体结构，所述半导体结构包括半导体衬底、位于所述半导体衬底上的堆叠结构和覆盖所述半导体衬底和所述堆叠结构的介质层；
    在所述介质层和堆叠结构中形成若干贯穿所述堆叠结构的沟道通孔；
    在所述沟道通孔内形成沟道结构，并在所述沟道通孔内及所述沟道结构上依次形成多晶硅层、位于所述多晶硅层上的第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；
    在形成第一金属硅化物层之后，在所述介质层中形成暴露出所述半导体衬底的第一通孔；
    在所述第一通孔底部形成第二金属硅化物层，在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞。
  2. 如权利要求1所述的3D NAND存储器的形成方法，其中，所述第一金属硅化物层和通孔接触金属层的形成过程为：在所述介质层表面和多晶硅层上的沟道通孔中形成第一金属层；对所述第一金属层进行退火，使所述第一金属层与所述沟道结构上的部分多晶硅层反应，在所述多晶硅层的表面形成第一金属硅化物层，所述第一金属硅化物层的表面低于所述介质层的顶部表面；去除未反应的所述第一金属层，在所述第一金属硅化物层表面形成通孔接触金属层，所述通孔接触金属层的表面与所述介质层的顶部表面齐平。
  3. 如权利要求2所述的3D NAND存储器的形成方法，其中，所述第一金属硅化物层的材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合。
  4. 如权利要求1至3任一项所述的3D NAND存储器的形成方法，其中，所述堆叠结构包括交替层叠的牺牲层和隔离层；形成所述通孔接触金属层之后，还包括：将所述牺牲层替换为控制栅结构。
  5. 如权利要求4所述的3D NAND存储器的形成方法，其中，所述控制栅结 构的形成过程为：在所述堆叠结构上形成硬掩膜层；在所述硬掩膜层和堆叠结构中形成栅极隔槽；沿所述栅极隔槽去除所述牺牲层；在所述去除牺牲层的位置形成控制栅结构；在所述栅极隔槽中形成阵列共源极。
  6. 如权利要求5所述的3D NAND存储器的形成方法，其中，所述硬掩膜层的材料与所述介质层的材料相同。
  7. 如权利要求5所述的3D NAND存储器的形成方法，其中，还包括：在所述硬掩膜层中形成与所述通孔接触金属层连接的位线连接结构，所述位线连接结构的尺寸小于通孔接触金属层的尺寸。
  8. 如权利要求7所述的3D NAND存储器的形成方法，其中，所述堆叠结构的端部具有台阶结构；在所述介质层中形成所述第一通孔的同时，还包括：在所述介质层中形成暴露出相应的台阶结构表面的若干第二通孔。
  9. 如权利要求8所述的3D NAND存储器的形成方法，其中，还包括：在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞。
  10. 如权利要求9所述的3D NAND存储器的形成方法，其中，所述第二金属硅化物层、第一接触插塞、第二接触插塞和位线连接结构的形成过程包括：刻蚀所述硬掩膜层和介质层，在所述硬掩膜层和介质层中形成暴露出堆叠结构一侧的所述半导体衬底的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔，以及在所述硬掩膜层中形成暴露出通孔接触金属层部分表面的第三通孔，所述第三通孔的尺寸小于所述沟道通孔的尺寸；在所述第一通孔中以及硬掩膜层的表面形成第二金属层；进行退火，使所述第二金属层与所述半导体衬底中的硅反应，在半导体衬底表面形成第二金属硅化物层；去除未反应的第二金属层；在所述第一通孔、第二通孔和第三通孔中填充金属层，在所述第一通孔中形成与第二金属硅化物层连接的第一接触插塞，在所述第二通孔中形成与相应的台阶结构表面连接的第二接触插塞，在所述第三通孔中形成与所述通孔接触金属层连接的位线连接结构。
  11. 如权利要求7所述的3D NAND存储器的形成方法，其中，所述第二金属硅化物层材料为硅化镍、硅化钴、硅化钽、硅化钛的一种或它们的组合。
  12. 如权利要求1至11任一项所述的3D NAND存储器的形成方法，其中，所 述沟道结构包括位于沟道通孔侧壁表面上的电荷存储层和位于电荷存储层侧壁表面的沟道层；和/或，所述电荷存储层包括位于沟道通孔侧壁表面上的阻挡层、位于阻挡层侧壁表面上的电荷捕获层以及位于电荷捕获层侧壁表面上的隧穿层；和/或，所述控制栅结构包括栅介质层和位于栅介质层上的栅电极；和/或，所述通孔接触金属层为位线接触插塞。
  13. 如权利要求1所述的3D NAND存储器的形成方法，其中，所述第一接触插塞与所述堆叠结构在所述半导体衬底上的正投影不重叠。
  14. 一种存储器，其中，包括：
    半导体层、位于所述半导体层上的堆叠结构和覆盖所述半导体层和所述堆叠结构的介质层；
    形成贯穿所述堆叠结构的的沟道孔，所述沟道孔包括沟道结构、多晶硅层、第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层；
    形成于所述介质层内的第二金属硅化物层和第一接触插塞，所述第二金属硅化物层位于所述半导体层上，所述第一接触插塞位于所述第二金属硅化物层上；
    其中，所述通孔接触金属层为位线接触插塞。
  15. 如权利要求14所述的存储器，其中，所述通孔接触金属层的直径与所述多晶硅层的直径相等。
  16. 如权利要求15所述的存储器，其中，还包括：位于所述介质层上的第二介质层；位于所述第二介质层内的位线连接结构，所述位线连接结构位于所述通孔接触金属层上；所述位线连接结构的直径小于所述沟道孔的直径。
  17. 如权利要求16所述的存储器，其中，所述通孔接触金属层的厚度小于所述位线连接结构的厚度。
  18. 如权利要求16所述的存储器，其中，所述位线连接结构的直径小于所述第一接触插塞的直径。
  19. 如权利要求16所述的存储器，其中，所述堆叠结构的端部具有台阶结构；还包括：位于所述介质层内的第二接触插塞，所述第二接触插塞与相应的台阶结构表面连接；第二接触插塞的直径大于所述位线连接结构的直径。
  20. 如权利要求19所述的存储器，其中，还包括：位于堆叠结构中的阵列共源极和第四接触插塞，所述阵列共源极位于所述半导体层上，所述第四接触插塞位于所述阵列共源极上。
  21. 一种存储系统，包括：一个或多个如权利要求14至20中任一项所述的存储器；以及存储控制器，其与所述存储器耦接。
PCT/CN2021/124789 2020-10-19 2021-10-19 3d nand存储器及其形成方法 WO2022083597A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180010962.3A CN115004368A (zh) 2020-10-19 2021-10-19 3d nand存储器及其形成方法
US18/090,440 US20230142924A1 (en) 2020-10-19 2022-12-28 3d nand memory device and forming method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011117206.4 2020-10-19
CN202011117206.4A CN112331671B (zh) 2020-10-19 2020-10-19 3d nand存储器的形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/090,440 Continuation US20230142924A1 (en) 2020-10-19 2022-12-28 3d nand memory device and forming method thereof

Publications (1)

Publication Number Publication Date
WO2022083597A1 true WO2022083597A1 (zh) 2022-04-28

Family

ID=74313205

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/124789 WO2022083597A1 (zh) 2020-10-19 2021-10-19 3d nand存储器及其形成方法

Country Status (3)

Country Link
US (1) US20230142924A1 (zh)
CN (3) CN112331671B (zh)
WO (1) WO2022083597A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331671B (zh) * 2020-10-19 2021-11-05 长江存储科技有限责任公司 3d nand存储器的形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130089974A1 (en) * 2011-10-11 2013-04-11 Sung-Hae Lee Method of manufacturing a non-volatile memory device having a vertical structure
CN109148461A (zh) * 2018-08-17 2019-01-04 长江存储科技有限责任公司 3d存储器件及其制造方法
CN110010619A (zh) * 2018-01-04 2019-07-12 旺宏电子股份有限公司 三维半导体元件及其制造方法
CN110797345A (zh) * 2018-08-03 2020-02-14 三星电子株式会社 垂直存储器件
CN112331671A (zh) * 2020-10-19 2021-02-05 长江存储科技有限责任公司 3d nand存储器的形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102198856B1 (ko) * 2014-02-10 2021-01-05 삼성전자 주식회사 니켈 함유막을 포함하는 반도체 소자의 제조 방법
CN112802854B (zh) * 2019-03-27 2021-11-05 长江存储科技有限责任公司 3d nand存储器及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130089974A1 (en) * 2011-10-11 2013-04-11 Sung-Hae Lee Method of manufacturing a non-volatile memory device having a vertical structure
CN110010619A (zh) * 2018-01-04 2019-07-12 旺宏电子股份有限公司 三维半导体元件及其制造方法
CN110797345A (zh) * 2018-08-03 2020-02-14 三星电子株式会社 垂直存储器件
CN109148461A (zh) * 2018-08-17 2019-01-04 长江存储科技有限责任公司 3d存储器件及其制造方法
CN112331671A (zh) * 2020-10-19 2021-02-05 长江存储科技有限责任公司 3d nand存储器的形成方法

Also Published As

Publication number Publication date
CN112331671A (zh) 2021-02-05
CN114188347A (zh) 2022-03-15
US20230142924A1 (en) 2023-05-11
CN115004368A (zh) 2022-09-02
CN112331671B (zh) 2021-11-05

Similar Documents

Publication Publication Date Title
US10903164B2 (en) Bonded assembly including a semiconductor-on-insulator die and methods for making the same
CN109328397B (zh) 含有两种类型的支柱结构的多层存储器堆叠结构
US10861869B2 (en) Three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same
US11355515B2 (en) Three-dimensional memory device including locally thickened electrically conductive layers and methods of manufacturing the same
US10672780B1 (en) Three-dimensional memory device having dual configuration support pillar structures and methods for making the same
CN107996001B (zh) 用于存储器结构中的控制栅电极的含钴导电层
EP3262684B1 (en) Three-dimensional memory device with stress compensation layer within a word line stack
US9583500B2 (en) Multilevel memory stack structure and methods of manufacturing the same
CN109817623B (zh) 3d nand存储器及其形成方法
US10224240B1 (en) Distortion reduction of memory openings in a multi-tier memory device through thermal cycle control
US20200266206A1 (en) Three-dimensional memory device including bit lines between memory elements and an underlying peripheral circuit and methods of making the same
CN109817634B (zh) 3d nand存储器及其形成方法
TWI693702B (zh) 三維儲存裝置及其製造方法
CN111512442A (zh) 包括波状字线的三维平坦nand存储器器件及其制造方法
CN111627918A (zh) 一种3d nand存储器及其制造方法
US11894298B2 (en) Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers
US11335790B2 (en) Ferroelectric memory devices with dual dielectric confinement and methods of forming the same
US20230142924A1 (en) 3d nand memory device and forming method thereof
US20220270967A1 (en) Three-dimensional memory device containing plural metal oxide blocking dielectric layers and method of making thereof
CN113228281A (zh) 具有背侧接触结构的三维存储器设备及其制造方法
US20240196610A1 (en) Three-dimensional memory device with dielectric fins in staircase region and methods of making thereof
US10586801B2 (en) Flash memory cells
CN114171533A (zh) 3d nand存储器及其形成方法
CN116803229A (zh) 包含多位电荷存储元件的三维存储器装置以及其形成方法
TW200849563A (en) NAND flash memory cell array and method of fabricating the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21882013

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21882013

Country of ref document: EP

Kind code of ref document: A1