TW200849563A - NAND flash memory cell array and method of fabricating the same - Google Patents

Abstract

A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells.

Description

200849563 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a NAND flash memory, and more particularly to a self-aligned process (self-aligned) Process) A method of manufacturing a gate-type flash memory. [Previous technique #f] Flash memory has the advantages of small area, power saving, high speed, good tolerance and low operating voltage. Therefore, the flash memory system has become an important component of products such as digital cameras, mobile phones, printers, and personal digital assistants (PDAs). NAND flash memory is a type of flash memory. The cell lines of the gate-type flash memory are connected to each other and arranged in an array, wherein only the first cell and the last cell of one of the arrays are connected to a word line, respectively. And a bit-line. Due to the above structure, the inverse type flash memory can access more data than the reverse or NOR flash memory. It means that the anti-gate type flash memory has a larger memory capacity and a faster rewriting speed. The anti-gate flash memory system is widely used to store large amounts of data and can be used as a memory card for a digital camera or a music digital slot player (Mp3 player). U.S. Patent No. 6,936,885 discloses an anti-gate type flash memory device and a method of fabricating the same. Figure la is a top view showing a cell array region partially transmissive to the gate type flash memory device. Lb diagram

Client's Docket No: 95146TW TT^s Docket No:0593-A41201-TW/Finayianchen/070605 5 200849563 A cross-sectional view of the I-inch line of the first drawing showing a flash memory component. Referring to the first and lb diagrams, the string selection line pattern Is and the ground selection line pattern lg essentially define a string selection transistor 13 and a ground selection transistor. (ground selection transistor) 19. A plurality of unit cell transistors 15 and 17 are formed at the intersection of the active area 2 and the word lines WP1 WPWPn. A string selection transistor 13 and a ground selection transistor 19 are used to drive the cells 15 and 17 of the above columns. Due to this special structure and the selection of the two crystals 13 and 19, the process complexity is increased. In addition, the selection of transistors 13 and 19, which are conventionally opposed to the glare flash memory components, have problems with high precision requirements. This necessary South Jincheng will inevitably increase the cost of the process. U.S. Patent No. 6,8 8 5,5 8 6 discloses a self-aligned split-gate and gate-type flash memory and a method of fabricating the same. First, a layer of conductive layer comprising doped polysilicon or polysilicon is deposited. The aforesaid conductive layer is then anisotropically patterned to form a select gate for driving a column of inverted gate-type flash memory cells. The above-mentioned conventional structure of the gate type flash memory has a problem that the gap width between the unit cells is too large, and the size of the anti-gate type flash memory is hard to be reduced. Therefore, there is a need for an anti-gate type flash memory cell array and a method of fabricating the same to solve the shortcomings of the conventional process, such as the south process cost or the complicated process. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to reduce the number of masks for selecting a transistor in a reverse-gate type flash memory cell array and to reduce the number of such masks, etc.

Client's Docket No:: 95146TW TT's Docket Νο:0593-Α41201-Τλν/Ρίη&1/ί&η(:1ΐ6η/070605 . 200849563, to control process cost. Another aspect of the present invention is to reduce the reverse and open type The gap width between the flash memory cells can effectively reduce the size of the wafer and increase the component density of the wafer.

The invention provides a reverse-gate type flash memory cell array, comprising: a substrate comprising: an active region; a plurality of aligned cells arranged on the active region; and a first barrier layer Covering the plurality of unit cells and the active regions surrounding each end of the column; a first oxide deposited in the gap between the plurality of unit cells and filling the gap. - oxide "wall" Formed on the sidewalls of the unit cell along each end of the column; a polysilicon spacer spacer is formed on the oxide spacer, and the polysilicon spacer is used as a selection gate for driving the column cell. The aspect ratio of the above gap is preferably between 18 and 32. ' · ·

The first oxide layer has excellent step coverage ability, and the pores can be formed without filling the gap between the unit cells. In another embodiment, only the gap between the unit cells is sealed, and the material having a low step coverage capability is also used. X The reverse gate type flash memory cell array of the preferred embodiment of the present invention further includes - The irrigating area is formed in the active region at each end of the above column by using a predetermined ion implantation method; an oxidized;, 9 9 is accumulated in the cerevisiae spacer, the oxide spacer a portion of the barrier layer and the first oxide-second barrier layer deposited on the oxidized reed; an interlayer dielectric layer deposited on the second barrier B 及Around the above

Client, s Docket No:: 95146TW TT5s Docket No:0593-A41201-TW/Finayianchen/070605 7 200849563 On each of the active regions at each end of the column; a contact plug that uses a plug material to deposit in the above column An opening of each end is formed by planarizing the plug material by a chemical mechanical polishing process; a metal line is formed on the contact hole plug; and a metal interlayer dielectric layer is formed on the different metal Between the lines. Further, the first barrier layer and the above-mentioned first barrier layer are made of a nitride layer or a thin oxynitride layer.

The above metal wires are preferably made of an aluminum-copper alloy or the like. In another embodiment, after forming the metal lines, a metal interlayer dielectric layer is deposited to prevent the conductive elements in the cell array from being electrically connected to each other. In addition, the present invention provides a method for fabricating a reverse-gate type flash memory cell array, which includes: forming a plurality of aligned cells in an active region of a substrate; and depositing-first blocking a layer covering the plurality of unit cells and the active region surrounding each end of the column; depositing a first oxide in a gap between the plurality of unit cells to fill the gap; forming an oxide gap The walls are on the sidewalls of the unit cell along each end of the column; a polysilicon spacer is formed on the oxide spacer. In another embodiment of the present invention, after the oxide spacer is formed on sidewalls of the unit cell at each end of the column, a pre-clean process is further performed, and then a through-hole process is performed. Tunnel oxide oxidation process. In another embodiment of the present invention, the method further includes removing a portion of the first barrier layer, and implanting predetermined ions in the active region surrounding each end of the column; depositing an oxide layer over the substrate; forming a first a second barrier layer on the oxide layer; and then forming an interlayer dielectric over the substrate

Client's Docket No:: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 8 200849563 layer; forming a contact hole plug at each end of the above column; forming the above contact hole plug at each end of the above column Forming a metal line on the contact hole plug. In another embodiment of the invention, the metal wires are each connected to a conductive pad. However, the above metal lines of the above-described anti-gate type flash memory cell array can be connected to a conductive trench. The anti-gate type flash memory cell array of the preferred embodiment of the present invention has a simple structure and a high aspect ratio, and combines with a self-aligned process to make it have many advantages over conventional ones. The advantages of gate-type flash memory cell arrays. [Embodiment] Hereinafter, a reverse-gate type flash memory cell array and a method for forming the same according to a preferred embodiment of the present invention will be described in more detail by using a process cross-sectional view. In the embodiments of the present invention, the same reference numerals are used. The same or similar components. The mouth reference brothers 2a to 2b show a layout formed by a Self-Aligned-Shallow Trench Isolation Technology (SA-STI Technology) according to a preferred embodiment of the present invention. In each layout, the label "Wl~Wn" is used to define the word line on the substrate. The label "AA" of the layout is used to define the active region on the substrate, and the layout label "FP" Used to define a plurality of floating polycrystalline layers. In addition, the layout label, CB" is used to define the contact hole of the bit-line, and the layout symbol "cs," Used to define a source line contact hole on the substrate. A plurality of inverse gate type flash memory cell systems are formed in the layout "AA" and the layout.

Client's Docket No.: 95146TW TT’s Docket No:0593-A41201-TW/Final/ianchen/070605 9 200849563, at the intersection; and the above cell lines are arranged in the array (10). The operation of the gate-type flash memory cell is replaced by a bit line contact hole, a common source line contact hole, an array gate layer, and a selection gate (not shown). The voltage is controlled. It must be noted that each source line contact hole is connected to a metal wire. In another embodiment of the invention as shown in Figure 2b, the source line contact holes are connected to a conductive trench. The above structure can result in lower resistance and simplification of the process. Clear reference brothers 3a to 3b, which show the layout of two types of anti-gate type flash memory cells, and the above two types of anti-gate type flash memory cells use self-alignment Formed by Self-Aligned Poly Technology (SAP Technology). Each of the source line contact holes in Fig. 3a is a metal line, and each of the source line contact holes in Fig. 3b is a groove. Comparing Fig. 3a with Fig. 2a, the difference is that the 3a figure lacks the layout "FP". In Figure 2a, which uses the SA_STI process, the floating polysilicon layer defined by the layout "FP" is used as an isolation between the gate cell and the gate cell. When the anti-gate type flash memory cell is fabricated using a 0. 1 μηι (or less than 0.1/xm) process, the layout "FP" is removed from the design rule to simplify the process and avoid micro Misalignment during the shadowing process. In Figure 3a, which utilizes the SAP process, a floating polycrystalline germanium layer is first deposited, and the floating polycrystalline germanium layer is removed using a chemical mechanical polishing process. Therefore, it is possible to reduce the number of masks required to define the gate memory of the gate type flash memory. In addition, the above-mentioned anti-gate type flash memory structure is located in a single area.

Clienfs Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianchen/070605 10 200849563 On the single block. The above composition is repeatedly formed on the wafer, and the layout "CB" and the layout "CS" are located between the two blocks. Referring to Fig. 4a, a plurality of unit cells 32 arranged in a row are formed on the substrate 30. First, an active area structure is formed using an SA_STI or SAP process. After the silver engraving process of floating polysilicon gates (not shown), a gate stack is formed on the substrate 30. Then, after forming a plurality of access polysilicon gates 36 on the substrate 30 by using a lithography and dry etching process, an ion implantation process is performed to adjust the cell 32 and the selective transistor (select transistor Source/dip characteristics. In addition, an oxide layer 42 and a first barrier layer 43 are disposed on the substrate 30 and the access polysilicon gate 36. Oxide layer 42 is typically a thin oxide layer. The first barrier layer 43 is usually formed on the oxide layer 42 by remote plasma chemical vapor deposition (RPCVD) or plasma enhanced chemical vapor deposition (PECVD). A thin nitride layer or a thin layer of oxynitride, and having a thickness between 5 Å and 150 Å. The etching selectivity of the first barrier layer 43 to the oxide layer 42 must be high enough for subsequent etchback processes to be performed. Referring to FIG. 4b, a first oxide 47 is filled in the gap between the unit cells 32 by using a high density plasma chemical vapor deposition (HDP-CVD) or the like. The thickness of the first oxide 47 is between 1500 A and 5000 A on the active regions surrounding the respective ends of the above columns. As shown in Figure 4c, proceed

Client's Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 11 200849563 An etching process is performed to form oxide spacers 49 on the cell sidewalls at the respective ends of the above columns. The first oxide 47 still fills the gap between the unit cells 32. During the etch back process, the first barrier layer 43 can be considered an etch stop layer. The first oxide 47 of the preferred embodiment of the present invention has excellent step coverage ability. The pores can be formed without filling the gap between the unit cells 32. If only the gap between the unit cells is sealed, a material having a lower step coverage can be used without using the first oxide 47 which can completely fill the gap. In a preferred embodiment of the invention, the aspect ratio of the gap between the unit cells 32 is between ι·8 and 3.2. Controlling the aspect ratio described above in particular helps to increase the component density of the wafer. As shown in Fig. 4d, a wet etching or dry etching process may be performed to remove the exposed first barrier layer 43. Next, an ion implantation process is performed to adjust the threshold voltage of the selection transistor formed by the subsequent performance. An ion implantation region 52 is formed at each end of the above column, and then a pre-clean process is performed. Then, after performing a tunnel oxide oxidation process, a polysilicon spacer is formed to serve as a gate for selecting a transistor. As shown in FIGS. 4e to 4f, first, a polysilicon layer 54 having a thickness of between 1200 A and 3200 A is deposited, and then an etching process is performed to etch the polysilicon layer 54 anisotropically, in each of the above columns. A polysilicon spacer 56 is formed on the sidewall of the unit cell 32 at the end. & Next, as shown in Fig. 4g, an oxide layer 60, typically a thin oxide layer, is deposited over the substrate 30. Then, a nitrogen is deposited on the oxide layer 60.

Client's Docket No.: 95146TW TT’s Docket No:0593-A41201-TW/Final/ianchen/070605 12 200849563 The layer 62, the nitride layer 62 can be regarded as a barrier layer, which is the second barrier layer. Using a low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or other similar process to deposit an interlevel dielectric layer after 64 ° 'to perform a chemical mechanical polishing (chemicai polishing, CMP) process The interlayer dielectric layer 64 is planarized. Then, a lithography and anisotropic etching process is performed to form a bit line contact hole and a source/bump contact hole. Please refer to FIG. 4h for an ion implantation process to form an ohmic contact 76. The contact hole plug 66 is filled in the bit line and the source/drain contact hole. First, an intercalation material such as polycrystalline germanium or tungsten is deposited. The plug material is then planarized by a chemicai mechanical ai polishing (CMP) process to form contact hole plugs 66. Next, a conductive layer is deposited on the contact hole interposer 66 and the interlayer dielectric layer 64 by physical vapor deposition or the like, and the conductive layer I is an aluminum-copper alloy or the like. Thereafter, a metal line 72 is formed on the contact hole plug 66 by a lithography and etching process. In one embodiment, after the metal lines 72 are formed, a metal interlayer dielectric layer (not shown) is deposited to prevent electrical connections in the cell array from electrically connecting to each other. According to the above process, the metal line 72 is located between the two inverted gate type flash memory cell array blocks. The layout of the conventional inverted gate type flash memory cell array as shown in Figs. 1a and 1b, for example, the two select line patterns 1 s and 1 g are determined separately.

Client's Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 13 200849563 Two types of transistors 13 and 19 are selected. Since the present invention replaces the selective transistor with a polycrystalline turn 2 formed in each of the Self_aligned processes. Indicates that at least two selection line patterns can be privately removed in the above process. In addition, since the polycrystalline galvanic spacer is formed by a self-aligned process, it is possible to reduce the level of a process machine such as a stepping machine (steppe〇, etc.). Therefore, the manufacturing cost of the process of the embodiment of the present invention is Substantially lower than the manufacturing cost of the prior art. f In addition, for a wafer having an inverted gate type flash memory cell array, the present invention provides a higher aspect ratio of the gap between the cells. 'It is particularly helpful to increase the component density of the wafer. Due to the inverse gate type flash memory cell array and self-aligned process, the critical dimension (CD) and stacking loss in the lithography process is less. Therefore, the stability of the process has been increased. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one skilled in the art, without departing from the spirit of the invention, The scope of protection V of the present invention is subject to the definition of the scope of the appended patent application. [Simple description of the schema] The brother 1 a diagram is a top view, which shows the habit A portion of the cell array region of the gate-type flash memory device is known. Figure lb is a cross-sectional view taken along line I-Ι of the first panel showing a conventional inverse gate-type flash memory structure. Figure 2a shows a layout formed using a self-aligned shallow trench isolation process in accordance with a preferred embodiment of the present invention.

Client's Docket No: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 14 200849563 Figure 2b shows a layout formed by a self-aligned shallow trench isolation process in accordance with another embodiment of the present invention. Figure 3a shows the layout of the self-aligned polysilicon process of the preferred embodiment of the present invention. Figure 3b shows a layout of a self-aligned polysilicon process in accordance with another embodiment of the present invention. 4a through 4h are cross-sectional views taken along line A-A' of the 2a, 2b, 3a, and 3b, respectively, showing a process cross-sectional view of the inverted gate type flash memory cell array of the embodiment of the present invention. [Main component symbol description] lg ~ pattern; Is ~ pattern; 2 ~ active area; 13 ~ string selection transistor; 15, 17 ~ cell transistor; 19 ~ ground selection transistor; WP1 ~ WPn ~ word line ; Wi ~ Wn ~ word line; AA ~ active area; CB ~ contact hole; CS ~ source line contact hole; FP ~ floating polysilicon layer; 30 ~ substrate; 32 ~ unit cell; 36 ~ access polycrystalline seconds gate Extremely; 42~ oxide layer; 43~ first barrier layer; 47~ first, oxide; 49~ oxide spacer; 52~ ion implantation region; 54~ polysilicon layer; 56~ polysilicon spacer; Oxide layer; 62~ nitride layer; 64~ interlayer dielectric layer; 66~ contact hole plug; 72~ metal line; 76~ ohmic contact.

Client’s Docket No.: 95146TW TT9s Docket No:0593-A41201-TW/Final/ianchen/070605 15

Claims (1)

200849563 X. Patent application scope: 1. An anti-gate type flash memory cell array, comprising: a substrate comprising an active region; a plurality of unit cells arranged in a row, located on the active region; a barrier layer covering the plurality of unit cells and the active region surrounding each end of the column, a first oxide deposited in a gap between the plurality of unit cells and filling the gap; An oxide spacer formed on a sidewall of the unit cell along each end of the column; and a polysilicon spacer formed on the oxide spacer, the polysilicon spacer being used to drive the column cell A choice of gates. 2. The anti-gate type flash memory cell array according to claim 1, further comprising an implant region formed by implanting a predetermined ion pattern around each end of the column In the district. 3. The anti-gate type flash memory I cell array according to claim 1, further comprising an oxide layer deposited on the polysilicon spacer, the oxide spacer, and the first portion a barrier layer and the first oxide. 4. The anti-gate type flash memory cell array according to claim 3, further comprising a second barrier layer deposited on the oxide layer. 5. The anti-gate type flash memory cell array according to claim 4, further comprising an interlayer dielectric layer deposited on the second barrier layer and surrounding each end of the column On the active area. 6. The anti-gate type flash memory client's Docket No. as described in item 4 of the patent application scope: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 16 200849563 The cell array, including one The contact hole is formed by depositing a plug material in an opening at each end of the column and planarizing the plug material by a chemical mechanical polishing process. 7. The anti-gate type flash memory cell array according to claim 6, further comprising a metal line formed on the contact hole plug. 8. The scope of the gap between the plurality of unit cells is between 1.8 and 3.2, as described in the first paragraph of the patent application scope and the gate type flash memory cell array. 9. The anti-gate type flash memory cell array as described in claim 1 wherein the first barrier layer is made of a nitride layer or a thin oxynitride layer. 10. The anti-gate type flash memory cell array according to claim 4, wherein the first barrier layer and the second barrier layer are nitrided or thin oxynitride layers. to make. 11. A method of fabricating a gate-type flash memory cell array, comprising the steps of: forming a plurality of cells arranged in a row on an active region of a substrate; depositing a first barrier layer, covering The plurality of unit cells and the active region surrounding each end of the column; depositing a first oxide in a gap between the plurality of unit cells to fill the gap; forming an oxide spacer along the Located on the sidewalls of the unit cell at each end of the column; and forming a polysilicon spacer on the oxide spacer. Client's Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianclien/070605 17 200849563 12. Method for manufacturing reverse-gate type flash memory cell array according to claim 11 After the step of forming the oxide spacers along the sidewalls of the unit cell at each end of the column, further comprising removing a portion of the first barrier layer and implanting predetermined ions around the The steps in the active zone at each end of the column. 13. The method of fabricating an anti-gate type flash memory cell array according to claim 11, wherein the step of forming the polysilicon spacer on the oxide spacer further comprises depositing a layer The step of oxidizing the layer over the substrate. 14. The method of fabricating an anti-gate type flash memory cell array according to claim 13, wherein the step of depositing the oxide layer over the substrate further comprises forming a second barrier. The step of layering on the oxide layer. 15. The method of fabricating an anti-gate type flash memory cell array according to claim 14, wherein the step of forming the second barrier layer on the oxide layer further comprises forming a layer. The step of inter-dielectric layer on the substrate. 16. The method for manufacturing a reverse-gate type flash memory cell array according to claim 15, wherein the step of forming the interlayer dielectric layer over the substrate further comprises forming a contact hole. The step of plugging at each end of the column. 17. The method of manufacturing the anti-gate type flash memory cell array according to claim 16, wherein the step of forming the contact hole at each end of the column further comprises forming a metal. Line the steps in the contact hole plug Client's Docket No.: 95146TW TT^s Docket No:0593-A41201-TW/Final/ianchen/070605 200849563. Clienfs Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605